VA70 BA52HR/CR

dpu NP /L/T V0 LOK IRM PE 0~ PIE X PU andy ridge Ivy ridge FI x PE -0 MI x R /00 MHz channel R /00 MHz channel U.0 R-III O-IMM* R-III O-IMM* amera PE PE POWER PU VORE PE 0 YTEM, +V, +V PE +VP & +VP_VT PE R & VTT PE.V &.V &.V PE MRT HRER PE V POWER PU VORE +.0V_V +.V_V +V_V +V_V LO WITH PE 0 PE HMI PE RT PE LV/eP K/ T/P FN PE Head Phone (ombo Jack) MI PE PE PE PE zalia odec RTK/L (V) PE PE 0 E ITE zalia LP HPI PH ougar Point Panther Point HM PE - U.0 U.0 U.0 U.0 U.0 U.0 PIE * U.0 U PORT U PORT U0 PORT U0 PORT U0 PORT0 U0 PORT PE PE Miniard WLN/WMX T combo PE POWER ETET PE 0 LO WITH PE POWER PROTET PE Power Rails leep tate 0 RT V VU ON ON ON V ON ON ON ON ON ON ON ON OFF / ON ON ON OFF / ON ON OFF OFF PIe Port PIE_P PIE_P RREER Mini R (WLN) POWER PROTET PE V ON OFF OFF OFF OFF PI ROM M (IO/E) PI ROM M (ME) PE PE 0 PI T H T PIE * PIE * PIE * U0 I FL00 PE iga LN R/R ard Reader RT0 PE PE 0 RJ PE PIE_P PIE_P PIE_P PIE_P U P00 U P0 U P0 U P0 U P0 LN U0 PORT mt U0 External M External M External PE 0 T H PIE * T.0 mt/ U P0 U P0 U P0 T amera External PE 0 T O PE U P0 U P U P PE 0 U P IO OR U PORT HP_OUT U PORT MI IN TP T OR Touch P utton LI W PWR OR POWER utton POWER LE LI W T PORT T P0 H T P H T P O T P mt T P T P U-R iv.-hw R ept. LOK IRM Wing_heng ustom HR/R Friday, February 0, 0 ate: heet of.0

OM optional N/ /T /nimt /HOME /HR /Non_HPI Entry Main /U0 Remark For 上上 For T, 上上 For no imt, 上上 For 上上 For Huron River, 上上 For ROM ETTIN, 上上 For 上上 For 上上 For U.0, 上上 /HPI /HMI /TP_U /TP_T /TP_MER /TP_R /TP_LN /TP_O /TP_WLN /THERM /usb0 /ZPO /MP For 不上上 For HMI 用, 不上上 For power control, 不上上 For power control, 不上上 For power control, 不上上 For power control, 不上上 For power control, 不上上 For power control, 不上上 For power control, 不上上 For Palm Rest 溫溫, 不上上 For U.0, 不上上 For O battery saving 使用 Mount R0, 不上上 For 不上上 For debug port, MP 不上上 /T0 /OMO_T /T+ 視 keypat list 而而視 keypat list 而而 For ata Repeater, R 先上上 PETRON OMPUTER IN ystem etting Wing_heng HR/R ate: Friday, February 0, 0 heet of.0

+VP +VP,,,,,,,,, P ompensation U00 MI_TXN0 MI_RX#[0] MI_TXN MI_RX#[] MI_TXN MI_RX#[] MI_TXN MI_RX#[] MI_TXP0 MI_RX[0] MI_TXP MI_RX[] MI_TXP MI_RX[] MI_TXP MI_RX[] MI_RXN0 MI_TX#[0] MI_RXN E MI_TX#[] MI_RXN F MI_TX#[] MI_RXN MI_TX#[] MI_RXP0 MI_TX[0] MI_RXP MI_TX[] MI_RXP F0 MI_TX[] MI_RXP MI_TX[] FI_TXN[:0] FI_TXN0 FI_TXN FI0_TX#[0] H FI_TXN FI0_TX#[] E FI_TXN FI0_TX#[] F FI_TXN FI0_TX#[] FI_TXN FI_TX#[0] 0 FI_TXN FI_TX#[] FI_TXN FI_TX#[] E FI_TX#[] FI_TXP[:0] FI_TXP0 FI_TXP FI0_TX[0] FI_TXP FI0_TX[] E0 FI_TXP FI0_TX[] FI_TXP FI0_TX[] 0 FI_TXP FI_TX[0] FI_TXP FI_TX[] FI_TXP FI_TX[] F FI_TX[] FI_FYN0 J FI0_FYN FI_FYN J FI_FYN FI_INT H0 FI_INT FI_LYN0 J FI0_LYN FI_LYN H FI_LYN +VP.Ohm % R00 P_OMP ep_ompio ep_iompo P_HP#_PH ep_hp P_UXP_PH ep_ux P_UXN_PH ep_ux# P_TXP0_PH ep_tx[0] P_TXP_PH F T00 P_TXP_PH ep_tx[] T00 P_TXP_PH ep_tx[] ep_tx[] P_TXN0_PH ep_tx#[0] P_TXN_PH E T00 P_TXN_PH ep_tx#[] T00 P_TXN_PH ep_tx#[] F ep_tx#[] MI Intel(R) FI ep PI EXPRE* - RPHI PE_IOMPI PE_IOMPO PE_ROMPO PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] +VP J PE_OMP R00 %.Ohm J H PIEN_RXN[:0] 0 K PIEN_RXN M PIEN_RXN L PIEN_RXN J PIEN_RXN J PIEN_RXN H PIEN_RXN0 H PIEN_RXN PIEN_RXN 0 PIEN_RXN F PIEN_RXN E PIEN_RXN E PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN0 PIEN_RXP[:0] 0 J PIEN_RXP L PIEN_RXP K PIEN_RXP H PIEN_RXP H PIEN_RXP PIEN_RXP0 PIEN_RXP F PIEN_RXP F0 PIEN_RXP E PIEN_RXP E PIEN_RXP F PIEN_RXP PIEN_RXP E PIEN_RXP PIEN_RXP PIEN_RXP0 M PIEN_TXN0 X00 0.UF/0V PIE_RXN M PIEN_TXN X00 0.UF/0V PIE_RXN M PIEN_TXN X00 0.UF/0V PIE_RXN L PIEN_TXN X00 0.UF/0V PIE_RXN L PIEN_TXN X00 0.UF/0V PIE_RXN K PIEN_TXN X00 0.UF/0V PIE_RXN0 K PIEN_TXN X00 0.UF/0V PIE_RXN J0 PIEN_TXN X00 0.UF/0V PIE_RXN J PIEN_TXN X00 0.UF/0V PIE_RXN H PIEN_TXN X00 0.UF/0V PIE_RXN PIEN_TXN0 X0 0.UF/0V PIE_RXN E PIEN_TXN X0 0.UF/0V PIE_RXN F PIEN_TXN X0 0.UF/0V PIE_RXN PIEN_TXN X0 0.UF/0V PIE_RXN F PIEN_TXN X0 0.UF/0V PIE_RXN E PIEN_TXN X0 0.UF/0V PIE_RXN0 M PIEN_TXP0 X0 0.UF/0V PIE_RXP M PIEN_TXP X0 0.UF/0V PIE_RXP M0 PIEN_TXP X0 0.UF/0V PIE_RXP L PIEN_TXP X00 0.UF/0V PIE_RXP L PIEN_TXP X0 0.UF/0V PIE_RXP K0 PIEN_TXP X0 0.UF/0V PIE_RXP0 K PIEN_TXP X0 0.UF/0V PIE_RXP J PIEN_TXP X0 0.UF/0V PIE_RXP J PIEN_TXP X0 0.UF/0V PIE_RXP H PIEN_TXP X0 0.UF/0V PIE_RXP PIEN_TXP0 X0 0.UF/0V PIE_RXP E PIEN_TXP X0 0.UF/0V PIE_RXP F PIEN_TXP X0 0.UF/0V PIE_RXP PIEN_TXP X00 0.UF/0V PIE_RXP E PIEN_TXP X0 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP0 PE ompensation Enable PIE Lane Reversal Need to P F[] PIE_RXN[:0] 0 PIE_RXP[:0] 0 OKET V0IM000 0-00000 - for Huron River If upport PIE en, change ap to 0.uF PETRON OMPUTER IN PU()_MI,PE,FI,LK,MI Wing_heng HR/R Friday, February 0, 0 ate: heet of.0

elect the termination voltage of MI and FI Tx/Rx (PH trap) H_N_IV# connected to F_TV via Kohm F_TV needs PU via.kohm to +.V H_N_IV# T00 T00 TP_KTO#_R TP_TERR#_R U00 N_IV# N KTO# L TERR# MI LOK LK LK# PLL_REF_LK PLL_REF_LK# LK_EXP_P_R LK_EXP_N_R LK_P_P_R LK_P_N_R P00 R00 P00 R00 R0 KOhm RN00 RN00 R00 KOhm +VP LK_EXP_P LK_EXP_N LK_P_P LK_P_N +.V_VQ +V +VU +VP +V +.V_VQ +V,,0,,,,,,,,,0,,,,0,,,,,,,0,,,,, +VU,,,,0,,,,, +VP,,,,,,,,, +V,,,,, do not remove because POWER removed thier PU R. Joyoung0 +VP H_PEI Ohm R.0, H_THRMTRIP# H_PROHOT# R00 R00 R00 Ohm H_PROHOT#_ H_THRMTRIP#_R P00 N L N PEI PROHOT# THERMTRIP# THERML R MI M_RMRT# M_ROMP[0] M_ROMP[] M_ROMP[] R RM Reset. R K M_ROMP_0 R0 % M_ROMP_ R0 %.Ohm M_ROMP_ R00 % 0 PURMRT# ystem Memory Impedance ompensation Huron River platform esign uide P. Table. Eric Fang to lan hien //00 Huron River platform esign uide Update 0 M_ROMP_ use ohm % PRY# PREQ# P P XP_PRY# XP_PREQ# T00 T00 R.0 PU/P for JT signals H_PM_YN 0KOhm H_PUPWR PM_RM_PWR R00 R00 R00 H_PM_YN_R P00 H_PUPWR_R P00 VPWROO_R R00 UF_PU_RT# M P V R PM_YN UNOREPWROO M_RMPWROK REET# PWR MNEMENT JT & PM TK TM TRT# TI TO R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] R R P0 R P L T R R0 T0 P R T R XP_TK XP_TM XP_TRT# XP_TI_R XP_TO_R H_R#_R XP_PM0_R XP_PM_R XP_PM_R XP_PM_R XP_PM_R XP_PM_R XP_PM_R XP_PM_R T00 T00 T00 T00 T00 T00 T0 T0 T0 T0 T0 T0 T0 T0 XP_TM XP_TI_R XP_TO_R XP_PREQ# XP_TK XP_TRT# R00 R00 R00 R00 R00 R00 Ohm Ohm Ohm Ohm Ohm Ohm +VP PM_Y_PWR is the power good for +.V_VQ OKET V0IM000 If don't support power reduction. Unmount R00, R0, U00, R0, Q00, 00, R0, R0, 00. hange R0 to 00ohm from kohm, change R00 to 0ohm from 0ohm - esign uide.0 page 0 +.V_VQ +VU +V. Unmount Q00, 00, R00, R00, R00. Mount R00, change r00 to 0ohm from kohm R0 0 %. Volt U00 V R0 0KOhm +.V_VQ Unmount Q00, R00, R00, Q00. Mount R00 and short JP00. Unmount R, R, Q0 PM_RM_PWR R00 P00 R. change to short pin 0 R00 KOhm % R0.KOhm % N Y Vcc=.~. 00 0.UF/0V E Q00 PM0 00 0.UF/0V R0 %.KOhm R0 KOhm % Power good for +.V_VQ (delay > 00ns) Reserve power reduction schematic +VP PLT_RT# U00 N V Y N +V 00 0.UF/V UFO_PU_RT# R0 Ohm R0 Ohm UF_PU_RT# 0 VR_HOT# R0 R0 Vcc=.~..KOhm heck Frank remove or not?? R0 % R0 R.0 0 andy ridge:r0 = 0 ohm (0V00000) Ivy ridge:r0 = 0 ohm (0V00000) R.0 0 Intel omments H_PROHOT# 00 PF/0V Q00 N00 THRO_PU THRO_PU 0 Frank 00 EVERT check PETRON OMPUTER IN PU()_MI,PE,FI,LK,MI Wing_heng HR/R Friday, February 0, 0 ate: heet of.0

+.V +.V,,,, U00 U00 M Q[:0] M 0 M M M # M R# M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q F0 M Q F M Q0 0 M Q M Q F M Q F M Q M Q M Q K M Q K M Q K M Q J M Q0 J M Q J M Q J M Q K M Q M M Q N0 M Q N M Q N M Q M0 M Q M M Q0 N M Q M M Q M Q M Q K M Q K M Q H M Q H M Q J M Q J M Q0 J M Q K M Q J M Q K M Q H M Q H M Q L M Q L M Q P M Q N M Q0 L M Q M M Q M M Q L M Q P M Q N M Q J M Q H M Q L M Q K M Q0 L M Q K M Q J M Q H E0 F0 V E F _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _[0] _[] _[] _# _R# _WE# R YTEM MEMORY _LK[0] _LK#[0] _KE[0] _LK[] _LK#[] _KE[] _LK[] _LK#[] _KE[] _LK[] _LK#[] _KE[] _#[0] _#[] _#[] _#[] _OT[0] _OT[] _OT[] _OT[] _Q#[0] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[0] _M[] _M[] _M[] _M[] _M[] V V0 W W0 K L H H H J M L M R M F K N L M R M 0 W W W V V W W V W V W F V V M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M 0 M M M M M M M M M M 0 M M M M M M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_LK_R M IM0_LK_R# M IM0_KE M IM0_LK_R M IM0_LK_R# M IM0_KE M IM0_LK_R M IM0_LK_R# M IM0_KE M IM0_#0 M IM0_# M IM0_# M IM0_# M IM0_OT0 M IM0_OT M IM0_OT M IM0_OT M Q#[:0] M Q[:0] M [:0] M Q[:0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M 0 M M M # M R# M WE# 0 F F F F J J K0 K J J0 K K M N N N M N M M M M R P N N N P P N T T P N R R R J T T H R J H T N R T T N R T R 0 _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _[0] _[] _[] _# _R# _WE# R YTEM MEMORY _LK[0] _LK#[0] _KE[0] _LK[] _LK#[] _KE[] _LK[] _LK#[] _KE[] _LK[] _LK#[] _KE[] _#[0] _#[] _#[] _#[] _OT[0] _OT[] _OT[] _OT[] _Q#[0] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[0] _M[] _M[] _M[] _M[] _M[] E R E R0 T T0 E E E E F K N N P K P J M N P K P T R T T T T R T R R T 0 R R M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M 0 M M M M M M M M M M 0 M M M M M M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_LK_R M IM0_LK_R# M IM0_KE M IM0_LK_R M IM0_LK_R# M IM0_KE M IM0_LK_R M IM0_LK_R# M IM0_KE M IM0_#0 M IM0_# M IM0_# M IM0_# M IM0_OT0 M IM0_OT M IM0_OT M IM0_OT M Q#[:0] M Q[:0] M [:0] OKET V0IM000 OKET V0IM000 R.0 circuit:- RM_RT# to memory should be high during +.V R.0 00 hange R00 to K ohm R00 close to IMM R00 KOhm 0-change Q00 from UMKN to N00 R00 Q00 N00 R00 PURMRT#_R, R_RMRT# KOhm PURMRT# % R00.KOhm, RMRT_NTRL_PH 00 0.0UF/V Reserve power reduction schematic If don't support power reduction. Unmount R00, R0, U00, R0, Q00, 00, R0, R0, 00. hange R0 to 00ohm from kohm, change R00 to 0ohm from 0ohm - esign uide.0 page 0. Unmount Q00, 00, R00, R00, R00. Mount R00, change r00 to 0ohm from kohm Unmount Q00, R00, R00, Q00. Mount R00 and short JP00 PETRON OMPUTER IN PU()_R Wing_heng. Unmount R, R, Q0 HR/R Friday, February 0, 0 ate: heet of.0

+VP 0-Remove 0 and nostuff 0,0,0 Vcc for processor core Voltage range: 0. -.V V-Q IMX V- IMX +VORE 0 F F F F F F0 F F F F 0 0 0 Y Y Y Y Y Y0 Y Y Y Y V V V V V V0 V V V V U U U U U U0 U U U U R R R R R R0 R R R R P P P P P P0 P P P P U00F POWER heck net name?? V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 ORE UPPLY ENE LINE VI PE N R VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VILERT# VILK VIOUT V_ENE V_ENE VIO_ENE VIO_ENE Voltage for the memory controller and shared cache defined at the motherboard VIO_ENE and V_ENE_VIO H H0 0 0 Y0 U0 P0 L0 J J J J H H H F F F F E E E J J J0 J J J 0 0 IMX_VIO. +VP R.0 0 Intel omments H_PU_VILRT# H_PU_VILK H_PU_VIT V_ENE_R V_ENE_R R.0 0 Intel omments R.0 0 Intel omments R00 P00 P00 lose to PU Ohm VENE VENE +VORE 0-Remove E00(powre schematic reserve) +VP +VP +VP +VP VP_ENE VP_ENE VENE 0 VENE 0 lose to VR Frank 000 check pull up/pull down reserve power schematic or not. R00 R00 R00 Ohm % 00 0UF/.V 0 UF/.V VR_VI_LERT# 0 P00 R00 0 UF/.V VR_VI_LK 0 Frank 00 hange VP_ENE to VIO_ENE and change VP_ENE to VIO_ENE for meet power schematic. Frank 00 Remove R00 and R00, because Power is already reserved 0 UF/.V 0 UF/.V 0 UF/.V 00 0UF/.V 0 UF/.V R00.Ohm % 0 UF/.V 0 UF/.V 0 UF/.V 00 0UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0-Remove E00(powre schematic reserve) 0 UF/.V 00 0UF/.V 0 UF/.V 00 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V lose to PU 0 0UF/.V 0 UF/.V 0 UF/.V 00 0UF/.V 0 UF/.V 0 UF/.V R00 % 0 UF/.V 00 UF/.V 0 0UF/.V 0 UF/.V 00 UF/.V 00 UF/.V 0 UF/.V 00 0UF/.V lose to VR P00 R00 00 UF/.V 0 UF/.V R00 % 00 0UF/.V 0 UF/.V +VP +VORE 0 0UF/.V 00 UF/.V VR_VI_T 0 +VP,,,,,,,,, +VORE,0 heck net name?? HR_ecoupling guide from Intel (POWER + EE) +VP uf * pcs ( nostuff) 0uF * pcs EIH/0 (EE) +VP 0uF * pcs (pcs no stuff) uf* 0 pcs (total no stuff) 0 uf *pcs Power support R_ecoupling guide from Intel (POWER + EE) +VP uf * pcs ( nostuff) 0uF * pcs ecoupling guide for Everest (EE) +VP uf * pcs ( no stuff) 0uF * pcs ( no stuff)=>jehr/r power support HR_ecoupling guide from Intel (POWER + EE) +V_ORE uf * pcs 0uF * 0pcs 0uF * pcs EIH/0 +V_ORE uf * pcs(pcs unmount) 0uF * pcs (pcs unmount) 0uF * pcs (Power support) R_ecoupling guide from Intel (POWER + EE) +V_ORE uf * pcs 0uF * 0pcs 0uF * pcs ecoupling guide for Everest (EE) +V_ORE uf * pcs ( nostuff) 0uF * 0pcs ( nostuff) 0uF * pcs=>jehr/r power support OKET V0IM000 PETRON OMPUTER IN PU()_PWR Wing_heng HR/R Friday, February 0, 0 ate: heet of.0

V-Q IMX_VX V- IMX_VX +VFX_ORE raphics core voltage Voltage range: 0 -.V 0-Remove E00(powre schematic reserve) HR_ecoupling guide from Intel (POWER + EE) +VFX_ORE uf * pcs 0uF * pcs EIH/0 00 UF/.V 0 UF/.V 00 UF/.V 0 UF/.V +VP uf* pcs ( unmount) 0uF * pcs (power support) 0uF *pcs (EIH el 0uF For Layout) R_ecoupling guide from Intel (POWER + EE) +VFX_ORE uf * pcs 0uF * pcs ecoupling guide for Everest (EE) +VFX_ORE uf * pcs ( nostuff) 0uF * pcs (JEHR/R power support) +.V uf * pcs 0uF * pcs 0uF * pcs EIH/0 PLL supply voltage ( + specification) IMX_VPLL. +.V HR_ecoupling guide from Intel (POWER + EE) +.V uf * pcs 0uF * pcs.uf*pcs.uf*pcs uf * pcs (un-mount) R_ecoupling guide from Intel (POWER + EE) +.V uf * pcs 0uF * pcs 0uF * pcs ecoupling guide from Everest (EE) +.V uf * pcs 0uF * pcs 00uF * pcs 00 UF/.V 0 UF/.V + E00 0UF/.V V0000000 00 UF/.V 0 UF/.V 0 0UF/.V 00 UF/.V 0 UF/.V 0 UF/.V 00 UF/.V 0 UF/.V 0 UF/.V U00 T VX T VX T VX T0 VX T VX T VX R VX R VX R VX R0 VX0 R VX R VX P VX P VX P VX P0 VX P VX P VX N VX N VX0 N VX N0 VX N VX N VX M VX M VX M VX M0 VX M VX M VX0 L VX L VX L VX L0 VX L VX L VX K VX K VX K VX K0 VX0 K VX K VX J VX J VX J VX J0 VX J VX J VX H VX H VX0 H VX H0 VX H VX H VX VPLL VPLL VPLL OKET V0IM000 POWER RPHI.V RIL ENE LINE RIL R -.V RIL VREF MI VX_ENE VX_ENE M_VREF VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ VQ VQ VQ VQ V V V V V V V V V_ENE F_ V_VI R.0 dd net name. Joyoung 0 0-dd P00,P00 K K L F F F Y Y Y U U U P P P M M L J J J H H H VT_ENE_R VT_ENE_R +V_M_REF 0mil +V_M_VREF_NT IMX_V R.0 00 Intel omments V_EL0 V_EL R00 00KOhm lose to PU 0 0UF/.V +VP 0 0UF/.V lose to PU 0 0UF/.V N/ V_ENE V_EL0 V_EL VT_ENE 0 VT_ENE 0 Voltage for the ystem gent and V_ENE 0-Remove 0 R00 P00 P00 0 0UF/.V R00 KOhm R00 KOhm R00 Q00 I0-T-E R00 R00 R.0 00 R00 KOhm R00 KOhm 0 0UF/.V 0 0UF/.V 0 0UF/.V N/ +V L H R Reference Voltage +V_M_VREF L H L H +.V_VQ +V_EL0 +V_EL L H V 0.V 0.V >00 ns 0.V 0.V HR_ecoupling guide from Intel (POWER + EE) +V 0uF * pcs 0uF * pcs EIH/0 + 0 0UF/.V N/ E00 00UF/.V +V 0uF * pcs ( nostuff) 00uF * pcs R_ecoupling guide from Intel (POWER + EE) +V 0uF * pcs 0uF * pcs 00 0UF/.V N/ ecoupling guide for Everest (EE) +V 0uF * pcs ( nostuff) 00uF * pcs + E00 0UF/.V +VP +.V +V +.V +VFX_ORE +.V_VQ +V_M_VREF Reserve power reduction schematic Q00 P_NTRL_.V_R IY_T_E MM_OPEN_MIL JP00 0-hange JP(MM_OPEN_MIL) +VP,,,,,,,,, +.V,,,, +V +.V,,, +VFX_ORE,0 +.V_VQ +V_M_VREF +.V P_NTRL_.V IMX_VQ Joyoung 0 Reduce to (E R.) Processor I/O supply voltage for R ( + specification) > 0 U_E# EIH 00 R00 0PF/0V +.V_VQ +.V_VQ Power ood (U00 pin ) +0.V +VQ 0uF * pcs ( nostuff) 0uF * pcs R. HR_ecoupling guide from Intel (POWER + EE) +VQ 0uF * pcs 0uF * pcs R_ecoupling guide from Intel (POWER + EE) +VQ 0uF * pcs 0uF * pcs ecoupling guide for Everest (EE) +VQ 0uF * pcs ( nostuff) 0uF * pcs PETRON OMPUTER IN PU()_PWR Wing_heng HR/R Friday, February 0, 0 ate: heet of.0

TP_V_IE_ENE ate: heet of Friday, February 0, 0 PETRON OMPUTER IN PU()_F,RV,N.0 HR/R Wing_heng ate: heet of Friday, February 0, 0 PETRON OMPUTER IN PU()_F,RV,N.0 HR/R Wing_heng ate: heet of Friday, February 0, 0 PETRON OMPUTER IN PU()_F,RV,N.0 HR/R Wing_heng R.0 V U00I OKET V0IM000 V U00I OKET V0IM000 V T V T V T V T V T V T0 V T V T V T V0 T V P V P V P V P V P V P V N V N V N V0 N V N V N0 V N V N V N V N V M V L V L0 V0 L V L V L V L V L V L V L V L V L V K V00 K V0 K V0 K V0 J V0 J V0 H V0 H0 V0 H V0 H V0 H V0 H V H V H V H0 V H V H V H V H V H V H V0 H V H V H V V V V V V 0 V V0 V F V F V F V F V F V E0 V E V E V E V0 E V E V E V E0 V E V E V E V E V E V E V0 E V E V E V V V V V 0 V V V0 V V V V V 0 V V V V V0 V V V V V V V V V V0 V V V V 0 V T00 T00 V U00H OKET V0IM000 V U00H OKET V0IM000 V T V T V T V T V T V T V T V T V T V0 T0 V T V T V T V R V R V R V R V R V R0 V0 R V R V R V P V P V P V P V P V P V P V0 P V P0 V P V P V P V N0 V N V N V N V N V0 N V N V N0 V N V N V M V M V M V M V M V0 M V M0 V M V M V M V M V M V L V L V L V0 L V L V L V L V L V L0 V L V L V L V K V0 K0 V K V K V K V K V K V K V K0 V K V K V0 J V J V J V J V J V J0 V J V J V J V J V0 J V H V H V H V H0 V H V H V H V H V H V00 H V0 H V0 H V0 H V0 V0 V0 V0 F V0 F V0 F V0 F V E V E V E V E V E V E0 V E V E V E V0 E V E V V V V V V V V V0 V V V V 0 V V V V V Y V0 Y V Y V Y V Y V Y V W V W V W V W V W V0 W0 V W V W V W V W V U V U V U V U V U V0 U

F strapping information: F[]: PIE tatic Numbering Lane Reversal- F[] is for the x - : (efault) Normal Operation, Lane # definition matches sockect pin map definition - 0: Lane Numbers Reversed -> 0, ->,... F[]: Embedded isplayport etection - : (efault) isabled ; No Physical isplay Port attached to Embedded isplayport - 0: Enabled ; n external isplay Port device is connected to the Embedded isplay Port F[:]: PI Express Port ifurcation traps - : (efault) x - 0 : x, x - 0 : Reserved - 00 : x, x, x F[]: PE EFER TRININ - : (efault) PE Train immediately following xxreet de assertion - 0: PE Wait for IO training F F F F F R00 R00 R00 R00 R00 % KOhm % KOhm % KOhm % KOhm % KOhm R.0 dd F0 This model is UM, unmount R00(use efault) Power schematic reserve.0v or not?? +VIO_EL.0V 0.00V IV VIO for Mobile and esktop is changed from.0v to.0v, same as PPT VIO. (0 WW') TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT T0 T0 T0 T0 T0 T0 T0 T0 T00 T00 T00 T00 T00 T00 T00 T00 T00 T00 T0 T0 T0 T00 R_WR_VREF0 R_WR_VREF0 R.0 0 IMM0_VREF_Q_R Pull own k ohm IMM_VREF_Q_R Pull own k ohm esign uide.0 P. Figure () R.0 0 Frank 0 Remove FO to XP elete VIO_EL. Joyoung0 TPT T0 F0 F F F F F F F F F F0 F F F F F F F VX_VL_ENE VX_VL_ENE V_VL_ENE V_VL_ENE VIO_EL_R Frank 00 hange VP_EL to VIO_EL for meeting Power schematic defined R00 % KOhm R00 % KOhm U00E K F[0] K F[] L F[] L F[] K F[] L F[] L0 F[] M F[] M F[] M0 F[] M F[0] M F[] N F[] N F[] N F[] M F[] K F[] N F[] J RV H RV J RV H RV J RV RV RV F RV F RV F RV0 RV RV RV E RV RV 0 RV RV 0 RV RV 0 RV0 RV 0 RV RV J0 RV RV RV J RV REERVE RV RV RV0 RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV KEY L E K W T M J T J H R T T P R J K H N M T T R TP_V_IE_ENE T0 TPT PROEOR RIVEN Vref PTH W TUFFE Y EFULT: R0 OKET V0IM000 R_WR_VREF0 O00 UMKN IMM0_VREF_Q, RMRT_NTRL_PH M Path:0 Ohm at Page R0 R_WR_VREF0 O00 UMKN IMM_VREF_Q Reserve power reduction schematic M: Processor enerated O-IMM VREFQ New Requirement andy ridge PU Only: M Implementation andy ridge/ivy ridge PU: M and M Implementation PETRON OMPUTER IN PU()_F,RV,N Wing_heng HR/R Friday, February 0, 0 ate: heet of.0

+VTT_PH_OR +VU +VP +V +VTT_PH_OR,, +VU,,,,,0,,,,, +VP,,,,,,,,,, +V,,,0,,,,,,,,,0,,,,0,,,,,,,0,,,,, PU XP connector PH XP connector PETRON OMPUTER IN N()_**** Wing_heng HR/R Friday, February 0, 0 ate: heet of 0.0

PM_EXTT#0_IM_ M M M M M M M M 0 M M M M M 0 M M M M Q# M Q# M Q# M Q# M Q M Q M Q M Q M Q M Q# M Q M Q M Q M Q# M Q M Q# M Q# M Q M Q# M Q#0 M Q M Q# M Q0 M Q# M M M M M M M M 0 M M M M M 0 M M M M_T_ M R# M Q# M Q# M Q# M Q# M M M 0 M Q M Q M Q M Q R_RMRT# M_LK_ M WE# PM_EXTT#0_IM_ M # M IM0_LK_R#0 M IM0_LK_R0 M IM0_LK_R# M IM0_LK_R M IM0_LK_R# M IM0_LK_R M IM0_LK_R# M IM0_LK_R M Q# M Q M Q#0 M Q0 M Q# M Q M Q# M Q M Q# M Q M Q# M Q M Q# M Q M Q#0 M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q0 M Q0 M Q M Q +V,,0,,,,,,,,,0,,,,0,,,,,,,0,,,,, +0.V,, +.V,,,, +.V_R, M Q[:0] M Q[:0] M [:0] M Q#[:0] R_RMRT#, M IM0_KE0 M IM0_KE M IM0_LK_R M IM0_LK_R# M M M 0 M IM0_LK_R0 M IM0_LK_R#0 M # M IM0_OT M IM0_OT0 M IM0_# M IM0_#0 M R# M WE# M_T_,,,, M_LK_,,,, M IM0_LK_R M IM0_KE M IM0_KE M IM0_LK_R# M IM0_LK_R M IM0_LK_R# M IM0_OT M IM0_OT M IM0_# M IM0_# +0.V +V +0.V +.V +.V_R +V +.V_R +V_VREF IMM0 +V_VREF_Q_IMM0 +.V_R +.V +.V_R +0.V +.V_R +V +.V_R +V_VREF IMM0 +V_VREF_Q_IMM0 +0.V +.V_R +0.V +.V_R +V ate: heet of Friday, February 0, 0 --HW R& ept. R()_O-IMM0.0 PLF hren_chen ate: heet of Friday, February 0, 0 --HW R& ept. R()_O-IMM0.0 PLF hren_chen ate: heet of Friday, February 0, 0 --HW R& ept. R()_O-IMM0.0 PLF hren_chen Layout Note: Place these caps near O IMM 0 Reserve 0 H:.mm M should connect to N directly esign uide 0. p () Mus lave ddress: 0H 0 Layout Note: Place these caps near O IMM 0 Reserve H:.mm M should connect to N directly esign uide 0. p () Mus lave ddress: H +.V PWR: UF*P EE:0UF*P Layout Note: Place these caps near O IMM 0 Layout Note: Place these caps near O IMM 0 +.V PWR: UF*P EE:0UF*P ok ok ok ok ok ok ok ok 0 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V 0 0UF/.V 0 0UF/.V RN0 0KOhm RN0 0KOhm.UF/.V.UF/.V T0 T0 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V ON0 R_IMM_0P V0WM000 ON0 R_IMM_0P V0WM000 0 0/P 0 /# 0 0 0 0 0 # K0# 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q Q#0 0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q # 0# OT 0 OT0 WE# R# 0 0 0 L 0 00 REET# 0 0UF/.V 0UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V 0.UF/V 0.UF/V RN0 0KOhm RN0 0KOhm 0 0UF/.V 0 0UF/.V 0PF/0V 0PF/0V 0 0.UF/V 0 0.UF/V UF/.V UF/.V 0.UF/V 0.UF/V.UF/.V.UF/.V UF/.V UF/.V R R 0UF/.V 0UF/.V 0 0.UF/V 0 0.UF/V T0 T0.UF/.V.UF/.V.UF/.V.UF/.V 0UF/.V 0UF/.V R R 0 0UF/.V 0 0UF/.V UF/.V UF/.V R0 R0 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0 0PF/0V 0 0PF/0V 0.UF/V 0.UF/V ON0 R_IMM_0P V0M000 ON0 R_IMM_0P V0M000 EVENT# N 0 N 0 N N NP_N 0 NP_N 0 TET V V0 00 V 0 V 0 V V V V V V V V V V V V V V VP VREF VREFQ V V 0 V V V V V0 0 V V V V V V V V V V V0 V V V V V V 0 V V V V V0 V V V V V V V V V V 0 V0 V V V V V V V V V V V0 V VTT 0 VTT 0 UF/.V UF/.V RN0 0KOhm RN0 0KOhm UF/.V UF/.V 0.UF/V 0.UF/V RN0 0KOhm RN0 0KOhm 0UF/.V 0UF/.V R R UF/.V UF/.V 0.UF/V 0.UF/V.UF/.V.UF/.V 0PF/0V 0PF/0V ON0 R_IMM_0P V0M000 ON0 R_IMM_0P V0M000 0 0/P 0 /# 0 0 0 0 0 # K0# 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q Q#0 0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q # 0# OT 0 OT0 WE# R# 0 0 0 L 0 00 REET# 0 + E0 0UF/V + E0 0UF/V UF/.V UF/.V 0.UF/V 0.UF/V 0PF/0V 0PF/0V UF/.V UF/.V UF/.V UF/.V 0 0UF/.V 0 0UF/.V UF/.V UF/.V ON0 R_IMM_0P V0WM000 ON0 R_IMM_0P V0WM000 EVENT# N 0 N 0 N N NP_N 0 NP_N 0 TET V V0 00 V 0 V 0 V V V V V V V V V V V V V V VP VREF VREFQ V V 0 V V V V V0 0 V V V V V V V V V V V0 V V V V V V 0 V V V V V0 V V V V V V V V V V 0 V0 V V V V V V V V V V V0 V VTT 0 VTT 0.UF/.V.UF/.V UF/.V UF/.V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0UF/.V 0UF/.V UF/.V UF/.V 0UF/.V 0UF/.V

PM_EXTT#0_IM_ M Q# M Q# M Q# M Q# M Q# M Q#0 M Q# M Q# PM_EXTT#0_IM_ M Q# M Q# M Q# M Q# M Q# M Q#0 M Q# M Q# M_LK_ M Q M Q M Q M Q M Q M Q M Q M Q0 R_RMRT# M M M M M M M M 0 M M M M M 0 M M M M WE# M # M_T_ M M 0 M M R# M Q M Q M Q M Q M Q M Q M Q M Q0 M M M M M M M M 0 M M M M M 0 M M M M Q#0 M Q M Q M Q# M Q M Q# M Q# M Q M Q# M Q M Q0 M Q M Q# M Q# M Q# M Q M IM0_LK_R# M IM0_LK_R M IM0_LK_R#0 M IM0_LK_R0 M IM0_LK_R# M IM0_LK_R M IM0_LK_R# M IM0_LK_R M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q0 M Q0 M Q0 M Q +V,,0,,,,,,,,,0,,,,0,,,,,,,0,,,,, +0.V,, +.V,,,,, +.V_R, M Q#[:0] M Q[:0] M Q[:0] M [:0] M_T_,,,, M_LK_,,,, M M 0 M M # M R# R_RMRT#, M IM0_OT0 M IM0_OT M WE# M IM0_LK_R M IM0_LK_R# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_KE M IM0_# M IM0_#0 M IM0_LK_R# M IM0_KE M IM0_KE M IM0_LK_R M IM0_OT M IM0_OT M IM0_LK_R# M IM0_LK_R M IM0_# M IM0_# +0.V +.V_R +0.V +.V_R +V +0.V +.V +.V_R +0.V +.V_R +V +.V_R +V +V_VREF IMM +V_VREF_Q_IMM +0.V +.V_R +V +.V_R +V +V_VREF IMM +V_VREF_Q_IMM ate: heet of Friday, February 0, 0 --HW R& ept. R()_O-IMM.0 PLF hren_chen ate: heet of Friday, February 0, 0 --HW R& ept. R()_O-IMM.0 PLF hren_chen ate: heet of Friday, February 0, 0 --HW R& ept. R()_O-IMM.0 PLF hren_chen Layout Note: Place these caps near O IMM +.V PWR: UF*P EE:0UF*P Layout Note: Place these caps near O IMM +.V PWR: UF*P EE:0UF*P M should connect to N directly esign uide 0. p () M should connect to N directly esign uide 0. p () Reserve Reserve 0 Layout Note: Place these caps near O IMM 0-000R000 (V0IRM00) Mus lave ddress: H H:MM 0 Layout Note: Place these caps near O IMM Mus lave ddress: H H:MM ok ok ok ok ok ok ok ok.uf/.v.uf/.v 0PF/0V 0PF/0V 0.UF/V 0.UF/V RN0 0KOhm RN0 0KOhm ON0 R_IMM_0P V0IRM00 ON0 R_IMM_0P V0IRM00 EVENT# N 0 N 0 N N NP_N 0 NP_N 0 TET V V0 00 V 0 V 0 V V V V V V V V V V V V V V VP VREF VREFQ V V 0 V V V V V0 0 V V V V V V V V V V V0 V V V V V V 0 V V V V V0 V V V V V V V V V V 0 V0 V V V V V V V V V V V0 V VTT 0 VTT 0.UF/.V.UF/.V UF/.V UF/.V UF/.V UF/.V RN0 0KOhm RN0 0KOhm.UF/.V.UF/.V UF/.V UF/.V RN0 0KOhm RN0 0KOhm UF/.V UF/.V UF/.V UF/.V 0.UF/V 0.UF/V UF/.V UF/.V R R.UF/.V.UF/.V 0UF/.V 0UF/.V ON0 R_IMM_0P V0RM00 ON0 R_IMM_0P V0RM00 0 0/P 0 /# 0 0 0 0 0 # K0# 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q Q#0 0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q # 0# OT 0 OT0 WE# R# 0 0 0 L 0 00 REET# 0 UF/.V UF/.V 0.UF/V 0.UF/V 0.UF/V 0.UF/V UF/.V UF/.V 0UF/.V 0UF/.V 0PF/0V 0PF/0V 0 0.UF/V 0 0.UF/V T0 N/ T0 N/ R R R R 0 0PF/0V 0 0PF/0V 0 0UF/.V 0 0UF/.V 0 0.UF/V 0 0.UF/V 0UF/.V 0UF/.V 0 0.UF/V 0 0.UF/V UF/.V UF/.V UF/.V UF/.V 0 0UF/.V 0 0UF/.V 0PF/0V 0PF/0V UF/.V UF/.V.UF/.V.UF/.V 0UF/.V 0UF/.V + E0 0UF/V + E0 0UF/V 0.UF/V 0.UF/V R0 R0 ON0 R_IMM_0P V0IRM00 ON0 R_IMM_0P V0IRM00 0 0/P 0 /# 0 0 0 0 0 # K0# 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q Q#0 0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q # 0# OT 0 OT0 WE# R# 0 0 0 L 0 00 REET# 0 0 0.UF/V 0 0.UF/V 0 0UF/.V 0 0UF/.V 0.UF/V 0.UF/V 0UF/.V 0UF/.V.UF/.V.UF/.V UF/.V UF/.V T0 N/ T0 N/ ON0 R_IMM_0P V0RM00 ON0 R_IMM_0P V0RM00 EVENT# N 0 N 0 N N NP_N 0 NP_N 0 TET V V0 00 V 0 V 0 V V V V V V V V V V V V V V VP VREF VREFQ V V 0 V V V V V0 0 V V V V V V V V V V V0 V V V V V V 0 V V V V V0 V V V V V V V V V V 0 V0 V V V V V V V V V V V0 V VTT 0 VTT 0 RN0 0KOhm RN0 0KOhm UF/.V UF/.V 0 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V 0 0.UF/V 0 0.UF/V UF/.V UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V UF/.V UF/.V UF/.V UF/.V 0.UF/V 0.UF/V

R Vref +.V_R +V_VREF IMM0 +.V_R, +V_VREF IMM0 +V_VREF_R +V_VREF IMM0 +V_VREF_Q_IMM0 +V_VREF_Q_IMM0 M_VREF P0 R00 +V_VREF IMM +V_VREF IMM +V_VREF IMM M_VREF R0 P0 R00 For R_VREF command & address. +V_VREF_Q_IMM +V_M_VREF +V_VREF_Q_IMM +V_M_VREF +V_M_VREF R.0 0 For M test only M: Fixed O-IMM VREF_Q +.V_R R0 KOhm P0 R0 R0 R00 Q +V_VREF_Q_IMM0 +V_VREF_Q_IMM R0 R0 +.V_R R KOhm 0 0.UF/V R0 KOhm R.0 0 0.UF/V R0 KOhm IMM0_VREF_Q R0 IMM_VREF_Q R0 efault M M M: Processor enerated O-IMM VREFQ New Requirement M If support M :(andy ridge PU Only). Un mount R0,R0,R0,R0,R0,R,0. Mount R0,R0 ==> and Q are the same path If support M and M :(andy ridge/ivy ridge PU). Mount R0,R0,R0,R0,R0,R,0. Un mount R0,R0 ==> and Q are separate path andy ridge PU Only: M Implementation andy ridge/ivy ridge PU: M and M Implementation PETRON OMPUTER IN R()_/Q Voltage Wing_heng HR/R Friday, February 0, 0 ate: heet of.0

R.-- PETRON OMPUTER IN VI ontroller Wing_heng HR/R Friday, February 0, 0 ate: heet of.0

RT battery N +RTT R00 J00 TT_HOLER_P V0M000 +V +RT_T KOhm R.0 00 增增增增增 00 V/0. +V_RT N onnector Type -00L000 00 UF/.V Z_LK_U 00 0PF/0V EMI solution +V_RT +V +V +VU_OR +.0VM_OR +VTT_PH_VIO +V_RT, +V,0,,,,,, +V,,,,,,,,,,,0,,,,0,,,,,,,0,,,,, +VU_OR,,,, +.0VM_OR +VTT_PH_VIO, R.0 elete +RTT +V_RT RTRT# R delay should be ms~ms R00 0KOhm 00 UF/.V JRT00 L_JUMP Request by for MO clear function MO ettings lear MO Keep MO JRT00 hunt Open (efault) N N 00 PF/0V RT_X_ P00 X00 R00.KHZ R00 0MOhm U00 R00 T0 N N T0 N 0KOhm T0 R00 MOhm N TPM ettings lear ME RT Registers Keep ME RT Registers 00 UF/.V N JRT00 hunt JRT00 L_JUMP Open (efault) INTVRMEN: Integrated U.0V VRM Enables Low: Enable External VRs High:Enable Internal VRs PH_INTVRMEN R00 % 00KOhm N 0, Z_LK_U Z_YN_U _PKR Z_RT#_U Z_IN0_U PH_FLH_ERIPTOR Z_OUT_U 0 00 +V_RT MEFLH_EN# T0 PF/0V T00 0KOhm % R00 R0 R0 R0 R00 R0 R0 Ohm Ohm Ohm RT_X RT_X RT_RT# RT_RT# M_INTRUER# PH_INTVRMEN Z_LK Z_YN Z_RT# Remove TP Z_OUT R00 near R00 H_OK_EN# RREER_REET PH_JT_TK_UF 0 0 0 K N L T0 K E N J RTX RTX RTRT# RTRT# INTRUER# INTVRMEN H_LK H_YN PKR H_RT# H_IN0 H_IN H_IN H_IN H_O RT IH H_OK_EN#/PIO H_OK_RT#/PIO JT_TK T LP T FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/PIO ERIRQ T0RXN T0RXP T0TXN T0TXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP E K V M M P P M0 M P P0 H H 0 F F Y Y Y Y NN_PH_RQ#0 NN_LP_RQ# erial Interrupt Request T0 T0 LP_0 0, LP_ 0, LP_ 0, LP_ 0, LP_FRME# 0, INT_ERIRQ 0, T_RXN0 0 T_RXP0 0 T_TXN0 0 T_TXP0 0 T_RXN T_RXP T_TXN T_TXP T_RXN 0 T_RXP 0 T_TXN 0 T_TXP 0 T_RXN 0 T_RXP 0 T_TXN 0 T_TXP 0 H 0 mt O 0 H T0 T0 T0 PH_JT_TM PH_JT_TI PH_JT_TO H K H JT_TM JT_TI JT_TO JT TIOMPO TIOMPI TROMPO Y Y0 T_OMP R00 %.Ohm +VTT_PH_VIO TOMPI T_OMP R0 %.Ohm +VTT_PH_VIO,0 PH_PILK T PI_LK TRI H RI_T R0 % N H_KEN : Flash escriptor ecurity Overide H = isabled (efault) L = Enabled Note : Rising edge of PWROK H_OK_EN# JRT MM_OPEN_MM R00 KOhm PH_PI0#,0 PH_PI#,0 PH_PII,0 PH_PIO PH_PI# Y PI_0# T PI_# V PI_MOI U PI_MIO OUR_POINT_E 0V00000000 PI TLE# T0P/PIO TP/PIO P V P T0P _IT0_R R0 0KOhm T_LE# P00 R00 +V T_LE# _IT0 R.0 add JRT to follow I0. Joyoung 0 000-00HU000. 0 QMVY INTEL/OUR POINT PH trap information: _PKR R00 KOhm +V Pull High +V _PKR: No reboot strap Low: isable (efault) High:Enable Z_OUT R0 KOhm +VU_OR INT_ERIRQ T0P R0 0KOhm R0 0KOhm Z_OUT:.Flash descriptor security: ampled Low: in effect. Z_YN ampled High: override.z_outwhich sample high on the rising edge of PWROK Will also disable Intel ME. R0 KOhm VVRM use +.V in mobile +VU_OR Z_YN: On ie PLL VR voltage selector Low:.V (efault) High:.V note : R has no strap Hrron River Platform chematic esign hecklist (0 page ) PETRON OMPUTER IN PH()_T,IH,RT,LP Wing_heng HR/R Friday, February 0, 0 ate: heet of 0.0

+V +V,,,0,,,,,,,,0,,,,0,,,,,,,0,,,,, +VTT_PH_OR +VTT_PH_OR,, +VU_OR +VU_OR 0,,,, PIE_RXN_WLN PIE_RXP_WLN PIE_TXN_WLN PIE_TXP_WLN PIE_RXN_mT PIE_RXP_mT PIE_TXN_mT PIE_TXP_mT PIE_RXN_LN PIE_RXP_LN PIE_TXN_LN PIE_TXP_LN 0 0 0 0 PIE_RXN_U0 PIE_RXP_U0 PIE_TXN_U0 PIE_TXP_U0 0 0 PIE_RXN_R PIE_RXP_R PIE_TXN_R PIE_TXP_R LK_PIE_R#_PH LK_PIE_R_PH 0 0 0 0 0 0 0 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V /FL00 /FL00 T0 T T0 0.UF/V 0.UF/V 0.UF/V 0.UF/V P P PIE_TXN_WLN_ PIE_TXP_WLN_ PIE_TXN_mT_ PIE_TXP_mT_ PIE_TXN_U0_ PIE_TXP_U0_ LK_PH_R0_N LK_PH_R0_P LK_REQ0# PIE_TXN_R_ PIE_TXP_R_ PIE_TXN_LN_ PIE_TXP_LN_ LK_PH_R_N LK_PH_R_P J V U E F Y J V U F E Y H Y J U V 0 J0 Y0 0 E W Y Y0 Y J U00 PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp LKOUT_PIE0N LKOUT_PIE0P PI-E* 00MHz PIELKRQ0#/PIO LKOUT_PIEN 00MHz LKOUT_PIEP LOK MU ontroller MLERT#/PIO MLK MT ML0LERT#/PIO0 ML0LK ML0T MLLERT#/PHHOT#/PIO MLLK/PIO MLT/PIO L_LK Link L_T L_RT# PE LKRQ#/PIO 00MHz LKOUT_PE N LKOUT_PE P 00MHz LKOUT_MI_N LKOUT_MI_P E H E M M T P0 M0 V U EXT_I# L RMRT_NTRL_PH ML0_LK ML0_T MLLERT# ML_LK ML_T LK_REQ_PE_# LK_PIE_PE#_PH_L LK_PIE_PE_PH_L P P P T R00 R00 R00 EXT_I# 0 L RMRT_NTRL_PH, T T T T T ML_LK ML_T LKREQ_PE# 0 LK_PIE_PE#_PH 0 LK_PIE_PE_PH 0 LK_EXP_N LK_EXP_P LK_UF_PYLK_N LK_UF_PYLK_P RN0 0KOhm RN0 0KOhm LK_UF_EXP_N LK_UF_EXP_P RN0 LK_UF_OT_N 0KOhm RN0 0KOhm LK_UF_OT_P RN0 0KOhm LK_UF_K_N RN0 LK_UF_K_P 0KOhm RN 0KOhm RN 0KOhm LK_UF_REF R 0KOhm LOK TERMINTION for FIM efault power-on mode is I. N +VU_OR EXT_I# R 0KOhm L_ RN0.KOhm _ RN0.KOhm RMRT_NTRL_PH R0 KOhm ML0_LK RN0.KOhm ML0_T RN0.KOhm ML_LK RN0.KOhm ML_T RN0.KOhm MLLERT# R 0KOhm +V PU_EI_ELET# R 0KOhm PU_PRNT# R /UM 0KOhm LK_PIE_WLN#_PH LK_PIE_WLN_PH 0 LK_REQ_WLN# LK_REQ_R# P0 P0 P0 P R00 R00 R00 LK_PH_R_N LK_PH_R_P LK_REQ# LK_REQ# M V0 PIELKRQ#/PIO LKOUT_PIEN 00MHz LKOUT_PIEP PIELKRQ#/PIO0 0MHz LKOUT_P_N LKOUT_P_P 00MHz LKIN_MI_N LKIN_MI_P M M F E LK_P_N LK_P_P LK_UF_EXP_N LK_UF_EXP_P LK_P_N LK_P_P PU_PRNT# R 0KOhm N LK_PIE_mT#_PH LK_PIE_mT_PH P0 P0 R00 R00 LK_PH_R_N LK_PH_R_P Y Y LKOUT_PIEN LKOUT_PIEP 00MHz LKIN_N_N LKIN_N_P J0 0 LK_UF_PYLK_N LK_UF_PYLK_P PH LKREQ etting: Not connected to device. LK_REQ_PIE_mT#.U.0 LK_PIE_U#_PH LK_PIE_U_PH LK_REQ_U0# P0 R00 P P0 P LK_REQ# LK_PH_R_N LK_PH_R_P LK_REQ# Y Y L PIELKRQ#/PIO OUR_POINT_E LKOUT_PIEN 00MHz LKOUT_PIEP PIELKRQ#/PIO MHz LKIN_OT_N LKIN_OT_P 00MHz LKIN_T_N LKIN_T_P E K K LK_UF_OT_N LK_UF_OT_P LK_UF_K_N LK_UF_K_P R.0 0 LK_REQ_LN# LK_REQ0# R R +VU_OR 0KOhm 0KOhm LK_PIE_LN# LK_PIE_LN LK_REQ_LN# P0 P0 P0 T T T T T T R00 R00 R00 LK_PH_R_N LK_PH_R_P LK_REQ# LK_PH_PE N LK_PH_PE P LK_REQ_PE_# LK_PH_R_N LK_PH_R_P LK_REQ# V V L 0 E V0 V T LKOUT_PIEN 00MHz LKOUT_PIEP PIELKRQ#/PIO LKOUT_PE N 00MHz LKOUT_PE P PE LKRQ#/PIO LKOUT_PIEN 00MHz LKOUT_PIEP PIELKRQ#/PIO.MHz REFLKIN MHz LKIN_PILOOPK XTL_IN XTL_OUT XLK_ROMP K H V V Y LK_UF_REF XTL_IN XTL_OUT XLK_OMP R0 0.Ohm LK_PI_F +VIFFLKN MOhm R MOhm XTL_OUT_ R00 P 0 0PF/0V X0 MHZ 0 0PF/0V N N N LK_REQ# R 0KOhm R.0 LK_REQ# is change to +VU 00 LK_REQ# R 0KOhm LK_REQ# R 0KOhm LK_REQ# R 0KOhm LK_REQ_PE_# R0 0KOhm LK_REQ_PE_# R 0KOhm T T T LK_PH_R_N LK_PH_R_P LK_REQ# R.0 Remove PIE_LK_XP 00 V V K K K LKOUT_PIEN 00MHz LKOUT_PIEP PIELKRQ#/PIO LKOUT_ITPXP_N 00MHz LKOUT_ITPXP_P FLEX LOK LKOUTFLEX0/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO K F H K PU_EI_ELET# LK_OUT LK_OUT PU_PRNT# T T T T0 onnected to device. LK_REQ_WLN# R 0KOhm +V 0V00000000 LK_REQ# R 0KOhm LK_REQ# R 0KOhm LK_REQ_LN# R 0KOhm LK_REQ_WLN# R 0KOhm LK_REQ# R 0KOhm LK_REQ# R 0KOhm N PETRON OMPUTER IN PH()_PIE,LK,M,PE Wing_heng HR/R Friday, February 0, 0 ate: heet of.0

+VU_OR +VU_OR 0,,,, +V +V,,,0,,,,,,,,0,,,,0,,,,,,,0,,,,, U00 +VTT_PH_OR +V +VTT_PH_OR, +V 0,,0,,,,,, MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP E0 0 E 0 J J0 W W0 V Y Y0 Y U MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT J Y E H J 0 F E J0 H W FI_INT_R P0 R00 FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_INT +V_RT +VU +VU +VU +V_RT 0, +VU,,,,0,,,,, +VU,0,0,,,,,,,,, +VU,0,, J MI_ZOMP FI_FYN0 V FI_FYN0_R P0 R00 FI_FYN0 +VTT_PH_OR R0 %.Ohm MI_OMP_R MI_IROMP FI_FYN 0 FI_FYN_R P0 R00 FI_FYN N R0 % RI_PY H MIRI FI_LYN0 V FI_LYN0_R P0 R00 FI_LYN0 FI_LYN 0 FI_LYN_R P0 R00 FI_LYN WVRMEN WOVREN R R 0KOhm 0KOhm N +V_RT WOVREN - On ie W VR Enable HIH - Enabled(EFULT) ; LOW-isabled 0, PM_RMRT# has pull down 0k ohm in E PM_PWROK 0 PM_RM_PWR 0 T0 U_PWR_K_R P R00 UK# R0 +V PM_RMRT# ME_UPWRNK Y_PWROK R.0 R0.V/0. 0 P P P P P 0KOhm R00 R00 R00 R00 R00 UK#_R PM_YRT#_R Y_PWROK_R PM_PH_PWROK_R PM_PWROK_R PM_RMRT_R U_PWR_K_R K P L L0 K UK# Y_REET# Y_PWROK PWROK PWROK RMPWROK RMRT# ystem Power Management UWRN#/UPWRNK/PIO0 PWROK WKE# LKRUN#/PIO U_TT#/PIO ULK/PIO LP_#/PIO LP_# LP_# E N N 0 H F PH_PROK U_TT U_LK LP_# LP_#_R LP_#_R P0 T0 P0 P0 R00 PM_RMRT_R PIE_WKE#,, PM_LKRUN# 0 Remove ULK signal for TPM 00 R00 R00 T0 T0 R. Remove U_LK signal 00 R.0 delete P for unuse. Joyoung 0 PM_U# 0 PM_U# 0 0 0 PM_PWRTN# ME PREENT T0 P R00 P R00 _PREENT_R TLOW# E0 H0 E0 PWRTN# PREENT/PIO TLOW#/PIO LP_# LP_U# PMYNH 0 P ME_PM_LP_#_R R LP_U#_R R R.0 00 LP_U# 0 H_PM_YN R.0 0 ME_PM_LP_# 0 i-mt T0 RI# 0 RI# LP_LN#/PIO K ME_PM_LP_LN#_R R ME_PM_LP_LN# 0 R.0 cut trace. Joyoung 0 i-mt 0V00000000 OUR_POINT_E R.0 0 Y_PWROK for PH R0 +VU PM_PWROK U0 V ELY_VR_N_LL_Y N Y Vcc=~. Y_PWROK R0 +VU_OR RI# R 0KOhm +VU +VU +VU TLOW# R 0KOhm R0 0KOhm R 0KOhm % R 00KOhm P_NTRL_.V R.0 00 +V R.0 00 PIE_WKE# R KOhm PM_LKRUN# R0 0KOhm ME_PM_LP_#_R R 0KOhm Q0 UMKN PM_PWROK R 0KOhm ME_UPWRNK R 0KOhm,0,,, U_E# PM_U# P R00 R Q0 UMKN N ME PREENT ME_PM_LP_LN#_R R 0KOhm R 0KOhm PETRON OMPUTER IN PH()_FI,MI,Y PWR Wing_heng N N HR/R Friday, February 0, 0 ate: heet of.0

+V +V,,,0,,,,,,,,0,,,,0,,,,,,,0,,,,, +V L_KEN_PH L_V_EN_PH P0 P0 R00 R00 J M U00 L_KLTEN L_V_EN VO_TVLKINN VO_TVLKINP P P L_TRL_LK L_TRL_T _PH _PH.KOhm.KOhm.KOhm.KOhm RN0 RN0 RN0 RN0 Frank 00 Pull up.k ohm in bus for RT and LV. Frank 0 modify RT net name. L_L_PWM_PH LV_LK_PH LV_T_PH R.0 irect link. Joyoung 0 T0 R.0 0 T0 Use ep panel,l is N R0 Un mount R0 R0 LV_LLKN_PH LV_LLKP_PH LV_L0N_PH LV_LN_PH LV_LN_PH LV_L0P_PH LV_LP_PH LV_LP_PH LV_LLKN_PH LV_LLKP_PH LV_L0N_PH LV_LN_PH LV_LN_PH LV_L0P_PH LV_LP_PH LV_LP_PH N P0 L_TRL_LK L_TRL_T.KOhm R00 P T0 K T P F F E E K K0 N M K J N M K J F0 F H H F F H H F F L_KLTTL L LK L T L_TRL_LK L_TRL_T LV_I LV_V LV_VREFH LV_VREFL LV_LK# LV_LK LV_T#0 LV_T# LV_T# LV_T# LV_T0 LV_T LV_T LV_T LV_LK# LV_LK LV_T#0 LV_T# LV_T# LV_T# LV_T0 LV_T LV_T LV_T LV igital isplay Interface VO_TLLN VO_TLLP VO_INTN VO_INTP VO_TRLLK VO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P M M0 P P0 P M T T T0 V V0 V V U U V V P P P P T Y Y Y Y isplay Port isplay Port VO PH PH _R_PH RT PH RT PH RT_R_PH 0 ohm 0 ohm 0 ohm JP0 lose to PU HORT_PIN JP0 HORT_PIN JP0 HORT_PIN R0 /UM R0 /UM N. ohm. ohm. ohm R0 /UM _PH _PH _HYN_PH _VYN_PH N N _PH _PH R_PH P0 P0 R0 0.% R00 R00 KOhm N P T T M0 M M T T RT_LUE RT_REEN RT_RE RT LK RT T RT_HYN RT_VYN _IREF RT_IRTN RT P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P M M T T H F E F E J P_UXN P_UXP HMI LK_PH HMI T_PH T0 T0 HMI_HP_PH HMI_TXN_PH HMI_TXP_PH HMI_TXN_PH HMI_TXP_PH HMI_TXN0_PH HMI_TXP0_PH HMI_LKN_PH HMI_LKP_PH isplay Port OUR_POINT_E 0V00000000 RT isable: (For discrete graphic). N: RT_RE,RT_REEN,RT_LUE RT_HYN,RT_VYN. -kω ±0.% pull-down to N: _IREF. onnected to N: RT_ITRN. onnect to +V.: V isplay Port isable: (For discrete graphic). N: LL LV isable: (For discrete graphic). N: LV_T [:0], LV_T# [:0], LV_LK, LV_LK#, LV_T [:0], LV_T# [:0], LV_LK, LV_LK# L_V_EN, L_KLTEN, L_KLTTL, LV_VREFH LV_VREFL, LV_I, LV_V. onnected to N: VccLV,VccTX_LV PETRON OMPUTER IN PH()_P,LV,RT Wing_heng HR/R Friday, February 0, 0 ate: heet of.0

+V +VU +V +VU,,,,0,,,,, +V,,,0,,,,,,,,0,,,,0,,,,,,,0,,,,, +V V_PWRON +V +V RN0 RN0 RN0 RN0 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm R KOhm R 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm R0 0KOhm R R RN0 RN0 RN0 RN0 +VU T_O_# EXTT_NI_RV_PH PU_ELET# INT_PIRQ# MP_PWR_TRL# INT_PIRQ# INT_PIRQ# INT_PIRQ# PU_PWM_ELET# EXTT_NI_RV0_PH PU_HOL_RT#_R PU_PWR_EN R U0 V Y N NLV0KR R0 0KOhm N R 0 U_E#,0,,, PU_HOL_RT# PU_PWR_EN PU_PWR_EN 0 0 U_RX_N U_RX_N U_RX_P U_RX_P U_TX_N U_TX_N U_TX_P U_TX_P T_O_# PU_PWR_EN PLT_RT# LK_PI_F LK_KPI_PH LK_EU N T0 Y RV RV E TP 0 T TP RV E F TP RV J TP TP E0 TP0 F TP U_PN0 TP UP0N V U_PP0 TP UP0P U_PN TP UPN U U_PP TP UPP Y0 TP UPN U TP UPP Y U_PN TP UPN K V U_PP TP UPP H W0 U_PN UPN E T TP0 U_PP UPP T U_PN UPN U_PP UPP UPN INT_PIRQ# UPP K0 U_PN INT_PIRQ# PIRQ# UPN N T K U_PP INT_PIRQ# PIRQ# UPP M T H U_PN INT_PIRQ# PIRQ# UPN L0 U_PP PIRQ# UPP K0 U_PN P0 PU_HOL_RT#_R UPN 0 R00 U_PP T0 PU_ELET# REQ#/PIO0 UPP E0 U_PN0 T REQ#/PIO UP0N 0 E0 U_PP0 REQ#/PIO UP0P 0 T U_PN _IT UPN L U_PP T0 PU_PWM_ELET# NT#/PIO UPP K E U_PN TP_OVR NT#/PIO UPN T F U_PP NT#/PIO UPP E T OUR_POINT_E UPN R0 KOhm MP_PWR_TRL# UPP T_O_# PIRQE#/PIO 0 EXTT_NI_RV0_PH PIRQF#/PIO EXTT_NI_RV_PH PIRQ#/PIO URI# PIRQH#/PIO T0 Ohm Ohm Ohm T0 0 0PF/0V PI_PME# PLT_RT# :R0=00ohm for E. R0 R0 R LKOUT_PI0_R LK_PI_F_R LK_KPI_PH_R LK_EU_R LK R R.0 00 J H J H H K K N0 H H M M Y K L M0 Y K0 H H J K H0 U00E TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP PME# PLTRT# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI 0V00000000 RV PI MHz U RV RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV URI O0#/PIO O#/PIO0 O#/PIO O#/PIO O#/PIO O#/PIO O#/PIO0 O#/PIO Y V U T0 U T T T Y T V V E F V V0 T K0 L NV_ROMP U_I O0#/PIO O#/PIO0 O#/PIO O#/PIO O#/PIO O#/PIO O#/PIO0 O#/PIO +V +VU_OR +V +.V R R % % +V,,,,, +VU_OR 0,,,, +V,,, +.V,,,, P0.Ohm.Ohm N N U_PN0 U_PP0 U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 Place within 00 mils of PH R00 +VU_OR U_O0# U PORT U P00 U P0 U P0 U P0 U P0 U P0 U P0 U P0 U P0 U P0 U P U P U P External.0/.0 External.0/.0 External.0 WiFi amera External.0 T PIE/mT N PU_PWR_EN is active high P0 R00 U_O# +V _IT0,_IT : oot IO trap oot IO trap _IT _IT0 oot IO Location 0 0 LP TP_OVR: swap override trap/ Top-lock swap override jumper Low=Enabled swap override/ Top-lock swap override PLT_RT# U0 V N Y NLV0KR UF_PLT_RT# 0,,0,,,,,0 0 Reserved (NN) 0 Reserved PI (PH) High=efault N R R 0KOhm ampled on rising edge of PWROK. N 0 _IT0 _IT0 R KOhm TP_OVR R KOhm _IT R KOhm N N PETRON OMPUTER IN PH()_PI,NVRM,U Wing_heng HR/R Friday, February 0, 0 ate: heet of.0

+V +V,,,0,,,,,,,,0,,,,0,,,,,,,0,,,,, +VU +VU,,,,,0,,,,, P_I P_I0 +VU_OR +VU_OR 0,,,, L L L H R.0 MP H L dd PH_PIO0_R. ENOR_INT_PH R0 0 PH_PIO0_R PIO T U00F MUY#/PIO0 TH/PIO TH/PIO TH/PIO 0 R %.KOhm N T_O_PWRT 0 +V +V elete I_EN#. ep_on# ep_on# T0 PU_HP_INTR# H E TH/PIO TH/PIO TH/PIO0 TH/PIO 0 R R % %.KOhm.KOhm +V +V dd PM_LNPHY_EN, U0_EXT_MI# WLN_RT#_PH P0 R00 U0_EXT_MI# PM_LNPHY_EN 0 PIO LN_PHY_PWR_TRL/PIO need close to E R 0KOhm R 0KOhm R 0KOhm R 0KOhm N N Frank 00 Modify P_I P_I0 P_I dd HOT_LERT#_R. dd T_ET#_R. PU_PWROK has 00 ms software delay, no hardware delay requirement Reserve PH_PIO dd PLL_OVR_EN. dd PT_PWR_EN#_R. dd T_O_PRNT#_R and FI_OVRVLT.,, 0 0, EXT_MI# PU_PWROK WLN_LE T0 T_O_PRNT# PU_PWROK LN_LPWR P0 P0 P0 T0 R00 R00 R00 HOT_LERT#_R T_ET# WLN_LE PH_PIO PIO WLN_ON_R TP_PI# T_PWR_EN#_R T_O_PRNT#_RV FI_OVRVLT P_I0 P_I U 0 T E E P K K M N M PIO TP/PIO TH0/PIO LOK/PIO PIO/MEM_LE PIO PIO TP_PI#/PIO PIO TP/PIO TP/PIO LO/PIO TOUT0/PIO PIO PU/MI 0TE PEI RIN# PROPWR THRMTRIP# INIT_V# F_TV T_V T_V T_V T_V N_ P U P Y Y0 T Y H K H0 K0 P H_PEI_R PM_THRMTRIP# INIT_V# NV_LE N R % R T0 R0 KOhm T ignal isable uideline T_V[:] should pull down to N esign uide 0. () Ohm R R0 R Ohm.KOhm 0TE 0 H_PEI H_PEI_E 0 RIN# 0 H_PUPWR H_THRMTRIP#, +VP H_N_IV# +.V T_ON_PH V TOUT/PIO Vss_NTF +VU_OR dd RIT_TEMP_REP#_R. 0 PH_LERT# T0 P0 R00 RIT_TEMP_REP#_R T_LE V TP/PIO PIO Vss_NTF Vss_NTF Vss_NTF H H EXT_MI# U0_EXT_MI# PM_LNPHY_EN PH_PIO R R R R 0KOhm R.0 mount R for LN_LPWR 0 /nimt KOhm 0KOhm 0KOhm +V R.0 0 Intel omments R.0 00, WLN_ON +V R 0KOhm +V R0 0KOhm Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF NTF Vss_NTF Vss_NTF0 Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF J J J J J J RIN# has pull high at E side PU_HP_INTR# PH_LERT# PU_PWROK ep_on# R R R R 0KOhm 0KOhm 0KOhm 0KOhm R.0 0 Q0 UMKN Q0 UMKN WLN_ON_R E E F F Vss_NTF0 Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF0 Vss_NTF Vss_NTF E E F F Unused PIO ENOR_INT_PH R 0KOhm N N OUR_POINT_E 0V00000000 PIO R 0KOhm R.0 0 TP_PI# T_ET# PIO #0 hecklist R R R 0KOhm 0KOhm 0KOhm N +V +V R % KOhm FI_OVRVLT R FI TERMINTION VOLTE OVERRIE - PIO (FI_OVRVLT) LOW - TX, RX terminated to same voltage ( ouplong Mode) EFULT R0 % 00KOhm T_O_PRNT#_R 00KOhm N R.0 REMOVE PU_PWROK schematic 00 PU_PWROK R0 0KOhm MI TERMINTION VOLTE OVERRIE - PIO (T_O_PRNT#) LOW - TX, RX terminated to same voltage ( ouplong Mode) EFULT N WLN_ON_R R KOhm PLL ON IE VR ENLE NHIH - ILE (EFULT) LOW - ENLE R.0 hange net name for single net. Joyoung 0 PETRON OMPUTER IN PH()_PU,PIO,MI Wing_heng HR/R Friday, February 0, 0 ate: heet of.0

H 0 0 E E F0 F F F F F F F F F F F F F F F H H H H H0 H H H J J J J J K K U00H V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V K K K K K L L L L L L L L L L L L M M M M M M M M N N N N P P P P0 P P P P P P R R T T T T T T T0 T T T T T T U U0 V V0 V V0 V V V V W W W W W W W W W W0 W V Y Y Y +VTT_PH_OR +VTT_PH_VIO R0 +VTT_PH_V +VTT_PH_VIO +VTT_PH_OR +VTT_PH_VIO P0 0 0UF/0V N P0 +VTT_PH_V_EXP +V_V_ +VTT_PH_VPLL_FI +VTT_PH_VPLL_FI 0 0UF/0V R00 L0 0 UF/.V N 0 UF/.V N +VTT_PH_VPLL_EXP R00 kohm/00mhz +VTT_PH_VPLL_EXP R.0 0 Intel omments 0 UF/.V P0 R00 R.0 0 Intel omments 0 UF/.V N N +VTT_PH_VPLL_EXP.0/=m N Total pin (E R.) Joyoung0 0 UF/.V N +V_V m/=.m H change to m total pin (E R.) Vcc Joyoung0 0.UF/V m/=.m +VFI_VRM P Joyoung0 VccVRM change to m total pin (E R.) +VIO_PU_V_MI UF/.V 0 0UF/0V. N N VccIO.0/*=. N Total pin (E R.) Joyoung0 VccIO 0 UF/.V.0/=m P Total pin (E R.) Joyoung0 m/=m F F J J J J J J N N N P P P P T N N U0 U00 Vccore Vccore Vccore Vccore Vccore Vccore Vccore Vccore Vccore Vccore0 Vccore Vccore Vccore Vccore Vccore Vccore Vccore VccIO VccPLLEXP VccIO VccIO VccIO VccIO VccIO VccIO VccIO0 VccIO VccIO VccIO VccFIPLL VccIO VccMI POWER V ORE VIO FI OUR_POINT_E RT LV FT / PI MI HVMO Vcc Vss VccLV VssLV VccTX_LV VccTX_LV VccTX_LV VccTX_LV Vcc U m N m N m/=.m T +VFI_VRM Joyoung0VccVRM change to m total pin (E R.) +VIO_PU_V_MI VccFTERM VccFTERM 0V00000000 U K K M M P P V J R. m/=m 0m J (E R.) Joyoung0 V 0m (E R.) Joyoung0 0.UF/V 0m (E R.) Joyoung0 N N N N R.0 0 UF/.V N N N +V_V_IO +VM_VPPI +V N N +VTT_PH_OR_VLKMI 0 0UF/0V +V_NVRM_VPNN 0.UF/V 0.0UF/0V V m/*pin=m Vcc change to m total pin (E R.) Joyoung0 VccMI VccFTERM VccFTERM VccPI T0 m VcclkMI (E R.) Joyoung0 0.0UF/0V kohm/00mhz R P0 P0 R R 0.0UF/0V 0.UF/V 0.UF/V N +V_V_LV +.V_VTX_LV P0 L0 UF/.V R00 R00 UF/.V +VP +VTT_PH_OR +.V +V +VM_PI L0 kohm/00mhz P0 R00 kohm/00mhz R00 L0 +V_V_ +V +V +.V N OUR_POINT_E 0V00000000 N N R.0 0 +.0V +VTT_PH_OR +VTT_PH_V JP0 JP0.=0m+.+.. MM_OPEN_MIL MM_OPEN_MIL +VTT_PH_VIO 0-hange JP(MM_OPEN_MIL) JP0. MM_OPEN_MIL R.0 fellow everest 0 +VTT_PH_OR JP0 MM_OPEN_MM +.V +VFI_VRM P0 0m R00 VVRM use +.V in mobile H_YN should pull high to +VU +VTT_PH_VIO +VTT_PH_OR +.0V +.V +VFI_VRM +V +V_V_ +VM_PI +.V +VP R.0 elete +VTT_PH_V +VTT_PH_VPLL_EXP +VTT_PH_VPLL_EXP +VTT_PH_VPLL_FI +VTT_PH_VPLL_FI +V_V +V_V_IO +V +V_V_LV +VM_VPPI +V_NVRM_VPNN +.V_VTX_LV +VIO_PU_V_MI +VTT_PH_OR_VLKMI +VTT_PH_VIO 0, +VTT_PH_OR, +.0V,,0,, +.V,,, +VFI_VRM +V,,,0,,,,,,,,0,,,,0,,,,,,,0,,,,, +V_V_ +VM_PI +.V,,, +VP,,,,,,,,, PETRON OMPUTER IN PH()_POWER,N Wing_heng HR/R Friday, February 0, 0 ate: heet of.0

PH_VW +VTT_PH_VLK +VU_OR_VPU +VTT_PH_V PL +VPLL_PY_PH +VPW +VU +VRTEXT +VIFFLK +VU_OR_VU +VUPLL +V_UU PH_V PH_V PH_V 0 VT +V.0VM_OR_VU +V,,,0,,,,,,,,0,,,,0,,,,,,,0,,,,, +.0V,,0,, +VTT_PH_VIO 0, +VTT_PH_OR, +VU,,,,0,,,,, +V_RT 0, +VU,0,0,,,,,,,,, +V 0,,,,,,,0,,,0,, +VU_OR 0,,,, +VP,,,,,,,,, +V 0,0,,,,,, +VFI_VRM +V_V_ +VIFFLKN +.0VM_OR +VTT_PU_VPPU +V_RT N N N N N N N N N N N N +VTT_PH_OR_VPLL_T +V_PH_VREF +VTT_PH_VIO N +VTT_PH_OR +V N N +VU_OR N N N +.0VM_OR N +VU_OR +VU_OR +V +VU_PH_VREFU +VTT_PH_OR N N +VTT_PH_V PL +VTT_PH_V PL N +VTT_PH_OR N +.0VM_OR +VU_OR_VPZU +VU_OR +V +.0V +VTT_PH_VIO +VTT_PH_OR +VU +V_RT +VU +V +VU +VU_OR +VU +VU_OR +VU_OR +V +VU_OR N N N +V_V_LKF +V_V_LKF +VPLL_PY N +VFI_VRM N +VTT_PH_V PL +VTT_PH_V PL N N +VTT_PH_OR N +VTT_PH_OR +VIFFLKN +VTT_PH_OR_V +.0VM_OR N +VTT_PH_VUORE +VU_OR N N N +VU_OR +VU_OR_VPU +VU_OR_VPU N N +V_VPORE +V_VPPI N +VTT_PH_VIO_T +VFI_VRM +VTT_PH_VIO_V_T N +VP +VP +V +V_V_ +V_V_ +V_V_ +V_V_ +V_V_ +VTT_PH_OR +VTT_PH_VIO +VTT_PH_VIO +VTT_PH_VIO +VTT_PH_VIO +VTT_PH_VIO +V +V_V_ +VFI_VRM +VIFFLKN N N +.0V N N N N ate: heet of Friday, February 0, 0 PETRON OMPUTER IN PH()_POWER,N.0 HR/R Wing_heng ate: heet of Friday, February 0, 0 PETRON OMPUTER IN PH()_POWER,N.0 HR/R Wing_heng ate: heet of Friday, February 0, 0 PETRON OMPUTER IN PH()_POWER,N.0 HR/R Wing_heng m.0 m u 0mil trace m m m m m m 0m 0m m m m/*pin=m m/=.m m/=.m m/=.m.0/=m.0/=m.0/*= m.0/=m.0/*= m.0/*= m 0.0/*0= m 0.0/*= m m/=.m m/=.m 00m/=m 00m/*=m R.0 fellow everest 0 R 0 R 0 P0 R00 P0 R00 0.UF/V 0.UF/V 0 V/0. 0 V/0. P0 R00 P0 R00 UF/.V UF/.V 0 UF/.V 0 UF/.V JP0 MM_OPEN_MM JP0 MM_OPEN_MM R0 R0 P0 R00 P0 R00 R0 R0 UF/.V UF/.V P R00 P R00 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0 0UF/0V 0 0UF/0V 0.UF/V 0.UF/V UF/.V UF/.V 0.UF/V 0.UF/V P0 R00 P0 R00 JP0 MM_OPEN_MM JP0 MM_OPEN_MM P R00 P R00 L0 kohm/00mhz L0 kohm/00mhz 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0.UF/V 0.UF/V P0 R00 P0 R00 L0 kohm/00mhz L0 kohm/00mhz UF/.V /HR UF/.V /HR R0 R0 0 UF/.V /HR 0 UF/.V /HR JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL UF/.V UF/.V P0 R00 P0 R00 UF/.V UF/.V R0 R0 UF/.V UF/.V 0.UF/V 0.UF/V P0 R00 P0 R00 0.UF/V 0.UF/V POWER T U lock and Miscellaneous H PU RT PI/PIO/LP MI U00J OUR_POINT_E POWER T U lock and Miscellaneous H PU RT PI/PIO/LP MI U00J OUR_POINT_E cpusyp V VccW VccW VccW VccW VccW VccusH P Vccus P VccIO T VccIO VccW VccW VccW VccW0 VccW VccW VREF P Vcc T VccRT Vccus V Vccus V Vccus T Vccus T VccIO VccPLL F VccIFFLKN F VREF_us M VccIO cpus T Vcc VccPLL VccVRM Y Vcclk cprt N VccW VccIFFLKN F VccIO F cpt V VccIO F VccW T VccW V VccW T Vcc Vcc W Vccus N0 Vccus N Vccus P0 Vccus 0 P VccIO N VccIO P VccIO P VccIO0 T V_PRO_IO J VccIO T VccIFFLKN VccW VccW W VccW W VccW W VccW W VccW W VccW W VccW0 W VccIO F VccVRM F VccIO H VccIO H Vcc J VccPLLT K cpus L VccIO L cpus N Vccus N VccPLLMI H cpus V VccW_ T Vcc T 0UF/0V 0UF/0V P0 R00 P0 R00 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0.UF/V 0.UF/V L0 kohm/00mhz L0 kohm/00mhz UF/.V UF/.V P0 R00 P0 R00 0 UF/V 0 UF/V 0 0.UF/V 0 0.UF/V L0 kohm/00mhz L0 kohm/00mhz UF/.V UF/.V P0 R00 P0 R00 0.UF/V 0.UF/V R0 R0 U00I OUR_POINT_E 0V00000000 U00I OUR_POINT_E 0V00000000 V Y V0 Y V Y V Y V V V V V V V V0 V V V V 0 V V V V 0 V0 V V V V V V V V V V0 V 0 V V V V V E V E V E0 V F0 V00 F V0 F V0 F0 V0 F V0 F V0 F V0 F V0 V0 F0 V0 F V0 F0 V F V V V V V V H V H V H V0 H V H V H V H V H V H V H V H V V0 V V V V V V 0 V V K V L V L V L0 V L V L V0 L V L V M V P V M V M V M V M0 V M V M V0 M V M V M V M V M V N V P0 V P V P V0 T V P0 V P V P V P V R V R V T V T V T V00 T V0 W V0 T V0 T V0 T V0 V V0 V V0 V V0 V V0 V V0 V V V V V V V V V V W V W V V V0 V V E V E V V 0 V V V V V0 H V H V W V W V W V0 Y V Y V Y V Y V Y V Y V V N V J V N V H V H V H V H0 V H V H V F V K V K V H V0 K V K V V0 V E0 V V V H V T V V V V P V F V H0 V0 M V P V P V E V V V J 0.UF/V 0.UF/V R0 R0 L0 kohm/00mhz L0 kohm/00mhz P R00 P R00 UF/.V UF/.V UF/.V UF/.V 0.UF/.V 0.UF/.V P R00 P R00 R 0 R 0 UF/.V UF/.V 0 0.UF/V 0 0.UF/V UF/.V UF/.V JP0 MM_OPEN_MM JP0 MM_OPEN_MM 0 0UF/0V 0 0UF/0V UF/V UF/V UF/.V UF/.V 0.UF/V 0.UF/V UF/.V UF/.V P R00 P R00 0 V/0. 0 V/0.