6.823 2002 180 22 6 : 6 Part A: ( 1 4) 20 Part B: ( 5 7) 16 Part C: ( 8 12) 24 Part D: ( 13 20) 24 Part E: ( 21 24) 31 Part F: ( 25 27) 16 Part G: ( 28 30) 12 Part H: ( 31 37) 31 : 180
Part A: 20 DLX 14 128 DLXISA 32 32 1 4 2 4 3 6 A B C D E F 2 / 22 4 6 MOVZ DLXISA MOVZ MOVZ Rd,Rs1,Rs2; if (Rs2 = = 0) then Rd <- Rs1 Rs2 Rs1 Rd MOVZ R R-type instruction Part A MOVZ 3 / 22
Part B Cache 16 Cache Cache 2 k Cache 2 L 2 w Cache 2 b 2 32 2 32 5 (6 ) 6 (6 ) k L b w Cache 7 4 Cache 4 / 22
Part C: 24 Ben Bitdiddle DLX IF ID EX MA - EX1 8 3 BEQZ BNEZ 9 8 Ben ID1 BHT 5 / 22
10 3 JR 11 4 Louis Reasoner Ben BHT IF1 6 / 22 12 6 Ben BHT ID1 PS4 0/1 ( 0101010 ) R3 32 R1 0 R2 0 R2 PS4 2 L13-11 0X 1X
PS4 BHT Ben BHT 00 BHT Part D: 24 7 / 22 13 3 14 3
15 3 16 3 8 / 22 17 3 18 3 19 3
20 3 9 / 22 Part E: Cache 31 PS6-3 Cache Ben Cache Cache - Cache PS6 C- H- H- PS6 PS6 FIFO FIFO 21 5 Alyssa Ben 10 / 22
22 16 Ben k 1 Cache 2 11 / 22
23 5 Ben Alyssa 24 (5 ) PS6 FIFO FIFO
12 / 22 Part F: I 16 17-18 Dekker c1 c2 turn c1 c2 0 1 DLX DLX
13 / 22 25 2 Dekker PSO Dekker PSO A. B. C. D. 26 8 14 / 22
27 6 PSO MEMBAR MEMBAR MEMBAR MEMBAR MEMBAR Dekker PSO 15 / 22 part G: II 12 N Lamport's Bakery
28 4 16 / 22 29 2 Lamport's Bakery A. B. C. D. 30 6
1 2 17 / 22 Part H 31 DLX DLX SEQ 1 BNEZ 2 18 / 22
31 4 Cache 100 cpu 32 4 CDC 6600 PPUs L23-7 N N 19 / 22 33 4 34 5 20 / 22
35 5 Cache 31 Cache Cache 100 8 4 Cache Cache 50% 36 4 31 Cache 21 / 22 37 5 Cache Cache 50% Cache 22 / 22