PC Base Standalone LA-100 Q&A
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- SCOPE - - LA
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- ( Embedded )
( Skew )
- Data In External CLK Internal CLK Display Buffer ASIC CPU Memory Trigger Level
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- Clock BUS Timing State
- ( Timing )
- ( Timing ) - LA LA LA
- ( Timing ) - Data LA LA
- (State) Signal Probe
- (State) D (Hold Time) CLK (Setup Time)
- ( Event ) - ( Level ) - ( Examination ) - -
- Pattern trigger : - Ch 1 Ch 2 Ch 1 1 Ch 2 0
- Edge trigger : ( ) - Logic H or Logic L TTL Vt 1.5V. 1.5V H ; 1.5V L
- - Data Input Clock D CLK Q Data Output Data Input Clock D Q Data Output CLK
- Data Input D Q Data Output Clock CLK Data Input Clock Data Output
- ( Deeper memory )
- -A: End of memory All pre-trigger -B: Center of memory ½, ½ -C: Beginning of memory All post-trigger PRE-Trigger data Trigger point Post-Trigger data A B C
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- (Glitch )
- (Skew ) Ch 1 Ch 2 Probe Ch 1 Ch 2 Skew
- PC Base Standalone Pc Base Windows Standalone (Parallel Port...) PC Base PC
- PC Base Standalone Pc Base Standalone
- LA-100 1673G TLA5201 1683A Timing 200MHz 200/500MHz (full/half channels) 2GHz 400/800MHz (full/half channels) State 100MHz 150MHz 235MHz 200MHz Channel 32 34 34 34 Memory 64K~1M 64K/128K (full/half channel) 512K/1M (full/half channel) 512K/1M (full/half channel) Built-in display 5.7inch,320*240,Color Color 10.4inch,1024*768,Color 12.1inch,Color Channel-to-Channel Skew 2ns (typical) 2ns (typical) 900ps (typical) <1.5ns (typical) Maximum Input Voltage +/-30V peak +/-40V peak +/-15V peak L*D*H (mm) 310*90*150 440*367*205 438*288*285 442.7*384.53*256.71 Operation Temperature ( C) 0 ~ +45 +5 ~ +50 +5 ~ +50
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- Timing State Clock BUS Clock Clock
Q&A