EFM8 Busy Bee 系列 EFM8BB2 数据表 EFM8BB2,Busy Bee MCU 系列的一部分, 是一款在小封装上带有全面功能集的多用途 8 位微控制器 这些设备通过在小的封装上集成先进的模拟和增强型高速通信外设为用户提供高价值, 使得它们成为空间受限应用的理想选择 由于采用了高效

EFM8 Busy Bee 系列 EFM8BB2 数据表 EFM8BB2,Busy Bee MCU 系列的一部分, 是一款在小封装上带有全面功能集的多用途 8 位微控制器 这些设备通过在小的封装上集成先进的模拟和增强型高速通信外设为用户提供高价值, 使得它们成为空间受限应用的理想选择 由于采用了高效的 8051 核心 增强型脉冲宽度调制和高精度模拟,EFM8BB2 系列也是嵌入式应用的最佳选择 EFM8BB2 应用包括以下 : 电机控制 消费电子 传感器控制器 医疗器械 照明系统 高速通信集线器 主要特点 管线化 8 位 C8051 核心,50 MHz 最高工作频率 最多 22 组多功能 5 V 容限 I/O 引脚 一个 12 位模数转换器 (ADC) 两个低电流模拟比较器, 内置 DAC 作为参考输入 集成式温度传感器 3 通道 PWM / PCA, 配有硬件停用 / 安全状态的特殊功能 五个 16 位定时器 两个 UART SPI 主 / 从 SMBus/I2C 和从 I2C 便于引脚映射的优先级交叉开关 Core / Memory Clock Management Energy Management CIP-51 8051 Core (50 MHz) External CMOS Oscillator High Frequency 49 MHz RC Oscillator Internal LDO Regulator Power-On Reset Flash Program Memory (16 KB) RAM Memory (2304 bytes) Debug Interface with C2 Low Frequency RC Oscillator High Frequency 24.5 MHz RC Oscillator Brown-Out Detector 5 V-to 3.3 V LDO Regulator 8-bit SFR bus Serial Interfaces I/O Ports Timers and Triggers Analog Interfaces Security 2 x UART SPI External Interrupts Pin Reset Timer 0/1/2 PCA/PWM ADC Comparator 0 16-bit CRC I 2 C / SMBus High-Speed I2C Slave General Purpose I/O Pin Wakeup Watchdog Timer Timer 3/4 Comparator 1 Internal Voltage Reference Lowest power mode with peripheral operational: Normal Idle Suspend Snooze Shutdown silabs.com Smart. Connected. Energy-friendly. Rev. 1.4

EFM8BB2 数据表功能列表 1. 功能列表 EFM8BB2 突出功能如下所列 内核 : 流水线式 CIP-51 内核 与标准 8051 指令集完全兼容 70% 指令的执行时间为 1-2 系统时钟周期 50 MHz 最高工作频率 内存 : 最高 16 KB 闪存, 可在系统内对固件重新编程, 其中包括 64 字节扇区的 1 KB 和 512 字节扇区的 15 KB 最高 2304 字节 RAM( 包括 256 字节标准 8051 RAM 和 2048 字节上 XRAM) 电源 : 5 V 输入 LDO 稳压器 用于 CPU 内核电压的内部 LDO 稳压器 加电复位电路和掉电检测器 I/O: 最多共 22 组多功能 I/O 引脚 : 偏压下所有引脚耐受 5 V 电压 用于外围路由的灵活的外围设备交叉开关 5 ma 源电流,12.5 ma 吸收器允许直接驱动 LED 时钟源 : 内部 49 MHz 振荡器, 精度 ±1.5% 内部 24.5 MHz 振荡器, 精度 ±2% 内部 80 khz 低频振荡器 外部 CMOS 时钟选项 定时器 / 计数器和 PWM: 3 通道可编程计数器阵列 (PCA), 支持 PWM 捕获 / 比较和频率输出模式 5 个 16 位通用定时器 独立的监视程序定时器, 由低频振荡器设定时钟频率 通信和数字外围设备 : 2 个 UART, 最高 3 兆波特 SPI 主 / 从, 最高 12 Mbps SMBus /I2C 主 / 从, 最高 400 kbps I 2 C 高速从, 最高 3.4 Mbps 16 位 CRC 单位, 支持 256 字节边界内闪存自动 CRC 模拟 : 12 位 AD 转换器 (ADC) 2 个带有可调节参考的低电流模拟比较器 片上非侵入式调试 全内存和寄存器检查 四个硬件断点 单步执行 预装 UART 引导装载程序 -40 至 85 ºC 或 -40 至 125 ºC 温度范围 可用汽车级 ( 需要 PPAP) 2.2 至 3.6 V 或 3.0 至 5.25 V 单电源 QFN28 QSOP24 和 QFN20 封装 借助芯片上加电复位 电源电压监控器 监视程序定时器和时钟振荡器,EFM8BB2 设备成为真正独立的系统单芯片解决方案 闪存是可编程内部电路, 提供非易失性数据存储以及支持固件的现场升级 片上调试接口 (C2) 允许使用安装在最终应用中的生产 MCU 进行非侵入式 ( 不使用片上资源 ) 全速 内部电路调试 此调试逻辑支持检查和修改存储器与寄存器 设置断点 单步执行以及运行和停止命令 进行调试时, 所有模拟和数字外围设备的功能都得到充分发挥 各设备的指定运行电压是 2.2 到 3.6 V( 或在 5 V 稳压器选项下最高 5.25 V) G 级和 I 设备均提供 28 引脚 QFN 20 引脚 QFN 和 24 引脚 QSOP 封装,A 级设备提供 28 引脚 QFN 和 20 引脚 QFN 封装 所有封装选项均符合无铅和 RoHS 要求 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 2

EFM8BB2 数据表订购信息 2. 订购信息 EFM8 BB2 2 F 16 G A QFN28 R Package Type Tape and Reel (Optional) Revision Temperature Grade G (-40 to +85), I (-40 to +125), A (-40 to +125, Automotive Grade) Flash Memory Size 16 KB Memory Type (Flash) Family Feature Set Busy Bee 2 Family Silicon Labs EFM8 Product Line Figure 2.1. EFM8BB2 部件编号 所有 EFM8B2 产品系列都具备以下功能 : 运行频率高达 50 MHz 的 CIP-51 内核 三种内部振荡器 (49 MHz 24.5 MHz 和 80 khz) SMBus I2C 从 SPI 2 个 UART 3 信道可编程计数器阵列 (PWM 时钟生成 捕获/ 比较 ) 5 个 16 位定时器 2 个模拟比较器 12 位 AD 转换器, 配有集成多路复用器 电压参考和温度传感器 16 位 CRC 单元 经过 AEC-Q100 认证 预装 UART 引导程序除了这些功能之外,EFM8BB2 系列中的各部件编号随产品系列不同具有不同的功能集 产品选择指南列出了各系列元件的可用功能 Table 2.1. Product Selection Guide Ordering Part Number Flash Memory (KB) RAM (Bytes) Digital Port I/Os (Total) ADC0 Channels Comparator 0 Inputs Comparator 1 Inputs Pb-free (RoHS Compliant) 5-to-3.3 V Regulator Temperature Range Package EFM8BB22F16G-C-QFN28 16 2304 22 20 10 12 Yes Yes -40 to +85 ºC QFN28 EFM8BB21F16G-C-QSOP24 16 2304 21 20 10 12 Yes -40 to +85 ºC QSOP24 EFM8BB21F16G-C-QFN20 16 2304 16 15 10 7 Yes -40 to +85 ºC QFN20 EFM8BB22F16I-C-QFN28 16 2304 22 20 10 12 Yes Yes -40 to +125 ºC QFN28 EFM8BB21F16I-C-QSOP24 16 2304 21 20 10 12 Yes -40 to +125 ºC QSOP24 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 3

EFM8BB2 数据表订购信息 Ordering Part Number Flash Memory (KB) RAM (Bytes) Digital Port I/Os (Total) ADC0 Channels Comparator 0 Inputs Comparator 1 Inputs Pb-free (RoHS Compliant) 5-to-3.3 V Regulator Temperature Range Package EFM8BB21F16I-C-QFN20 16 2304 16 15 10 7 Yes -40 to +125 ºC QFN20 EFM8BB22F16A-C-QFN28 16 2304 22 20 10 12 Yes Yes -40 to +125 ºC QFN28 EFM8BB21F16A-C-QFN20 16 2304 16 15 10 7 Yes -40 to +125 ºC QFN20 A 级 ( 即 EFM8BB21F16A-C-QFN20) 设备可获得全汽车质量生产现状, 包括 AEC-Q100 认证 国际材料数据系统 (IMDS) 注册和部件生产批准工艺 (PPAP) 文档 欲了解 PPAP 文档, 可利用已注册且经过 NDA 批准的用户账户登录 www.silabs.com 获取 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 4

目录 1. 功能列表................................. 2 2. 订购信息................................. 3 3. 系统概述................................. 7 3.1 介绍................................. 7 3.2 电源................................. 8 3.3 I/O................................. 8 3.4 时钟................................. 9 3.5 定时器 / 计数器和 PWM........................... 9 3.6 通信和其他数字外围设备......................... 10 3.7 模拟................................ 11 3.8 复位源............................... 12 3.9 调试................................ 12 3.10 引导装载程序............................ 13 4. 电气特性................................ 15 4.1 电气特性.............................. 15 4.1.1 建议的工作条件.......................... 15 4.1.2 功耗.............................16 4.1.3 复位和电源监控器......................... 19 4.1.4 闪存.............................19 4.1.5 电源管理定时..........................20 4.1.6 内部振荡器........................... 20 4.1.7 外部时钟输入..........................21 4.1.8 ADC.............................. 22 4.1.9 参考电压............................ 23 4.1.10 温度传感器........................... 24 4.1.11 1.8 V 内部 LDO 稳压器......................24 4.1.12 5 V 电压稳压器......................... 24 4.1.13 比较器............................25 4.1.14 端口 I/O...........................26 4.2 热能条件.............................. 26 4.3 绝对最大额定值............................ 27 4.4 典型性能曲线............................. 28 5. 典型连接图............................... 32 5.1 电源................................ 32 5.2 调试................................ 33 5.3 其他连接.............................. 33 6. 引脚定义................................ 34 6.1 EFM8BB2x-QFN28 引脚定义........................ 34 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 5

6.2 EFM8BB2x-QSOP24 引脚定义........................ 38 6.3 EFM8BB2x-QFN20 引脚定义........................ 41 7. QFN28 封装规格.............................44 7.1 QFN28 封装尺寸............................ 44 7.2 QFN28 PCB 焊盘布局.......................... 46 7.3 QFN28 封装标识............................ 47 8. QSOP24 封装规格............................. 48 8.1 QSOP24 封装尺寸...........................48 8.2 QSOP24 PCB 焊盘布局.......................... 50 8.3 QSOP24 封装标识...........................51 9. QFN20 封装规格.............................52 9.1 QFN20 封装尺寸............................ 52 9.2 QFN20 PCB 焊盘布局.......................... 54 9.3 QFN20 封装标识............................ 55 10. 版本历史...............................56 10.2 修订版 1.31............................. 56 10.3 修订版 1.3............................. 56 10.5 版本 1.1.............................. 56 10.6 版本 1.0.............................. 56 10.7 版本 0.3.............................. 56 10.8 版本 0.2.............................. 56 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 6

EFM8BB2 数据表系统概述 3. 系统概述 3.1 介绍 C2CK/RSTb C2D Debug / Programming Hardware Port I/O Configuration VDD VREGIN Power-On Reset Supply Monitor Reset Power Net Voltage Regulators CIP-51 8051 Controller Core 16 KB ISP Flash Program Memory 256 Byte SRAM 2048 Byte XRAM Digital Peripherals UART0 UART1 Timers 0, 1, 2, 3, 4 3-ch PCA I2C Slave I2C / SMBus SPI Priority Crossbar Decoder Port 0 Drivers Port 1 Drivers P0.n P1.n GND Independent Watchdog Timer SYSCLK SFR Bus CRC Crossbar Control Port 2 Drivers P2.n System Clock Configuration 49 MHz 1.5% Oscillator VDD Analog Peripherals Internal Reference VREF Port 3 Drivers P3.n 24.5 MHz 2% Oscillator Low-Freq. Oscillator 12/10 bit ADC AMUX VDD Temp Sensor EXTCLK CMOS Oscillator Input + - - 2 Comparators Figure 3.1. EFM8BB2 方框图详情 本部分描述的是较高水平的 EFM8BB2 产品系列 欲了解关于各个模块的更多信息, 包括寄存器定义, 请参见 EFM8BB2 参考手册 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 7

EFM8BB2 数据表系统概述 3.2 电源 所有内部电路由 VDD 供电引脚供电 外部 I/O 引脚由 VIO 电源电压供电 ( 或设备上无独立 VIO 连接的 VDD), 大多数内部电路由片上 LDO 调节器供电 根据需要启用 / 禁用各个外围设备可以控制设备功耗 每个模拟外围设备在不使用时都可以禁用, 从而置于低功耗模式 在不使用数字外围设备 ( 如定时器或串行总线 ) 时, 时钟将关闭且消耗较少电量 Table 3.1. Power Modes Power Mode Details Mode Entry Wake-Up Sources Normal Core and all peripherals clocked and fully operational Idle Core halted Set IDLE bit in PCON0 Any interrupt All peripherals clocked and fully operational Code resumes execution on wake event Suspend Core and peripheral clocks halted HFOSC0 and HFOSC1 oscillators stopped Regulators in normal bias mode for fast wake Timer 3 and 4 may clock from LFOSC0 1. Switch SYSCLK to HFOSC0 2. Set SUSPEND bit in PCON1 Timer 4 Event SPI0 Activity I2C0 Slave Activity Port Match Event Code resumes execution on wake event Comparator 0 Falling Edge Stop All internal power nets shut down 5 V regulator remains active (if enabled) Internal 1.8 V LDO on Pins retain state 1. Clear STOPCF bit in REG0CN 2. Set STOP bit in PCON0 Any reset source Exit on any reset source Snooze Core and peripheral clocks halted HFOSC0 and HFOSC1 oscillators stopped Regulators in low bias current mode for energy savings Timer 3 and 4 may clock from LFOSC0 Code resumes execution on wake event 1. Switch SYSCLK to HFOSC0 2. Set SNOOZE bit in PCON1 Timer 4 Event SPI0 Activity I2C0 Slave Activity Port Match Event Comparator 0 Falling Edge Shutdown All internal power nets shut down 5 V regulator remains active (if enabled) Internal 1.8 V LDO off to save energy Pins retain state 1. Set STOPCF bit in REG0CN 2. Set STOP bit in PCON0 RSTb pin reset Power-on reset Exit on pin or power-on reset 3.3 I/O 数字和模拟资源可以通过设备的多功能 I/O 引脚来实现外部调用 端口引脚 P0.0-P2.3 可以被定义为通用 I/O (GPIO), 通过交叉开关或专用信道被分配至其中一个内部数字资源, 或者被分配至模拟功能 端口引脚 P3.0 和 P3.1 可被用作 GPIO 此外,C2 接口数据信号 (C2D) 可与 P3.0 共享 端口控制模块具备以下功能 : 最多 22 个多功能 I/O 引脚, 支持数字和模拟功能 用于数字外围设备分配的灵活优先级交叉开关译码器 每个端口配有两个驱动强度设置 配有专用中断向量 (INT0 和 INT1) 的两个直接引脚中断源 最多 20 个配有共用中断向量 ( 端口匹配 ) 的直接引脚中断源 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 8

EFM8BB2 数据表系统概述 3.4 时钟 CPU 内核和外围设备子系统可以按照内部和外部振荡器资源来设定时钟 默认情况下, 系统时钟运行的情况为 :24.5 MHz 振荡器 8 分频 时钟控制系统具备以下功能 : 为核心和外围设备提供时钟 24.5 MHz 内部振荡器 (LPOSC0), 随电源和温度变化, 精度为 ±2% 49 MHz 内部振荡器 (HFOSC1), 随电源和温度变化, 精度为 ±1.5% 80 kh 低频振荡器 (LFOSC0) 外部 CMOS 时钟输入 (EXTCLK) 时钟分频器具有八个设置, 可实现灵活的时钟调整 : 将所选的时钟源分频为 :1 2 4 8 16 32 64 或 128 HFOSC0 和 HFOSC1 包括更加灵活的 1.5x 预分频器 3.5 定时器 / 计数器和 PWM 可编程计数器阵列 (PCA0) 可编程计数器阵列 (PCA) 提供增强的定时器和 PWM 功能的多个信道, 与标准计数器 / 定时器相比, 它需要较少的 CPU 干预 PCA 的各信道由一个专用的 16 位计数器 / 定时器和一个 16 位捕获 / 比较模块组成 计数器 / 定时器由具有灵活的外部和内部时钟选项的可编程时基驱动 每个捕获 / 比较模块可配置为在五种模式中的一种模式下独立运行 : 边沿触发捕获 软件定时器 高速输出 频率输出 或脉宽调制 (PWM) 输出 每个捕获 / 比较模块有其自己的关联 I/O 线 (CEXn), 这些线在启用时通过交叉开关连接到端口 I/O 16 位时基 可编程时钟分频器和时钟源选择 最多三个个独立配置的信道 8 9 10 11 和 16 位 PWM 模式 ( 中心或边沿对齐操作 ) 输出极性控制 频率输出模式 捕获上升沿 下降沿或任何沿 任意波形生成的比较功能 软件定时器 ( 内部比较 ) 模式 可以从比较器 0 接收硬件 停用 信号 定时器 ( 定时器 0 定时器 1 定时器 2 定时器 3 和定时器 4) 设备中包含几个计数器 / 定时器 : 两个是 16 位计数器 / 定时器与标准 8051 中的计数器 / 定时器兼容, 另外两个是 16 位自动重新加载定时器, 可用于定时外围设备或作为通用定时器使用 这些定时器可以用于测量时间间隔 对外部事件计数或生成周期性中断请求 定时器 0 和定时器 1 几乎完全相同, 有四种主要工作模式 其他定时器都提供带有自动重新加载和捕获功能的 16 位和分割 8 位定时器功能 定时器 0 和定时器 1 包括以下功能 : 标准 8051 定时器, 支持向后兼容固件和硬件 时钟源包括 SYSCLK SYSCLK(12 4 或 48 分频 ) 或外部时钟 (8 分频 ) 或外部引脚 8 位自动重新加载计数器 / 定时器模式 13 位计数器 / 定时器模式 16 位计数器 / 定时器模式 双 8 位计数器 / 定时器模式 ( 定时器 0) 定时器 2 定时器 3 和定时器 4 是包括以下功能的 16 位定时器 : 所有定时器的时钟源包括 SYSCLK SYSCLK 12 分频或外部时钟 8 分频 LFOSC0 8 分频在激活或挂起 / 贪睡功耗模式下可用于时钟定时器 3 和定时器 4 定时器 4 是低功耗唤醒源, 可与定时器 3 串接到一起 16 位自动重新加载定时器模式 双 8 位自动重新加载定时器模式 外部引脚捕获 LFOSC0 捕获 比较器 0 捕获 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 9

EFM8BB2 数据表系统概述 监视程序定时器 (WDT0) 设备包括在低频振荡器之外运行的可编程监视程序定时器 (WDT) WDT 溢出会迫使 MCU 处于复位状态 为了避免复位,WDT 必须在溢出之前通过应用软件重启 如果系统遇到阻止软件重启 WDT 的软件或硬件故障, 则 WDT 溢出并引起复位 复位之后,WDT 自动开启并以默认最大时间间隔运行 WDT 可以根据需要由系统软件禁用或锁定以避免意外禁用 锁定后, 在下一次系统复位之前将不能禁用 WDT RST 引脚的状态不受此复位的影响 监视程序定时器具有如下功能 : 可编程超时间隔 从低频振荡器运行 在系统复位之前锁定功能, 阻止任何修改 3.6 通信和其他数字外围设备 通用异步接收器 / 发射器 (UART0) UART0 是一个异步 全双工串口, 它提供标准 8051 UART 的模式 1 和 3 增强的波特率支持允许各种时钟源来生成标准波特率 接收数据缓冲机制允许 UART0 在软件尚未读取前一个数据字节的情况下开始接收第二个输入数据字节 UART 模块提供以下功能 : 异步发射和接收 波特率高达 SYSCLK/2( 发射 ) 或 SYSCLK/8( 接收 ) 8 位或 9 位数据 自动启动和停止发生 发射和接收端的单字节 FIFO 通用异步接收器 / 传输器 (UART1) UART1 是一个异步 全双工串行端口, 提供多种数据格式选择 它包括含一个 16 位定时器和可选预分频器的专用波特率发生器, 能生成宽范围的波特率 接收数据 FIFO 允许 UART1 在发生数据丢失或溢出之前接收多个字节 UART1 提供以下功能 : 异步发射和接收 专用波特率发生器支持高达 SYSCLK/2( 发射 ) 或 SYSCLK/8( 接收 ) 的波特率 5 6 7 8 或 9 位数据 自动起始位和停止位生成 自动奇偶生成和校验 四字节传输与接收 FIFO 自动波特率检测 LIN 间隔和同步场检测 CTS / RTS 硬件流控 串行外围设备接口 (SPI0) 串行外围设备接口 (SPI) 模块可以访问灵活的全双工同步串行总线 SPI 可作为主设备或从属设备在 3 线或 4 线模式下运行, 支持单个 SPI 总线上的多个主设备或从属设备 从选择 (NSS) 信号可配置为输入, 以在从模式中选择 SPI, 或在多主环境中禁用主模式操作, 以避免多个主设备试图同时进行数据传输时发生 SPI 总线冲突 NSS 可以在主模式中配置为固件控制的片选输出, 或被禁用以减少所需引脚的数量 在主模式中, 可以用其它通用端口 I/O 引脚选择多个从属设备 支持 3 或 4 线主机或从机模式 在主机或从机模式中支持高达 12 Mbps 的外部时钟频率 支持所有时钟相位和极性模式 8 位可编程时钟频率 ( 主 ) 可编程接收超时 ( 从 ) 四字节传输与接收 FIFO 可以在挂起或贪睡模式下运行并接收一个字节来唤醒 CPU 支持同一数据线上的多主机模式 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 10

EFM8BB2 数据表系统概述 系统管理总线 / I2C (SMB0) SMBus I/O 接口是一个二线的双向串行总线 SMBus 完全符合系统管理总线规范 1.1 版, 并与 I 2 C 串行总线兼容 SMBus 模块包括以下功能 : 标准 ( 最高 100 kbps) 和快速 (400 kbps) 传输速度 支持主 从和多主模式 多主模式的硬件同步和仲裁 时钟低延长 ( 时钟拉伸 ) 以连接到较快的主模式 硬件支持 7 位从模式和一般调用地址识别 固件支持 10 位从地址解码 能够阻止所有从状态 可编程数据建立 / 保持时间 发射和接收 FIFO ( 一字节 ), 以协助提高较快应用中的吞吐量 I2C 从机 (I2CSLAVE0) I2C 从接口是一个双线的双向串行总线, 兼容 I2C 总线规格 3.0 其可在高速模式 (HS 模式 ) 下最高以 3.4 Mbps 进行传输 固件可以写入 I2C 接口, 并且 I2C 接口可以自主控制数据的串行传输 在核心可能在 I2C 处理过程中临时无法传输字节或处理已接收的字节时, 此接口还支持时钟拉伸 此模块仅以 I2C 从设备运行 I2C 模块包括以下功能 : 标准 ( 最高 100 kbps) 快速 (400 kbps) 超快 (1 Mbps) 和高速 (3.4 Mbps) 传输速度 仅支持从模式 时钟低延长 ( 时钟拉伸 ) 以连接到较快的主模式 硬件支持 7 位从地址识别 发射和接收 FIFO ( 两字节 ) 以协助提高较快应用中的吞吐量 16 位 CRC (CRC0) 循环冗余校验 (CRC) 模块使用 16 位多项式执行 CRC CRC0 接受 8 位数据流并将 16 位结果存入内部寄存器中 除了使用 CRC 模块对数据进行操作外, 硬件也可以对设备的闪存内容自动执行 CRC CRC 模块可以为闪存验证和通信协议进行硬件计算 CRC 模块支持标准 CCITT-16 16 位多项式 (0x1021), 包括以下功能 : 支持 CCITT-16 多项式 字节级位序颠倒 对一个或多个 256- 字节块上的闪存内容自动执行 CRC 初始种子选择为 0x0000 或 0xFFFF 3.7 模拟 12 位 AD 转换器 (ADC0) ADC 是一款逐次逼近寄存器 (SAR) ADC, 具有 12 10 和 8 位模式, 集成了跟踪保持电路和可编程窗口检测器 该 ADC 可完全在软件控制下通过几个寄存器来配置 ADC 可通过使用模拟多路复用器配置, 以测量各种不同信号 ADC 的电压参考可在内部和外部参考源之间选择 高达 20 的外部输入 单端 12 位和 10 位模式 支持 12 位模式下每秒 200 ksps 样本的输出更新速率或 10 位模式下每秒 800 ksps 样本的输出更新速率 在低功耗模式下运行时具有较低的转换速度 异步硬件转换触发器, 可以在软件 外部 I/O 和内部定时器来源之间选择 输出数据窗口比较器允许自动范围检查 支持突发模式, 各转换启动触发器生成一组累计数据并具有可编程的加电稳定和跟踪时间 支持转换完成和窗口比较中断 灵活的输出数据格式 包括内部双电平 (1.65 V 和 2.4 V) 的快速设定参考和支持外部参考和信号接地 集成温度传感器 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 11

EFM8BB2 数据表系统概述 低电流比较器 (CMP0, CMP1) 模拟比较器用于比较两种模拟输入的电压, 其中数字输出显示两者之中较高的输入电压 设备 I/O 引脚的外部输入连接以及内部连接可通过正负输入端上彼此独立的多路复用器来启用 滞后 响应时间和电流消耗可进行编程, 以适应应用的特定需求 比较器具备下列功能 : 高达 10 (CMP0) 或 12 (CMP1) 个外部正输入 高达 10 (CMP0) 或 12 (CMP1) 个外部负输入 附加输入选项 : 内部连接到 LDO 输出 直接连接到 GND 直接连接到 VDD 专用 6 位参考 DAC 同步和异步输出可以通过交叉开关被路由至引脚 可编程滞后介于 0 和 ±20 mv 之间 可编程响应时间 在上升沿 下降沿或双沿均可生成中断 PWM 输出停用功能 3.8 复位源 复位电路允许很容易地将控制器置于一个预定义的缺省状态 在进入此复位状态时, 将发生以下过程 : 内核停止程序执行 如果位复位不是仅使用加电复位, 模块寄存器被初始化为指定的复位值 外部端口引脚被置于已知状态 中断和定时器被禁用 如果位复位不是仅使用加电复位, 则所有寄存器都被复位为寄存器说明中备注的预定义值 在复位期间 RAM 的内容不受影响 ; 之前存储的数据在断电之前保持不变 端口 I/O 锁存器在开路漏极模式下复位为 1 在复位期间和复位之后弱上拉启用 对于电源监视器和加电复位,RSTb 引脚被驱动为低电平, 直到设备退出复位状态 在退出复位状态时, 程序计数器 (PC) 被复位, 并且系统时钟默认为内部振荡器 监视程序定时器被启用, 从位置 0x0000 开始程序执行 设备上的复位源包括以下 : 上电复位 外部复位引脚 比较器复位 软件触发复位 电源监控器复位 ( 监控器 VDD 电源 ) 监视程序定时器复位 时钟丢失检测器复位 闪存错误复位 3.9 调试 EFM8BB2 设备包括一个片上 Silicon Labs 2 线 (C2) 调试接口, 支持闪存编程和使用安装在终端应用中的生产件进行系统内调试 C2 接口使用一个时钟信号 (C2CK) 和一个双向 C2 数据信号 (C2D) 在设备和主机系统之间传输信息 有关 C2 协议的详细信息, 请参见 C2 接口规范 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 12

EFM8BB2 数据表系统概述 3.10 引导装载程序 所有设备预编程了一个 UART 引导装载程序 引导装载程序驻留在代码安全页和代码闪存的最后一页 ; 如果不需要可以删除 锁定字节的前一个字节是引导装载程序签名字节 如果此字节的值设为 0xA5 则表示系统中存在引导装载程序 该位置出现任何其他值都表示闪存中没有引导装载程序 存在引导装载程序时, 设备将在执行任何复位操作后, 跳转至引导装载程序向量, 允许运行引导装载程序 随后, 引导装载程序将确定设备是应该停留在引导装载模式中, 还是跳转至位于 0x0000 的复位向量 不存在引导装载程序时, 设备将在执行任何复位操作后, 跳转至 0x0000 的复位向量 欲了解关于引导装载程序协议和使用率的更多信息, 请参见 AN945:EFM8 工厂引导装载程序用户指南 欲了解应用说明, 请参见 Silicon Labs 网站 (www.silabs.com/8bit-appnotes) 或通过 [ 应用说明 ] 方块访问 Simplicity Studio 0xFFFF 0xFFC0 0xFFBF 0xFC00 0xFBFF Read-Only Reserved Lock Byte 0xFBFE 0xFBC0 0xFBBF 0xF800 0xF7FF 0x4000 0x3FFF Bootloader Signature Byte Code Security Page 64 Bytes Nonvolatile Data Reserved Bootloader Bootloader Bootloader Vector 16 KB Code (32 x 512 Byte pages) 0x0000 Reset Vector Figure 3.2. 闪存映射引导装载程序 16 KB 设备 Table 3.2. 用于引导装载程序通信的引脚摘要 引导装载程序 用于引导装载通信的引脚 UART TX P0.4 RX P0.5 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 13

EFM8BB2 数据表系统概述 Table 3.3. 用于引导装载模式入口的引脚摘要 设备封装 QFN28 QSOP24 QFN20 用于引导装载模式入口的引脚 P3.0/C2D P3.0/C2D P2.0/C2D silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 14

EFM8BB2 数据表电气特性 4. 电气特性 4.1 电气特性 除非另有说明, 各表中的所有电气参数都适用于 Table 4.1 Recommended Operating Conditions on page 15( 第 11 页表 4.1 推荐操作条件 ) 中所列的条件 4.1.1 建议的工作条件 Table 4.1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Operating Supply Voltage on VDD V DD 2.2 3.6 V Operating Supply Voltage on VREGIN V REGIN 3.0 5.25 V System Clock Frequency f SYSCLK 0 50 MHz Operating Ambient Temperature T A G-grade devices -40 85 C I-grade or A-grade devices -40 125 C Note: 1. All voltages with respect to GND. 2. GPIO levels are undefined whenever VDD is less than 1 V. silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 15

EFM8BB2 数据表电气特性 4.1.2 功耗 Table 4.2. Power Consumption Parameter Symbol Test Condition Min Typ Max Unit Digital Core Supply Current (G-grade devices, -40 C to +85 C) Normal Mode-Full speed with code executing from flash I DD F SYSCLK = 49 MHz (HFOSC1) 2 9.4 10.1 ma F SYSCLK = 24.5 MHz (HFOSC0) 2 4.5 5.2 ma F SYSCLK = 1.53 MHz (HFOSC0) 2 600 900 μa F SYSCLK = 80 khz 3 145 410 μa Idle Mode-Core halted with peripherals running I DD F SYSCLK = 49 MHz (HFOSC1) 2 6.3 6.8 ma F SYSCLK = 24.5 MHz (HFOSC0) 2 2.9 3.3 ma F SYSCLK = 1.53 MHz (HFOSC0) 2 440 750 μa F SYSCLK = 80 khz 3 130 420 μa Suspend Mode-Core halted and high frequency clocks stopped, Supply monitor off. Snooze Mode-Core halted and high frequency clocks stopped. Regulator in low-power state, Supply monitor off. Stop Mode Core halted and all clocks stopped,internal LDO On, Supply monitor off. Shutdown Mode Core halted and all clocks stopped,internal LDO Off, Supply monitor off. I DD LFO Running 125 400 μa LFO Stopped 120 390 μa I DD LFO Running 25 300 μa LFO Stopped 20 290 μa I DD 120 390 μa I DD 0.2 3 μa Digital Core Supply Current (I-grade or A-grade devices, -40 C to +125 C) Normal Mode-Full speed with code executing from flash I DD F SYSCLK = 49 MHz (HFOSC1) 2 9.4 10.9 ma F SYSCLK = 24.5 MHz (HFOSC0) 2 4.5 5.6 ma F SYSCLK = 1.53 MHz (HFOSC0) 2 600 1555 μa F SYSCLK = 80 khz 3 145 1070 μa Idle Mode-Core halted with peripherals running I DD F SYSCLK = 49 MHz (HFOSC1) 2 6.3 7.4 ma F SYSCLK = 24.5 MHz (HFOSC0) 2 2.9 3.9 ma F SYSCLK = 1.53 MHz (HFOSC0) 2 440 1400 μa F SYSCLK = 80 khz 3 130 1050 μa Suspend Mode-Core halted and high frequency clocks stopped, Supply monitor off. I DD LFO Running 125 1050 μa LFO Stopped 120 1045 μa silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 16

EFM8BB2 数据表电气特性 Parameter Symbol Test Condition Min Typ Max Unit Snooze Mode-Core halted and high frequency clocks stopped. Regulator in low-power state, Supply monitor off. Stop Mode Core halted and all clocks stopped,internal LDO On, Supply monitor off. Shutdown Mode Core halted and all clocks stopped,internal LDO Off, Supply monitor off. I DD LFO Running 25 950 μa LFO Stopped 20 940 μa I DD 120 1045 μa I DD 0.2 15 μa Analog Peripheral Supply Currents (-40 C to +125 C) High-Frequency Oscillator 0 I HFOSC0 Operating at 24.5 MHz, 105 μa T A = 25 C High-Frequency Oscillator 1 I HFOSC1 Operating at 49 MHz, 865 940 μa T A = 25 C Low-Frequency Oscillator I LFOSC Operating at 80 khz, 4 μa T A = 25 C ADC0 Always-on 4 I ADC 800 ksps, 10-bit conversions or 820 1200 μa 200 ksps, 12-bit conversions Normal bias settings V DD = 3.0 V 250 ksps, 10-bit conversions or 405 580 μa 62.5 ksps 12-bit conversions Low power bias settings V DD = 3.0 V ADC0 Burst Mode, 10-bit single conversions, external reference I ADC 200 ksps, V DD = 3.0 V 370 μa 100 ksps, V DD = 3.0 V 185 μa 10 ksps, V DD = 3.0 V 20 μa ADC0 Burst Mode, 10-bit single conversions, internal reference, Low power bias settings ADC0 Burst Mode, 12-bit single conversions, external reference I ADC 200 ksps, V DD = 3.0 V 485 μa 100 ksps, V DD = 3.0 V 245 μa 10 ksps, V DD = 3.0 V 25 μa I ADC 100 ksps, V DD = 3.0 V 505 μa 50 ksps, V DD = 3.0 V 255 μa 10 ksps, V DD = 3.0 V 50 μa silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 17

EFM8BB2 数据表电气特性 Parameter Symbol Test Condition Min Typ Max Unit ADC0 Burst Mode, 12-bit single conversions, internal reference I ADC 100 ksps, V DD = 3.0 V, Normal bias 50 ksps, V DD = 3.0 V, Low power bias 10 ksps, V DD = 3.0 V, Low power bias 950 μa 415 μa 80 μa Internal ADC0 Reference, I VREFFS Normal Power Mode 680 790 μa Always-on 5 Low Power Mode 160 210 μa Temperature Sensor I TSENSE 70 120 μa Comparator 0 (CMP0, CMP1) I CMP CPMD = 11 0.5 μa CPMD = 10 3 μa CPMD = 01 8.5 μa CPMD = 00 22.5 μa Comparator Reference 6 I CPREF 1.2 μa Voltage Supply Monitor (VMON0) I VMON 15 20 μa 5V Regulator I VREG Normal Mode 245 340 μa (SUSEN = 0, BIASENB = 0) Suspend Mode 60 100 μa (SUSEN = 1, BIASENB = 0) Bias Disabled 2.5 10 μa (BIASENB = 1) Disabled 2.5 na Note: (BIASENB = 1, REG1ENB = 1) 1. Currents are additive. For example, where I DD is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 2. Includes supply current from internal LDO regulator, supply monitor, and High Frequency Oscillator. 3. Includes supply current from internal LDO regulator, supply monitor, and Low Frequency Oscillator. 4. ADC0 always-on power excludes internal reference supply current. 5. The internal reference is enabled as-needed when operating the ADC in burst mode to save power. 6. This value is the current sourced from the pin or supply selected as the full-scale reference to the comparator DAC. silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 18

EFM8BB2 数据表电气特性 4.1.3 复位和电源监控器 Table 4.3. Reset and Supply Monitor Parameter Symbol Test Condition Min Typ Max Unit VDD Supply Monitor Threshold V VDDM 1.95 2.05 2.15 V Power-On Reset (POR) Threshold V POR Rising Voltage on VDD 1.2 V Falling Voltage on VDD 0.75 1.36 V VDD Ramp Time t RMP Time to V DD > 2.2 V 10 μs Reset Delay from POR t POR Relative to V DD > V POR 3 10 31 ms Reset Delay from non-por source t RST Time between release of reset source and code execution 50 μs RST Low Time to Generate Reset t RSTL 15 μs Missing Clock Detector Response Time (final rising edge to reset) Missing Clock Detector Trigger Frequency t MCD F SYSCLK >1 MHz 0.625 1.2 ms F MCD 7.5 13.5 khz VDD Supply Monitor Turn-On Time t MON 2 μs 4.1.4 闪存 Table 4.4. Flash Memory Parameter Symbol Test Condition Min Typ Max Units Write Time 1,2 t WRITE One Byte, 19 20 21 μs F SYSCLK = 24.5 MHz Erase Time 1,2 t ERASE One Page, 5.2 5.35 5.5 ms F SYSCLK = 24.5 MHz V DD Voltage During Programming 3 V PROG 2.2 3.6 V Endurance (Write/Erase Cycles) N WE 20k 100k Cycles CRC Calculation Time t CRC One 256-Byte Block 5.5 µs Note: SYSCLK = 49 MHz 1. Does not include sequencing time before and after the write/erase operation, which may be multiple SYSCLK cycles. 2. The internal High-Frequency Oscillator 0 has a programmable output frequency, which is factory programmed to 24.5 MHz. If user firmware adjusts the oscillator speed, it must be between 22 and 25 MHz during any flash write or erase operation. It is recommended to write the HFO0CAL register back to its reset value when writing or erasing flash. 3. Flash can be safely programmed at any voltage above the supply monitor threshold (V VDDM ). 4. Data Retention Information is published in the Quarterly Quality and Reliability Report. silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 19

EFM8BB2 数据表电气特性 4.1.5 电源管理定时 Table 4.5. Power Management Timing Parameter Symbol Test Condition Min Typ Max Units Idle Mode Wake-up Time t IDLEWK 2 3 SYSCLKs Suspend Mode Wake-up Time t SUSPENDWK SYSCLK = HFOSC0 170 ns CLKDIV = 0x00 Snooze Mode Wake-up Time t SLEEPWK SYSCLK = HFOSC0 12 µs CLKDIV = 0x00 4.1.6 内部振荡器 Table 4.6. Internal Oscillators Parameter Symbol Test Condition Min Typ Max Unit High Frequency Oscillator 0 (24.5 MHz) Oscillator Frequency f HFOSC0 Full Temperature and Supply Range 24 24.5 25 MHz Power Supply Sensitivity PSS HFOSC0 T A = 25 C 0.5 %/V Temperature Sensitivity TS HFOSC0 V DD = 3.0 V 40 ppm/ C High Frequency Oscillator 1 (49 MHz) Oscillator Frequency f HFOSC1 Full Temperature and Supply Range 48.25 49 49.75 MHz Power Supply Sensitivity PSS HFOSC1 T A = 25 C 0.02 %/V Temperature Sensitivity TS HFOSC1 V DD = 3.0 V 45 ppm/ C Low Frequency Oscillator (80 khz) Oscillator Frequency f LFOSC Full Temperature and Supply Range 75 80 85 khz Power Supply Sensitivity PSS LFOSC T A = 25 C 0.05 %/V Temperature Sensitivity TS LFOSC V DD = 3.0 V 65 ppm/ C silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 20

EFM8BB2 数据表电气特性 4.1.7 外部时钟输入 Table 4.7. External Clock Input Parameter Symbol Test Condition Min Typ Max Unit External Input CMOS Clock f CMOS 0 50 MHz Frequency (at EXTCLK pin) External Input CMOS Clock High Time External Input CMOS Clock Low Time t CMOSH 9 ns t CMOSL 9 ns silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 21

EFM8BB2 数据表电气特性 4.1.8 ADC Table 4.8. ADC Parameter Symbol Test Condition Min Typ Max Unit Resolution N bits 12 Bit Mode 12 Bits 10 Bit Mode 10 Bits Throughput Rate (High Speed Mode) Throughput Rate (Low Power Mode) f S 12 Bit Mode 200 ksps 10 Bit Mode 800 ksps f S 12 Bit Mode 62.5 ksps 10 Bit Mode 250 ksps Tracking Time t TRK High Speed Mode 230 ns Low Power Mode 450 ns Power-On Time t PWR 1.2 μs SAR Clock Frequency f SAR High Speed Mode, 6.25 MHz Reference is 2.4 V internal High Speed Mode, 12.5 MHz Reference is not 2.4 V internal Low Power Mode 4 MHz Conversion Time t CNV 10-Bit Conversion, 1.1 μs SAR Clock = 12.25 MHz, System Clock = 24.5 MHz. Sample/Hold Capacitor C SAR Gain = 1 5 pf Gain = 0.5 2.5 pf Input Pin Capacitance C IN 20 pf Input Mux Impedance R MUX 550 Ω Voltage Reference Range V REF 1 V DD V Input Voltage Range 1 V IN Gain = 1 0 V REF V Gain = 0.5 0 2xV REF V Power Supply Rejection Ratio PSRR ADC 70 db DC Performance Integral Nonlinearity INL 12 Bit Mode ±1 ±2.3 LSB 10 Bit Mode ±0.2 ±0.6 LSB Differential Nonlinearity (Guaranteed Monotonic) DNL 12 Bit Mode -1 ±0.7 1.9 LSB 10 Bit Mode ±0.2 ±0.6 LSB Offset Error E OFF 12 Bit Mode, VREF = 1.65 V -3 0 3 LSB 10 Bit Mode, VREF = 1.65 V -2 0 2 LSB Offset Temperature Coefficient TC OFF 0.004 LSB/ C silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 22

EFM8BB2 数据表电气特性 Parameter Symbol Test Condition Min Typ Max Unit Slope Error E M 12 Bit Mode ±0.02 ±0.1 % 10 Bit Mode ±0.06 ±0.24 % Dynamic Performance 10 khz Sine Wave Input 1 db below full scale, Max throughput, using AGND pin Signal-to-Noise SNR 12 Bit Mode 61 66 db 10 Bit Mode 53 60 db Signal-to-Noise Plus Distortion SNDR 12 Bit Mode 61 66 db 10 Bit Mode 53 60 db Total Harmonic Distortion (Up to 5th Harmonic) THD 12 Bit Mode 71 db 10 Bit Mode 70 db Spurious-Free Dynamic Range SFDR 12 Bit Mode -79 db 10 Bit Mode -70 db Note: 1. Absolute input pin voltage is limited by the V DD supply. 4.1.9 参考电压 Table 4.9. Voltage Reference Parameter Symbol Test Condition Min Typ Max Unit Internal Fast Settling Reference Output Voltage (Full Temperature and Supply Range) V REFFS 1.65 V Setting 1.62 1.65 1.68 V 2.4 V Setting, V DD > 2.6 V 2.35 2.4 2.45 V Temperature Coefficient TC REFFS 50 ppm/ C Turn-on Time t REFFS 1.5 μs Power Supply Rejection PSRR REFFS 400 ppm/v External Reference Input Current I EXTREF Sample Rate = 800 ksps; VREF = 3.0 V 8 μa silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 23

EFM8BB2 数据表电气特性 4.1.10 温度传感器 Table 4.10. Temperature Sensor Parameter Symbol Test Condition Min Typ Max Unit Offset V OFF T A = 0 C 757 mv Offset Error 1 E OFF T A = 0 C 17 mv Slope M 2.85 mv/ C Slope Error 1 E M 70 μv/ Linearity 0.5 C Turn-on Time 1.8 μs Note: 1. Represents one standard deviation from the mean. 4.1.11 1.8 V 内部 LDO 稳压器 Table 4.11. 1.8V Internal LDO Voltage Regulator Parameter Symbol Test Condition Min Typ Max Unit Output Voltage V OUT_1.8V 1.78 1.85 1.92 V 4.1.12 5 V 电压稳压器 Table 4.12. 5V Voltage Regulator Parameter Symbol Test Condition Min Typ Max Unit Input Voltage Range 1 V REGIN 3.0 5.25 V Output Voltage on VDD 2 V REGOUT Output Current = 1 to 100 ma 3.1 3.3 3.6 V Regulation range (VREGIN 4.1 V) Output Current = 1 to 100 ma Dropout range (VREGIN < 4.1 V) V REGIN V DROPOUT V Output Current 2 I REGOUT 100 ma Dropout Voltage V DROPOUT Output Current = 100 ma 0.8 V Note: 1. Input range to meet the Output Voltage on VDD specification. If the 5V voltage regulator is not used, VREGIN should be tied to VDD. 2. Output current is total regulator output, including any current required by the device. silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 24

EFM8BB2 数据表电气特性 4.1.13 比较器 Table 4.13. Comparators Parameter Symbol Test Condition Min Typ Max Unit Response Time, CPMD = 00 (Highest Speed) Response Time, CPMD = 11 (Lowest Power) t RESP0 +100 mv Differential, V CM = 1.65 V -100 mv Differential, V CM = 1.65 V t RESP3 +100 mv Differential, V CM = 1.65 V -100 mv Differential, V CM = 1.65 V 110 ns 160 ns 1.2 μs 4.5 μs Positive Hysteresis Mode 0 (CPMD = 00) HYS CP+ CPHYP = 00 0.4 mv CPHYP = 01 8 mv CPHYP = 10 16 mv CPHYP = 11 32 mv Negative Hysteresis Mode 0 (CPMD = 00) HYS CP- CPHYN = 00-0.4 mv CPHYN = 01-8 mv CPHYN = 10-16 mv CPHYN = 11-32 mv Positive Hysteresis Mode 3 (CPMD = 11) HYS CP+ CPHYP = 00 1.5 mv CPHYP = 01 4 mv CPHYP = 10 8 mv CPHYP = 11 16 mv Negative Hysteresis Mode 3 (CPMD = 11) HYS CP- CPHYN = 00-1.5 mv CPHYN = 01-4 mv CPHYN = 10-8 mv CPHYN = 11-16 mv Input Range (CP+ or CP-) V IN -0.25 V DD +0.25 V Input Pin Capacitance C CP 7.5 pf Internal Reference DAC Resolution N bits 6 bits Common-Mode Rejection Ratio CMRR CP 70 db Power Supply Rejection Ratio PSRR CP 72 db Input Offset Voltage V OFF T A = 25 C -10 0 10 mv Input Offset Tempco TC OFF 3.5 μv/ silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 25

EFM8BB2 数据表电气特性 4.1.14 端口 I/O Table 4.14. Port I/O Parameter Symbol Test Condition Min Typ Max Unit Output High Voltage (High V OH I OH = -7 ma, V DD 3.0 V V DD - 0.7 V Drive) 1 I OH = -3.3 ma, 2.2 V V DD < V DD x 0.8 V 3.0 V Output Low Voltage (High V OL I OL = 13.5 ma, V DD 3.0 V 0.6 V Drive) 1 I OL = 7 ma, 2.2 V V DD < 3.0 V V DD x 0.2 V Output High Voltage (Low V OH I OH = -4.75 ma, V DD 3.0 V V DD - 0.7 V Drive) 1 I OH = -2.25 ma, 2.2 V V DD < V DD x 0.8 V 3.0 V Output Low Voltage (Low Drive) 1 V OL I OL = 6.5 ma, V DD 3.0 V 0.6 V I OL = 3.5 ma, 2.2 V V DD < 3.0 V V DD x 0.2 V Input High Voltage V IH V DD - 0.6 V Input Low Voltage V IL 0.6 V Pin Capacitance C IO 7 pf Weak Pull-Up Current I PU V DD = 3.6-30 -20-10 μa (V IN = 0 V) Input Leakage (Pullups off or Analog) I LK GND < V IN < V DD -1.1 1.1 μa Input Leakage Current with V IN I LK V DD < V IN < V DD +2.0 V 0 5 150 μa above V DD Note: 1. See Figure 4.6 常见 V OH 曲线 on page 31 and Figure 4.7 常见 V OL 曲线 on page 31 for more information. 4.2 热能条件 Table 4.15. Thermal Conditions Parameter Symbol Test Condition Min Typ Max Unit Thermal Resistance (Junction to Ambient) θ JA QFN-20 Packages 60 C/W QFN-28 Packages 26 C/W QSOP-24 Packages 65 C/W Thermal Resistance (Junction to Case) θ JC QFN-20 Packages 28.86 C/W Note: 1. Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad. silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 26

EFM8BB2 数据表电气特性 4.3 绝对最大额定值 超过 Table 4.16 Absolute Maximum Ratings on page 27( 第 20 页表 4.17 最大额定值 ) 中所列的应力值可能会永久损坏设备 这仅为应力额定值, 不表示在此值之下或在此规范的操作列表中标明的额定值之上的任何其他条件下可以对设备进行功能性操作 长期在最大额定值条件下工作可影响设备的可靠性 有关质量参数和可靠性数据的更多信息, 请访问 http://www.silabs.com/support/ quality/pages/default.aspx 参阅 质量和可靠性监视报告 Table 4.16. Absolute Maximum Ratings Parameter Symbol Test Condition Min Max Unit Ambient Temperature Under Bias T BIAS -55 125 C Storage Temperature T STG -65 150 C Voltage on VDD V DD GND-0.3 4.2 V Voltage on VREGIN V REGIN GND-0.3 5.8 V Voltage on I/O pins or RSTb V IN V DD > 3.3 V GND-0.3 5.8 V V DD < 3.3 V GND-0.3 V DD +2.5 V Total Current Sunk into Supply Pin I VDD 200 ma Total Current Sourced out of Ground Pin Current Sourced or Sunk by any I/O Pin or RSTb I GND 200 ma I IO -100 100 ma Operating Junction Temperature T J T A = -40 C to 85 C 40 105 C T A = -40 C to 125 C (I-grade or A-grade parts only) -40 130 C Note: 1. Exposure to maximum rating conditions for extended periods may affect device reliability. silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 27

EFM8BB2 数据表电气特性 4.4 典型性能曲线 Figure 4.1. 使用 HFOSC0 时典型的运行电源电流 Figure 4.2. 使用 HFOSC1 时典型的运行电源电流 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 28

EFM8BB2 数据表电气特性 Figure 4.3. 使用 LFOSC 时典型的运行电源电流 Figure 4.4. 突发模式下典型的 ADC0 和内部参考电源电流 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 29

EFM8BB2 数据表电气特性 Figure 4.5. 正常 ( 常开 ) 模式下典型的 ADC0 电源电流 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 30

EFM8BB2 数据表电气特性 Figure 4.6. 常见 V OH 曲线 Figure 4.7. 常见 V OL 曲线 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 31

EFM8BB2 数据表典型连接图 5. 典型连接图 5.1 电源 Figure 5.1 使用电压稳压器的连接图 on page 32 显示使用 5 V 至 3.3 V 稳压器时,EFM8BB2 设备的电源引脚典型连接图 4.7 µf and 0.1 µf bypass capacitors required for each power pin placed as close to the pins as possible. 2.7-5.25 V (in) 3.3 V (out) VREGIN VDD EFM8BB2 Device Voltage Regulator GND Figure 5.1. 使用电压稳压器的连接图 Figure 5.2 未使用电压稳压器的连接图 on page 32 显示未使用内部 5 V 至 3.3 V 稳压器时,EFM8BB2 设备电源引脚的典型连接图 EFM8BB2 Device 4.7 µf and 0.1 µf bypass capacitors required for each power pin placed as close to the pins as possible. 2.2-3.6 V (in) VREGIN VDD Voltage Regulator GND Figure 5.2. 未使用电压稳压器的连接图 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 32

EFM8BB2 数据表典型连接图 5.2 调试 下图为调试连接引脚的典型连接图 仅在 C2D( 一种 GPIO 引脚 ) 和 C2CK (RSTb) 路由到外部电路的情况下, 才要求引脚共享电阻 例如, 如果 RSTb 引脚连接到带有消抖滤波器的外部开关, 或者与 C2D 引脚共享的 GPIO 连接到外部电路, 则引脚共享电阻和调试适配器连接必须放置在硬件 否则, 这些元件和连接可能被忽略 欲了解关于调试连接的更多信息, 请参见 AN124 中的示例原理图和信息 :C2 接口的引脚共享技术中的示例原理图和信息 欲了解应用说明, 请参见 Silicon Labs 网站 (http://www.silabs.com/8bit-appnotes) 或 Simplicity Studio EFM8BB2 Device VDD 1 k External System C2CK 1 k 1 k (if pin sharing) C2D (if pin sharing) 1 k 1 k GND Debug Adapter Figure 5.3. 调试连接图 5.3 其他连接 其他元件或连接可能需要满足系统级要求 应用说明 AN203:8 位 MCU 印刷电路板设计说明 中对这些连接进行了详细说明 应用说明位于 Silicon Labs 网站上 (www.silabs.com/8bit-appnotes) silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 33

EFM8BB2 数据表引脚定义 6. 引脚定义 6.1 EFM8BB2x-QFN28 引脚定义 28 27 26 25 P0.1 1 21 P1.1 P0.0 2 20 P1.2 GND 3 19 P1.3 N/C 4 18 P1.4 P3.1 RSTb / C2CK P3.0 / C2D P2.3 8 9 10 11 24 23 22 P0.2 P0.3 P0.4 P0.5 P0.7 P1.0 N/C 5 17 P1.5 VDD 6 16 P1.6 VREGIN 7 GND 15 P1.7 P2.2 P2.1 P2.0 12 13 14 P0.6 28 pin QFN (Top View) Figure 6.1. EFM8BB2x-QFN28 引脚分配 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 34

EFM8BB2 数据表引脚定义 Table 6.1. Pin Definitions for EFM8BB2x-QFN28 Pin Number Pin Name Description Crossbar Capability Additional Digital Functions Analog Functions 1 P0.1 Multifunction I/O Yes P0MAT.1 INT0.1 INT1.1 ADC0.1 CMP0P.1 CMP0N.1 AGND 2 P0.0 Multifunction I/O Yes P0MAT.0 INT0.0 INT1.0 ADC0.0 CMP0P.0 CMP0N.0 VREF 3 GND Ground 4 N/C No Connection 5 N/C No Connection 6 VDD Supply Power Input / 5V Regulator Output 7 VREGIN 5V Regulator Input 8 P3.1 Multifunction I/O 9 RST / C2CK 10 P3.0 / C2D Active-low Reset / C2 Debug Clock Multifunction I/O / C2 Debug Data 11 P2.3 Multifunction I/O Yes P2MAT.3 ADC0.23 CP1P.12 CP1N.12 12 P2.2 Multifunction I/O Yes P2MAT.2 ADC0.22 CP1P.11 CP1N.11 13 P2.1 Multifunction I/O Yes P2MAT.1 ADC0.21 CP1P.10 CP1N.10 14 P2.0 Multifunction I/O Yes P2MAT.0 ADC0.20 CP1P.9 CP1N.9 15 P1.7 Multifunction I/O Yes P1MAT.7 ADC0.15 CP1P.7 CP1N.7 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 35

EFM8BB2 数据表引脚定义 Pin Number Pin Name Description Crossbar Capability Additional Digital Functions Analog Functions 16 P1.6 Multifunction I/O Yes P1MAT.6 I2C0_SCL ADC0.14 CP1P.6 CP1N.6 17 P1.5 Multifunction I/O Yes P1MAT.5 I2C0_SDA ADC0.13 CP1P.5 CP1N.5 18 P1.4 Multifunction I/O Yes P1MAT.4 ADC0.12 CP1P.4 CP1N.4 19 P1.3 Multifunction I/O Yes P1MAT.3 ADC0.11 CP1P.3 CP1N.3 20 P1.2 Multifunction I/O Yes P1MAT.2 ADC0.10 CP1P.2 CP1N.2 21 P1.1 Multifunction I/O Yes P1MAT.1 ADC0.9 CP1P.1 CP1N.1 CMP0P.10 CMP0N.10 22 P1.0 Multifunction I/O Yes P1MAT.0 ADC0.8 CP1P.0 CP1N.0 CMP0P.9 CMP0N.9 23 P0.7 Multifunction I/O Yes P0MAT.7 INT0.7 INT1.7 24 P0.6 Multifunction I/O Yes P0MAT.6 CNVSTR INT0.6 ADC0.7 CMP0P.7 CMP0N.7 ADC0.6 CMP0P.6 CMP0N.6 INT1.6 25 P0.5 Multifunction I/O Yes P0MAT.5 INT0.5 INT1.5 ADC0.5 CMP0P.5 CMP0N.5 UART0_RX silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 36

EFM8BB2 数据表引脚定义 Pin Number Pin Name Description Crossbar Capability Additional Digital Functions Analog Functions 26 P0.4 Multifunction I/O Yes P0MAT.4 INT0.4 INT1.4 ADC0.4 CMP0P.4 CMP0N.4 UART0_TX 27 P0.3 Multifunction I/O Yes P0MAT.3 EXTCLK INT0.3 ADC0.3 CMP0P.3 CMP0N.3 INT1.3 28 P0.2 Multifunction I/O Yes P0MAT.2 INT0.2 INT1.2 ADC0.2 CMP0P.2 CMP0N.2 Center GND Ground silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 37

EFM8BB2 数据表引脚定义 6.2 EFM8BB2x-QSOP24 引脚定义 P0.3 1 24 P0.4 P0.2 2 23 P0.5 P0.1 3 22 P0.6 P0.0 4 21 P0.7 GND 5 20 P1.0 VDD RSTb / C2CK 6 7 24 pin QSOP (Top View) 19 18 P1.1 P1.2 P3.0 / C2D 8 17 P1.3 P2.3 9 16 P1.4 P2.2 10 15 P1.5 P2.1 11 14 P1.6 P2.0 12 13 P1.7 Figure 6.2. EFM8BB2x-QSOP24 分配 Table 6.2. Pin Definitions for EFM8BB2x-QSOP24 Pin Number Pin Name Description Crossbar Capability Additional Digital Functions Analog Functions 1 P0.3 Multifunction I/O Yes P0MAT.3 EXTCLK INT0.3 ADC0.3 CMP0P.3 CMP0N.3 INT1.3 2 P0.2 Multifunction I/O Yes P0MAT.2 INT0.2 INT1.2 ADC0.2 CMP0P.2 CMP0N.2 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 38

EFM8BB2 数据表引脚定义 Pin Number Pin Name Description Crossbar Capability Additional Digital Functions Analog Functions 3 P0.1 Multifunction I/O Yes P0MAT.1 INT0.1 INT1.1 ADC0.1 CMP0P.1 CMP0N.1 AGND 4 P0.0 Multifunction I/O Yes P0MAT.0 INT0.0 INT1.0 ADC0.0 CMP0P.0 CMP0N.0 VREF 5 GND Ground 6 VDD Supply Power Input 7 RSTb / C2CK 8 P3.0 / C2D Active-low Reset / C2 Debug Clock Multifunction I/O / C2 Debug Data 9 P2.3 Multifunction I/O Yes P2MAT.3 ADC0.23 CMP1P.12 CMP1N.12 10 P2.2 Multifunction I/O Yes P2MAT.2 ADC0.22 CMP1P.11 CMP1N.11 11 P2.1 Multifunction I/O Yes P2MAT.1 ADC0.21 CMP1P.10 CMP1N.10 12 P2.0 Multifunction I/O Yes P2MAT.0 ADC0.20 CMP1P.9 CMP1N.9 13 P1.7 Multifunction I/O Yes P1MAT.7 ADC0.15 CMP1P.7 CMP1N.7 14 P1.6 Multifunction I/O Yes P1MAT.6 I2C0_SCL ADC0.14 CMP1P.6 CMP1N.6 15 P1.5 Multifunction I/O Yes P1MAT.5 I2C0_SDA ADC0.13 CMP1P.5 CMP1N.5 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 39

EFM8BB2 数据表引脚定义 Pin Number Pin Name Description Crossbar Capability Additional Digital Functions Analog Functions 16 P1.4 Multifunction I/O Yes P1MAT.4 ADC0.12 CMP1P.4 CMP1N.4 17 P1.3 Multifunction I/O Yes P1MAT.3 ADC0.11 CMP1P.3 CMP1N.3 18 P1.2 Multifunction I/O Yes P1MAT.2 ADC0.10 CMP1P.2 CMP1N.2 19 P1.1 Multifunction I/O Yes P1MAT.1 ADC0.9 CMP1P.1 CMP1N.1 CMP0P.10 CMP0N.10 20 P1.0 Multifunction I/O Yes P1MAT.0 ADC0.8 CMP1P.0 CMP1N.0 CMP0P.9 CMP0N.9 21 P0.7 Multifunction I/O Yes P0MAT.7 INT0.7 INT1.7 22 P0.6 Multifunction I/O Yes P0MAT.6 CNVSTR INT0.6 ADC0.7 CMP0P.7 CMP0N.7 ADC0.6 CMP0P.6 CMP0N.6 INT1.6 23 P0.5 Multifunction I/O Yes P0MAT.5 INT0.5 INT1.5 ADC0.5 CMP0P.5 CMP0N.5 UART0_RX 24 P0.4 Multifunction I/O Yes P0MAT.4 INT0.4 INT1.4 ADC0.4 CMP0P.4 CMP0N.4 UART0_TX silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 40

EFM8BB2 数据表引脚定义 6.3 EFM8BB2x-QFN20 引脚定义 P0.1 20 19 18 17 P0.2 P0.3 P0.4 P0.5 1 16 P0.6 P0.0 2 15 P0.7 GND VDD 3 4 20 pin QFN (Top View) 14 13 P1.0 P1.1 RSTb / C2CK 5 GND 12 GND P2.0 / C2D 6 11 7 8 9 10 P1.2 P1.6 P1.5 P1.4 P1.3 Figure 6.3. EFM8BB2x-QFN20 引脚分配 Table 6.3. Pin Definitions for EFM8BB2x-QFN20 Pin Number Pin Name Description Crossbar Capability Additional Digital Functions Analog Functions 1 P0.1 Multifunction I/O Yes P0MAT.1 INT0.1 INT1.1 ADC0.1 CMP0P.1 CMP0N.1 AGND 2 P0.0 Multifunction I/O Yes P0MAT.0 INT0.0 INT1.0 ADC0.0 CMP0P.0 CMP0N.0 VREF silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 41

EFM8BB2 数据表引脚定义 Pin Number Pin Name Description Crossbar Capability Additional Digital Functions Analog Functions 3 GND Ground 4 VDD Supply Power Input 5 RSTb / C2CK 6 P2.0 / C2D Active-low Reset / C2 Debug Clock Multifunction I/O / C2 Debug Data Yes 7 P1.6 Multifunction I/O Yes P1MAT.6 ADC0.14 CMP1P.6 CMP1N.6 8 P1.5 Multifunction I/O Yes P1MAT.5 ADC0.13 CMP1P.5 CMP1N.5 9 P1.4 Multifunction I/O Yes P1MAT.4 ADC0.12 CMP1P.4 CMP1N.4 10 P1.3 Multifunction I/O Yes P1MAT.3 I2C0_SCL ADC0.11 CMP1P.3 CMP1N.3 11 P1.2 Multifunction I/O Yes P1MAT.2 I2C0_SDA ADC0.10 CMP1P.2 CMP1N.2 12 GND Ground 13 P1.1 Multifunction I/O Yes P1MAT.1 ADC0.9 CMP1P.1 CMP1N.1 CMP0P.10 CMP0N.10 14 P1.0 Multifunction I/O Yes P1MAT.0 ADC0.8 CMP1P.0 CMP1N.0 CMP0P.9 CMP0N.9 15 P0.7 Multifunction I/O Yes P0MAT.7 INT0.7 INT1.7 ADC0.7 CMP0P.7 CMP0N.7 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 42

EFM8BB2 数据表引脚定义 Pin Number Pin Name Description Crossbar Capability Additional Digital Functions Analog Functions 16 P0.6 Multifunction I/O Yes P0MAT.6 CNVSTR INT0.6 ADC0.6 CMP0P.6 CMP0N.6 INT1.6 17 P0.5 Multifunction I/O Yes P0MAT.5 INT0.5 INT1.5 ADC0.5 CMP0P.5 CMP0N.5 UART0_RX 18 P0.4 Multifunction I/O Yes P0MAT.4 INT0.4 INT1.4 ADC0.4 CMP0P.4 CMP0N.4 UART0_TX 19 P0.3 Multifunction I/O Yes P0MAT.3 EXTCLK INT0.3 ADC0.3 CMP0P.3 CMP0N.3 INT1.3 20 P0.2 Multifunction I/O Yes P0MAT.2 INT0.2 INT1.2 ADC0.2 CMP0P.2 CMP0N.2 Center GND Ground silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 43

EFM8BB2 数据表 QFN28 封装规格 7. QFN28 封装规格 7.1 QFN28 封装尺寸 Figure 7.1. QFN28 封装图 Table 7.1. QFN28 Package Dimensions Dimension Min Typ Max A 0.70 0.75 0.80 A1 0.00 0.05 A3 0.20 REF b 0.20 0.25 0.30 D 5.00 BSC D2 3.15 3.25 3.35 e E 0.50 BSC 5.00 BSC E2 3.15 3.25 3.35 L 0.45 0.55 0.65 aaa 0.10 bbb 0.10 ddd 0.05 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 44

EFM8BB2 数据表 QFN28 封装规格 Dimension Min Typ Max eee 0.08 Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Solid State Outline MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 45

EFM8BB2 数据表 QFN28 封装规格 7.2 QFN28 PCB 焊盘布局 X1 Y2 Y1 C0.35 C2 X2 E C1 Figure 7.2. QFN28 PCB 焊盘布局图 Table 7.2. QFN28 PCB Land Pattern Dimensions Dimension Min Max C1 4.80 C2 4.80 E 0.50 X1 0.30 X2 3.35 Y1 0.95 Y2 3.35 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 46

EFM8BB2 数据表 QFN28 封装规格 Dimension Min Max Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. A 2 x 2 array of 1.2 mm square openings on a 1.5 mm pitch should be used for the center pad. 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 7.3 QFN28 封装标识 EFM8 PPPPPPPP TTTTTT YYWW # Figure 7.3. QFN28 封装标识 封装标识的组成为 : PPPPPPPP 指定部件编号 TTTTTT 跟踪或生产代码 YY 生产年份的最后 2 位数字 WW 设备生产时的 2 位工作周 # 设备版本 (A B 等 ) silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 47

EFM8BB2 数据表 QSOP24 封装规格 8. QSOP24 封装规格 8.1 QSOP24 封装尺寸 Figure 8.1. QSOP24 封装图 Table 8.1. QSOP24 Package Dimensions Dimension Min Typ Max A 1.75 A1 0.10 0.25 b 0.20 0.30 c 0.10 0.25 D E E1 e 8.65 BSC 6.00 BSC 3.90 BSC 0.635 BSC L 0.40 1.27 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 48

EFM8BB2 数据表 QSOP24 封装规格 Dimension Min Typ Max theta 0º 8º aaa 0.20 bbb 0.18 ccc 0.10 ddd 0.10 Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-137, variation AE. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 49

EFM8BB2 数据表 QSOP24 封装规格 8.2 QSOP24 PCB 焊盘布局 Figure 8.2. QSOP24 PCB 焊盘布局图 Table 8.2. QSOP24 PCB Land Pattern Dimensions Dimension Min Max C 5.20 5.30 E 0.635 BSC X 0.30 0.40 Y 1.50 1.60 Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 guidelines. 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. A No-Clean, Type-3 solder paste is recommended. 8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 50

EFM8BB2 数据表 QSOP24 封装规格 8.3 QSOP24 封装标识 EFM8 PPPPPPPP # TTTTTTYYWW Figure 8.3. QSOP24 封装标识 封装标识的组成为 : PPPPPPPP 指定部件编号 TTTTTT 跟踪或生产代码 YY 生产年份的最后 2 位数字 WW 设备生产时的 2 位工作周 # 设备版本 (A B 等 ) silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 51

EFM8BB2 数据表 QFN20 封装规格 9. QFN20 封装规格 9.1 QFN20 封装尺寸 Figure 9.1. QFN20 封装图 Table 9.1. QFN20 Package Dimensions Dimension Min Typ Max A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A3 0.20 REF b 0.18 0.25 0.30 c 0.25 0.30 0.35 D 3.00 BSC D2 1.6 1.70 1.80 e E 0.50 BSC 3.00 BSC silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 52

EFM8BB2 数据表 QFN20 封装规格 Dimension Min Typ Max E2 1.60 1.70 1.80 f 2.50 BSC L 0.30 0.40 0.50 K 0.25 REF R 0.09 0.125 0.15 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. The drawing complies with JEDEC MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 53

EFM8BB2 数据表 QFN20 封装规格 9.2 QFN20 PCB 焊盘布局 Figure 9.2. QFN20 PCB 焊盘布局图 Table 9.2. QFN20 PCB Land Pattern Dimensions Dimension Min Max C1 3.10 C2 3.10 C3 2.50 C4 2.50 E 0.50 X1 0.30 X2 0.25 0.35 X3 1.80 Y1 0.90 Y2 0.25 0.35 Y3 1.80 silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 54

EFM8BB2 数据表 QFN20 封装规格 Dimension Min Max Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 8. A 2 x 2 array of 0.75 mm openings on a 0.95 mm pitch should be used for the center pad to assure proper paste volume. 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 9.3 QFN20 封装标识 PPPP PPPP TTTTTT YYWW # Figure 9.3. QFN20 封装标识 封装标识的组成为 : PPPPPPPP 指定部件编号 TTTTTT 跟踪或生产代码 YY 生产年份的最后 2 位数字 WW 设备生产时的 2 位工作周 # 设备版本 (A B 等 ) silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 55

EFM8BB2 数据表版本历史 10. 版本历史 10.1 Revision 1.6 March 13th, 2017 Updated the language in 1. Feature List to clarify the package offerings for each of the different temperature grades. Corrected the application note number for AN124: Pin Sharing Techniques for the C2 Interface in 5.2 Debug. 10.2 Revision 1.5 October 7th, 2016 Added A-grade parts. Added specifications for 4.1.13 SMBus. Added bootloader pinout information to 3.10 Bootloader. Added CRC Calculation Time to 4.1.4 Flash Memory. Added Thermal Resistance (Junction to Case) for QFN20 packages to 4.2 Thermal Conditions. Added a note linking to the Typical VOH and VOL Performance graphs in 4.1.12 Port I/O. Added 4.1.10 1.8 V Internal LDO Voltage Regulator. Added a note to 3.1 Introduction referencing the Reference Manual. 10.3 Revision 1.4 April 22nd, 2016 Added a reference to AN945: EFM8 Factory Bootloader User Guide in 3.10 Bootloader. Added I-grade devices. Added a note that all GPIO values are undefined when VDD is below 1 V to 4.1.1 Recommended Operating Conditions. Adjusted the Total Current Sunk into Supply Pin and Total Current Sourced out of Ground Pin specifications in 4.3 Absolute Maximum Ratings. 10.4 Revision 1.3 January 7th, 2016 Added 5.2 Debug. Updated 3.10 Bootloader to include information about the bootloader implementation. 10.5 Revision 1.2 Updated Port I/O specifications in 4.1.12 Port I/O to include new V OL specifications. Added a note to Table 4.3 Reset and Supply Monitor on page 18 regarding guaranteed operation. Updated package diagram and landing diagram specifications for the QFN20 package. 10.6 Revision 1.1 Initial release. silabs.com Smart. Connected. Energy-friendly. Rev. 1.4 56

Simplicity Studio One-click access to MCU and wireless tools, documentation, software, source code libraries & more. Available for Windows, Mac and Linux! IoT Portfolio www.silabs.com/iot SW/HW www.silabs.com/simplicity Quality www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. Trademark Information Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, Bluegiga, Bluegiga Logo, Clockbuilder, CMEMS, DSPLL, EFM, EFM32, EFR, Ember, Energy Micro, Energy Micro logo and combinations thereof, "the world s most energy friendly microcontrollers", Ember, EZLink, EZRadio, EZRadioPRO, Gecko, ISOmodem, Micrium, Precision32, ProSLIC, Simplicity Studio, SiPHY, Telegesis, the Telegesis Logo, USBXpress, Zentri and others are trademarks or registered trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders. Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 USA http://www.silabs.com