Micro SD Card TM Product Specification Version 1.0 Information in this document is provided in connection with TwinMOS products. No license, express or implied, by estoppels or otherwise, to any intellectual property rights is granted by this document. Except as provided in TwinMOS's Terms and Conditions of Sale for such products, TwinMOS assumes no liability whatsoever, and TwinMOS disclaims any express or implied warranty, relating to sale and/or use of TwinMOS products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. TwinMOS may make changes to specifications and product descriptions at any time, without notice. Copyright TwinMOS Technology Inc. 2001 1
Table of Contents A. Product Outline.. 3 B. Features.. 4 C. Block Diagram... 5 D. Pin Assignments. 6 E. Physical Specifications... 7 F. DC Characteristics...11 G. AC Characteristics...12 Change History Version Date Description 1.0 24/10/2005 New Release 2
A. Product outline The TwinMOS Micro SD Memory Card is functionally compatible with the SD Memory card but is smaller in dimensions. It can be inserted into a passive SD or minisd memory Card Adapter and operate as an SD Memory Card. TwinMOS Micro SD Card TM is ideal for digital devices designed to use Micro SD Card. It is fully compatible to a new consumer standard, called the Micro SD system standard and meets SDC Physical Layer specification V1.10, and provides error correcting code (ECC) reliability to detect and correct errors automatically. 3
B. Features Support SD memory card specification V1.1 (50Mhz 4bits bus) Fully compatible with SD specification V1.01 Form Factor : 8 Pads MicroSD (Secure Digital) Memory Cards High performance with lower power consumption Powerful support for SD common command, Class 0,2,4,5,6,7,8 Targeted for portable and stationary applications Designed for read-only and read / write cards Card Detection (Insertion /Removal) Card removal during read operation will never harm the content Forward compatibility to MultiMedia Card Supports firmware ISP (in system programming) Single Channel with high performance Operating Voltage range 2.7 3.6V Correction of memory field errors Comfortable erase mechanism Total memory capacity up to 256MBytes High-speed Flash Controller inside Flash Memory Support Samsung/ST-Micro/Hynix SLC NAND type Flash 4
C. Block Diagram Memory core Power on Detection reset reset Memory core interface Flash & Card Controller (SM264) SCR CSD DSR RCA CID OCR DAT0 DAT1 CLK Vss CD/DAT3 CMD DAT2 Vdd 5
D. Pin Assignments Figure : Contact Area Pin# SD Mode SPI Mode Name Type 1 Description Name Type Description 1 DAT2 I/O/PP Data Line [Bit 2] RSV Reserved 2 CD/DAT3 2 I/O/PP 3 Card Detect / CS I 3 Chip Select (neg true) Data Line [Bit 3] 3 CMD PP Command/Response DI I Data In 4 V DD S Supply voltage V DD S Supply voltage 5 CLK I Clock SCLK I Clock 6 V SS S Supply voltage ground V SS S Supply voltage ground 7 DAT0 I/O/PP Data Line [Bit 0] DO O/PP Data Out 8 DAT1 I/O/PP Data Line [Bit 1] RSV Reserved Table : microsd Contact Pad Assignment 1) S: power supply; I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers ; 2) The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after SET_BUS_WIDTH command. The Host shall keep its own DAT1-DAT3 lines in input mode, as well, while they are not used. It is defined so, in order to keep compatibility to MultiMediaCards. 3) After power up this line is input with 50KOhm pull-up (can be used for card detection or SPI mode selection). The pull-up should be disconnected by the user, during regular data transfer, with SET_CLR_CARD_DETECT (ACMD42) command Function / Electrical Characteristics / Registers Refer to the SD Memory Card Specifications Part 1 Physical Layer Specification Version 1.10. 6
E. Physicial Specifications E-1. Mechanical Form Factor A VIEW A B1 Figure E-1 : Mechanical Description: Top View DETAIL A 7
Figure E-2 : Mechanical Description: Bottom View 8
KEEP OUT AREA Figure E-4 : Mechanical Description: Keep Out Area 9
COMMON DIMENSIONS Notes: SYMBOL MIN NOM MAX NOTE A 10.90 11.00 11.10 1. DIMENSIONING AND TOLERANCING PER A1 9.60 9.70 9.80 ASME Y14.5M-1994. A2-3.85 - BASIC A3 7.60 7.70 7.80 2. DIMENSIONS ARE IN MILLIMETERS. A4-1.10 - BASIC A5 0.75 0.80 0.85 3. COPLANARITY IS ADDITIVE TO C1 MAX A6 - - 8.50 THICKNESS. A7 0.90 - - A8 0.60 0.70 0.80 A9 0.80 - - B 14.90 15.00 15.10 B1 6.30 6.40 6.50 B2 1.64 1.84 2.04 B3 1.30 1.50 1.70 B4 0.42 0.52 0.62 B5 2.80 2.90 3.00 B6 5.50 - - B7 0.20 0.30 0.40 B8 1.00 1.10 1.20 B9 - - 9.00 B10 7.80 7.90 8.00 B11 1.10 1.20 1.30 C 0.90 1.00 1.10 C1 0.60 0.70 0.80 C2 0.20 0.30 0.40 C3 0.00-0.15 D1 1.00 - - D2 1.00 - - D3 1.00 - - R1 0.20 0.40 0.60 R2 0.20 0.40 0.60 R3 0.70 0.80 0.90 R4 0.70 0.80 0.90 R5 0.70 0.80 0.90 R6 0.70 0.80 0.90 R7 29.50 30.00 30.50 R10-0.20 - R11-0.20 - R17 0.10 0.20 0.30 R18 0.20 0.40 0.60 R19 0.05-0.20 Table : microsd Package: Dimensions 10
F. DC Characteristics Symbol PARAMETER CONDITIONS MIN TYP MAX UNITS V IL Input low voltage V SS 0.3 0.25V CC V V IH Input high voltage 0.625V CC V CC + 0.3 V V OL Output low voltage I OL = 100μA 0.125V CC V @ V CC _min V OH Output high voltage I OH = -100μA 0.75V CC V @ V CC _min I IN Input leakage current V IN = V CC or 0-10 +/- 1 10 μa I OUT Tri-state output leakage current I STBY Standby current 3.3V@clock 0.3 0.6 ma stop I OP Operation current 3.3V@25MHz 15 25 ma (Write) 3.3V@25MHz (Read) I OP Operation current 3.3V@50MHz 30 45 ma (Write) 3.3V@50MHz (Read) -10 +/- 1 15 30 10 25 45 μa ma ma 11
G. AC Characteristics G -1 Bus Timing (Default Mode) SYMBOL PARAMETER MIN MAX UNIT Note F SD SD clock frequency 0 25 MHz t WL Clock low time 10 ns t WH Clock high time 10 ns t TLH Clock rise time 10 ns t THL Clock fall time 10 ns t ISU Input setup time 5 ns t IH Input hold time 5 ns t ODLY Output delay time 0 14 ns 12
G -2 Bus Timing (High-speed Mode) SYMBOL PARAMETER MIN MAX UNIT Note F SD SD clock frequency 0 25 MHz t WL Clock low time 10 ns t WH Clock high time 10 ns t TLH Clock rise time 10 ns t THL Clock fall time 10 ns t ISU Input setup time 5 ns t IH Input hold time 5 ns t ODLY Output delay time 0 14 ns t OH Output hold time 2.5 ns 13