查询 5962-8964601PA 供应商 a FEATURES AC PERFORMANCE Small Signal Bandwidth: 80 MHz (A V = 1) Slew Rate: 450 V/ s Full Power Bandwidth: 6.8 MHz at 20 V p-p, R L = 500 Fast Settling: for 10 V Step: 110 ns to 0.01%, 80 ns to 0.1% Differential Gain: <0.01% @ 4.4 MHz Differential Phase: <0.028 @ 4.4 MHz Total Harmonic Distortion (THD): 0.0005% @ 100 khz Open-Loop Transimpedance: 200 M Input Voltage Noise: 2 nv/ Hz DC PERFORMANCE Input Offset Voltage: 75 V max (B Grade) Input Offset Drift: 3.5 V/ C max (B Grade) Quiescent Supply Current: 6.5 ma max APPLICATIONS High Speed DAC Buffers Multiflash ADC Error Amplifiers Flash ADC Buffers Coaxial Cable Drivers High Performance Audio Circuitry Available in Plastic Mini-DIP, Hermetic Cerdip, and Plastic SOIC (A) Package MIL-STD-883B Part Available PRODUCT DESCRIPTION The is a monolithic, very high speed operational amplifier offering high performance. Although technically classed as a current-feedback or transimpedance amplifier, it may be used in much the same way as traditional op amps while providing significant performance benefits. Employing Analog Devices junction isolated complementary bipolar (CB) process, the achieves true 12-bit (0.01%) precision on critical ac and dc parameters, a level of performance unmatched by amplifiers fabricated using either the dielectrically isolated (DI) or other bipolar processes. The offers significant advantages over conventional high speed operational amplifiers. It maintains a nearly constant bandwidth and settling time to 0.01% over a wide range of closed-loop gains. This makes the ideal for amplifying the residue in multiple-pass analog-to-digital converters. Other advantages include: low input errors and high open-loop transresistance (200 MΩ) into a 500 Ω load, ensuring true 12-bit dc accuracy for closed-loop gains from 1 to gains greater than 100. This combination of ac and dc performance makes the an excellent choice for buffering precision high speed DACs and flash ADCs. 捷多邦, 专业 PCB 打样工厂,24 小时加急出货 450 V/ s, Precision, Current-Feedback Op Amp CONNECTION DIAGRAMS Plastic Mini-DIP (N) Package and Cerdip (Q) Package SOIC (R) Package NC 1 NC 2 INPUT 3 NC 4 +INPUT 5 NC 6 V S 7 NC 8 + TOP VIEW (Not to Scale) NC = NO CONNECT 16 NC 15 NC 14 +V S 13 NC 12 OUTPUT 11 COMPENSATION 10 NC 9 NC The is available in three performance grades. The A and B are rated over the industrial temperature range of 40 C to +85 C. The S is rated over the full military temperature range of 55 C to +125 C and is available processed to MIL-STD-883B, Rev C. The is available in two types of 8-lead packages: plastic mini-dip and hermetic cerdip. The AR-16 is available in the 16-lead SOIC package. A and S grade chips are also available. PRODUCT HIGHLIGHTS 1. The achieves settling times of 110 ns to 0.01% for gains of 1 to 10, with a 450 V/µs slew rate, while consuming only 5 ma of supply current. 2. For closed-loop gains of 1 to 100, the high speed performance of the is achieved without sacrificing full 12-bit dc precision. 3. The is well suited to line driver and video buffer applications where the properties of low distortion and high slew rate are required. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
SPECIFICATIONS (@ +25 C and 15 V dc, unless otherwise noted) A B S Model Conditions Min Typ Max Min Typ Max Min Typ Max Units INPUT OFFSET VOLTAGE 1 Initial 25 200 25 75 25 200 µv T MIN T MAX 50 350 50 125 100 350 µv vs. Temperature 0.8 5 0.8 3.5 1 5.5 µv/ C vs. Supply (PSRR) 5 V 18 V 2 Initial 110 125 120 125 110 125 db T MIN T MAX 110 120 116 120 94 116 db vs. Common Mode (CMRR) V CM = ± 10 V Initial 110 125 120 125 110 125 db T MIN T MAX 110 120 116 120 94 116 db INPUT BIAS CURRENT 3 Input Bias Current Initial 150 450 100 250 150 450 na T MIN T MAX 450 1200 400 750 1000 1500 na vs. Temperature 6 20 6 17 9 20 na/ C vs. Supply 5 V 18 V 2 Initial 9 15 9 10 9 15 na/v T MIN T MAX 11 20 11 15 11 25 na/v vs. Common Mode V CM = ± 10 V Initial 5 10 3 5 5 10 na/v T MIN T MAX 5 15 3 7 5 20 na/v +Input Bias Current Initial 3 15 3 5 3 15 µa T MIN T MAX 4 20 4 7 5 20 µa vs. Temperature 15 80 15 45 15 80 na/ C vs. Supply 5 V 18 V 2 Initial 5 15 5 10 5 15 na/v T MIN T MAX 5 20 5 15 5 20 na/v vs. Common Mode V CM = ± 10 V Initial 5 15 3 10 5 15 na/v T MIN T MAX 5 15 3 10 5 20 na/v INPUT CHARACTERISTICS Input Resistance Input 50 50 50 Ω +Input 10 10 10 kω Input Capacitance Input 2 2 2 pf +Input 2 2 2 pf INPUT VOLTAGE RANGE Common Mode ± 10 ± 10 ± 10 V INPUT VOLTAGE NOISE F = 1 khz 2 2 2 nv/ Hz Input Current Noise Input 1 khz 20 20 20 pa/ Hz +Input 1 khz 6 6 6 pa/ Hz OPEN LOOP TRANSRESISTANCE V OUT = ± 10 V R LOAD = 500 Ω 100 200 150 200 100 200 MΩ T MIN T MAX 50 75 50 MΩ OUTPUT CHARACTERISTICS Voltage R LOAD = 500 Ω 10 10 10 V Current Short Circuit 65 65 65 ma Output Resistance Open Loop 16 16 16 Ω FREQUENCY RESPONSE Small Signal Bandwidth A V = 1 R F = 1k 80 80 80 MHz ( 3 db) A V = 10 R F = 875 Ω 31 31 31 MHz A V = 30 R F = 875 Ω 15 15 15 MHz Full Power Bandwidth 4 V OUT = 20 V p-p R I = 500 Ω 6.8 6.8 6.8 MHz Rise Time A V = 1 110 10 10 ns Overshoot A V = 1 20 20 20 % Slew Rate A V = 1 450 450 450 V/µs Settling Time 10 V Step, A V = 1 to 0.1% 80 80 80 ns to 0.01% 110 110 110 ns TOTAL HARMONIC DISTORTION 5 F = 100 khz 0.0005 0.0005 0.0005 %
A B S Model Conditions Min Typ Max Min Typ Max Min Typ Max Units DIFFERENTIAL GAIN F = 4.4 MHz, R L = 100 Ω 0.01 0.01 0.01 % DIFFERENTIAL PHASE F = 4.4 MHz, R L = 100 Ω 0.028 0.028 0.028 Degrees POWER SUPPLY Rated Performance ± 15 ± 15 ± 15 V Operating Range ± 5 18 ± 5 18 5 18 V Quiescent Current T MIN T MAX 5 6.5 5 6.5 5 7 ma TRANSISTOR COUNT 72 72 72 NOTES 1 Input Offset Voltage Specifications are guaranteed after 5 minutes at T A = +25 C. 2 Test Conditions: +V S = 15 V, V S = 5 V to 18 V and +V S = 5 V to 18 V, V S = 15 V. 3 Bias Current Specifications are guaranteed maximum after 5 minutes at T A = +25 C. 4 FPBW = Slew Rate/2 π V PEAK. 5 Total Harmonic Distortion. All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage............................... ± 18 V Internal Power Dissipation 2 Plastic Package.............................. 1.5 W Cerdip Package............................. 1.3 W Common-Mode Input Voltage, Max Safe....... V S 3 V Output Short Circuit Duration................ Indefinite Differential Input Voltage....................... ± 1 V Continuous Input Current Inverting or Noninverting.................... 2.0 ma Storage Temperature Range (Q)......... 65 C to +150 C Storage Temperature Range (N)......... 65 C to +125 C Storage Temperature Range (R)......... 65 C to +125 C Operating Temperature Range A/B........................ 40 C to +85 C S.......................... 55 C to +125 C Lead Temperature Range (Soldering 60 sec)....... +300 C ESD Rating................................. 3500 V NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Maximum internal power dissipation is specified so that T J does not exceed +175 C at an ambient temperature of +25 C, derate cerdip (Q) package at 8.7 mw/ C and plastic (N) package at 10 mw/ C. Plastic Package: θ JA = 100 C/Watt, θ JC = 33 C/W. Cerdip Package: θ JA = 110 C/Watt, θ JC = 30 C/W. SOIC Package: θ JA = 100 C/Watt, θ JC = 33 C/W. ORDERING GUIDE Package Model 1 Temperature Range Option 2 AN 40 C to +85 C N-8 BN 40 C to +85 C N-8 AQ 40 C to +85 C Q-8 BQ 40 C to +85 C Q-8 SQ 55 C to +125 C Q-8 SQ/883B 55 C to +125 C Q-8 5962-8964601PA 55 C to +125 C Q-8 AR-16 40 C to +85 C R-16 AR-16-REEL 40 C to +85 C R-16 NOTES 1 A and S grade chips are also available. 2 N = Plastic DIP Package; Q = Cerdip Package, R = SOIC Package METALIZATION PHOTOGRAPH Dimensions shown in inches and (mm). Consult factory for latest dimensions.
Typical Characteristics Figure 1. Input Voltage Swing vs. Supply Figure 2. Output Voltage Swing vs. Supply Figure 3. Quiescent Current vs. Supply Voltage Figure 4. Quiescent Supply Current vs. Temperature Figure 5. Output Voltage Swing vs. Resistive Load Figure 6. Large Signal Frequency Response Figure 7. Open-Loop Transimpedance vs. Supply Figure 8. Positive Input Bias Current vs. Common-Mode Voltage Figure 9. Negative Input Bias Current vs. Common-Mode Voltage
Figure 10. Positive Input Bias Current vs. Temperature Figure 11. Negative Input Bias Current vs. Temperature Figure 12. Power Supply Rejection vs. Frequency Figure 13. Common-Mode Rejection vs. Frequency Figure 14. Input Noise Voltage Spectral Density Figure 15. Inverting Input Noise Current Spectral Density Figure 16. Short Circuit Current Limit vs. Temperature Figure 17. Slew Rate vs. Temperature Figure 18. Slew Rate vs. Input Error Signal
Typical Characteristics, Inverting Gain of 1 Figure 19a. Inverting Amplifier, Gain of 1 Figure 19b. Large Signal Pulse Response, Gain of 1 Figure 20. Normalized Output Amplitude vs. Frequency vs. Load Figure 21. Phase Shift vs. Frequency Figure 22. Total Harmonic Distortion vs. Frequency Figure 23. Settling Time vs. Step Size Figure 24. 3 db Bandwidth vs. Supply Voltage Figure 25. Output Impedance vs. Frequency Figure 26. 3 db Bandwidth vs. Temperature
Typical Characteristics, Inverting Gain of 10 Figure 27a. Inverting Amplifier, Gain of 10 Figure 27b. Large Signal Pulse Response, Gain of 10 Figure 28. Normalized Output Amplitude vs. Frequency vs. Load Figure 29. Phase vs. Frequency vs. Load Figure 30. Harmonic Distortion vs. Frequency Figure 31. Settling Time vs. Step Size Figure 32. 3 db Bandwidth vs. Supply Voltage Figure 33. Output Impedance vs. Frequency Figure 34. 3 db Bandwidth vs. Temperature
POWER SUPPLY CONSIDERATIONS The power supply connections to the must maintain a low impedance to ground over a bandwidth of 40 MHz or more. This is especially important when driving a significant resistive or capacitive load, since all current delivered to the load comes from the power supplies. Multiple high quality bypass capacitors are recommended for each power supply line in any critical application. A 0.1 µf ceramic and a 2.2 µf electrolytic capacitor as shown in Figure 35 placed as close as possible to the amplifier (with short lead lengths to power supply common) will assure adequate high frequency bypassing, in most applications. A minimum bypass capacitance of 0.1 µf should be used for any application. Figure 37. Overload Recovery Test Circuit Figure 35. Recommended Power Supply Bypassing THEORY OF OPERATION The differs from conventional operational amplifiers in that it is a transimpedance device rather than a conventional voltage amplifier. Figure 36 is a simplified schematic of the. The input stage consists of a pair of transistors, Q1 and Q2, which are biased by two diode-connected transistors, Q3 and Q4. Transistors Q1 and Q2 have their emitters connected together, and this common point functions as the inverting input of the amplifier. Correspondingly, the common connection of the two biasing diodes acts as the noninverting input. Figure 36. Simplified Schematic When operated as a closed-loop amplifier, feedback error current, I IN : flows into the inverting input terminal and is conveyed via current mirrors (transistors Q5, Q6, Q7, and Q8) to the compensation capacitor, C COMP. The voltage developed across C COMP is buffered by the output stage, consisting of transistors Q9 Q12. Figure 38. Overload Recovery Time Photo Because the input error signal developed is in the form of a current, not a voltage, the differs from conventional operational amplifiers. This also means that, unlike most operational amplifiers which rely on negative feedback to produce a virtual ground at the inverting input terminal, this terminal explicitly has a low impedance. A unique circuit approach allows the to realize an openloop transimpedance of close to 200 MΩ. This is nearly three orders of magnitude greater than that of any other operational transimpedance amplifier and results in extremely high levels of dc precision. As an example, the output voltage gain error is approximately equal to the value of the feedback resistor divided by the value of the open-loop transimpedance of the amplifier. That is, when using a 1 kω feedback resistor, this error is one part in 200,000. For a transimpedance amplifier with 1 MΩ transimpedance, this error is only one part in 1000; such an amplifier would barely be able to achieve 10-bit precision. Figure 39 is a simplified three-terminal model for the. Figure 40 is a simplified three-terminal model for a conventional voltage op amp. The action of current feedback serves to modify the behavior of the amplifier under closed-loop conditions. The feedback resistor, R F, is somewhat analogous to the input stage transconductance of a conventional voltage amplifier; and therefore, if the value of R F is held constant, the closed-loop bandwidth also remains virtually constant, independent of closed-loop voltage gain.
A simple equation can, therefore, be used to determine the bandwidth of an amplifier employing the in the inverting configuration. 3 db Bandwidth = 23 R F + 0.05 1+ G ( ) Figure 39. Three-Terminal Model where: The 3 db bandwidth is in MHz G is the closed-loop inverting gain of the R F is the feedback resistance in kω. NOTE: This equation applies only for values of R F between 10 kω and 100 kω, and for R LOAD greater than 500 Ω. For R F = 1 kω the bandwidth should be estimated from Figure 41. Figure 41 illustrates the closed-loop voltage gain vs. frequency of the for various values of feedback resistor. For comparison purposes, the characteristic of a conventional amplifier having an 80 MHz unity gain bandwidth is also shown. Figure 40. Op Amp Three-Terminal Model A more detailed examination of the closed-loop transfer function of the results in the following equation: Closed-Loop Gain G(s) = R F R S 1+ C COMP R F + 1+ R F R S R IN s Compare this to the equation for a conventional op amp: Closed-Loop Gain G(s) = R F R S 1+ C COMP 1+ R F g M R S s where: C COMP is the internal compensation capacitor of the amplifier; g M is the input stage transconductance of the amplifier. In the case of the voltage amplifier, the closed-loop bandwidth decreases directly with increasing values of (1 + R F /R S ), the closed-loop gain. However, for the transimpedance amplifier, the situation is different. At low gains, where (1 + R F /R S ) R IN is small compared to R F, the closed-loop bandwidth is controlled by the internal compensation capacitance of 7 pf and the value of R F, and not by the closed-loop gain. At higher gains, where (1 + R F /R S ) R IN is much larger than R F, the behavior is that of a conventional operational amplifier in which the input stage transconductance is equal to the inverting terminal input impedance of the transimpedance amplifier (R IN = 50 Ω). Figure 41. Closed-Loop Voltage Gain vs. Bandwidth for Various Values of R F For the case where R F = 1 kω and R S = 100 Ω (closed-loop gain of 10), the closed-loop bandwidth is approximately 28 MHz. It should also be noted that the use of a capacitor to shunt R F, a normal practice for stabilizing conventional op amps, will cause this amplifier to become unstable because the closed-loop bandwidth will increase beyond the stable operating frequency. A similar approach can be taken to calculate the noise performance of the amplifier. A simplified noise model is shown in Figure 42. The equivalent mean-square output noise voltage spectral density will equal: ( ) 2 + 1+ R F V ON 2 = R F I NN R + 4 kt R F F +1 R S R S 2 [V 2 N + ( R P I NP ) 2 + 4 kt R P ]
Where: R P is the external resistance placed in series with the noninverting input R F is the feedback resistor R S is the source resistor I NN is the noise current in the inverting input I NP is the noise current in the noninverting input V N is the input noise voltage. Typical values for these parameters (@ 1 khz) in pa/ Hz are: I NN = 20, I PN = 6, V N = 2. Or, referring to the signal input, the equivalent mean-square input voltage noise is: V 2 IN = ( R F I NN ) 2 + 1+ R 2 S R V 2 N + R P I NP F ( ) 2 + 4 kt R P + 4 kt R S 1+ R S R F Resistor R P is required for both inverting and noninverting (follower) operation, to insure stable operation. The amplifier s noninverting input current (flowing through R P of 100 Ω) will typically add less than 300 µv to the s input offset voltage. This can be trimmed-out using the optional network shown in Figure 44. The following table gives recommended values for R P. Recommended Supply Voltage Gain (R F /R S ) Value for R F 6 V to 15 V 1 10 100 Ω 6 V to 15 V 10 20 47 Ω 6 V to 15 V 20 200 0 Ω 5 V 1 10 47 Ω 5 V 10 200 0 Ω (R F = 1 kω, R S = 10 Ω) it will be 4 MHz. At gains of 3 or greater, a small capacitor (2 pf 5 pf) connected across the feedback resistor will help reduce overshoot; but when operating at noninverting gains below 3, this same capacitance will cause instability. Figure 43. Noninverting Amplifier Configuration USING THE COMPENSATION PIN OF THE Additional compensation may be provided for the by applying an external capacitance between Pin 5 and analog ground (Figure 44). The nominal value of the s internal compensation capacitor is 7 pf. For a given value of feedback resistance (R F ), any added external capacitance reduces the amplifier s slew rate and bandwidth proportionally. Figure 42. Op Amp Simplified Noise Model NONINVERTING GAIN OPERATION The can be used as a noninverting amplifier or voltage follower, operating at gains between 1 and 200. A minimum value of R F equal to 1 kω should be employed. For low gains (1 to 2), the input signal should be applied to the s noninverting input through a 100 Ω series resistor; this will help reduce peaking. The best transient response will occur when the amplifier s output level is below 5 V peak to peak. At closed-loop gains of 3 or more, the input resistor is not required unless peak signals greater than 3 V will be applied. The amplifier s bandwidth can be determined by using the inverting amplifier s bandwidth equation or from Figure 41. For example, at a gain of + 10 (R F = 1 kω, R S = 100 Ω) the bandwidth of the Figure 44. Inverting Amplifier Showing External Compensation Connection, R P and Optional V OS Trim In addition to providing for external compensation, Pin 5 may be used to clamp the output of the amplifier, as shown in Figure 45. The output can be clamped anywhere within the output range (approximately ± 10 V) of the amplifier. The input should also be clamped as a precaution against damaging the amplifier s input transistors. Figure 45. Used as a Clamped Amplifier
This compensation node may also be used as an additional output terminal as in the precision transconductance amplifier application of Figure 46. Figure 46. A Precision Transconductance Amplifier The can be used in either the inverting transconductance mode as shown in Figure 46, or in a noninverting mode with R S grounded and V IN applied to the noninverting terminal. The current output is essentially constant over a compliance range of ± 10 V at the compensation node. The output current (from Pin 5) is limited to about ± 1 ma due to internal saturation. Under these circumstances the normal output pin provides a buffered version of the compensation node output voltage. Output load impedance of 500 Ω or greater will not affect the accuracy of the transconductance conversion. THE IN A 2 MHz, 12-BIT SUBRANGING A/D CONVERTER CIRCUIT The combination of fast settling times at high gains and low dc errors make the ideal for use as an error amplifier in high speed, 12-bit subranging A-D applications. In the circuit of Figure 47, an AD842 serves as an input amplifier. First pass conversion is accomplished, in a straightforward manner, determining the top 7 bits. The latch then holds these top 7 bits which are applied to a 7 bit, 12-bit accurate DAC and also to the highest 7 bits of the adder (note that a sample-and-hold should be used ahead of this converter to minimize errors due to its 500 ns acquisition time). In the second pass, the input switches S1 and S2 and S3 are set to state 2. The DAC output is then subtracted from the input signal and the resulting difference is then amplified by an gain of 32 follower. This gain, together with a 1/64th scale offset, insures a unipolar residue which can be converted by the flash A-D. Conversion is accomplished via switches S1, S2 and S3 in state 1. Switch S1 connects the input signal of the residue amplifier to ground which minimized overload recovery time. THE AS AN OPEN-LOOP LEVEL SHIFTER The can also be used for open-loop level shifting. As shown in Figure 48, resistor R S is used to develop an input current which is proportional to the input voltage, V IN. This current flows from the compensation node (Pin 5) developing a voltage across resistor R C (R C is equal in value to resistor R S ) which, rather than being grounded, has one end tied to reference voltage V2. The voltage appearing at Pin 5 is, therefore, voltage V IN plus voltage V2 and will directly follow changes in V IN. By scaling resistor R C, a level shift with voltage gain can be produced. In addition, the normal voltage output at Pin 6 is approximately equal to the voltage at Pin 5 thus providing a low impedance, buffered output for the level shifter. Figure 48. Connected as a Level Shift Amplifier THE AS A HIGH SPEED DAC BUFFER The will enable the AD568 12-bit DAC to develop a 10 V output step which settles to within 0.025 percent of itsfinal value in about 100 ns. This /AD568 combination is shown in the circuit of Figure 49. Correct power supply decoupling is essential: a 2.2 µf tantalum capacitor connected in parallel with a 0.1 µf to 0.01 µf ceramic disc capacitor is usually sufficient. These should be placed as close to the power supply pins as possible. Also, a ground plane should be employed; this ensure that there is a low impedance signal path to ground which allows the fastest possible output settling. In 12-bit systems with the operating at gains of 10 or less, inadequate supply decoupling can cause the output settling to degrade from 100 ns to as much as 300 ns, with a 10 V output step applied. Figure 47. Block Diagram of a 2 MHz, 12-Bit Subranging Figure 49. The Serving as a DAC Buffer
OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic Mini-DIP (N) Package SEATING PLANE 0.165 0.01 (4.19 0.25) 0.125 (3.18) MIN 8 0.018 0.003 0.46 0.08 0.39 (9.91) MAX 0.10 (2.54) TYP 5 1 4 0.25 (6.35) 0.31 (7.87) 0.035 0.01 (0.89 0.25) 0.033 (0.84) NOM 0.18 0.03 (4.57 0.76) 0-15 0.30 (7.62) REF 0.011 0.003 (0.28 0.08) C1155 0 5/00 (rev. C) 00898 Cerdip (Q) Package 0.005 (0.13) MIN 0.055 (1.4) MAX 0.25 (0.64) 8 5 1 4 0.220 (5.59) 0.310 (7.87) SEATING PLANE 0.20 (5.08) MAX 0.125 (3.18) 0.200 (5.08) 0.014 (0.36) 0.023 (0.58) 0.405 (10.29) MAX 0.015 (0.38) 0.06 (1.52) 0.1 0.03 (1.76) (2.54) 0.07 (0.78) BSC 0.150 (3.81) MIN 0-15 0.290 (7.37) 0.320 (8.13) 0.008 (0.20) 0.015 (0.38) R-16 Package 0.4133 (10.50) 0.3977 (10.00) 16 9 1 8 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) PIN 1 0.0118 (0.30) 0.0040 (0.10) 0.050 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) SEATING PLANE 0.0125 (0.32) 0.0091 (0.23) 8 0 0.0291 (0.74) 45 0.0098 (0.25) 0.0500 (1.27) 0.0157 (0.40) PRINTED IN U.S.A.