查询 供应商 捷多邦, 专业 PCB 打样工厂,24 小时加急出货 2-Bit Analog-to-Digital Converter For Bridge Sensors FEATURES DESCRIPTION Complete Front-End for Bridge Sensor The is a precision 2-bit analog-to-digital Onboard PGA with Gain of 64 or 128 converter (ADC). With an onboard low-noise Onboard Oscillator programmable gain amplifier (PGA), onboard oscillator, and precision 2-bit delta-sigma ADC, the RMS Noise: provides a complete front-end solution for 4nV at 1SPS (G = 128) bridge sensor applications including weigh scales, 88nV at 8SPS (G = 128) strain gauges, and pressure sensors. 18-Bit Noise-Free Resolution The low-noise PGA has a gain of 64 or 128, Selectable 1SPS or 8SPS Data Rates supporting a full-scale differential input of ±39mV or Simultaneous 5Hz and 6Hz Rejection at ±19.5mV, respectively. The delta-sigma ADC has 1SPS 2-bit effective resolution and is comprised of a 3rd-order modulator and 4th-order digital filter. Two External Voltage Reference up to 5V for data rates are supported: 1SPS (with both 5Hz Ratiometric Measurements and 6Hz rejection) and 8SPS. The can Simple, Pin-Driven Control be clocked by the internal oscillator or an external Two-Wire Serial Digital Interface clock source. Offset calibration is performed on-demand, and the can be put in a Tiny 16-pin TSSOP Package low-power standby mode or shut off completely in Supply Range: 2.7V to 5.3V power-down mode. 4 C to +85 C Temperature Range All of the features of the are controlled by APPLICATIONS Weigh Scales Strain Gauges Pressure Sensors Industrial Process Control dedicated pins; there are no digital registers to program. Data are output over an easily-isolated serial interface that connects directly to the MSP43 and other microcontrollers. The is available in a TSSOP-16 package and is specified from 4 C to +85 C. AVDD CAP REFP REFN DVDD Gain = 64 or 128 PDWN AINP AINN PGA ADC DRDY/DOUT Internal Oscillator SPEED AGND GAIN CAP CLKIN DGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Copyright 26, Texas Instruments Incorporated
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT AVDD to AGND.3 to +6 V DVDD to DGND.3 to +6 V AGND to DGND.3 to +.3 V Input Current 1, Momentary ma 1, Continuous ma Analog Input Voltage to AGND.3 to AVDD +.3 V Digital Input Voltage to DGND.3 to DVDD +.3 V Maximum Junction Temperature +15 C Operating Temperature Range 4 to +85 C Storage Temperature Range 6 to +15 C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 Submit Documentation Feedback
ELECTRICAL CHARACTERISTICS All specifications at T A = 4 C to +85 C, AVDD = DVDD = REFP = +5V, REFN = AGND, and Gain = 64, unless otherwise noted. Analog Inputs PARAMETER CONDITIONS MIN TYP MAX UNIT Full-Scale Input Voltage (AINP AINN) ±.5V REF /PGA V Common-Mode Input Range AGND + 1.5V AVDD 1.5V V Differential Input Current ±2 na System Performance Resolution No Missing Codes 2 Bits Data Rate Internal Oscillator, SPEED = High 69.5 8 86.4 SPS Internal Oscillator, SPEED = Low 8.68 1 1.8 SPS External Oscillator, SPEED = High f CLK /61,44 SPS External Oscillator, SPEED = Low f CLK /491,52 SPS Digital Filter Settling Time Full Settling 4 Conversions Integral Nonlinearity (INL) Differential Input, End-Point Fit, G = 64 ±1 ppm Differential Input, End-Point Fit, G = 128 ±6 ppm Input Offset Error (1) ±3 ppm of FS Input Offset Drift ±1 nv/ C Gain Error ±.8 % Gain Drift ±4 ppm/ C Normal-Mode Rejection (2) Internal Oscillator, f DATA = 1SPS 9 db External Oscillator, f DATA = 1SPS f IN = 5Hz or 6Hz, ±1Hz 1 db Common-Mode Rejection at DC, VDD =.1V 11 db Input-Referred Noise f DATA = 1SPS 53 nv, rms f DATA = 8SPS 1 nv, rms Power-Supply Rejection at DC, VDD =.1V 9 1 db Voltage Reference Input Voltage Reference Input (V REF ) V REF = REFP REFN 1.5 AVDD AVDD +.1V V Negative Reference Input (REFN) AGND.1 REFP 1.5 V Positive Reference Input (REFP) REFN + 1.5 AVDD +.1 V Voltage Reference Input Current 1 na Digital All digital inputs except CLKIN.7 DVDD DVDD +.1 V V IH CLKIN.7 DVDD 5.1 V Logic Levels V IL DGND.2 DVDD V V OH I OH = 1mA DVDD.4 V V OL I OL = 1mA.2 DVDD V Input Leakage < V IN < DVDD ±1 µa External Clock Input Frequency (f CLKIN ).2 4.9152 6 MHz Serial Clock Input Frequency (f ) 5 MHz (1) Offset calibration can minimize these errors to the level of noise at any temperature. (2) Specification is assured by the combination of design and final production test. Submit Documentation Feedback 3
ELECTRICAL CHARACTERISTICS (continued) All specifications at T A = 4 C to +85 C, AVDD = DVDD = REFP = +5V, REFN = AGND, and Gain = 64, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNIT Power Supply Power-Supply Voltage (AVDD, DVDD) 2.7 5.3 V Normal Mode, AVDD = 3V 9 14 µa Analog Supply Current Normal Mode, AVDD = 5V 9 14 µa Standby Mode.1 1 µa Power-Down.1 1 µa Normal Mode, DVDD = 3V 6 1 µa Normal mode, DVDD = 5V 95 14 µa Digital Supply Current Standby Mode, = High, DVDD = 3V 45 65 µa Standby Mode, = High, DVDD = 5V 65 8 µa Power-Down.2 µa Normal Mode, AVDD = DVDD = 3V 2.9 4.5 mw Power Dissipation, Total Normal Mode, AVDD = DVDD = 5V 5. 7.7 mw Standby Mode, AVDD = DVDD = 5V.3.4 mw 4 Submit Documentation Feedback
PIN CONFIGURATION PW PACKAGE TSSOP-16 (Top View) DVDD 1 16 DRDY/DOUT DGND 2 15 CLKIN 3 14 PDWN GAIN CAP 4 5 13 12 SPEED AVDD CAP 6 11 AGND AINP 7 1 REFP AINN 8 9 REFN ANALOG/DIGITAL NAME TERMINAL INPUT/OUTPUT DESCRIPTION PIN DESCRIPTIONS DVDD 1 Digital Digital Power Supply: 2.7V to 5.3V DGND 2 Digital Digital Ground CLKIN 3 Digital/Digital Input External Clock Input: typically 4.9152MHz. Tie low to activate internal oscillator. GAIN 4 Digital Input PGA Gain Select GAIN PGA 64 1 128 CAP 5 Analog Gain Amp Bypass Capacitor Connection CAP 6 Analog Gain Amp Bypass Capacitor Connection AINP 7 Analog Input Positive Analog Input AINN 8 Analog Input Negative Analog Input REFN 9 Analog Input Negative Reference Input REFP 1 Analog Input Positive Reference Input AGND 11 Analog Analog Ground AVDD 12 Analog Analog Power Supply, 2.7V to 5.3V SPEED 13 Digital Input Data Rate Select: SPEED DATA RATE 1SPS 1 8SPS PDWN 14 Digital Input Power-Down: Holding this pin low powers down the entire converter and resets the ADC. Serial Clock: Clock out data on the rising edge. Also used to initiate Offset Calibration and Sleep 15 Digital Input modes. See the Offset Calibration, Standby Mode, and Standby Mode with Offset Calibration sections for more details. Dual-Purpose Output: DRDY/DOUT 16 Digital Output : Indicates valid data by going low. Data Output: Outputs data, MSB first, on the first rising edge of. Submit Documentation Feedback 5
NOISE PERFORMANCE The offers outstanding noise performance. Table 1 summarizes the typical noise performance with inputs shorted externally for different data rates and voltage reference values. The RMS and Peak-to-Peak noise are referred to the input. The effective number of bits (ENOB) is defined as: ENOB = ln (FSR/RMS noise)/ln(2) The Noise-Free Bits are defined as: Noise-Free Bits = ln (FSR/Peak-to-Peak Noise)/ln(2) Where: FSR (Full-Scale Range) = V REF /Gain. Table 1. Noise Performance for AV DD = 5V and V REF = 5V RMS NOISE PEAK-TO-PEAK NOISE (1) ENOB DATA RATE GAIN (nv) (nv) (RMS) NOISE-FREE BITS 1 8 (1) Peak-to-peak data are based on direct measurement. 64 53 29 2.5 18 128 4 198 19.8 17.5 64 1 48 19.5 17.3 128 88 48 18.7 16.3 Table 2. Noise Performance for AV DD = 3V and V REF = 3V RMS NOISE PEAK-TO-PEAK NOISE (1) ENOB DATA RATE GAIN (nv) (nv) (RMS) NOISE-FREE BITS 1 8 (1) Peak-to-peak data are based on direct measurement. 64 46 29 2.6 18 128 49 259 19.6 17.2 64 1 576 19.5 17 128 12 461 18.5 16.3 6 Submit Documentation Feedback
TYPICAL CHARACTERISTICS At T A = +25 C, AVDD = DVDD = REFP = 5V, and REFN = AGND, unless otherwise noted. NOISE PLOT NOISE PLOT 4 PGA = 64 Data Rate = 1SPS 3 2 PGA = 64 Data Rate = 8SPS Output Code (LSB) 3 2 1 Output Code (LSB) 1 1 2 3 4 5 2 4 6 8 1 6 2 4 6 8 1 Time (Reading Number) Time (Reading Number) Figure 1. Figure 2. NOISE HISTOGRAM NOISE HISTOGRAM 9 8 PGA = 64 Data Rate = 1SPS 4 35 PGA = 64 Data Rate = 8SPS 7 3 Occurrence 6 5 4 3 Occurrence 25 2 15 2 1 1 5 1 2 3 5 4 3 2 1 1 2 Output Code (LSB) Output Code (LSB) Figure 3. Figure 4. NOISE PLOT NOISE PLOT 1 PGA = 128 Data Rate = 1SPS 8 6 4 PGA = 128 Data Rate = 8SPS Output Code (LSB) 2 3 4 5 Output Code (LSB) 2 2 4 6 8 6 2 4 6 8 1 1 2 4 6 8 1 Time (Reading Number) Time (Reading Number) Figure 5. Figure 6. Submit Documentation Feedback 7
TYPICAL CHARACTERISTICS (continued) At T A = +25 C, AVDD = DVDD = REFP = 5V, and REFN = AGND, unless otherwise noted. 5 45 4 PGA = 128 Data Rate = 1SPS NOISE HISTOGRAM 25 2 PGA = 128 Data Rate = 8SPS NOISE HISTOGRAM 35 Occurrence 3 25 2 Occurrence 15 1 15 1 5 5 5 4 3 2 1 Output Code (LSB) 7 6 5 4 3 2 1 1 2 3 4 5 6 7 Output Code (LSB) Figure 7. Figure 8. 1 8 OFFSET vs TEMPERATURE.2 GAIN ERROR vs TEMPERATURE PGA = 64 Data Rate = 1SPS Offset (nv) 6 4 2 2 4 Gain Error (%).3.4.5 6 PGA = 64 Data Rate = 1SPS 8 5 25 25 Temperature ( C) 5 75 1.6 5 25 25 Temperature ( C) 5 75 1 Figure 9. Figure 1. NOISE vs INPUT SIGNAL NOISE vs INPUT SIGNAL RMS Noise (nv) 5 45 4 35 3 25 2 15 1 PGA = 64 5 Data Rate = 1SPS 4 3 2 1 1 2 3 V IN (mv) 4 RMS Noise (nv) 12 1 8 6 PGA = 64 Data Rate = 8SPS 4 4 3 2 1 1 2 3 V IN (mv) 4 Figure 11. Figure 12. 8 Submit Documentation Feedback
TYPICAL CHARACTERISTICS (continued) At T A = +25 C, AVDD = DVDD = REFP = 5V, and REFN = AGND, unless otherwise noted. INTEGRAL NONLINEARITY vs INPUT SIGNAL INTEGRAL NONLINEARITY vs INPUT SIGNAL INL (ppm) 1 5 5 25 C 85 C 7 C PGA = 64 4 C Data Rate = 1SPS 1 4 3 2 1 1 2 3 V IN (mv) 2 C 4 INL (ppm) 1..5.5 1. 4 C 1.5 PGA = 128 Data Rate = 1SPS 2. 2 1 25 C 7 C 1 V IN (mv) 2 C 85 C 2 Figure 13. Figure 14. 12 ANALOG CURRENT vs TEMPERATURE (Normal Mode) 97 DIGITAL CURRENT vs TEMPERATURE (Normal Mode) Analog Current ( A) 1 8 6 4 2 5 PGA = 64, 128 25 25 Temperature ( C) 5 75 1 Digital Current ( A) 96 95 94 93 92 91 9 89 88 5 PGA = 128 25 PGA = 64 25 Temperature ( C) 5 75 1 Figure 15. Figure 16. 9.85 DATA RATE vs TEMPERATURE Data Rate (SPS) 9.8 9.75 9.7 5 25 25 Temperature ( C) 5 75 1 Figure 17. Submit Documentation Feedback 9
OVERVIEW The is a precision, 2-bit ADC that includes a low-noise PGA, internal oscillator, third-order delta-sigma ( Σ) modulator, and fourth-order digital filter. The provides a complete front-end solution for bridge sensor applications such as weigh scales, strain guages, and pressure sensors. Clocking can be supplied by an external clock or by a precision internal oscillator. Data can be output at 1SPS for excellent 5Hz and 6Hz rejection, or at 8SPS when higher speeds are needed. The is easy to configure, and all digital control is accomplished through dedicated pins; there are no registers to program. A simple two-wire serial interface retrieves the data. ANALOG INPUTS (AINP, AINN) The input signal to be measured is applied to the input pins AINP and AINN. The accepts differential input signals, but can also measure unipolar signals. When measuring unipolar (or single-ended signals) with respect to ground, connect the negative input (AINN) to ground and connect the input signal to the positive input (AINP). Note that when the is configured this way, only half of the converter full-scale range is used, since only positive digital output codes are produced. LOW-NOISE PGA The features a low-drift, low-noise PGA that provides a complete front-end solution for bridge sensors. A simplified diagram of the PGA is shown in Figure 18. It consists of two chopper-stabilized amplifiers (A1 and A2) and three accurately-matched resistors (R 1, R F1, and R F2 ), which construct a differential front-end stage with a gain of 64, followed by gain stage A3 (Gain = 1 or 2). The PGA inputs are equipped with an EMI filter, as shown in Figure 18. The cutoff frequency of the EMI filter is 19.6MHz. By using AVDD as the reference input, the bipolar input ranges from 39mV to +39mV (Gain = 64) or 19.5mV to +19.5mV (Gain = 128), and the unipolar input ranges from mv to +39mV (Gain = AINP AINN 45 45 18pF 18pF R 1 Bypass Capacitor A1 A2 R F1 R F2 R INT R INT CAP CAP Gain = 1 or 2 A3 64) or mv to +19.5mV (Gain = 128). The inputs of the are protected with internal diodes connected to the power-supply rails. These diodes clamp the applied signal to prevent it from damaging the input circuitry. ADC Figure 18. Simplified Diagram of the PGA By applying a.1µf external capacitor (C EXT ) across two capacitor pins combined with the internal 2kΩ resistor R INT (on-chip), a low-pass filter with a corner frequency of 72Hz is created to bandlimit the signal path before the modulator input. This low-pass filter serves two purposes. First, the input signal is bandlimited to prevent aliasing as well as to filter out the high-frequency noise. Second, it attenuates the chopping residue from the amplifier to improve temperature drift performance. It is not required to use high-quality capacitors (such as ceramic or tantalum capacitors) for a general application. However, high-quality capacitors such as poly are recommended for high-linearity applications. 1 Submit Documentation Feedback
VOLTAGE REFERENCE INPUTS ESD diodes protect the reference inputs. To prevent (REFP, REFN) these diodes from turning on, make sure the voltages on the reference pins do not go below GND The voltage reference used by the modulator is by more than 1mV, and likewise, do not exceed generated from the voltage difference between AVDD by 1mV: REFP and REFN: V REF = REFP REFN. The reference inputs use a structure similar to that of the GND 1mV < (REFP or REFN) < AVDD + 1mV analog inputs. In order to increase the reference input impedance, a switching buffer circuitry is used CLOCK SOURCES to reduce the input equivalent capacitance. A simplified diagram of the circuitry on the reference The can use an external clock source or inputs is shown in Figure 19. The switches and internal oscillator to accommodate a wide variety of capacitors can be modeled with an effective applications. Figure 2 shows the equivalent circuitry impedance of: of the clock source. The CLK_DETECT block determines whether the crystal oscillator/external Z EFF 1 clock signal is applied to the CLKIN pin so that the 2f MOD C BUF internal oscillator is bypassed or activated. When the Where: CLKIN pin frequency is above ~2kHz, the CLK_DETECT output goes low and shuts down the f MOD = modulator sampling frequency (76.8kHz) internal oscillator. When the CLKIN pin frequency is C BUF = input capacitance of the buffer below ~2kHz, the CLK_DETECT output goes high For the : Z EFF 1 2M (2)(76.8kHz)(32.5fF) and activates the internal oscillator. It is highly recommended to hard-wire the CLKIN pin to ground when the internal oscillator is chosen. REFP REFN CLKIN CLK_DETECT AVDD C BUF AVDD ESD Protection (1) Z EFF = 2M S MUX S1 To ADC S Internal Oscillator EN Figure 2. Equivalent Circuitry of the Clock Source (1) f MOD = 76.8kHz Figure 19. Simplified Reference Input Circuitry An external clock may be used by driving the CLKIN pin directly. The Electrical Characteristics table shows the allowable frequency range. The clock input may be driven with 5V logic, regardless of the DVDD or AVDD voltage. Submit Documentation Feedback 11
FREQUENCY RESPONSE The uses a sinc 4 digital filter with the frequency response (f CLK = 4.9152MHz) shown in Figure 21. The frequency response repeats at multiples of the modulator sampling frequency of 76.8kHz. The overall response is that of a low-pass filter with a 3dB cutoff frequency of 3.32Hz with the SPEED pin tied low (1SPS data rate) and 11.64Hz with the SPEED pin tied high (8SPS data rate). Gain (db) 5 1 Data Rate = 1SPS Gain (db) 2 4 6 8 1 12 14 f CLK = 4.9152MHz 15 1 2 3 4 5 6 7 8 9 1 Frequency (Hz) (a) 5 Data Rate = 1SPS 16 18 2 38.4 76.8 Frequency (khz) Gain (db) 1 Figure 21. Frequency Response To help see the response at lower frequencies, Figure 22(a) illustrates the response out to 1Hz, when the data rate = 1SPS. Notice that signals at multiples of 1Hz are rejected, and therefore simultaneous rejection of 5Hz and 6Hz is achieved. The benefit of using a sinc 4 filter is that every frequency notch has four zeros on the same location. This response, combined with the low drift internal oscillator, provides an excellent normal-mode rejection of line-cycle interference. Figure 22(b) shows the same plot, but zooms in on the 5Hz and 6Hz notches with the SPEED pin tied low (1SPS data rate). With only a ±3% variation of the internal oscillator, over 1dB of normal-mode rejection is achieved. 15 46 47 48 49 5 51 52 53 54 55 56 57 58 59 6 61 62 63 64 Frequency (Hz) (b) Figure 22. Frequency Response Out To 1Hz The data rate and frequency response scale directly with clock frequency. For example, if f CLK increases from 4.9152MHz to 6.144MHz when the SPEED pin is tied high, the data rate increases from 8SPS to 1SPS, while notches also increase from 8Hz to 1Hz. Note that these changes are only possible when the external clock source is applied. 12 Submit Documentation Feedback
SETTLING TIME DATA RATE DATA FORMAT In certain instances, large changes in input will The outputs 2 bits of data in binary two s require settling time. For example, an external complement format. The least significant bit (LSB) multiplexer in front of the can put large has a weight of.5v REF /(2 19 1). The positive changes in input voltage by simply switching the full-scale input produces an output code of 7FFFFh multiplexer input channels. Abrupt changes in the and the negative full-scale input produces an output input will require four data conversion cycles to code of 8h. The output clips at these codes for settle. When continuously converting, five readings signals exceeding full-scale. Table 4 summarizes the may be necessary in order to settle the data. If the ideal output codes for different input signals. change in input occurs in the middle of the first conversion, four more full conversions of the The is a 2-bit ADC. After data conversion fully-settled input are required to get fully-settled is completed, applying 2 s retrieves 2 bits of data. Discard the first four readings because they data (MSB first). However, if the s continue to contain only partially-settled data. Figure 23 be applied after 2 bits of data are retrieved, the illustrates the settling time for the in DOUT pin outputs four 1s for the 21st through the Continuous Conversion mode. 24th, as shown in Figure 24. Table 4. Ideal Output Code vs Input Signal (1) INPUT SIGNAL V IN (AINP AINN) The data rate is set by the SPEED pin, as shown in Table 3. When SPEED is low, the data rate +.5V REF /Gain 7FFFFh is nominally 1SPS. This data rate provides the (+.5V REF /Gain)/(2 19 1) 1h lowest noise, and also has excellent rejection of both h 5Hz and 6Hz line-cycle interference. For (.5V REF /Gain)/(2 19 1) FFFFFh applications requiring fast data rates, setting SPEED high selects a data rate of nominally 8SPS..5V REF /Gain 8h Table 3. Data Rate Settings DATA RATE SPEED Internal Oscillator External PIN or 4.9152MHz Crystal Oscillator 1SPS f CLKIN / 491,52 1 8SPS f CLKIN / 61,44 IDEAL OUTPUT (1) Excludes effects of noise, INL, offset, and gain errors. Abrupt Change in External V IN V IN DRDY/DOUT Start of Conversion 1st Conversion; includes unsettled V. IN 2nd Conversion; VIN settled, but digital filter unsettled. 3rd Conversion; VIN settled, but digital filter unsettled. 4th Conversion; VIN settled, but digital filter unsettled. 5th Conversion; VIN and digital filter both settled. Conversion Time Figure 23. Settling Time in Continuous Conversion Mode Data New MSB DRDY/DOUT 19 18 17 LSB 1 2 3 4 1 2 3 2 21 22 23 24 Figure 24. Data Retrieval Format Submit Documentation Feedback 13
DATA READY/DATA OUTPUT (DRDY/DOUT) DATA RETRIEVAL This digital output pin serves two purposes. First, it The continuously converts the analog input indicates when new data are ready by going low. signal. To retrieve data, wait until DRDY/DOUT goes Afterwards, on the first rising edge of, the low, as shown in Figure 25. After DRDY/DOUT goes DRDY/DOUT pin changes function and begins low, begin shifting out the data by applying s. outputting the conversion data, most significant bit Data are shifted out MSB first. It is not required to (MSB) first. Data are shifted out on each subsequent shift out all 2 bits of data, but the data must be rising edge. After all 2 bits have been retrieved before new data are updated (within t CONV ) retrieved, the pin can be forced high with an or else the data will be overwritten. Avoid data additional. It then stays high until new data are retrieval during the update period (t UPDATE ). If 24 ready. This configuration is useful when polling on s have been applied, DRDY/DOUT will be high the status of DRDY/DOUT to determine when to since the last four bits have been appended by '1'. begin data retrieval. However, if only 2 s have been applied, DRDY/DOUT remains at the state of the last bit SERIAL CLOCK INPUT () shifted out until it is taken high (see t UPDATE ), indicating that new data are being updated. To avoid This digital input shifts serial data out with each having DRDY/DOUT remain in the state of the last rising edge. As with CLK, this input may be driven bit, the 21st can be applied to force with 5V logic regardless of the DVDD or AVDD DRDY/DOUT high, as shown in Figure 26. This voltage. This input has built-in hysteresis, but care technique is useful when a host controlling the should still be taken to ensure a clean signal. device is polling DRDY/DOUT to determine when Glitches or slow-rising signals can cause unwanted data are ready. additional shifting. For this reason, it is best to make sure the rise and fall times of are both less than 5ns. 14 Submit Documentation Feedback
a) 2 Bits of Data Retrieval Data New MSB DRDY/DOUT 19 18 17 LSB t PD t HT t DS t tupdate 1 2 t t CONV b) 24 Bits of Data Retrieval Data New MSB DRDY/DOUT 19 18 17 LSB 1 2 3 4 t PD t HT t DS t tupdate 1 2 21 22 23 24 t t CONV Figure 25. Data Retrieval Timing SYMBOL DESCRIPTION MIN TYP MAX UNITS t DS DRDY/DOUT low to first rising edge ns t positive or negative pulse width 1 ns t PD rising edge to new data bit valid: propagation delay 5 ns t HT rising edge to old data bit valid: hold time ns t (1) UPDATE Data updating: no readback allowed 39 µs t (1) CONV Conversion time (1/data rate) SPEED = 1 12.5 ms SPEED = 1 ms (1) Value given for f CLK = 4.9152MHz. For different f CLK frequencies, scale proportional to CLK period. Data New DRDY/DOUT 19 18 17 1 2 21 21st to Force DRDY/DOUT High Figure 26. Data Retrieval with DRDY/DOUT Forced High Afterwards Submit Documentation Feedback 15
OFFSET CALIBRATION Offset calibration can be initiated at any time to remove the inherited offset error. To initiate offset calibration, apply at least two additional s after retrieving 2 bits of data plus four bits of '1'. Figure 27 shows the timing pattern. The 25th keeps DRDY/DOUT high. The falling edge of the 26th begins the calibration cycle. Additional pulses may be sent after the 26th ; however, activity on should be minimized during offset calibration for best results. During this time, the analog input pins are disconnected within the ADC and the appropriate signal is applied internally to perform the calibration. When the calibration is completed, DRDY/DOUT goes low, indicating that new data are ready. The first conversion after a calibration is fully settled and valid for use. The offset calibration takes exactly the same time as specified in (t CAL ) immediately after the falling edge of the 26th. After Calibration DRDY/DOUT 19 18 17 1 2 3 4 19 Calibration Begins 1 2 21 22 23 24 25 26 t CAL Figure 27. Offset-Calibration Timing SYMBOL DESCRIPTION MIN MAX UNITS t CAL (1) First data ready after calibration SPEED = 1 11.28 11.29 ms SPEED = 81.2 81.3 ms (1) Value given for f CLK = 4.9152MHz. For different f CLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an internal oscillator is used. 16 Submit Documentation Feedback
STANDBY MODE Standby mode dramatically reduces power consumption by shutting down most of the circuitry. In Standby mode, the entire analog circuitry is powered down and only the clock source circuitry is awake to reduce the wake-up time from the Standby mode. To enter Standby mode, simply hold high after DRDY/DOUT goes low; see Figure 28. Standby mode can be initiated at any time during readback; it is not necessary to retrieve all 2 bits of data beforehand. When t STANDBY has passed with held high, Standby mode activates. DRDY/DOUT stays high when Standby mode begins. must remain high to stay in Standby mode. To exit Standby mode (wakeup), set low. The first data after exiting Standby mode is valid. Standby Mode DRDY/DOUT 19 18 17 19 Start Conversion 1 2 t DSS t STANDBY t S_RDY Figure 28. Standby Mode Timing (can be used for single conversions) SYMBOL DESCRIPTION MIN MAX UNITS t DSS (1) t STANDBY (1) t S_RDY (1) high after DRDY/DOUT goes SPEED = 1 12.44 ms low to activate Standby mode SPEED = 99.94 ms Standby mode activation time Data ready after exiting Standby mode SPEED = 1 2 µs SPEED = 2 µs SPEED = 1 52.51 52.51 ms SPEED = 41.8 41.8 ms (1) Value given for f CLK = 4.9152MHz. For different f CLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an internal oscillator is used. Submit Documentation Feedback 17
STANDBY MODE WITH OFFSET-CALIBRATION Offset-calibration can be set to run immediately after exiting Standby mode. This option is useful when the is put in Standby mode for long periods of time, and offset-calibration is desired afterwards to compensate for temperature or supply voltage changes. To force an offset-calibration with Standby mode, shift 25 s and bring the pin high to enter Standby mode. Offset-calibration then begins after wake-up; Figure 29 shows the appropriate timing. Note the extra time needed after wake-up for calibration before data are ready. The first data after Standby mode with offset-calibration is fully settled and can be used right away. Standby Mode After Calibration DRDY/DOUT 19 18 17 1 2 3 4 Begin 19 Calibration 1 2 21 22 23 24 25 t STANDBY t SC_RDY Figure 29. Standby Mode with Offset-Calibration Timing (can be used for single conversions) SYMBOL DESCRIPTION MIN MAX UNITS t SC_RDY (1) Data ready after exiting Standby mode SPEED = 1 13 13 ms and calibration SPEED = 83 83 ms (1) Value given for f CLK = 4.9152MHz. For different f CLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an internal oscillator is used. 18 Submit Documentation Feedback
POWER-DOWN MODE Power-Down mode shuts down the entire ADC circuitry and reduces the total power consumption close to zero. To enter Power-Down mode, simply hold the PDWN pin low. Power-Down mode also resets the entire circuitry to free the ADC circuitry from locking up to an unknown state. Power-Down mode can be initiated at any time during readback; it is not necessary to retrieve all 2 bits of data beforehand. Figure 3 shows the wake-up timing from Power-Down mode. PDWN Power-Down Mode t PDWN CLK Source Wakeup Start Conversion DRDY/DOUT t WAKEUP t TS_RDY Figure 3. Wake-Up Timing from Power-Down Mode SYMBOL DESCRIPTION MIN TYP UNITS Wake-up time after Power-Down Internal clock 7.95 µs t WAKEUP mode External clock.16 µs t PDWN (1) PDWN pulse width 26 µs (1) Value given for f CLK = 4.9152MHz. For different f CLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an internal oscillator is used. Submit Documentation Feedback 19
APPLICATION EXAMPLES Weigh Scale System Noise Free Counts 2 BIT Eff FS LC FS AD Figure 31 shows a typical hook-up as part Where: of a weigh scale system. In this setup, the BIT EFF = effective noise-free bits (17.5 + 1 bit is configured at a 1SPS data rate. Note that the from software filtering/averaging) internal oscillator is used by grounding the CLKIN FS LC = full-scale output of the load cell (1mV) pin. The user can also apply a 4.9152MHz clock to FS AD = full-scale input of the (39mV, the CLKIN pin. For a typical 2mV/V load cell, the when PGA = 128) maximum output signal is approximately 1mV for a single +5V excitation voltage. The can Therefore: achieve 17.5 noise-free bits at 1SPS when PGA = 128. With the extra software filtering/averaging (typically done by a Noise Free Counts 2 (17.5 1) 1mV 95, 58 39mV microprocessor), an extra bit can be expected. With +5V supply voltage, 95,58 noise-free counts can be expected from the. 2.7V to 5.3V +.1 F.1 F 1 5 6 7 8 9 12 1 AVDD DVDD REFP CAP DRDY/DOUT CAP AINP AINN REFN PDWN 16 15 14 GAIN 4 3 CLKIN 13 SPEED VDD MSP43x4xx or Other Microprocessor AGND DGND 11 2, 4 GND Figure 31. Weigh Scale Application 2 Submit Documentation Feedback
SUMMARY OF SERIAL INTERFACE WAVEFORMS a) 2 Bits of Data Retrieval Data New MSB DRDY/DOUT 19 18 17 LSB t PD t HT t DS t tupdate 1 2 t t CONV b) 24 Bits of Data Retrieval Data New MSB DRDY/DOUT 19 18 17 LSB 1 2 3 4 t PD t HT t DS t tupdate 1 2 21 22 23 24 t t CONV c) Data Retrieval with DRDY/DOUT Forced High Afterwards Data New DRDY/DOUT 19 18 17 1 2 21 21st to Force DRDY/DOUT High d) Standby Mode/Single Conversions Standby Mode DRDY/DOUT 19 18 17 19 Start Conversion 1 2 t DSS t STANDBY t S_RDY Figure 32. Summary of Data Retrieval Waveforms Submit Documentation Feedback 21
a) Offset Calibration Timing 21st to Force DRDY/DOUT High After Calibration DRDY/DOUT 19 18 17 1 2 3 4 19 Calibration Begins 1 2 21 22 23 24 25 26 t CAL b) Standby Mode/Single Conversions Standby Mode DRDY/DOUT 19 18 17 19 Start Conversion 1 2 t DSS t STANDBY t S_RDY c) Standby Mode/Single Conversions with Offset Calibration Standby Mode After Calibration DRDY/DOUT 19 18 17 1 2 3 4 Begin 19 Calibration 1 2 21 22 23 24 25 t STANDBY t SC_RDY Figure 33. Summary of Standby Mode and Calibration Waveforms 22 Submit Documentation Feedback
PACKAGE OPTION ADDENDUM 2-Nov-26 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty IPW ACTIVE TSSOP PW 16 9 Green (RoHS & no Sb/Br) IPWR ACTIVE TSSOP PW 16 2 Green (RoHS & no Sb/Br) Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) CU NIPDAU CU NIPDAU Level-2-26C-1 YEAR Level-2-26C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http:///productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
MECHANICAL DATA MTSS1C JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE,3,65,1 M,19 14 8 4,5 4,3 6,6 6,2,15 NOM Gage Plane 1 A 7 8,25,75,5 1,2 MAX,15,5 Seating Plane,1 DIM PINS ** 8 14 16 2 24 28 A MAX 3,1 5,1 5,1 6,6 7,9 9,8 A MIN 2,9 4,9 4,9 6,4 7,7 9,6 4464/F 1/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed,15. D. Falls within JEDEC MO-153
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