中國文化大學教師教學創新暨教材研發獎勵期末成果報告書 壹 計畫名稱 英文計畫名稱 : Fundamental Design of Combinational and Sequential Logic Circuit 中文計畫名稱 : 組合電路與序列電路基礎設計 貳 實施課程 授課教師姓名 課程名稱 : 邏輯設計 (Logic Desgin) 開課系級 : 電機工程學系一年級授課教師 : 逄霖生電子郵件 : pls@faculty.pccu.edu.tw 參 前言 組合電路與序列電路是數位電路的基礎, 台灣在世界的工業鏈中, 在數位設計的能力有目共睹, 這個領域需要的相關科技人才, 必須有組合電路與序列電路的知識 電機系在此專業領域特別重視相關的技術與知識 唯有組合電路與序列電路的基本技能十分紮實, 才能有足夠的能力面對更大的挑戰 本教材創新計畫針對基本邏輯知識詳加介紹 : 包含 Boolean logic( 布林邏輯 ), 數位資料表示與實際基本邏輯閘的介紹應用 進階的數位序列電路的原理, 相關的實際電路應用 : 包含正反器 閘極開關 計算器與 Timer 的設計與實際應用的電路 本教材將使用 1
Altera 公司發展的 EDA 與 FPGA 硬體, 提供學有實際動手操作的設備, 希望透過專 案設計的方式, 提供學員了解硬體與軟體編寫及燒錄開發設計的過程, 讓學生了 解邏輯設計中數位組合電路與序列電路的設計 肆 計畫特色及具體內容邏輯電路設計與應用是台灣工業的強項, 這個領域需要大量的 3C 相關科技人才 電機工程系的學習領域, 包含了硬體實作與軟體應用, 因此特別適合同學在此項目中發揮所長 但是數位邏輯電路應用基本技能包含邏輯能力的分析, 組合與實際電路應用, 如此才能有足夠的知識挑戰不同的問題 學生也應不斷地吸收新的知識, 來面對計算機工程或數位電路設計日新月異的發展 本教材創新計畫針對基本邏輯知識與進階的數位序列電路的原理詳加介紹 : 內容有布林邏輯 數位資料 基本邏輯閘 數位應用電路 正反器 閘極開關 計算器與 Timer 的設計與實際應用的電路 本教材將使用 Altera 公司發展的 EDA 與 FPGA 硬體, 提供學有實際動手操作的設備, 讓學員有機會了解硬體與軟體編寫及燒錄開發設計的過程, 加強學生對邏輯設計中組合電路與序列電路的瞭解 Combinational Logic Circuit 數位組合電路 Number Systems, Arithmetic, and codes Digital Systems vs. Analog Systems 2
Digital Systems vs. Analog Systems Digital System Information is represented and processed by a finite number of discrete digits. Example: Binary Strings of 1 s and 0 s are used to represent information. Analog System Information is represented and processed along a continuum. Example: Consider making measurements with a ruler. Number Systems Positional Number Systems The above is a general form of a power series in radix r. A number N expressed in base-r system has coefficients multiplied by powers of r: N= d n 1 * r n 1 + d n 2 * r n 2 +...d 1 * r 1 + d 0 * r 0 + d 1 * r -1 + d 2 * r -2 +...d m * r -m Binary Arithmetic Binary Number Two discrete values are used in digital systems only. The values of a binary number could be False/True Low/High 0/1 Yes/No Go/No Go Ternary Arithmetic 3
Ternary Number Similar to the binary number, but the number of ternary number includes {0, 1, 2}. There are total three digital numbers to represent ternary system. Binary and Decimal Number Base Conversions Decimal to Binary Conversion A decimal number N, indicating as i.f (i.e. 3.13159), includes two parts: the first part is integer part, i, and the second part is fractional part, f. The procedures of decimal number to binary conversion are shown as follows: 1. Convert integer part 2. Convert fractional part 3. Combine integer and fractional parts together Polynomial Method of Number Conversion (Givone Text Book) The number N (r1) of Base-r1 N (r1) = (d n-1 d n-2 d 1 d 0. d -1 d -m ) (r1),0 <= d i <= (r1-1) N (r1) = d n-1(r1) * r 1 n-1 (r1) + d n-2(r1) * r 1 n-2 (r1) + + d 0(r1) * r 1 0 (r1) + d -1(r1) * r 1-1 (r1) + + d m(r1) * r 1 -m (r1) = d n-1(r1) * 10 n-1 (r1) + d n-2(r1) * 10 n-2 (r1) + + d 0(r1) * 10 0 (r1) + d -1(r1) * 10-1 (r1) + + d -m(r1) * 10 -m (r1) Note the quantity of 2 in binary is represent by 10 (2) Note the quantity of 3 in ternary is represent by 10 (3) The number N (r2) of Base-r2 N (r2) = d n-1(r2) * r 1 n-1 (r2) + d n-2(r2) * r 1 n-2 (r2) +... + d m(r2) * r 1 -m (r2) N (r1) is converted into of N (r2) Iterative method of number conversion Iterative method of converting integer (Givone Text Book) To convert an integer in base r 1 into its equivalent integer in r 2. Divide the number by r 2, then the remainder is the 0-th order digit. Repeat the previous step to get 1st order digit, Repeat the division process of r 2 until the remainder is zero. Signed and Unsigned Numbers 4
Signed Numbers Signed numbers denote whether the magnitudes is positive or negative. The form to show a singed number is called as sign-magnitude representation. The sign-magnitude representation includes the following methods: Proceeding with signed symbol, (+) or (-). (used in regular number representation) In digital system, it utilizes the binary digit 0 to denote the plus sign and the binary digit 1 to denote the minus sign. Complements of Number Complement notation The complement notation uses the most significant bit represents the sign bit, indicating whether the number is positive or negative. Overflow in unsigned and signed number Overflow the binary number operations need n + 1 digit to do n digit number operations. Floating number (IEEE-754 standard) 5
5-4 浮點數的表示法 浮點數表示法 不同 CPU 雖有其各自的浮點數表示法, 但一般較常採用 IEEE 協會所訂定的浮點數表示法標準 ( IEEE Standa rd 754), 其分成單精確度 (Single Precision) 及雙精確度 (Double Precision) 二種 兩者的差別在於單精確度是以 32 個位元來表示浮點數, 雙精確度則是用 64 位元表示 50 Binary Codes (BCD Codes) Decimal Codes BCD Binary Coded Decimal Represents decimal digits 0 9 It will need 4 binary digits to represent ten numbers, but leaves 6 combinations un-used. Weighted Codes Positional of number indicates weight (w 3 w 2 w 1 w 0 ) A number N = w 3* b 3 +w 2* b 2 +w 1* b 1 +w 0* b 0 BCD codes include several different forms, such as 8421, 2421, 5421, 7536, 5043210 codes. Unit-Distance Codes Unit-Distance Codes Only a single bit changes between any two successive coded integers The most popular of the unit distance codes are the Gray codes (named after their inventor Frank Gray). Angular position encoders. (a) Conventional binary encoder. (b) Gray code encoder. ASCII & Unicode 6
Error-Detection Codes (Parity Code) Error Correction Codes (Hamming Code) 7
BOOLEAN ALGEBRA AND COMBINATIONAL NETWORKS Introduction to Boolean Algebra Theorems & Postulates of Boolean Algebra Two-Valued Boolean Algebra 8
Boolean Formulas and Functions The Truth Table Canonical Formulas of Boolean Algebra & Manipulations of Boolean Formulas Canonical Forms 9
Gates and Combinational Networks Incomplete Boolean Functions and Don't-Care Conditions 10
Additional Boolean Operations and Gates Physical Properties of Logic Gates Simplification of Boolean Expressions 11
Prime Implicates and Irredundant Conjunctive Expressions KARNAUGH MAPS Using Karnaugh Maps to Obtain Minimal Expressions for Complete Boolean Functions 12
Minimal Expression of Incomplete Boolean Functions Five-variable and Six-variable Karnaugh Maps 13
The Quine-McCluskey Method of Generating Prime Implicants and Prime Implicates Decimal Method for Obtaining Prime Implicants LOGIC DESIGN WITH MSI COMPONENTS AND PROGRAMMABLE LOGIC DEVICES Binary Adders and Subtracter 14
Decimal Adders & Comparators Decoders & Encoders Multiplexers 15
Programmable Components & Programmable Logic Devices (PLDs) Programmable Read-Only Memory (PROMs) & Programmable Logic Arrays (PLAs) Programmable Array Logic (PAL) Devices 16
Sequential Logic Circuit 數位序列電路 Flip-Flops and Simple Flip-Flop Applications The Basic Bistable Element Latches & Progagation Delays 17
Master-Slave SR Flip-Flops (Pulse-Triggered Flip-Flops) The Master-Slave SR Flip-Flop 18
The Master-Slave JK Flip-Flop The Master-Slave D Flip-Flop 19
The Master-Slave T Flip-Flop Edge-Triggerred SR/JK/F/T Flip-Flop Characteristic Equations 20
Registers Counters 21
伍 實施成效及影響 ( 量化及質化 ) 實施成效 : 1. 學員數 : 102 人 2. 上課時數 : 18 小時 3. 作業次數 : 10 次作業 4. 數位電路範例 : 10 種 5. 作業完成率 : 782/1020=77% 6. 未完成率 : 238/1020=23% 7. 硬體程式語 : Schematic Layout 8. CAD 設計硬體 : Altera Quartus II v9.1 9. 作業繳交明細表 22
學員作業作業作業作業作業作業作業作業作業作業學號姓名排序 #1 #2 #3 #4 #5 #6 #7 #8 #9 #10 1 N/A N/A 1 1 1 3 2 2 2 1 3 2 2 N/A N/A 1 1 2 3 2 2 2 2 3 2 3 N/A N/A 1 x 2 3 2 2 2 2 3 2 4 N/A N/A 1 1 x x x x x x x x 5 N/A N/A 1 1 2 3 2 1 2 2 3 2 6 N/A N/A 1 1 2 3 2 2 2 2 3 2 7 N/A N/A 1 1 2 x 2 2 2 2 x 2 8 N/A N/A 1 1 2 x 2 2 x 2 x 2 9 N/A N/A 1 x x x x x x x x x 10 N/A N/A 1 x x x x x x x x x 11 N/A N/A x 1 x x x x x x x x 12 N/A N/A 1 1 1 3 2 x 2 1 3 2 13 N/A N/A 1 1 x 3 x 1 x x 3 x 14 N/A N/A 1 1 1 3 2 x 1 1 3 2 15 N/A N/A 1 1 x x x x x x x x 16 N/A N/A 1 1 x x x x x x x x 17 N/A N/A 1 1 2 3 2 2 2 2 3 2 18 N/A N/A 1 1 x 3 2 1 1 1 3 2 19 N/A N/A 1 1 1 1 2 x x 1 1 2 20 N/A N/A 1 1 2 x x x x 2 x x 21 N/A N/A 1 1 x x x x x x x x 22 N/A N/A 1 1 x 3 2 x x x 3 2 23 N/A N/A 1 1 x 1 x x x x 1 x 24 N/A N/A 1 x x 3 2 2 x x 3 2 25 N/A N/A 1 1 2 3 2 2 2 2 3 2 26 N/A N/A 1 x x x x x x x x x 27 N/A N/A 1 1 2 3 x x x 2 3 x 28 N/A N/A 1 1 1 x 1 x x 1 x 1 29 N/A N/A 1 1 2 x x x x 2 x x 30 N/A N/A x x x x x x x x x x 31 N/A N/A 1 1 1 1 1 x x 1 1 1 23
32 N/A N/A 1 1 x x x x x x x x 33 N/A N/A 1 1 x x x x x x x x 34 N/A N/A 1 1 x 3 2 2 1 1 3 2 35 N/A N/A 1 1 2 2 2 2 2 2 2 2 36 N/A N/A 1 1 2 3 2 2 x 2 3 2 37 N/A N/A 1 1 1 1 2 2 2 1 1 2 38 N/A N/A 1 1 x 3 x x x x 3 x 39 N/A N/A 1 1 1 x x x x 1 x x 40 N/A N/A 1 1 x x x x x x x x 41 N/A N/A 1 1 2 3 2 1 2 2 3 2 42 N/A N/A 1 x 2 x x 1 x 2 x x 43 N/A N/A 1 1 2 3 x 1 x 2 3 x 44 N/A N/A 1 x x 3 x x x x 3 x 45 N/A N/A 1 1 2 3 2 2 x 2 3 2 46 N/A N/A 1 x x x x x x x x x 47 N/A N/A x x x x x x x x x x 48 N/A N/A 1 1 1 3 x x x 1 3 x 49 N/A N/A 1 1 x 3 2 x x x 3 2 50 N/A N/A x x 1 1 1 x 1 1 1 1 51 N/A N/A 1 1 2 3 x x 2 2 3 x 52 N/A N/A 1 1 2 3 2 2 2 2 3 2 53 N/A N/A 1 1 2 3 2 2 2 2 3 2 54 N/A N/A 1 1 1 2 2 2 2 1 2 2 55 N/A N/A 1 1 2 x 2 x x 2 x 2 56 N/A N/A 1 1 2 1 x 1 2 2 1 x 57 N/A N/A 1 1 2 3 2 2 2 2 3 2 58 N/A N/A 1 1 1 1 x 1 x 1 1 x 59 N/A N/A 1 1 1 x x x 2 1 x x 60 N/A N/A 1 1 2 3 2 x x 2 3 2 61 N/A N/A x 1 2 x 2 x 1 2 x 2 62 N/A N/A 1 1 2 3 2 2 2 2 3 2 63 N/A N/A 1 1 2 3 2 2 1 2 3 2 64 N/A N/A 1 1 2 3 2 2 1 2 3 2 65 N/A N/A 1 1 1 x 2 2 x 1 2 2 66 N/A N/A 1 1 2 3 2 x x 2 3 2 67 N/A N/A 1 1 1 3 2 2 2 1 3 2 68 N/A N/A 1 1 2 x x x 2 2 x x 24
69 N/A N/A 1 1 2 x 2 2 x 2 x 2 70 N/A N/A 1 x x x x x x x x x 71 N/A N/A 1 1 2 3 2 2 2 2 3 2 72 N/A N/A x x x x x x x x x x 73 N/A N/A 1 x 2 x 2 2 x 2 x 2 74 N/A N/A x x x 3 2 1 x 1 3 2 75 N/A N/A 1 1 1 3 2 2 2 1 3 2 76 N/A N/A 1 1 2 3 2 2 2 2 3 2 77 N/A N/A 1 1 1 1 1 x x 1 1 1 78 N/A N/A 1 1 1 3 x 2 x 1 3 x 79 N/A N/A 1 1 x 3 x 2 2 x 3 x 80 N/A N/A 1 1 2 x x x x 2 x x 81 N/A N/A 1 1 2 3 x 2 x 2 3 x 82 N/A N/A 1 1 2 3 2 2 x 2 3 2 83 N/A N/A 1 1 1 3 x 2 x 1 3 x 84 N/A N/A 1 1 1 3 x 2 x 1 3 x 85 N/A N/A 1 1 1 3 2 2 x 1 3 2 86 N/A N/A 1 1 1 1 2 2 x 1 1 2 87 N/A N/A x 1 2 3 2 1 x 2 3 2 88 N/A N/A 1 1 1 3 2 2 x 1 3 2 89 N/A N/A x 1 1 x x x x 1 x x 90 N/A N/A x 1 1 1 1 1 2 1 1 1 91 N/A N/A x x x x x x x x x x 92 N/A N/A x x 1 x x x x 1 x x 93 N/A N/A 1 x 2 3 x 2 2 2 3 x 94 N/A N/A 1 x 2 3 2 2 2 2 3 2 95 N/A N/A x 1 2 3 x 2 2 2 3 x 96 N/A N/A 1 1 2 3 2 2 2 2 3 2 97 N/A N/A x 1 1 3 x 2 2 1 3 x 98 N/A N/A 1 1 2 x 2 2 x 2 x 2 99 N/A N/A x 1 x 1 1 1 1 1 1 1 100 N/A N/A x x 1 x 1 2 x 1 x 1 101 N/A N/A 1 1 2 3 x 2 x 2 3 x 102 N/A N/A x x 2 x 2 2 1 2 1 2 25
實施影響 : 對組合電路與序列電路的了解與實作有實際操作的機會, 讓學員設計數位基本元件, 同時亦了解設計時程式碼的編排, 並觀察軟體設計與硬體電路的連繫 為讓學員對此部分有更深刻的理解, 本教材特別對數位電路模擬 (simulation) 提出許多的範例與說明, 包括了大量的時序圖 (timing diagram), 寄望由這些例證, 能了解數位系統設計的基本原理, 進而發展硬體設計的能力, 提供學員在數位領域的競爭力, 進入職場後能更快速地融入工作, 追求自我生涯的更高層境界 陸 結論組合電路與序列電路對數位晶片與數位電路的了解與實作有很大的助益 透過有系統的教材資料, 針對各種不同的數位電路元件, 解說相對應的實際範例, 可以讓學員同時複習元件的基本運作原理, 同時亦了解設計時數位電路的基本原理, 並同時可觀察瞭解軟硬體的設計與其間的連接 對大部份的初學者, 數位訊號如何傳遞與在不同時間 (timing) 時訊號如何改變, 更對於訊號間如何互相影響, 無法立刻理解 為讓學員對此部分有更深刻的理解, 本教材特別對數位電路模擬 (simulation) 提出許多的範例與說明, 包括了大量的時序圖 (timing diagram), 寄望由這些例證, 能了解組合電路與序列電路的基本原則, 進而發展硬體設計的能力, 提供學員在數位領域的競爭力, 進入職場後能更快 26
速地融入工作, 追求自我生涯的更高層境界 柒 執行計畫活動照片 27
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捌 附件 光碟片 備註 : 1. 本報告書大綱得視需要自行增列項目 2. 成果報告書須另以光碟儲存, 並附加執行計畫活動照片電子檔 30