深圳市利圣辉科技有限公司 SHENZHEN LISHENGHUI TECHNOLOGY CO.,LTD 承认书 SPECIFICATION FOR APPROVAL 客户名称 : Customer: 产品名称及型号 : 集成电路 IC Part Name&No..: 客户料号 : Customer material No.: 送样日期 : Date: 客户确认签章 供应商确认签章 DESIGNER CHECKER APPROVER DESIGNER CHECKER APPROVER SHENZHEN LISHENGHUI TECHNOLOGY CO.,LTD 鲁艳涛刘子涵何东 公司地址 : 深圳市宝安区前进二路华盛辉智汇创新中心 D 栋 68 联系人 : 鲁先生 TEL:0755-328688 / 5986666086 www..com
7.5V to 40V Input Supply, Synchronous Buck PWM Controller FEATURES Wide 7.5V to 40V Input Voltage Range Drive Dual Low Cost N-Channel MOSFETs -Adaptive Shoot-Through-Protection High Efficiency Up to 95% 0.8V reference with +/-.5% accuracy Fast Load Transient Response Dual Output with Independent Programmable Over-Current Control Over-Current Control Accuracy +/-3% Nearly Zero Input Current at Output Over Current Protection or Output Under- Voltage Protection Internal Soft-Start Programmable Output Cable Compensation 200kHz Fixed Switching Frequency Thermal shutdown Protection Available in MSOP-0 Package ORDERING INFORMATION Order Information AAP650 A RA 0 Extension Package Type Pin Count Code ES: MSOP-0 RoHS Compliant and Halogen Free APPLICATIONS Car Charger/Adaptor Rechargeable Portable Devices Battery Charger DESCRIPTION The is a voltage mode synchronous buck controller that achieves excellent load and line regulation. The device operates from an input voltage range of 7.5V to 40V.The provides protection functions including: input under-voltage lockout, output under-voltage protection and programmable over-current protection with two independent outputs. The is housed in a MSOP0 Package. Top Marking Part Number X J X X X X Day Month Year Wafer version code Assembly house code Production code Aug-2-205 Rev 2.0 Page-2 http://www..com/
TYPICAL APPLICATION PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS (Note: Exceeding these limits may damage the device. Exposure to absolute maximum rating conditions for long periods may affect device reliability.) VCC... 0.3V to 40V PHASE(DC).....0V to (VCC+)V UG.....(VPHASE 0.3)V to (VBST+0.3)V BST.... (VPHASE-0.3)V to (VPHASE+7)V FB, COMP, CS, CS2, LG..... 0.3V to 7V Operating Temperature Range... 40 C to 50 C Storage Temperature Range. 55 C to 50 C ESD Rating HBM (Human Body Mode) 2KV MM (Machine Mode) 200V Aug-2-205 Rev 2.0 Page2-2 http://www..com/
PIN DESCRIPTION PIN # NAME DESCRIPTION VCC Supply Input 2 COMP Output pin of error amplifier, Connect an appropriate compensation network between this and the FB pin 3 FB Output Voltage Feedback Input. 4 CS2 Vout2 Output Over-Current Detection Pin. When this pin sense the voltage drop of senseresistor RCS2 greater than 20mV for 30µs, the IC shut down for about.3 seconds before restart. 5 CS Vout Output Over-Current Detection Pin. When this pin sense the voltage drop of senseresistor RCS greater than 20mV for 30µs, the IC shut down for about.3 seconds before restart. 6 GND Ground. Connect this pin to the PCB ground 7 LG Output to external low-side gate driver 8 PHASE Switching node. Connect this pin to the drain of low-side MOSFET and the source of hideside MOSFET. 9 UG Output to external high-side gate driver 0 BST Bootstrap pin. Connect a 00nF capacitor for BST pin to PHASE pin. This capacitor provides power supply to the integrated high-side MOSFET gate driver. Note: Connect the exposed pad of the package to a large ground copper area for maximum heat dissipation. Aug-2-205 Rev 2.0 Page3-2 http://www..com/
ELECTRICAL CHACRACTERISTICS (V CC 2V, unless otherwise specified. Typical values are at TA 25 C.) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Supply Input Supply voltage range VCC 7.5 40 V Supply input current ICC VFB0.7V.3.6 2 ma Power-On Reset Rising VCC threshold 7.0 V Falling VCC threshold 6. V Oscillator and Soft-Start Switching Frequency FOSC 80 200 220 khz Sawtooth Amplitude ΔVOSC.6 V Soft-Start Time TSS 2 ms Reference Voltage Reference Voltage VREF Measured at FB Pin 0.788 0.8 0.82 V Accuracy TA-20~80 C -.5 +.5 % PWM Controller Gate Drivers UGATE Maximum Voltage VUG-VPHASE 4 5.5 6 V LGATE Maximum Volatge VLG-VGND 5.5 V UGATE Source Output Impedance RDS(ON) IGATE00mA 4.3 Ω UGATE Sink Output Impedance RDS(ON) IGATE00mA 3.4 Ω LGATE Source Output Impedance RDS(ON) IGATE00mA 3.6 Ω LGATE Sink Output Impedance RDS(ON) IGATE00mA.3 Ω Over current Protection and FB Under Voltage Protection CS OCP threshold VCS 2 25 29 mv CS2 OCP threshold VCS2 2 25 29 mv OCP Debounce Time TOCP 30 µs FB Under Voltage Threshold VFB-UV Percent of VREF 83 % Recycle Time TR FB UV or OCP.3 S Aug-2-205 Rev 2.0 Page4-2 http://www..com/
TYPICAL CHARACTERISTICS (Typical values are at VIN2V, VOUT5V, TA 25 C unless otherwise specified) Soft Start Transient (IOUT0A~6A) CH: PHASE, 5V/div CH2: VIN, 5V/div CH3: IOUT, 2A/div CH4: VOUT, 5V/div TIME: ms/div VOUT Short Protection CH: SW, 0V/div CH3: IL, 5A/div CH4: VOUT, 5V/div TIME: 200µs/dv 00% %) 95% Efficiency. VS Load Current 90% 85% 80% Vin2V Efficiency( 75% Vin24V 70% 0 0.5.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Load Current(A) CH: PHASE, 5V/div CH2: VOUT, 200mV/div CH3: IOUT, 5A/div TIME: 2ms/div OCP Hiccup Mode CH: PHASE, 5V/div CH3: IOUT, 5A/div CH4: VOUT, 2V/div TIME: 500ms/dv Cable compensation. VS Sense Voltage. 700 600 5.kΩ mv) 500 6.8kΩ 400 8.2kΩ 5kΩ 300 24kΩ 200 00 Cable compensation( 0 0 0 20 30 40 50 60 70 80 9000020 Sense Voltage(V CS or V CS2 )(mv) Aug-2-205 Rev 2.0 Page5-2 http://www..com/
BLOCK DIAGRAM DETAIL DESCRIPTION The is a synchronous voltage-mode buck PWM controller with programmable dual-output over-current control. Initialization The creates its own internal supplies for use. The POR function continually monitors the input bias supply voltage at the VCC pin. The POR function initiates soft-start operation after VCC supply voltages exceed its POR rising threshold voltage. Soft-start The has an internal soft-start circuitry to reduce supply inrush current during startup conditions. The typical softstart time is about 2ms. The Power-On-Reset function initiates the soft-start process. Once the VCC voltage falls below 6.V, the controller will shut down until the voltage exceeds 7V again. Switch Frequency The on-chip oscillator clock switches at 200 khz Aug-2-205 Rev 2.0 Page6-2 http://www..com/
normally. Over-Current and UVP Protection When the load current is less than the currentlimit, the will regulate the output voltage and operates in the constant voltage mode. If the load current increased beyond the current-limit sensed by the CS pin or CS2 pin and this over-current condition is continuous for 30µs, then the will stop switching for about.3 seconds before initiating a new soft start, if the over current condition is not removed, the converter will hiccup. During this long time sleeping at overcurrent or output under-voltage condition, the input current of the system is nearly zero. OVP and Thermal Shutdown If the output voltage is higher than regulation target, the will immediately stop switching the high-side MOSFET but not lowside MOSFET. The will not open the high-side MOSFET until the output voltage decrease to regulation target. Over temperature protection limits total power dissipation in the device. When the junction temperature exceeds TJ +50 C, a thermal sensor forces the device into shutdown, allowing the die to cool. The thermal sensor turns the device on again after the junction temperature cools by 5 C. BST Capacitor, Bootstrap Refresh A capacitor from the PHASE pin to the BST pin is required for the bootstrap circuit for the High-side Gate driver. The voltage of the PHASE pin can go as high as the supply voltage during the High-side MOSFET opens. A diode is included on the IC (anode to internal PVCC, cathode to BST pin), such that the PVCC will be the bootstrap supply. In the event that the UGATE is on for an extended period of time, the charge on the BST capacitor can start to sag, raising the RDS(ON) of the High-side MOSFET. The has a circuit that detects a long UGATE on-time (7.5 oscillator clock periods), and forces the LG to go high for half an oscillator cycle, which allows the bootstrap capacitor to recharge. DESIGN PROCEDURE Setting Output Voltages Output voltages are set by external resistors. The VREF is 0.8V. According to the typical application diagram: + FIGURE. Setting VOUT with a Resistor-Divider Setting Over-Current Threshold The output over-current value is set by a sense resistor between CSx (x or 2) pin and GND, according to the following equation: I OCP 20mV R CS Output Cable Compensation Output cable compensation voltage can be set by R (FIGURE ). The relationship between R and output cable compensation voltage is calculated below: Aug-2-205 Rev 2.0 Page7-2 http://www..com/
V, If CS2 V V CS V OUT OUT 2 If CS2 V V 3 VCS R V 0kΩ 3 VCS R V 0kΩ V <, CS V OUT OUT 2 3 VCS 2 R V 0kΩ CS CS 2 CS 3 V R CS 2 0 kω Inductor Selection V CS 2 The external components required for the step-down are an inductor, input and output filter capacitors, and compensation RC network. provides best efficiency with continuous inductor current. A reasonable inductor value (LIDEAL) can be derived from the following: L IDEAL VIND( D) f I K SW OUT RIPPLE Where, KRIPPLE is the ratio of the inductor peakto-peak current to the inductor DC current, usually, we set KRIPPLE between 20%-50%. D is the duty cycle: V D V OUT Given LIDEAL, the peak-to-peak inductor current is KRIPPLEIOUT. The absolute-peak inductor current is IOUT(+0.5KRIPPLE). Inductance values smaller than LIDEAL can be used to reduce inductor size; however, if much smaller values are used, inductor current rises, and a larger output capacitance may be required to suppress output ripple. Larger values than LIDEAL can be used to obtain higher output current, but typically with larger inductor size. IN Input Capacitor Selection The input capacitor needs to be carefully selected to maintain sufficiently low ripple at the supply input of the converter. A low ESR capacitor is highly recommended. Since large current flows in and out of this capacitor during normal switching, its ESR also affects efficiency. Use small ceramic capacitors (CHF) for high frequency decoupling and bulk capacitors to supply the surge current needed each time high-side MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of high-side MOSFET and the source of lowside MOSFET. The input buck capacitor should also be placed close to the upper-mosfet s drain and GND, with the shortest layout traces possible. The important parameters for the buck input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least.25 times greater than the maximum input voltage and a voltage rating of.5 times is a conservative guideline. The RMS current is given by: I RMS VOUT VIN IOUT V V IN OUT IRMS has a maximum at VIN2VOUT, where IRMSIOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Output Capacitor Selection The output capacitor is determined by the required ESR to minimize voltage ripple. Aug-2-205 Rev 2.0 Page8-2 http://www..com/
Moreover, the amount of bulk capacitance is also a key for COUT selection to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response. The output ripple is given by: VOUT IL( RESR + ) 8F C SW OUT The output ripple will be highest at maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirement. EMI Consideration Since parasitic inductance and capacitance effects in PCB circuitry would cause a spike voltage on PHASE node when high-side MOSFET is turned on/off, this spike voltage on PHASE may impact on EMI performance in the system. In order to enhance EMI performance, there are two methods to suppress the spike voltage. One is to place an RC snubber between PHASE and GND and make them as close as possible to the high-side MOSFET s source and low-side MOSFET s drain. Another method is to add a resistor in series with the boostrap capacitor C. But this method will decrease the driving capability to the high-side MOSFET. It is strongly recommended to reserve the RC snubber during PCB layout for EMI improvement. Moreover, reducing the PHASE trace area and keeping the main power in a small loop will be helpful on EMI performance. Compensation FIGURE 2. Voltage-Mode Buck Converter Compensation Design The uses voltage-mode control to achieve compensation and fast load transient response. A type-3 feedback network is recommended (see Figure 2). The output voltage (VOUT) is regulated by VREF. The error amplifier output (COMP pin voltage) is compared with the oscillator (OSC) modified saw-tooth wave to provide a pulse-width modulated wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (L and C). The output filter capacitor bank s equivalent series resistance is represented by the series resistor E. The modulator transfer function is the smallsignal transfer function of VOUT/VCOMP. This function is dominated by a DC gain, given by D*VIN/ΔVOSC, and shaped by the output filter, with a double pole break frequency at FLC and a zero at FCE. For the purpose of this analysis, L and D represent the channel inductance and Aug-2-205 Rev 2.0 Page9-2 http://www..com/
its DCR, while C and E represent the total output capacitance and its equivalent series resistance. F LC 2 π L C F CE 2 π C E The compensation network consists of the error amplifier (internal to the ) and the external R-R3, C-C3 components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F0: typically 0. to 0.3 of FSW) and adequate phase margin (better than 45 degrees). Phase margin is the difference between the closed loop phase at F0dB and 80 o.the equations that follow relate the compensation network s poles, zeros and gain to the components (R, R2, R3, C, C2, and C3) in Figure 2. Use the following guidelines for locating the poles and zeros of the compensation network:. Select a value for R (kω~0kω, typically). Calculate value for R2 for desired converter bandwidth (F0). If setting the output voltage via an offset resistor connected to the FB pin, R0 in Figure 2, the design procedure can be followed as presented. R 2 V V OSC 0 IN R F F 2. Calculate C such that FZ is placed at fraction of the FLC, at 0. to 0.75 of FLC (to adjust, change the 0.5 factor to desired number). The higher the quality factor of the output filter and/or the higher the ratio FCE/FLC, the lower the FZ frequency (to maximize phase boost at FLC) C LC 2π R 2 0.5 F LC 3. Calculate C2 such that FP is placed at FCE. C 2 C 2π R 2 C F CE 4. Calculate R3 such that Fz2 is placed at FLC. Calculate C3 such that FP2 is placed below FSW (typically, 0.5 to.0 times FSW). FSW represents the switching frequency. Change the numerical factor to reflect desired placement of this pole. Placement of FP2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the HF ripple component at the COMP pin and minimizing resultant duty cycle jitter. R 3 C 3 F SW 2F R LC π R 3 F SW APPLICAITION INFORMATION Layout is critical to achieve clean and stable operation. The switching power stage requires particular attention. Follow these guidelines for good PC board layout: ) MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency and radiate noise, which results in over-voltage stress on devices. Careful component placement layout and printed circuit design can minimize the voltage spikes induced in the converter. Consider, as an example, the turn-off transition of the upper MOSFET prior to turn-off, the upper MOSFET was carrying the full load current. During turn-off, current stops flowing in the Aug-2-205 Rev 2.0 Page0-2 http://www..com/
upper MOSFET and is picked up by the low side MOSFET or schottky diode. Any inductance in the switched current path generates a large voltage spikes during the switching interval. Careful component selections, layout of the critical components, and use shorter and wider PCB traces help in minimizing the magnitude of voltage spikes. 2) There are two set of critical components in a DC-DC converter using the. The switching power components are most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. 3) The power components and the PWM controller should be placed firstly. Place the input capacitors, close to the power switches. Place the output inductor and output capacitors between the MOSFETs and the load. Also locate the PWM controller nearby MOSFETs. 4) If possible, a multi-layer printed circuit board is recommended. The capacitor CIN and COUT each of them represents numerous capacitors of input and output. Use a dedicated grounding plane and use vias to ground all critical components to this layer. Apply another solid layer as power plane and cut this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the PHASE node is subjected to very high dv/dt voltages, the stray capacitance formed between these islands and the surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal routing. The PCB traces between the PWM controller and the gate of MOSFET and also the traces connecting source of MOSFETs should be sized to carry 2A peak currents. Aug-2-205 Rev 2.0 Page-2 http://www..com/
PACKAGE OUTLINE MSOP0 PACKAGE OUTLINE AND DIMENSIONS Aug-2-205 Rev 2.0 Page2-2 http://www..com/