查询 DAC8541 供应商 捷多邦, 专业 PCB 打样工厂,24 小时加急出货 FEATURES Micropower Operation: 25 µa at 5 V AV DD Power-On Reset to Min-Scale 16-Bit Monotonic Settling Time: 1 µs to ±.3% FSR 16-Bit Parallel Interface On-Chip Output Buffer Amplifier With Rail-to-Rail Operation Hardware Reset to Min-Scale or Mid-Scale Double-Buffered Architecture Asynchronous LDAC Control Data Readback Support 1.8 V Compatible Digital Interface: DV DD = 1.8 V 5.5 V Wide Analog Supply Range: AV DD = 2.7 V 5.5 V 32-Lead 5 mm 5 mm TQFP Package APPLICATIONS Process Control Data Acquisition Systems Closed-Loop Servo Control PC Peripherals Portable Instrumentation DESCRIPTION The DAC8541 is a low-power, single channel, 16-bit, voltage output DAC. Its on-chip precision output amplifier allows rail-to-rail voltage swing to be achieved at the output. The DAC8541 utilizes a 16-bit parallel interface and features additional powerdown function pins as well as hardware-enabled, asynchronous DAC updating and reset capability. The DAC8541 requires an external reference voltage to set the output range of the DAC. The device incorporates a power-on-reset circuit that ensures that the DAC output powers up at min-scale and remains there until a valid write takes place to the device. In addition, the DAC8541 contains a power-down feature, accessed via two hardware pins, that when enabled reduces the current consumption of the device to 2 na at 5 V. The low power consumption of this device in normal operation makes it ideally suited for use in portable battery operated equipment applications. The power consumption is 1.2 mw at AV DD = 5 V reducing to 1 µw in power-down mode. The DAC8541 is available in a 32-lead TQFP package with an operating temperature range of 4 C to 85 C. AVDD DVDD VREFH DAC8541 Sense Data I/O 16 I/O Buffer Input Register DAC Register DAC CS R/W BTC/USB Control Logic Power Down Control Logic Resistor Network AGND DGND RSTSEL RST LDAC VREFL Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PD PD1 Copyright 21, Texas Instruments Incorporated
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. PRODUCT PACKAGE AVAILABLE OPTIONS PACKAGE DRAWING NUMBER TA PACKAGE MARKING DAC8541 32-TQFP PBS 4 C to 85 C E41Y ORDERING NUMBER DAC8541Y/25 DAC8541Y/2K absolute maximum ratings over operating free-air temperature (unless otherwise noted) TRANSPORT MEDIA Tape and Reel AV DD to AGND..........................................................................3 V to 6 V DV DD to DGND..........................................................................3 V to 6 V Digital input voltage to DGND.....................................................3 V to DV DD +.3 V V OUT to AGND.................................................................3 V to AV DD +.3 V Operating temperature range............................................................ 4 C to 85 C Storage temperature range, T stg........................................................ 65 C to 15 C Junction temperature, T J max................................................................... 15 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. electrical characteristics, DV DD = 1.8 V to 5.5 V; AV DD = 2.7 V to 5.5 V; R L = 2 kω to AGND; C L = 2 pf to AGND; all specifications 4 C to 85 C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE (see Note 1) Resolution 16 Bits Relative accuracy ±.98 %FSR Differential nonlinearity 16-Bit monotonic ±1 LSB Zero code error All zeroes loaded to DAC register 5 2 mv Full-scale error All ones loaded to DAC register.15.8 %FSR Gain error ±.8 %FSR Zero code error drift ±2 µv/ C Gain temperature coefficient ±5 OUTPUT CHARACTERISTICS (see Note 2) Output voltage range 2 VREFL VREFH V Output voltage settling time (full scale) RL = 2 kω; pf < CL < 2 pf 8 1 RL = 2 kω; CL = 5 pf 12 Slew rate 1 V/µs Capacitive load stability RL = 47 RL = 2 kω 1 ppm of FSR/ C Digital-to-analog glitch impulse 1 LSB change around major carry (see Note 3) 2 nv s Digital feedthrough.5 nv s DC output impedance 1 Ω Short circuit current Power-up time NOTES: AVDD = 5 V 5 AVDD = 3 V 2 Coming out of power-down mode, AVDD = 5 V 2.5 Coming out of power-down mode, AVDD = 3 V 5 1. Linearity calculated using a reduced code range of 485 to 64714. Output unloaded. 2. Assured by design and characterization, not production tested. 3. Specification for code changes at each N x 496 code boundary. µs pf ma µss
electrical characteristics, DV DD = 1.8 V to 5.5 V; AV DD = 2.7 V to 5.5 V; R L = 2 kω to AGND; C L = 2 pf to AGND; all specifications 4 C to 85 C (unless otherwise noted) (continued) REFERENCE INPUT Reference current PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AVDD = VREFH = 5 V, VREFL = AGND 5 75 AVDD = VREFH = 3.6 V, VREFL = AGND 35 6 VREFH input range VREFH>VREFL AVDD V VREFL input range 1 AGND 1 mv Reference input impedance 1 kω LOGIC INPUTS (see Note 2) Input current ±1 µa VINL, input low voltage DVDD = 1.8 V to 5.5 V.3 DVDD V VINH, input high voltage DVDD = 1.8 V to 5.5 V.7 DVDD V Pin input capacitance 3 pf POWER REQUIREMENTS DVDD 1.8 5.5 V DIDD DAC active and excluding load current, VIH = DVDD and VIL = DGND µaa.2 1. µa AVDD 2.7 5.5 V AIDD (normal operation) AVDD = 3.6 V to 5.5 V AVDD = 2.7 V to 3.6 V AIDD (all power-down modes) AVDD = 3.6 V to 5.5 V AVDD = 2.7 V to 3.6 V POWER EFFICIENCY DAC active and excluding load current, VIH = DVDD and VIL = DGND VIH = DVDD and VIL = DGND IOUT/AIDD I(LOAD) = 2 ma, AVDD = +5 V 89% NOTE 2; Assured by design and characterization, not production tested. 25 4 24 39.2 1.5 1 µaa µaa
PBS PACKAGE (TOP VIEW) DB15 DB14 DB13 DB12 DB11 DB1 DB9 DB8 1 2 3 4 5 6 7 8 32 31 3 29 28 27 26 25 24 23 22 DAC8541 21 2 19 18 17 9 1 11 12 13 14 15 16 V OUT V OUT Sense AGND V REF L V REF H AV DD DV DD DGND DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB CS R/W LDAC RST RSTSEL BTC/USB PD1 PD Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION DB15 DB 1 16 I/O Data input/output, (pin 1-MSB: pin 16-LSB) DGND 17 I Digital ground DVDD 18 I Digital supply input, 1.8 V to 5.5 V AVDD 19 I Analog power supply input, 2.7 V to 5.5 V VREFH 2 I Positive reference voltage input (referenced to AGND) VREFL 21 I Negative reference voltage input (referenced to AGND), nominally VREFL = AGND AGND 22 I Analog ground Sense 23 I Analog output sense. The feedback terminal of the output amplifier. 24 O Analog output voltage from DAC. The output amplifier has rail-to-rail operation. PD 25 I Powerdown control bit PD1 26 I Powerdown control bit 1 BTC/USB 27 I Data input format: binary twos complement or unipolar straight binary RSTSEL 28 I Reset on active RST to min-scale (RSTSEL = ) or mid-scale (RSTSEL = 1) RST 29 I reset to min-scale or mid-scale, rising edge (Does not reset input register data.) LDAC 3 I Asynchronous load command, rising edge R/W 31 I Read/Write control input CS 32 I Chip select, active low
timing characteristics, DV DD = 1.8 V to 5.5 V; AV DD = 2.7 V to 5.5 V; R L = 2 kω to AGND; C L = 2 pf to AGND; all specifications 4 C to 85 C (unless otherwise noted) MIN TYP MAX UNIT tw1 Pulse width: CS low for valid write 2 ns tsu1 Setup time: R/W low before CS falling (see Note 4) ns tsu2 Setup time: data in valid before CS falling ns th1 Hold time: R/W low after CS rising (see Note 4) 1 ns th2 Hold time: data in valid after CS rising 15 ns tw2 Pulse width: CS low for valid read 4 ns tsu3 Setup time: R/W high before CS falling 3 ns td1 Delay time: data out valid after CS falling 6 8 ns th3 Hold time: R/W high after CS rising 1 ns th4 Hold time: data out valid after CS rising 5 2 ns tsu4 Setup time: LDAC rising after CS falling (see Note 4) 1 ns td2 Delay time: CS low after LDAC rising 5 ns tw3 Pulse width: LDAC low 4 ns tw4 Pulse width: LDAC high 4 ns tw5 Pulse width: CS high (see Note 4) 8 ns tsu5 Setup time: RSTSEL valid before RST rising ns th5 Hold time: RSTSEL valid after RST rising 2 ns tw6 Pulse width: RST low 4 ns tw7 Pulse width: RST high 4 ns ts Settling time (settling time for a full scale code change) 1 µs NOTE 4: Simplified operation: CS and W/R can be tied low if the DAC8541 is the only device on the bus and Read operation is not needed. In this case, LDAC is still required to update the output of the DAC and tsu(4) is from Data In Valid to LDAC Rising. tw1 tw5 tw2 CS tsu1 th1 tsu3 th3 R/W Data I/O DB DB15 tsu2 th2 td1 Data In Valid tsu4 td2 Data Out Valid th4 LDAC tw3 tw4 ±.3% of FSR Error Bands ts Figure 1. Data Read/Write Timing
tsu5 RSTSEL tw6 th5 RST tw7 +FS (RSTSEL = Low) FS +FS (RSTSEL = High) FS ts Min-Scale Mid-Scale Figure 2. Reset Timing TYPICAL CHARACTERISTICS This condition applies to all typical characteristics: V REF H = AV DD, V REF L = AGND, T A = 25 C (unless otherwise noted) Linearity Error LSB 64 48 32 16 16 32 48 64 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR DIGITAL INPUT CODE AVDD = 2.7 V, TA = 85 C Differential Linearity Error LSB 2 1.5 1.5.5 1 1.5 2 8192 16384 24576 32768 496 49152 57344 65535 Digital Input Code Figure 3
Linearity Error LSB 64 48 32 16 16 32 48 64 TYPICAL CHARACTERISTICS LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR DIGITAL INPUT CODE AVDD = 2.7 V, TA = 25 C Differential Linearity Error LSB 2 1.5 1.5.5 1 1.5 2 8192 16384 24576 32768 496 49152 57344 65535 Digital Input Code Figure 4
TYPICAL CHARACTERISTICS Linearity Error LSB Differential Linearity Error LSB 64 48 32 16 16 32 48 64 2 1.5 1.5.5 1 1.5 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR DIGITAL INPUT CODE AVDD = 2.7 V, TA = 4 C 2 8192 16384 24576 32768 496 49152 57344 65535 Digital Input Code Figure 5
TYPICAL CHARACTERISTICS 2 15 ZERO-SCALE ERROR FREE-AIR TEMPERATURE AVDD = VREF = 5 V 2 15 FULL-SCALE ERROR FREE-AIR TEMPERATURE To Avoid Clipping of The Output Signal During The Test, VREF = AVDD 1mV Zero-Scale Error mv 1 5 5 1 AVDD = VREF = 2.7 V Full-Scale Error mv 1 5 5 1 AVDD= 2.7 V AVDD = 5 V 15 2 4 15 1 35 6 85 TA Free-Air Temperature C Figure 6 15 2 4 15 1 35 6 85 TA Free-Air Temperature C Figure 7 3 OUTPUT VOLTAGE DRIVE CURRENT CAPABILITY AVDD = VREF = 2.7 V 5 OUTPUT VOLTAGE DRIVE CURRENT CAPABILITY Output Voltage V V OUT 2.5 2 1.5 1.5 DAC Loaded With FFFFh DAC Loaded With h Output Voltage V V OUT 4 3 2 1 DAC Loaded With FFFFh AVDD = VREF = 5 V DAC Loaded With h AI DD Analog Supply Current µ A 5 1 15 I(SOURCE/SINK) Drive Current Capability ma 3 28 26 24 22 Figure 8 ANALOG SUPPLY CURRENT ANALOG SUPPLY VOLTAGE 2 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 AVDD Analog Supply Voltage V Figure 1 Frequency 5 1 15 I(SOURCE/SINK) Drive Current Capability ma 25 2 15 1 5 AVDD = 5 V TA = 25 C Figure 9 AIDD HISTOGRAM 1 15 2 25 3 35 4 AIDD µa Figure 11
TYPICAL CHARACTERISTICS Frequency 25 2 15 1 5 AVDD = 2.7 V TA = 25 C AIDD HISTOGRAM AI DD Analog Supply Current µ A 4 35 3 25 2 15 1 5 ANALOG SUPPLY CURRENT DIGITAL INPUT CODE Excluding Reference and Load Current. AVDD = DVDD = 5 V AVDD = DVDD = 2.7 V 1 15 2 25 3 35 4 AIDD µa 16384 32768 49152 65535 Digital Input Code Figure 12 Figure 13 AI DD Analog Supply Current µ A 35 3 25 2 15 1 5 ANALOG SUPPLY CURRENT FREE-AIR TEMPERATURE Excluding Reference and Load Current. AVDD = DVDD = 5 V AVDD = DVDD = 2.7 V 4 15 1 35 6 85 TA Free-Air Temperature C Figure 14 Power-Down Current na AI DD 5 45 4 35 3 25 2 15 1 5 POWER-DOWN CURRENT SUPPLY VOLTAGE TA = 85 C 2.7 3.4 4.1 4.8 5.5 Figure 15 TA = 4 C TA = 25 C AVDD Supply Voltage V DI DD Digital Supply Current µ A 5 4 3 2 1 DIGITAL SUPPLY CURRENT LOGIC INPUT VOLTAGE DIDD Values are Shown for Logic Level Change on one Digital Input. DVDD = 2.7 V 1 2 3 4 5 Figure 16 DVDD = 5 V VLOGIC Logic Input Voltage V POWER-ON RESET TO V Loaded With 2 kω to AGND AVDD (2 V/div) (1 V/div) 1 2 34 5 6 7 8 91 Figure 17
TYPICAL CHARACTERISTICS EXITING POWER-DOWN AV DD = V REF = 2.7 V Digital Code = 8h Scope Trigger (5 V/div) 2 4 6 8 1 12 14 16 18 2 Figure 18 V OUT (2 V/div) Output Voltage 2 mv/div V OUT MAJOR CARRY CODE CHANGE GLITCH AV DD = DV DD = V REF = 2.7 V Code 8 H to 7FFF H Glitch Occurs Every N 496 Code Boundary..5 1 1.5 2 2.5 3 3.5 4 4.5 5 Figure 19 Output Voltage 5 mv/div V OUT MAJOR CARRY CODE CHANGE GLITCH AV DD = DV DD = V REF = 5 V Code 8 H to 7FFF H Glitch Occurs Every N 496 Code Boundary..5 1 1.5 2 2.5 3 3.5 4 4.5 5 Figure 2 FULL-SCALE SETTLING TIME AV DD = 2.7 V Scope Trigger (5 V/div) Large-Signal Output (1 V/div) Small-Signal Error (1 mv/div) Full-Scale Code Change: H to FFFF H Output Loaded With 2 kω and 2 pf to AGND 2 4 6 8 1 12 14 16 18 2 Figure 21 FULL-SCALE SETTLING TIME AV DD = 2.7 V Large-Signal Output (1 V/div) Full-Scale Code Change: FFFF H to H Output Loaded With 2 kω and 2 pf to AGND Small-Signal Error (1 mv/div) HALF-SCALE SETTLING TIME AV DD = 2.7 V Half-Scale Code Change: 4 H to C H Output Loaded With 2 kω and 2 pf to AGND Large-Signal Output (1 V/div) Small-Signal Error (1 mv/div) Scope Trigger (5 V/div) 2 4 6 8 1 12 14 16 18 2 Figure 22 Scope Trigger (5 V/div) 2 4 6 8 1 12 14 16 18 2 Figure 23
TYPICAL CHARACTERISTICS HALF-SCALE SETTLING TIME FULL-SCALE SETTLING TIME AV DD = 2.7 V Half-Scale Code Change: C H to 4 H Output Loaded With 2 kω and 2 pf to AGND AV DD = 5 V Large-Signal Output (2 V/div) Small-Signal Error (1 mv/div) Large-Signal Output (1 V/div) Small-Signal Error (1 mv/div) Full-Scale Code Change: H to FFFF H Output Loaded With 2 kω and 2 pf to AGND Scope Trigger (5 V/div) 2 4 6 8 1 12 Figure 24 14 16 18 2 Scope Trigger (5 V/div) 2 4 6 8 1 12 Figure 25 14 16 18 2 FULL-SCALE SETTLING TIME Large-Signal Output (2 V/div) AV DD = 5 V Full-Scale Code Change: FFFF H to H Output Loaded With 2 kω and 2 pf to AGND Small-Signal Error (1 mv/div) HALF-SCALE SETTLING TIME AV DD = 5 V Half-Scale Code Change: 4 H to C H Output Loaded With 2 kω and 2 pf to AGND Large-Signal Output (1 V/div) Small-Signal Error (1 mv/div) Scope Trigger (5 V/div) 2 4 6 8 1 12 Figure 26 14 16 18 2 Scope Trigger (5 V/div) 2 4 6 8 1 12 Figure 27 14 16 18 2 HALF-SCALE SETTLING TIME AV DD = 5 V Half-Scale Code Change: C H to 4 H Output Loaded With 2 kω and 2 pf to AGND Small-Signal Error (1 mv/div) Large-Signal Output (1 V/div) Scope Trigger (5 V/div) 2 4 6 8 1 12 14 16 18 2 Figure 28
THEORY OF OPERATION D/A section The architecture of the DAC8541 consists of a string DAC followed by an output buffer amplifier. Figure 29 shows a generalized block diagram of the DAC architecture. VREFH = External Reference Voltage Sense DAC Register REF+ Resistor String REF + VREFL = AGND Figure 29. Generalized DAC Architecture The input coding to the DAC8541 is set by the BTC/USB input to the device. When this input is high, the input code is binary 2s complement. If the input is low, the format is unipolar straight binary, in which case the ideal output voltage is given by: V V H D OUT REF 65536 Where D = the decimal equivalent of the binary code that is loaded to the DAC register, which can range from to 65535 and V REF L = AGND. VREFH RDIVIDE VREFH 2 R R To Output Amplifier (2x Gain) R R VREFL Figure 3. Typical Resistor String
THEORY OF OPERATION resistor string The resistor string section is shown in Figure 3. It is simply a string of resistors, each of which has a value of R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off. This voltage is then presented to the output amplifier by closing one of the switches connecting the string to the amplifier. The negative tap of the resistor string, V REF L, can be tied to AGND or a small voltage can be applied in order to make minor adjustments to the offset seen at the V OUT pin. (This is discussed in more detail in the voltage reference inputs section.) output amplifier The output buffer amplifier is capable of generating near rail-to-rail voltages on its output, which gives an output range of V to AV DD (offset and gain errors affect the absolute V OUT range). It is also capable of driving a load of 2 kω in parallel with 1 pf to AGND while remaining stable. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate of the DAC8541 is typically 1 V/µs with a typical full-scale settling time of 8 µs. For additional functionality, the inverting input of the output amplifier is brought out via the V OUT Sense pin. This allows for better accuracy in critical applications by tying the V OUT Sense and V OUT together directly at the load. Other signal conditioning circuitry may also be connected between these points for specific applications. parallel interface The DAC8541 provides a 16-bit parallel interface and supports both writing to and reading from the DAC input register. (See the timing characteristics section for detailed information for a typical write or read command.) In addition to the data, CS, and R/W inputs, the DAC8541 s interface also provides powerdown, LDAC, data format, and reset/reset-select control. Tables 1 and 2 show the control signal actions and data format, respectively. These features are discussed in more detail in the remaining sections. Table 1. DAC8541 CONTROL SIGNAL SUMMARY CS R/W BTC/USB LDAC RST RSTSEL PD1 PD ACTION H X X X X X X X Device data I/O is disabled on the bus. L X X H,L X L L Write initiated, present input data to the bus. H X X H,L X L L Read initiated, data from input register is presented to data bus. X X X H,L X L L Input data is latched when writing to the device. X X X H,L X L L Data from input register is transferred to DAC register and is updated. X X L X X X X X Input/output data format is unipolar straight binary. X X H X X X X X Input/output data format is binary 2s complement. X X X X L L L DAC register and reset to min-scale. (If DAC is powered down during reset, DAC register resets and will settle to min-scale upon power up.) X X X X H L L DAC register and reset to mid-scale. (If DAC is powered down during reset, DAC register resets and will settle to mid-scale upon power up.) X X X X X X L H Powerdown device, impedance equals 1 kω to AGND X X X X X X H L Powerdown device, impedance equals 1 kω to AGND X X X X X X H H Powerdown device, impedance equals high impedance Only disables 16-bit data I/O interface. Other control lines remain active.
THEORY OF OPERATION data format Table 2 details the input data format of the DAC8541. Two data I/O formats are available to the host interface. These two formats are binary 2s complement (BTC) and unipolar straight binary (USB). The BTC/USB input pin controls the format used by the DAC. The data format selected by the BTC/USB input is used for data written into the device as well as data that is read back from the DAC8541. (Refer to Table 1 and Figure 1 for additional information for performing read and write operations.) LDAC function Table 2. DAC8541 Data Format BTC/USB = BTC/USB = 1 UNIPOLAR STRAIGHT BINARY BINARY 2s COMPLEMENT DIGITAL INPUT ANALOG OUTPUT DIGITAL INPUT ANALOG OUTPUT xh Min-scale x8h Min-scale x1h Min-scale + 1 LSB x81h Min-scale + 1 LSB x8h Mid-scale xh Mid-scale x81h Mid-scale + 1 LSB x1h Mid-scale + 1 LSB xffffh Full Scale x7fffh Full Scale The DAC8541 is designed using a double-buffered architecture. A write command transfers data from the data input pins into the input register. The data is held in the input register until a rising edge is detected on the LDAC input. This rising edge signal transfers the data from the input register to the DAC register. Upon issuance of the rising LDAC edge, the output of the DAC8541 begins settling to the newly written data value presented to the DAC register.(data in the input register is not changed when an LDAC command is given.) RST and RSTSEL The RST and RSTSEL inputs control the reset of the DAC register and consequently, the DAC output. The reset command is edge triggered by a low-to-high transition on the RST pin. Once a rising edge on RST is detected, the DAC output may settle to the mid-scale or min-scale code depending on the state of the RSTSEL input. A logic high value on RSTSEL causes the DAC output to reset to mid-scale and a logic low value resets the DAC to min-scale. Application of a valid reset signal to the DAC does not overwrite existing data in the input register. power-on reset The DAC8541 contains a power-on reset circuit that controls the output voltage during power up. On power up, the DAC register (and DAC output) is set to min-scale (plus a small offset error produced by the output buffer). It remains at min-scale until a valid write sequence is made to the DAC changing the DAC register data. This is useful in applications where it is important to know the state of the output of the DAC while the system is in the process of powering up. DGND must be applied to all digital inputs until the digital and analog supplies are applied to the DAC8541. Logic voltages applied to the input pins when power is not applied to DV DD and AV DD, may power the device through the ESD input structures causing undesired operation.
THEORY OF OPERATION power-down modes The DAC8541 utilizes four modes of operation. These modes are programmable via two inputs (PD1 and PD) to the device. Table 3 shows how the state of these pins correspond to the mode of operation of the DAC8541. Table 3. Modes of Operation for the DAC8541 PD1 PD OPERATING MODE Normal operation POWER-DOWN MODES 1 1 kω to AGND 1 1 kω to AGND 1 1 High impedance When both pins are set to, the device works normally with its typical power consumption of 25 µa at AV DD = 5 V. However, for the three power-down modes, the supply current falls to 2 na at AV DD = 5 V (5 na at AV DD = 3 V). Not only does the supply current fall, but the V OUT terminal is internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the device is known while in power-down mode. There are three different options: The output is connected internally to AGND through a 1-kΩ resistor, it is connected to AGND through a 1-kΩ resistor, or it is left open-circuited (high impedance). The output stage is illustrated in Figure 31. DAC Amplifier _ + Sense Powerdown Circuitry Resistor Network Figure 31. Output Stage During Power Down (High-Impedance) All analog circuitry is shut down when a power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. This allows the DAC s output voltage to return to the previous level when power-up resumes. The delay time required to exit power-down is typically 2.5 µs for AV DD = 5 V and 5 µs for AV DD = 3 V. (See the typical curves section for additional information.) voltage reference inputs Two voltage inputs provide the reference set points for the DAC architecture. These are V REF H and V REF L. For typical rail-to-rail operation, V REF H should be equivalent to AV DD and V REF L tied to AGND. The output voltage is given by: V OUT V REF H 2 V REF L The use of the V REF L input allows minor adjustments to be made to the offset of the DAC output by applying a small voltage to the V REF L input. The acceptable range is between 1 mv and 1 mv with respect to AGND. A low output impedance source is needed, so that the accuracy of the DAC over its operating range is not affected.
THEORY OF OPERATION analog and digital supplies The DAC8541 utilizes two separate supplies for operation. The analog supply (AV DD ) powers the output buffer and DAC while the digital supply (DV DD ) sets the I/O voltage thresholds. Refer to the device specification table for additional information. AV DD can operate from 2.7 V to 5.5 V while DV DD can independently function from 1.8 V to 5.5 V. The control and data I/O thresholds are determined by DV DD and are given in the electrical characteristics section. host processor interfacing APPLICATION INFORMATION DAC8541 to MSP43 microcontroller Figure 32 shows a typical parallel interface connection between the DAC8541 and a MSP43 microcontroller. The setup for the interface shown uses ports 4 and 5 of the MSP43 to send or receive the 16-bit data while bits 7 of port 2 provides the control signals for the DAC. When data is to be transmitted to the DAC8541, the data is made available to the DAC via P4 and P5 and P2.1 is taken low. The MSP43 then toggles P2. from high-to-low and back to high, transferring the 16-bit data to the DAC. This data is loaded into the DAC register by applying a rising edge to P2.4. The remaining five I/O signals of P2 shown in the figure control the reset, power-down, and data format functions of the DAC. Depending on the specific requirements of a given application, these pins may be tied to DGND or DV DD, enabling the desired mode of operation. MSP43F149 P4[:7] P5[:7] 8 Bits 8 Bits 16 Bits DAC8541 D[15:] AVDD.1 µf 1 µf AVDD P2: CS P2:1 P2:2 P2:3 R/W RST RSTSEL DVDD.1 µf 1 µf DVDD P2:4 P2:5 P2:6 LDAC PD PD1 SENSE P2:7 BTC/USB VREFL DGND VREFH AGND VREF.1 µf 1 to 1 µf (Other Connections Omitted for Clarity) DAC8541 to TMS32C542 DSP Figure 32. DAC8541 to MSP43 Microcontroller Figure 33 shows the connections between the DAC8541 and the TMS32C542 digital signal processor. Data is provided via the parallel data bus of the DSP while the DAC s CS control input is derived from the decoded I/O strobe signal. The IOSTRB in addition to the R/W and XF(I/O) signals control the data transmission to and from the DAC as well as the LDAC control. With additional decoding, multiple DAC8541 s can be connected to the same parallel data bus of the DSP.
APPLICATION INFORMATION TMS32C542 D[15:] 16 Bits D[15:] DAC8541 AVDD AVDD A[23:].1 µf 1 µf IOSTRB Address EN Decoder CS DVDD DVDD R/W XF(I/O) R/W LDAC SENSE.1 µf 1 µf VREFL DGND VREFH AGND VREF.1 µf 1 to 1 µf (Other Connections Omitted for Clarity) bipolar operation using the DAC8541 Figure 33. DAC8541 to TMS32 DSP The DAC8541 has been designed for single-supply operation but a bipolar output range is also possible using the circuit shown in Figure 34. The circuit allows the DAC8541 to achieve an analog output range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an OPA73 as the output amplifier. Setting BTC/USB = 1, sets the DAC into binary 2s complement I/O format for the bipolar V OUT configuration. When operated with BTC/USB set high, the output voltage for any input code can be calculated as follows: V OUT V REF H D 65536 R1 R2 R1 V REF H R2 where D represents the input code in decimal, unipolar straight binary ( 65535) and V REF L = AGND. With V REF H = 5 V, R 1 = R 2 = 1 kω: V OUT 1 D 5V 65536 This is an output voltage range of ±5 V with 8h corresponding to a 5 V output and 7FFFh corresponding to a 5 V output. Bipolar zero is given by h applied to the DAC. R1 R2 = 1 kω 1 µf 5 V.1 µf R1 = 1 kω VREFH DAC8541 Sense VREFL + 5 V 5 V OPA73 ±5 V (Other Pins Omitted for Clarity) Figure 34. Bipolar Operation With the DAC8541
APPLICATION INFORMATION layout A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The following measures should be taken to assure optimum performance of the DAC8541. The DAC8541 offers dual-supply operation, as it can often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more important it becomes to separate the analog and digital ground and supply planes at the DAC. Because the DAC8541 has both analog and digital ground pins, return currents can be better controlled and have less effect on the DAC s output error. Ideally, AGND would be connected directly to an analog ground plane and DGND to the digital ground plane. The analog ground plane would be separate from the ground connection for the digital components until they were connected at the power entry point of the system. The power applied to AV DD and V REF H (this also applies to V REF L if not tied to AGND) should be well-regulated and low-noise. Switching power supplies and dc/dc converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. As with the AGND connection, AV DD should be connected to a 5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. In addition, the 1-µF to 1-µF and.1-µf bypass capacitors are strongly recommended. In some situations, additional bypassing may be required, such as a 1-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors all designed to essentially lowpass filter the AV DD supply, removing the high frequency noise.
PBS (S-PQFP-G32) MECHANICAL DATA PLASTIC QUAD FLATPACK,23,5,8 M,17 24 17 25 16 32 9,13 NOM 1 8 3,5 TYP 5,5 4,95 SQ 7,1 SQ 6,9,1 MIN,25 Gage Plane 7 1,5,95,7,4 Seating Plane 1,2 MAX,8 487735/A 11/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.
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