STM32 PMSM FOC Shanghai, March,2008
Agenda STM32 FOC Clark Parke Circle limitation Mar 08 1
Agenda / Hall PMSM PLL MC_State_observer_param.h Mar 08 2
Agenda MC_Control_param.h / PI Mar 08 3
Plan STM32 Cortex-M3 NVIC PWM ADC Mar 08 4
Cortex-M3 Cortex-M3 3 & Thumb -2 ALU & & Cortex-M3 Cortex-M3 debug MPU & ETM (Not available in STM32F10x) Mar 08 5
Cortex-M3 (1/2) ARM v7m Thumb-2 16 32 (NVIC) ISR ( ARM7 ) C, ( & ) & (SysTick)OS Mar 08 6
Cortex-M3 (2/2) 3, & Source Destination Cycles 16b x 16b 32b 1 32b x 16b 32b 1 32b x 32b 32b 1 32b x 32b 64b 3-7* *UMULL, SMULL,UMLAL, and SMLAL source UDIV & SDIV (Unsigned or Signed divide) 2 12 ( / ) Mar 08 7
/ LDM/STM ISR ISR C Cortex-M3 (Nested Vectored Interrupt Controller---NVIC) 43 ( 16 Cortex-M3 ) 16 - Tail-chaining - Late-arrival Mar 08 8
{PC, xpsr, R0-R3, R12, LR} ISR. PUSH ISR. ISR,., POP POP, ISR Mar 08 9
Highest - Tail Chaining IRQ1 IRQ2 ARM7 Cortex-M3 ARM7 PUSH ISR 1 POP PUSH ISR 2 POP 26 16 26 16 PUSH ISR 1 ISR 2 POP 12 Tail-chaining 42 CYCLES 6 12 6 CYCLES Cortex-M3 65% Saving in Clock Cycles IRQ1 ISR1 26 LSM 42 ISR1 ISR2 42 ISR2 16 IRQ1 ISR1 12 LSM 12 ISR1 ISR2 6 ISR2 12 Mar 08 10
NVIC / / 1 0 1 1 0 --Active Bit 1 activestacked 4 Mar 08 11
NVIC PRIGROUP group-priority sub-priority Group priority IRQ3 IRQ4 Preempting Priority PRIGROUP Binary Point Sub-Priority (Group Priority) (3 Bits) (group.sub) Bits Levels Bits Levels 011 4.0 gggg 4 16 0 0 100 3.1 gggs 3 8 1 2 101 2.2 ggss 2 4 2 4 110 1.3 gsss 1 2 3 8 111 0.4 ssss 0 0 4 16 Mar 08 12
Cortex-M3 No. Exception Type Priority Type of Priority 1 Reset -3 (Highest) fixed Reset Descriptions 2 3 4 5 6 NMI Hard Fault -2-1 fixed fixed Non-Maskable Interrupt Default fault if other hander not implemented MemManage Fault 0 settable MPU violation or access to illegal locations Bus Fault Usage Fault 1 2 settable settable Fault if AHB interface receives error Exceptions due to program errors 7-10 Reserved N.A. N.A. 11 12 13 14 15 16 SVCall Debug Monitor 3 4 settable settable System Service call Break points, watch points, external debug Reserved PendSV SYSTICK Interrupt #0 N.A. 5 6 7 N.A. settable settable settable Pendable request for System Device System Tick Timer External Interrupt #0 256... settable... In STM32F10x 43 Interrupts are implemented (total interrupts available 59) Interrupt#240 247 settable External Interrupt #240 Mar 08 13
Plan Cortex-M3 NVIC PWM ADC Mar 08 14
ETR Clock ITR 1 ITR 2 ITR 3 ITR 4 Trigger/Clock Controller Trigger Output 16-Bit Prescaler +/- 16-Bit Counter Auto Reload REG CH1 CH2 CH3 CH4 BKIN Capture Compare Capture Compare Capture Compare Capture Compare CH1 CH1N CH2 CH2N CH3 CH3N CH4 Mar 08 15
PWM APB 2 72MHz 13.8ns ( ) PWM DMA Mar 08 16
MCPU PWM (U) duty cycle U on overflow N N+1 U on underflow U on underflow Comp = N Comp = N + 1 Comp from N to N + 1 U event during Underflow Single update U event during Over & Underflow Double update Mar 08 17
PWM U (Update) 4 duty cycle 1 PWM PWM duty cycles PWM U 8 / Mar 08 18
PWM counter Double update REP=0 Single update OVF REP=1 Single update UDF REP=1 ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR t t t REP=2 ISR ISR ISR t REP=3 ISR ISR t Mar 08 19
PWM DMA ( / )/ DMA Mar 08 20
PWM DMABurst mode DMA DMA ( ) RAM OC1 t0 OC2 t0 OC3 t0 OC1 t1 OC2 t1 OC3 t1 OC1 t2 OC2 t2 Registers OC1 OC2 OC3 Virtual Register OC3 t2 Mar 08 21
PWM 8 72MHz 13.8ns (from 0 to 14µs, ) OC1REF CH1 CH1N Delay 5V 0V 5V 0V 5V 0V Internal PWM before dead time generator High side PWM Low side PWM Delay 6 PWM () Mar 08 22
PWM 1/2 PWM timer used as a GP timer Motor Control (sinewave) Motor Control (6-steps) Motor Control (sinewave) Outputs disconnected from I/O ports All PWMs OFF (low Z for safe stop) Mar 08 23
PWM 2/2 : BLDC 6-steps T1 T3 T5 T1 T2 T4 T6 T2 T3 Step High Low OC1 OC1N OC2 OC2N OC3 OC3N 1 T1 T4 oc1ref 0 0 1 0 0 2 T1 T6 oc1ref 0 0 0 0 1 3 T3 T6 0 0 oc2ref 0 0 1 4 T3 T2 0 1 oc2ref 0 0 0 5 T5 T2 0 1 0 0 oc3ref 0 6 T5 T4 0 0 0 0 oc3ref 0 T4 T5 T6 Phase current Mar 08 24
: BRK : MOE ( ) = 0 1 OISx PMSM : AOE=0 MOE 0 1 BRK AOE=1 MOE U1 =U (ETR) Mar 08 25
( ) PWM ( ) MCU ( ) 4 GPIO PWM Mar 08 26
Debug debug PWM : duty cycle : PWM Mar 08 27
Plan Cortex-M3 NVIC PWM ADC Mar 08 28
Hall Hall ( Hall) 1, 2 & 3 (2x, 4x) Mar 08 29
TIM CLK ITR1 ITR2 ITR3 ITR4 Trigger Controller Controller TRGx 16 bit Prescaler 16 bit AutoReload Register +/- 16-Bit Counter Encoder Interface TI1 TI2 Polarity Select & Edge Controller Polarity Select & Edge Controller Mar 08 30
TIM STM32 : MCU (Z ) Example of counter operation in Encoder Interface mode forward reversal backward reversal forward IC2 IC1 Up Down Up Counter Mar 08 31
x4: 1000 4000 x2: A ( B) : / 0xFFFF 360 60, 90, Mar 08 32
TIM Hall TI1F_ED Trigger & Slave Mode Controller Hall A Hall B XOR Hall C Input Filter & Edge detector TRC IC1 Prescaler Capture/Compare 1 Register Input Filter & Edge detector TRC IC2 Prescaler Capture/Compare 2 Register Input Filter & Edge detector TRC IC3 Prescaler Capture/Compare 3 Register TI4 Input Filter & Edge detector TRC IC4 Prescaler Capture/Compare 4 Register Mar 08 33
Plan Cortex-M3 NVIC PWM ADC Mar 08 34
PWM TI1 TI2 CK_TIM TRG1 TRG2 TRG3 TIM0 Trigger Controller TRGO TRG0 TI1 TI2 : clock, reset, update, enable, Mar 08 35
Clock Master ARR Master CNT Master Trigger Out Slave CNT Clock New Master OCR1 Master OCR1 Master CNT Master OC1 Slave CNT Mar 08 36
1/3: MASTER CLOCK Timer 0 prescaler counter Update Trigger Controller TRG 0 SLAVE / MASTER ITR 0 ITR 1 ITR 2 Timer 1 prescaler counter Trigger Controller Update TRG 2 ITR0 SLAVE Timer 2 ITR 1 ITR 2 prescaler counter Mar 08 37
2/3: MASTER CLOCK prescaler counter Timer 0 Update Trigger Controller TRG 0 ITR 0 ITR 2 ITR 3 SLAVE 1 Timer 1 prescaler counter SLAVE 2 ITR 0 ITR 1 ITR 3 Timer 2 prescaler counter SLAVE 3 ITR 0 PWM ITR 1 ITR 2 prescaler counter Mar 08 38
3/3: BLDC Hall TIM1 MASTER ( ) Hall XOR ITR 0 ITR 1 prescaler TIM2 Trigger Controller TRG 2 ITR0 SLAVE ( ) TIM1 ITR 2 counter Update ITR 1 ITR 2 prescaler counter Mar 08 39
Plan Cortex-M3 NVIC PWM ADC Mar 08 40
ADC (1/3) ADC 1MHZ 12 (1.5~239.5cy) 107ns ADC 0<=VIN<=VREF+(LQFP100 VREF+) 18 DMA ADC ADC1 ADC2 ADC1 DMA ADC2 16 Mar 08 41
First channel Conversion First channel Conversion First injected channel Conversion Second channel Conversion Trigger Second channel Conversion Second injected channel Conversion Last channel Conversion Last channel Conversion Last injected channel Conversion Interrupt Mar 08 42
ADC (2/3) ADC ( ) 16DMA Mar 08 43
ADC (3/3) 4 1.5cy(Rin<1.2K) 239.5cy(Rin<350K) 8 1MSps Mar 08 44
VREF+ ADC VREF- VDDA VSSA ADCCLK ADC Prescalers: Div2, Div4, Div6 and Div8 PCLK2 ADC_IN0 ADC_IN1... ADC_IN15 GPIO Ports Temp Sensor ANALOG MUX Up to 4 Up to 16 ADC Injected Channels Regular Channels Regular data register (12bits) Injected data registers (4x12bits) DMA Request Address/data bus VREFINT Analog Watchdog End of conversion End of injected conversion TIM1_TRGO TIM1_CC4 TIM1_TRGO TIM2_CC1 Start Trigger (injected group) High Threshold register (12bits) Analog watchdog event Ext_IT_15 TIM3_CC4 TIM4_TRGO TIM1_CC1 JEXTRIG bit JEXTSEL[2:0] bits Low Threshold register (12bits) AWD EOC JEOC AWDIE EOCIE JEOCIE Flags Interrupt enable bits TIM1_CC2 TIM1_CC3 TIM2_CC2 Start Trigger (regular group) Ext_IT_11 TIM3_TRGO TIM4_CC4 EXTSEL[2:0] bits EXTRIG bit ADC interrupt to NVIC Mar 08 45
ADC (1/2) 2 ADC MCU ADC1 ADC2 8 ADC VREFINT ADC_IN15 ADC_IN1ADC_IN0 Temp Sensor GPIO Ports ANALOG MUX Up to 4 injected channels Up to 16 regular channels External event (Regular group) ADC1 Analog External event sync ADC2 Analog External event (Injected group) Digital Master Data register Digital Slave EOC/JEOC Mar 08 46
ADC (2/2) 4 Sampling ADC2 CH0 CH1 CH2 CH3 Conversion ADC1 CH15 CH13 CH1 CH2 Trigger for injected channels End of Injected Conversion on ADC1 and ADC2 ADC2 ADC1 Trigger for regular channels CH0 7 ADCCLK cycles CH0 CH0 CH0 CH0 CH0 Up to 2 MSps data throughput (DMA-based) Mar 08 47
DMA ADC 16-bit ADC1 Data2 Ctrl Status Data1 32-bit DMA transfer Data2 RAM Data1 Aliased Ctrl Data2 Data2 Data1 Data1 ADC2 Status Data2 1 single DMA transfer for two data Mar 08 48
STM32 PWMADC 2 PWM PWM 4 ADC DMA Mar 08 49
U PWM UADC MASTER CLOC K prescaler counter Update PWM Trigger Controller TRG 0 Injection trigger ADC1&2 Mar 08 50
TIM1 CH4 Mar 08 51
Plan Cortex-M3 NVIC PWM ADC Mar 08 52
STM32 3 / PMSM AC AC: Hall PMSM Mar 08 53