ebook122-11

11 (test bench) Verilog HDL 11.1 1) ( ) 2) 3) Verilog HDL module T e s t _ B e n c h; // L o c a l _ r e g _ a n d _ n e t _ d e c l a r a t i o n s G e n e r a t e _ w a v e f o r m s _ u s i n g & s t a t e m e n t s I n s t a n t i a t e _ m o d u l e _ u n d e r _ t e s t M o n i t o r _ o u t p u t _ a n d _ c o m p a r e _ w i t h _ e x p e c t e d _ v a l u e s m o d u l e 11.2 1) 2) 11.2.1 : R e s e t = 0; #100 R e s e t = 1; #80 Reset = 0; #30 Reset = 1; 11-1 I n i t i a l

11 119 R e s e t = 0; R e s e t = #100 1; R e s e t = #80 0; R e s e t = #30 1; 11-1 initial R e s e t <= 0; R e s e t <= #100 1; R e s e t <= #180 0; R e s e t <= #210 1; 11-1 11-2 p a r a m e t e r REPEAT_DELAY = 35; i n t e g e r C o i n V a l u e ; CoinValue = 0; #7 C o i n V a l u e = 25; #2 C o i n V a l u e = 5; #8 C o i n V a l u e = 10; #6 C o i n V a l u e = 5; #R E P E A T _ D E L A Y; 11-2 always 11.2.2

120 Verilog HDL a s s i g n # (P E R I O D/2) Clock = ~ C l o c k; C l o c k ( ) z x ~ x x C l o c k x C l o c k C l o c k = 0; C l o c k ( ) m o d u l e Gen_Clk_A (C l k _ A) ; o u t p u t C l k _ A; r e g C l k _ A ; p a r a m e t e r tperiod = 10; C l k _ A = 0; always # (t P E R I O D/2) Clk_A = ~ C l k _ A; m o d u l e 11-3 11-3 m o d u l e Gen_Clk_B (C l k _ B) ; o u t p u t C l k _ B; r e g S t a r t; S t a r t = 1; #5 S t a r t = 0; n o r #2 (Clk_B, Start, C l k _ B) ; m o d u l e // 2 S t a rt 1 0 ( x ) 5 S t a rt 0 4 11 - m o d u l e Gen_Clk_C (C l k _ C) ; p a r a m e t e r ton = 5, t O F F = 10; o u t p u t C l k _ C ;

11 121 r e g C l k _ C ; # ton Clk_C = 0; # toff Clk_C = 1; m o d u l e 11-4 0 1 11-5 f o r e v e r 11-5 m o d u l e Gen_Clk_D (Clk_D); o u t p u t C l k _ D ; r e g C l k _ D ; p a r a m e t e r START_DELAY = 5, LOW_TIME = 2, HIGH_TIME = 3; Clk_D = 0; # S T A R T _ D E L A Y ; f o r e v e r # LOW_TIME ; Clk_D = 1; # H I G H _ T I M E; Clk_D = 0; m o d u l e 11-6 r e p e a t

122 Verilog HDL m o d u l e Gen_Clk_E (C l k _ E) ; o u t p u t C l k _ E ; r e g C l k _ E ; p a r a m e t e r Tburst = 10, Ton = 2, Toff = 5; C l k _ E = 1'b0; r e p e a t(t b u r s t) # Toff Clk_E= 1'b1; # Ton Clk_E = 1'b0; m o d u l e 11-6 G e n _ C l k _ E T b u r s t To n To f f m o d u l e T e s t; w i r e Clk_Ea, Clk_Eb, Clk_Ec; Gen_Clk_E G1(C l k _ E a) ; // 10 2 5 Gen_Clk_E # (5, 1, 3) (C l k _ E b) ; // 5 1 3 Gen_Clk_E # (25, 8, 10) (C l k _ E c) ; // 25 8 10 m o d u l e C l k _ E b 11-7 11-7 11-8 m o d u l e Phase (Master_Clk, Slave_Clk ); o u t p u t Master_Clk, Slave_Clk; reg Master_Clk;

11 123 w i r e S l a v e _ C l k ; p a r a m e t e r t O N = 2, toff = 3, tphase_delay = 1; #ton Master_Clk= 0; #toff Master_Clk= 1; assign #tphase_delay Slave_Clk = M a s t e r _ C l k; m o d u l e 11-8 11.3 11.3.1 2-4 ` t i m e s c a l e 1ns / 1ns m o d u l e D e c 2 x 4 (A, B, Enable, Z) ; i n p u t A, B, Enable; o u t p u t [0:3] Z; w i r e Abar, Bbar; n o t # (1, 2) V0 (Abar, A), V1 (Bar, B) ; n a n d # (4, 3) N0 (Z [0], Enable, Abar, Bbar), N1 (Z [1], Enable, Abar, B), N2 (Z [2], Enable, A, Bbar), N3 (Z [3], Enable, A, B), m o d u l e m o d u l e D e c _ T e s t ; r e g Da, Db, Dena; w i r e [0:3] D z ; / / Dec2x4 D1 (Da, Db, Dena, Dz) ;

124 Verilog HDL // Dena = 0; Da = 0; D b = 0; #10 Dena = 1; #10 Da = 1; #10 D b = 1; #10 D a = 0; #10 D b = 0; #10 $stop; / / @ (Dena o r Da o r Db or D z) $d i s p l a y ("At time %t, input is %b%b%b, output is,%b" $ t i m e, Da, Db, Dena, Dz) ; m o d u l e At time 4, input is 000, output is 1111 At time 10, input is 001, output is 1111 At time 13, input is 001, output is 0111 At time 20, input is 101, output is 0111 At time 23, input is 101, output is 0101 At time 26, input is 101, output is 1101 At time 30, input is 111, output is 1101 At time 33, input is 111, output is 1100 At time 36, input is 111, output is 1110 At time 40, input is 011, output is 1110 At time 44, input is 011, output is 1011 At time 50, input is 001, output is 1011 At time 54, input is 001, output is 0111 11.3.2 D m o d u l e MSDFF (D, C, Q, Qbar) ; i n p u t D, C; o u t p u t Q, Qbar; not NT1 (NotD, D ) NT2 (NotC, C) NT3 (NotY, Y ) nand N D 1 (D1, D, C), N D 2 (D2, C, NotD), N D 3 (Y, D1, Ybar),

11 125 ND4 (Ybar, Y, D2), ND5 (Y1, Y, NotC), ND6 (Y2, NotY, NotC), N D 7 (Q, Qbar, Y1), N D 8 (Qbar, Y2, Q) ; m o d u l e m o d u l e T e s t ; r e g D, C; w i r e Q, Qb; MSDFF M1 (D, C, Q, Qb) ; #5 C = ~ C; D = 0; C = 0; #40 D = 1; #40 D = 0; #40 D = 1; #40 D = 0; $s t o p; $ m o n i t o r ("Time = %t ::", $t i m e,"c=%b, D=%b, Q=%b, Qb=%b", C,D, Q, Qb ); m o d u l e 0:: C=0, D=0, Q=x, Qb=x 5:: C=1, D=0, Q=x, Qb=x 10:: C=0, D=0, Q=0, Qb=1 15:: C=1, D=0, Q=0, Qb=1 20:: C=0, D=0, Q=0, Qb=1 25:: C=1, D=0, Q=0, Qb=1 30:: C=0, D=0, Q=0, Qb=1 35:: C=1, D=0, Q=0, Qb=1 40:: C=0, D=1, Q=0, Qb=1 45:: C=1, D=1, Q=0, Qb=1 50:: C=0, D=1, Q=1, Qb=0 55:: C=1, D=1, Q=1, Qb=0 60:: C=0, D=1, Q=1, Qb=0 65:: C=1, D=1, Q=1, Qb=0 70:: C=0, D=1, Q=1, Qb=0 75:: C=1, D=1, Q=1, Qb=0 80:: C=0, D=0, Q=1, Qb=0

126 Verilog HDL 85:: C=1, D=0, Q=1, Qb=0 90:: C=0, D=0, Q=0, Qb=1 95:: C=1, D=0, Q=0, Qb=1 100:: C=0, D=0, Q=0, Qb=1 105:: C=1, D=0, Q=0, Qb=1 110:: C=0, D=0, Q=0, Qb=1 115:: C=1, D=0, Q=0, Qb=1 120:: C=0, D=1, Q=0, Qb=1 125:: C=1, D=1, Q=0, Qb=1 130:: C=0, D=1, Q=1, Qb=0 135:: C=1, D=1, Q=1, Qb=0 140:: C=0, D=1, Q=1, Qb=0 145:: C=1, D=1, Q=1, Qb=0 150:: C=0, D=1, Q=1, Qb=0 155:: C=1, D=1, Q=1, Qb=0 11.4 $ re a d m e m b ( ) 3 t e s t. v e c A B m o d u l e Adder1Bit (A, B, Cin, Sum, Cout ); i n p u t A, B, Cin; o u t p u t Sum, Cout; a s s i g n S u m = (A ^ B ) ^ Cin; a s s i g n Cout = (A ^ B ) (A & Cin ) (B & Cin ); m o d u l e m o d u l e Adder3Bit (First, Second, Carry_In,Sum_Out, Carry_Out ); i n p u t [0:2] First, Second; i n p u t C a r r y _ I n; o u t p u t [0:2] S u m _ O u t; o u t p u t C a r r y _ O u t ; wire [0:1] C a r ; A d d e r 1 B i t A1 (F i r s t[2], S e c o n d[2], Carry_In,Sum_Out [2], C a r[ 1 ]) A2 (F i r s t[1], S e c o n d[1], C a r[1], Sum_Out [ 1 ],C a r[ 0 ]), A3 (F i r s t[0], S e c o n d[0], C a r[0], Sum_Out [0], C a r r y _ O u t) ; m o d u l e m o d u l e T e s t B e n c h;

11 127 p a r a m e t e r B I T S = 11, WORDS= 2 ; reg [1:BITS] V m e m [ 1 :W O R D S] ; r e g[ 0 : 2 ]A, B, S u m _ E x; r e g Cin, Cout_Ex; i n t e g e r J; w i r e [0:2] S u m; w i r e C o u t; / / A d d e r 3 B i t F1 (A, B, Cin, Sum, Cout) ; $readmemb ("test.vec", Vmem) ; f o r (J = 1; J <= W O R D S; J = J + 1) {A, B, Cin, Sum_Ex, Cout_Ex } = V m e m [J]; #5; // 5 i f ((S u m! = = S u m _ E x) (Cout! = = C o u t _ E x) ) $d i s p l a y ("****Mismatch on vector %b *****", Vmem [J]); e l s e $d i s p l a y ("No mismatch on vector %b", Vmem [J]); m o d u l e V m e m $re a d m e m b t e s t. v e c V m e m f o r No mismatch on vector 01001001000 No mismatch on vector 01001111100 11.5 $f d i s p l a y $ f m o n i t o r $ f s t r o b e m o n. O u t m o d u l e F _ T e s t _ B e n c h; p a r a m e t e r BITS = 11, WORDS= 2 ; r e g [ 1 :B I T S] Vmem [ 1 :W O R D S] ; r e g [0:2] A, B, Sum_Ex; r e g C i n, C o u t _ E x

128 Verilog HDL i n t e g e r J ; w i r e [0:2] S u m; w i r e C o u t; / / A d d e r 3 B i t F1 (A, B, Cin, Sum, Cout) ; : I N I T _ L A B L E i n t e g e r M o n _ O u t _ F i l e; Mon_Out_File = $f o p e n (" m o n. o u t "); $r e a d m e m b ("test.vec", Vmem) ; f o r (J = 1; J <= W O R D S; J = J + 1) {A, B, Cin, Sum_Ex, Cout_Ex } = Vmem [J]; #5; // 5 i f ((Sum! = = Sum_Ex) (Cout! = = Cout_Ex) ) $d i s p l a y ("****Mismatch on vector %b *****", V m e m [J]); e l s e $d i s p l a y ("No mismatch on vector %b", V m e m [J]); // : $f d i s p l a y (Mon_Out_File,"Input = %b%b%b, Output = %b%b", A, B, Cin, Sum, Cout) ; $f c l o s e (M o n _ O u t _ F i l e) ; m o d u l e m o n. o u t Input = 0100100, Output = 1000 Input = 0100111, Output = 1100 11.6 11.6.1 D i v m o d u l e D i v (Ck, Reset, TestN, Ena ); i n p u t Ck, Reset, TestN; o u t p u t E n a; r e g [0:3] C o u n t e r; al w a y s @ (p o s e d g e C k) i f (~ R e s e t)

11 129 Counter = 0; e l s e i f (~ T e s t N) Counter = 15; e l s e Counter = Counter + 1 assign E n a = (C o u n t e r = = 15)? 1: 0; m o d u l e m o d u l e D i v _ T B; i n t e g e r O u t _ F i l e; r e g Clock, Reset, TestN; w i r e E n a b l e; Out_File = $fopen ("out.vec"); #5 C l o c k = 0; #3 C l o c k = 1; Div D1 (Clock, Reset, TestN, Enable ); Reset = 0; #50 Reset = 1; TestN = 0; #100 TestN = 1; #50 TestN = 0; #50 $f c l o s e (O u t _ F i l e) ; $f i n i s h; // // $f m o n i t o r (O u t _ F i l e,"enable changed to %b at time %t", E n a b l e, $time); m o d u l e o u t. v e c Enable changed to x at time 0 Enable changed to 0 at time 8

130 Verilog HDL Enable changed to 1 at time 56 Enable changed to 0 at time 104 Enable changed to 1 at time 152 11.6.2 F S M ( f a c t o r i a l ) 11-9 11-9 R e s e t D a t a S t a rt D o n e F a c _ O u t E x p _ O u t F a t _ O u t * 2 E x p _ O u t D a t a 1 20 S t a rt D o n e ` t i m e s c a l e 1ns / 1ns m o d u l e FACTORIAL (Reset, StartSig, Clk, Data, Done, FacOut, ExpOut) ; i n p u t Reset, StartSig, Clk, i n p u t [4:0] D a t a; o u t p u t D o n e; o u t p u t [ 7 : 0 ] FacOut, ExpOut; r e g S t o p; reg [4 : 0] I n L a t c h; r e g [7:0] Exponent, Result; integer I; S t o p = 1; @ (p o s e d g e C l k) i f (( S t a r t S i g = = 1) && (Stop = = 1) && (Reset = = 1)) R e s u l t = 1; E x p o n e n t = 0; InLatch = D a t a;

11 131 Stop = 0; e l s e if (( InLatch > 1) && (Stop = = 0) begin Result = Result * InLatch ; InLatch = InLatch - 1; i f (I n L a t c h < 1) Stop = 1; // f o r (I = 1; I <= 5; I = I + 1) i f (Result > 256 ) R e s u l t = R e s u l t / 2; Exponent = Exponent+ 1; a s s i g n Done = Stop; a s s i g n FacOut = Result; a s s i g n ExpOut = Exponent; m o d u l e m o d u l e F A C _ T B; p a r a m e t e r I N _ M A X = 5, O U T _ M A X = 8; p a r a m e t e r RESET_ST = 0, START_ST = 1, A P P L _ D A T A _ S T = 2, W A I T _ R E S U L T _ S T = 3; r e g Clk, Reset, Start; w i r e D o n e; r e g [I N _ M A X-1 : 0] Fac_Out, Exp_Out; i n t e g e r N e x t _ S t a t e; p a r a m e t e r MAX_APPLY = 20; i n t e g e r N u m _ A p p l i e d; Num_Applied = 1; : C L K _ P #6 Clk = 1; #4 Clk = 0; @ (n e g e d g e C l k) // c a s e (N e x t _ S t a t e)

132 Verilog HDL R E S E T _ S T: R e s e t = 1; S t a r t = 0; Next_State = APPL_DATA_ST ; A P P L _ D A T A _ S T : Data = Num_Applied; Next_State = START_ST ; S T A R T _ S T : Start = 1; Next_State = WAIT_RESULT_ST; W A I T _ R E S U L T _ S T: Reset = 0; Start = 0; w a i t (Done = = 1); i f (N u m _ A p p l i e d = = Fac_Out * ('h0001 << E x p _ O u t) ) $d i s p l a y ("Incorrect result from factorial", "model for input value %d", Data ); Num_Applied = Num_Applied + 1; if (Num_Applied < MAX_APPLY) Next_State = APPL_DATA_ST ; e l s e $d i s p l a y ("Test completed successfully "); $f i n i s h; // d e f a u l t : Next_State = START_ST ; c a s e / / FACRORIAL F1 (Reset, Start, Clk, Data, Done, Fac_Out, Exp_Out) ; m o d u l e 11.6.3 1 11-10

11 133 m o d u l e Count3_ls (Data, Clock, Detect3_ls ); i n p u t Data, Clock; o u t p u t D e t e c t 3 _ l s ; i n t e g e r C o u n t ; r e g D e t e c t 3 _ 1 s; initial Count = 0; Detect3_ls = 0; @ (n e g e d g e C l o c k) i f ( D a t a = = 1) Count = Count + 1; e l s e Count = 0; i f (Count >= 3) D e t e c t 3 _ l s = 1; e l s e Detect3_ls = 0; m o d u l e m o d u l e To p; r e g Data, Clock; i n t e g e r O u t _ F i l e; / / Count3_ls F1 (Data, Clock, Detect ); C l o c k = 0; f o r e v e r #5 Clock = ~ Clock; D a t a = 0; #5 Data = 1; #40 D a t a = 0; #10 D a t a = 1; #40 D a t a = 0; #20 $s t o p; //

134 Verilog HDL // O u t _ F i l e = $f o p e n (" r e s u l t s. v e c t o r s "); $f m o n i t o r (O u t _ F i l e,"clock = %b, Data = %b, Detect = %b", C l o c k, Data, Detect); m o d u l e 11-10 1. 3 ns 10 ns 2. 11-11 Verilog HDL 11-11 3. C l o c k V G e n _ C l k _ D C l k _ D( 11-6 ) 15 ns [ ] 4. 10010 1 0 5. C l o c k A C l o c k B C l o c k A 10 ns C l o c k B 40 n s 1 ns 2 n s C l o c k B C l o c k A 6. 4 / 7. 4 (<, <=, >, >=) A L U 8. 32 1 12

11 135 8 9. N [ 10. 0 1 11. C o u n t _ F l a g 1 ( ) M A X _ C O U N T O v e r F l o w M A X _ C O U N T C o u n t _ F l a g 0 12. G r a y 3 R e s e t 0 4 13. T 1 0 1 0 s p e c i f y T 2 ns 3 ns