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EDA VHDL

VHDL VHDL EDA VHDL 1 7 9 10 FPGA 11 VHDL EDA 12 VHDL 13 VHDL 14 VHDL 12 VHDL 13 EDA / VHDL EDA 028 6636481 6241146 3201496 VHDL : ( 610054) : : : : 787 1092 1/16 14.875 343 : 1999 12 : 1999 12 : ISBN 7 81065 290 7/TP 172 : 1 5000 : 25.00

VLSI 1 EDA Electronic Design Automation 2 3 4 ASIC SOC System On a Chip EDA VLSI FPGA CPLD Xilinx Altera FPGA/CPLD FPGA GAL Lattice PLD/CPLD ISP CPLD 23% Cadence Data I/O Mentor Graphics OrCAD Synopsys Viewlogic EDA EDA CAD CAM CAT CAE EDA ESDA Electronic System Design Automation EDA EDA VHDL FPGA CPLD EDA VHDL IEEE EDA EDA EDA VHDL VHDL EDA ASIC IP Intelligence Property Core

EDA EDA VHDL VHDL VHDL EDA VHDL 1 VHDL 2 VHDL VHDL 3 VHDL 1 VHDL 11 14 2 12 3 PC VHDL EDA VHDL / EDA 3 1 2 VHDL VHDL / EDA E-mail span88@mail.hz.zj.cn 0571-5525171 / 5972935 65 310012 E-mail Hjwang@uestc.edu..cn 028 3203189 028 3251067-8999 610054 2001 3

1...1 1.1 EDA...1 1.2 VHDL...3 1.3...5 1.4 VHDL EDA...6 1.5...9 1.6 FPGA/CPLD...10 1.7 VHDL...10 2 VHDL...12 2.1 VHDL...12 2.2 VHDL...15 3 VHDL...19 3.1 ENTITY...19 3.2 ARCHITECTURE...26 3.3 BLOCK...29 3.4 PROCESS...32 3.5 (SUBPROGRAM)...35 3.5.1 FUNCTION...36 3.5.2 OVERLOADED FUNCTION...39 3.5.3 PROCEDURE...42 3.5.4 OVERLOADED PROCEDURE...44 3.6 LIBRARY...45 3.7 PACKAGE...48 3.8 CONFIGURATION...51... 53 4 VHDL...55 4.1 VHDL...55 4.2 VHDL...58 4.2.1 (VARIABLE)...59 4.2.2 (SIGNAL)...60 4.2.3 (CONSTANT)...63 4.3 VHDL...64 4.3.1 VHDL...65 4.3.2 IEEE...68 4.3.3...70 4.3.4...71 4.3.5...73 4.3.6...74 1

2 4.3.7...74 4.3.8...76 4.3.9...78 4.4 VHDL...82 4.4.1...82 4.4.2...83 4.4.3...85 4.4.4...87 4.4.5...93...94 5 VHDL...95 5.1...95 5.1.1...96 5.1.2...97 5.2...99 5.2.1 IF...99 5.2.2 CASE...102 5.2.3 LOOP...106 5.2.4 NEXT...109 5.2.5 EXIT...110 5.3 WAIT...111 5.4...115 5.5 (RETURN)...118 5.6 (NULL)...119 5.7...120 5.7.1 (ATTRIBUTE)...120 5.7.2 (TEXTIO)...125 5.7.3 ASSERT...127 5.7.4 REPORT...128 5.7.5...128...129 6 VHDL...131 6.1...132 6.2...137 6.3...138 6.3.1...138 6.3.2...138 6.3.3...139 6.4...141

6.5...143 6.6...145 6.7...146...151 7 VHDL...153 7.1...153 7.2...155 7.3...156...157 8...158 8.1 VHDL...158 8.2...162 8.2.1...163 8.2.2...163 8.3 δ...164 8.4...164 8.5 VHDL...166 8.6 VHDL...169...170 9...171 9.1 VHDL...171 9.2...174 9.3...175 9.3.1...175 9.3.2...180 9.3.3...183 9.3.4...184 9.3.5...184 9.4...186 9.5...190 9.6...194...196 10 FSM...198 10.1...199 10.2...210 10.3...212...213 11...215 11.1 FPGA...215 3

4 11.2 FIR...217 11.2.1 FIR...217 11.2.2 FIR...220 11.2.3 FIR...223 11.2.4 FIR...227 11.3 IIR...229 11.3.1 IIR...229 11.3.2 IIR...232...234 12 VHDL...235 12.1 ispvhdl...235 12.1.1 isplsi...236 12.1.2 ispvhdl...236 12.1.3 ispvhdl...237 12.2 Altera MAX+plus II VHDL...246 12.3 MAX+plus II Synplify...254 12.4 Xilinx Foundation VHDL...256 12.4.1 Foundation...256 12.4.2 VHDL...257...264 13 VHDL...265 13.1 8...265...267 13.2...267...268 13.3 SRAM...269...270 13.4...270...271 13.5 8...271...273 13.6 8...273...278 13.7...278...283 13.8...283...284 13.9...284...286

13.10...287...292 13.11 RS232...292...295 13.12...296...299 13.13 PC FPGA...299...301 13.14 VGA...301...304 13.15 A/D...304...308 13.16 D/A...308...310 13.17 MCS-51 CPLD...310 13 17 1...310 13 17 2...312...313 13.18 PS/2...314 13.19 7 LED...315...316 14...317 14.1...317 14.1.1...317 14.1.2...318 14.1.3 VHDL...320 14.1.4...323 14.1.5...324 14.2...325...326 1 GW48 EDA...327 2 FPGA CPLD...344 5

1 1 1 SSI MCU SSI MCU SSI FPGA/CPLD / EDA MCU MCU FPGA/CPLD MCU EDA FPGA/CPLD MCU MPU DSP A/D D/A RAM ROM / IP CPLD FPGA EDA 1.1 EDA 8255

2 VHDL PLD EDA TTL EDA EDA Electronic Design Automation 90 CAD CAM CAT CAE EDA EDA HDL EDA EDA EDA CPLD/FPGA EDA CPLD/FPGA EDA EDA PCB VHDL Verilog HDL ABEL-HDL EDA CPLD FPGA EDA EDA SOC

1 VHDL 3 1.2 VHDL VHDL Very-High-Speed Integrated Circuit Hardware Description Language 1982 1987 VHDL IEEE The Institute of Electrical and Electronics Engineers IEEE-1076 IEEE VHDL EDA VHDL VHDL VHDL 1993 IEEE VHDL VHDL VHDL IEEE 1076-1993 VHDL Verilog IEEE EDA VHDL Verilog 1 VHDL VHDL VHDL VHDL ( ) VHDL VHDL h VHDL EDA VHDL VHDL FPGA CPLD h VHDL VHDL h VHDL VHDL

4 VHDL h VHDL EDA VHDL EDA VHDL h VHDL VHDL VHDL CPLD FPGA h VHDL 2 VHDL Verilog ABEL RTL VHDL RTL Verilog RTL RTL VHDL RTL Verilog RTL Verilog VHDL FPGA/CPLD ASIC VHDL Verilog ASIC VHDL Verilog VHDL Verilog Verilog VHDL Verilog VHDL VHDL Verilog VHDL VHDL VHDL Verilog Verilog VHDL Verilog EDA VHDL Verilog VHDL Verilog

1 EDA ABEL Verilog ABEL HDL ABEL Verilog Verilog EDA ABEL PLD ABEL-HDL HDL ABEL-HDL DOS ABEL3.0 GAL Lattice ispexpert DATAIO Synario Vantis Design-Direct Xilinx FOUNDATION WEBPACK EDA ABEL-HDL FPGA/CPLD ABEL-HDL ABEL-HDL VHDL Verilog-HDL VHDL Verilog-HDL ABEL-HDL DOS Windows PLD EDA ABEL-HDL ABEL-HDL EDA DATAIO Internet ABEL 5 1.3 EDA TOP-TO-DOWN VHDL VHDL VHDL VHDL MCU RAM ROM FPGA ASIC EDA VHDL 1

6 VHDL 2 IP 3 4 EDA IP Core VHDL IP VHDL 1.4 VHDL EDA VHDL 12 13 VHDL EDA 1-1 VHDL VHDL 1-1 VHDL VHDL EDA VHDL EDA IC FPGA CPLD 1-1 FPGA CPLD VHDL VHDL EDA VHDL EDA VHDL EDA / EDA

1 PROTEL 7 1-1 VHDL 1 2 3 VHDL EDA VHDL StateCAD Renoir Active-FSM VHDL VHDL VHDL DEA VHDL VHDL VHDL VHDL VHDL VHDL

8 VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL EDIF/XNF VHDL VHDL VHDL VHDL 1-1 VHDL Netlist EDIF Xilinx XNF Xilinx FPGA/CPLD XNF VHDL VHDL VHDL VHDL EDIF/XNF FPGA CPLD VHDL VHDL VHDL / FPGA/CPLD / / FPGA CPLD 1-1 Hardware Debug VHDL VHDL VHDL VHDL VHDL VHDL

1 VHDL VHDL ASIC ASIC FPGA VHDL ASIC FPGA CPLD VHDL VHDL VHDL EDA CAD PROTEL PSPICE EWB POWERPCB EDA EDA EDA PROTEL PSPICE EWB POWERPCB HDL EDA FPGA/CPLD ASIC JEDEC FPGA/CPLD EDA Lattice PAC-DESIGNER EDA EDA FPGA/CPLD 9 1.5 EEPROM PLCC TQFP PQFP BGA Lattice ISP In-System Programmability PLD

10 VHDL ISP 4 5 PLD ISP PC ISP ISP CPLD/FPGA ISP ISP EDA 1.6 FPGA/CPLD FPGA/CPLD MCU PC CPLD/FPGA FPGA/CPLD EDA FPGA/CPLD TI ASIC 80% IP CPLD/FPGA IP ASIC FPGA/CPLD VHDL ASIC 11 VHDL FPGA/CPLD 1.7 VHDL C VHDL VHDL VHDL

1 CPU CPU CPU CPU VHDL VHDL VHDL VHDL VHDL ADA ADA VHDL VHDL VHDL VHDL VHDL RTL VHDL CPU VHDL VHDL VHDL 0 0 1000 10 11

12 VHDL 2 VHDL VHDL 2.1 VHDL 1 2 1 2-1 2 1 a b s y y b s 0 y a s 1 VHDL 2-1 LIBRARY IEEE; IEEE USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux21 IS mux21 PORT ( a b : IN STD_LOGIC; PORT s : IN STD_LOGIC; y : OUT STD_LOGIC ); END ENTITY mux21; mux21 ARCHITECTURE one OF mux21 IS y <= a WHEN s = '0' ELSE b WHEN s = '1' ; END ARCHITECTURE one; 2 1 VHDL VHDL EDIF ALTERA EPM7128S 2-1 EPM7128S 2-1 2 1 mux21

2 VHDL 13 HARDWARE DEBUG EDA MUX+PLUSII( 12 ) VHDL mux21 4 a b s y MUX+PLUSII 2-1 FPGA CPLD 2-1 2 1 mux21 2 1 VHDL VHDL (1) (LIBRARY) IEEE STD_LOGIC_1164 VHDL VHDL (2) (ENTITY) mux21 mux21 a b s y PORT mux21 PORT IN a b a b OUT y a b s y IEEE STD_LOGIC_1164 STD_LOGIC (3) (ARCHITECTURE) mux21 <= y <= a a ( )y 2-1 END ENTITY mux21 END ARCHITECTURE one VHDL IEEE STD 1076_1993 VHDL 87 IEEE STD 1076_1987 END mux21 END one EDA VHDL VHDL'87 VHDL VHDL 87 VHDL VHDL IEEE

14 VHDL 2-1 VHDL VHDL 2.2 2.3 VHDL 2-1 VHDL VHDL VHDL VHDL 2-1 3 HDL 2 1 VHDL 2-2 D ENA ENA Q 2-2 VHDL 2-2 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Latch IS PORT D : IN STD_LOGIC; ENA : IN STD_LOGIC; Q : OUT STD_LOGIC ); 1 END ENTITY Latch ARCHITECTURE one OF Latch IS SIGNAL sig_save : STD_LOGIC; PROCESS (D, ENA) IF ENA = '1' THEN sig_save <= D ; END IF ; Q <= sig_save ; END PROCESS ; END ARCHITECTURE one; 2-1 1 (1) SIGNAL 2-2 1 SIGNAL sig_save

2 VHDL 15 D (2) PROCESS (D, ENA) END PROCESS D ENA (VHDL ) ENA D sig_save sig_save Q ENA sig_save Q IF_THEN VHDL IF sig_save <= D END IF IF_THEN PROCESS VHDL VHDL PROCESS(D ENA) (D ENA) D ENA ( ) ( ) VHDL 2-1 2-2 VHDL VHDL 2-1 2-2 ABEL COM REG 2.2 VHDL 1 1 2-3 1 a b 2-3 so 1 co h_adder 2-4 2-4 f_adder 3 u1 u2 u3 2-3 VHDL 2-4 VHDL EDA

16 VHDL 2-3 -- LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2 IS PORT (a,b :IN STD_LOGIC; c : OUT STD_LOGIC ); END ENTITY or2 ARCHITECTURE fu1 OF or2 IS c <= a OR b ; END ARCHITECTURE fu1; -- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder IS PORT (a b : IN STD_LOGIC; co, so : OUT STD_LOGIC); END ENTITY h_adder ARCHITECTURE fh1 OF h_adder IS so <= (a OR b)and(a NAND b); co <= NOT( a NAND b); END ARCHITECTURE fh1; --1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_adder IS PORT ( ain bin cin : IN STD_LOGIC; cout sum : OUT STD_LOGIC ); END ENTITY f_adder; ARCHITECTURE fd1 OF f_adder IS COMPONENT h_adder PORT ( a b : IN STD_LOGIC; co so : OUT STD_LOGIC); END COMPONENT COMPONENT or2 PORT (a b : IN STD_LOGIC; c : OUT STD_LOGIC); END COMPONENT SIGNAL d e f : STD_LOGIC; u1 : h_adder PORT MAP( a =>ain b =>bin co=>d so =>e); u2 : h_adder PORT MAP( a =>e b =>cin co =>f so =>sum); u3 : or2 PORT MAP(a =>d b =>f c =>cout); END ARCHITECTURE fd1 ;, 2-3 EDA 2-3 3 VHDL 2 f_adder VHDL or2.vhd h_adder.vhd f_adder.vhd 2-3 (1) -- VHDL -- (2) or2 or2 a b ( ) c ( )

2 VHDL 17 a b c (3) h_adder fh1 2-3 ( 2-1) VHDL NAND NOT OR AND (4) VHDL 2-4 1 f_adder ain bin cin cout sum 1 fd1 COMPONENT COMPONENT or2 h_adder 2-4 2-2 2-4 1 2-1 H_ADDER a B so co 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 2-2 F_ADDER ain Bin cin Cout sum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 (5) fd1 COMPONENT END COMPONENT (Component Declaration) SIGNAL

18 VHDL d e f PORT MAP( ) (Component Instantiation) MAP u2 h_adder a b co so e cin f sum => (6) 2-3 f_adder IEEE IEEE.STD_LOGIC_1164.ALL VHDL VHDL VHDL 2-5 WORK VHDL 3 2-5 VHDL ENTITY ARCHITECTURE CONFIGURATION 2-5 VHDL

3 VHDL 19 3 VHDL VHDL VHDL VHDL VHDL 2-5 VHDL VHDL ENTITY ARCHITECTURE VHDL VHDL VHDL LIBRARY PACKAGE VHDL 2-5 CONFIGURATION VHDL 3.1 ENTITY

20 VHDL VHDL 1. ENTITY IS [GENERIC ( ) ] [PORT ( ) ] END ENTITY ENTITY IS END ENTITY VHDL VHDL VHDL END ENTITY nand nand 2. 2-3 1 3-1... COMPONENT h_adder -- PORT ( a b : IN STD_LOGIC ; co so : OUT STD_LOGIC ); END COMPONENT;... u1 : h_adder PORT MAP ( a =>ain b =>bin co=>d so =>e)... -- => h_adder 2-3 EDA VHDL MAX+PLUSII h_adder.vhd VHDL

3. GENERIC 3 VHDL 21 GENERIC GENERIC([ [ : ] { [ : ] } ) GENERIC PORT GENERIC INTEGER TIME VHDL 3-2 3-3 3-2 ENTITY mcu1 IS GENERIC (addrwidth : INTEGER := 16); PORT( add_bus : OUT STD_LOGIC_VECTOR(addrwidth-1 DOWNTO 0) );... GENERIC mcu1 add_bus add_bus 16 addrwidth INTEGER addrwidth 1 15 PORT (add_bus : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)); 3-2 addrwidth 3-3 2

22 VHDL ENTITY PGAND2 IS GENERIC ( trise : TIME := 1 ns; tfall : TIME := 1 ns ) ; PORT ( a1 : IN STD_LOGIC ; a0 : IN STD_LOGIC ; z0 : OUT STD_LOGIC ); END ENTITY PGAND2; 2 trise tfall 1ns 3-5 3-4 3-4 n 3-2 n 3-5 GENERIC MAP ( ) 3-4 3-5 3-4 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY andn IS GENERIC ( n : INTEGER ); PORT(a : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); c : OUT STD_LOGIC); END; ARCHITECTURE behav OF andn IS PROCESS (a) VARIABLE int : STD_LOGIC; int := '1'; FOR i IN a'length - 1 DOWNTO 0 LOOP IF a(i)='0' THEN int := '0'; END IF; END LOOP; c <=int ; END PROCESS; END; 3-5 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY exn IS PORT(d1,d2,d3,d4,d5,d6,d7 : IN STD_LOGIC; q1,q2 : OUT STD_LOGIC); END; ARCHITECTURE exn_behav OF exn IS COMPONENT andn GENERIC ( n : INTEGER); PORT(a: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); c: OUT STD_LOGIC); END COMPONENT ; u1: andn GENERIC MAP (n =>2) PORT MAP (a(0)=>d1,a(1)=>d2,c=>q1);

3 VHDL u2: andn GENERIC MAP (n =>5) PORT MAP (a(0)=>d3,a(1)=>d4,a(2)=>d5, a(3)=>d6,a(4)=>d7, c=>q2); END; 23 4. PORT PORT MODE TYPE LIBRARY USE PORT ( : { : } ) ; VHDL nand2 a c b 3-6 2 3-1 nand 3-1 3-6 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY nand2 IS PORT(a : IN STD_LOGIC ; b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END nand2 ;... 3-1 nand2 a b c IEEE 1076

24 VHDL hin IN Variable Signal hout OUT hinout INOUT INOUT IN OUT BUFFER 3-7 MCS51 P0 INOUT P0 hbuffer BUFFER 3-7... ENTITY MCS51 IS PORT ( -- 8031 : P0 : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- / P2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- 8 RD WR : IN STD_LOGIC; --... END MCS51;... PROCESS( WR_ENABLE2 ) IF WR_ENABLE2'EVENT AND WR_ENABLE2 = '1' THEN LATCH_OUT2 <= P0; END IF; -- P0 END PROCESS; PROCESS( P2,LATCH_ADDRES,READY,RD ) IF (LATCH_ADDRES="01111110") AND (P2="10011111") AND (READY='1') AND (RD='0') THEN P0 <= LATCH_IN1 ; -- P0, P0 ELSE P0 <= "ZZZZZZZZ" ; END IF -- P0 END PROCESS;... BUFFER OUT, INOUT BUFFER BUFFER 3-8 SIGNAL 3-9

3 VHDL 3-2 3-8 3-9 3-2 BUFFER 3-8 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY bfexp IS PORT( clk,rst,din : IN STD_LOGIC ; q1 : BUFFER STD_LOGIC ; q2 : OUT STD_LOGIC ) ; END bfexp ; ARCHITECTURE behav1 OF bfexp IS PROCESS(clk,rst) IF rst ='0' THEN q1 <= '0' ; q2 <= '0' ; ELSIF clk'event AND clk = '1' THEN q1 <= din ; -- din q1 q2 <= q1 ; -- q1, q2 END IF; END PROCESS; END; 3-9 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY bfexp IS PORT(clk,rst,din : IN STD_LOGIC ; q1 : OUT STD_LOGIC ; q2 : OUT STD_LOGIC ) ; END bfexp ; ARCHITECTURE behav1 OF bfexp IS SIGNAL qbuf : STD_LOGIC; -- qbuf PROCESS(clk,rst) IF rst ='0' THEN qbuf <= '0' ; q2 <= '0' ; ELSIF clk'event AND clk = '1' THEN qbuf <= din ; -- din qbuf q2 <= qbuf ; -- qbuf q2 END IF; q1 <= qbuf; -- qbuf q1, END PROCESS; END; IN OUT BUFFER TRI INOUT 25

26 VHDL BIDIR OUT 3-1 3-1 IN OUT BUFFER INOUT BIT BIT_VECTOR BIT 1 0 1 3-3 a0 a1 z0 STD_LOGIC IEEE STD_LOGIC_1164 BIT BIT_VECTOR 3-2 add_bus 16 3-2 3-8 3-9 add_bus STD_LOGIC_VECTOR IEEE STD_LOGIC_1164 3.2 ARCHITECTURE 2-5 / h h h 2-3 CONFIGURATION

3 VHDL 27 1. ARCHITECTURE OF IS [ ] [ ] END ARCHITECTURE ; ARCHITECTURE END ARCHITECTURE 2-2 Latch one sig_save STD_LOGIC 3-3 3-3 3-3 2. (SIGNAL) (TYPE) (CONSTANT) (COMPONENT) (FUNCTION) (PROCEDURE) 3. 3-3 3-3 h h h

28 VHDL h h ARCHITECTURE BLOCK PROCESS 3-3 3-10 3-3 PGAND2 behav a0 a1 z0

3 VHDL 3-10 ARCHITECTURE behav OF PGAND2 IS PROCESS (a1 a0) VARIABLE zdf : STD_LOGIC ; zdf := a1 AND a0 ; -- IF zdf ='1' THEN z0 <= TRANSPORT zdf AFTER trise ; ELSIF zdf ='0' THEN z0 <= TRANSPORT zdf AFTER tfall ; ELSE z0 <= TRANSPORT zdf ; END IF ; END PROCESS ; END ARCHITECTURE behav ; 29 VHDL AFTER tfall 3.3 BLOCK BLOCK PROTEL98 BLOCK BLOCK BLOCK VHDL BLOCK BLOCK BLOCK 1. BLOCK BLOCK BLOCK [ ]

30 VHDL END BLOCK BLOCK BLOCK END BLOCK PORT GENERIC PORT MAP GENERIC MAP BLOCK BLOCK BLOCK h USE h h h h h h BLOCK BLOCK 2. BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK 3-11 BLOCK 3-12 BLOCK VHDL 3-11... ENTITY gat IS GENERIC(l_time : TIME ; s_time : TIME ) ; -- PORT (b1, b2, b3 : INOUT BIT) ; -- END ENTITY gat ; ARCHITECTURE func OF gat IS SIGNAL a1 : BIT ; -- a1 Blk1 : BLOCK -- blk1 GENERIC (gb1, gb2 : Time) ; -- GENERIC MAP (gb1 => l_time,gb2 => s_time) ; --

3 VHDL 31 PORT (pb : IN BIT; pb2 : INOUT BIT ); -- PORT MAP (pb1 => b1, pb2 => a1 ) ; -- CONSTANT delay : Time := 1 ms ; -- SIGNAL s1 : BIT ; -- s1 <= pb1 AFTER delay ; pb2 <= s1 AFTER gb1, b1 AFTER gb2 ; END BLOCK blk1 ; END ARCHITECTURE func ; 3-11 BLOCK 3-12... b1 : BLOCK SIGNAL s1: BIT ; S1 <= a AND b ; b2 : BLOCK SIGNAL s2: BIT ; s2 <= c AND d ; b3 : BLOCK Z <= s2 ; END BLOCK b3 ; END BLOCK b2 ; y <= s1 ; END BLOCK b1 ; 3-12 3. BLOCK VHDL BLOCK 3-13 3-14 3-13 a1 : out1 <= '1' after 3 ns ; blk1 : BLOCK A2 : out2 <= '1' AFTER 3 ns ; A3 : out3 <= '0' AFTER 2 ns ; END BLOCK blk1 ; 3-14 a1 : out1 <= '1' AFTER 3 ns ; a2 : out2 <= '1' AFTER 3 ns ; a3 : out3 <= '0' AFTER 2 ns ;

32 VHDL VHDL BLOCK GUARDED BLOCK BLOCK BLOCK VHDL COMPONENT INSTANTIATION 3.4 PROCESS PROCESS VHDL PROCESS PROCESS PROCESS C PASCAL VHDL PROCESS PROCESS PROCESS 1. PROCESS PROCESS [ ] PROCESS [ ( ) ] [IS] [ ] END PROCESS [ ] PROCESS PROCESS PROCESS BLOCK

3 VHDL WAIT Suspention PROCESS PROCESS PROCESS PROCESS END PROCESS [ ] [IS] 2. PROCESS PROCESS (1) (2) h SIGNAL h VARIABLE h PROCESS WAIT WAIT WAIT h h IF CASE LOOP NULL h NEXT EXIT (3) WAIT 3-15 p1 WAIT clock clock WAIT driver CASE 3-15 ARCHITECURE s_mode OF stat IS p1 PROCESS WAIT UNTIL clock ; IF (driver = '1' ) THEN CASE output IS WHEN s1 => output <= s2 ; -- clock 33

34 VHDL WHEN s2 => output <= s3 ; WHEN s3 => output <= s4 ; WHEN s4 => output <= s1 ; END CASE END IF END PROCESS p1 END ARCHITECURE s_mode ; 3-16 4 IF clk clear stop cnt4 clk clear stop 3-16 SIGNAL cnt4 : INTEGER RANGE 0 TO 15 ; -- cnt4... PROCESS (clk, clear, stop) IF clear = '0' THEN cnt4 <= 0 ; ELSIF clk'event AND clk = '1' THEN -- IF stop = '0' THEN -- stop END IF ; END IF ; END PROCESS ; 3. cnt4 <= cnt4 + 1 ; -- VHDL VHLD 1 CPU 2 VHDL 3 (1) END PROCESS PROCESS (2) PROCESS CPU

3 VHDL CPU PROCESS PROCESS END PROCESS PROCESS VHDL δ 0 PROCESS 10 1000 (3) (4) WAIT WAIT WAIT (5) VHDL 93 (6) VHDL BLOCK (7) VHDL VHDL 9 10 35

36 VHDL 3.5 (SUBPROGRAM) VHDL VHDL VHDL 3 VHDL PROCEDURE FUNCTION 5 6 PC VHDL VHDL 3.5.1 FUNCTION VHDL FUNCTION RETURN --

3 VHDL FUNCTION RETURN IS [ ] END FUNCTION -- 37 1. FUNCTION VHDL CONSTANT SIGNAL 3-17 PACKAGE packexp IS -- FUNCTION max( a,b IN STD_LOGIC_VECTOR) -- RETURN STD_LOGIC_VECTOR FUNCTION func1 ( a,b,c : REAL ) -- RETURN REAL FUNCTION "*" ( a,b : INTEGER ) -- RETURN INTEGER FUNCTION as2 (SIGNAL in1,in2 : REAL ) -- RETURN REAL END PACKAGE BODY packexp IS FUNCTION max( a,b IN STD_LOGIC_VECTOR) -- RETURN STD_LOGIC_VECTOR IS IF a > b THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION max; -- FUNCTION END; -- PACKAGE BODY --

38 VHDL... USE WORK. packexp.all ENTITY axamp IS PORT(...); END; ARCHITECTURE bhv OF axamp IS... out1 <= max(dat1,dat2); -- PROCESS(dat3,dat4) out2 <= max(dat3,dat4); -- END PROCESS;... END; 3-17 4 packexp 1 a b a b 2 a b c 3 "*" "+" SIGNAL in1 in2 REAL 2 END FUNCTION 3-17 max 3-18 PROCESS a a 3 a(0) a(1) a(2) sam m 3-18 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY func IS PORT a : IN STD_LOGIC_VECTOR (0 to 2 ) ; m : OUT STD_LOGIC_VECTOR (0 to 2 ) ;

3 VHDL END ENTITY func ARCHITECTURE demo OF func IS FUNCTION sam(x,y,z : STD_LOGIC) RETURN STD_LOGIC IS RETURN ( x AND y ) OR y ; END FUNCTION sam PROCESS ( a ) m(0) <= sam( a(0), a(1), a(2) ) ; m(1) <= sam( a(2), a(0), a(1) ) ; m(2) <= sam( a(1), a(2), a(0) ) ; END PROCESS ; END ARCHITECTURE demo ; 39 3-19 MAX+PLUSII IF CASE RETURN 3-19 MAX+PLUSII 3-19 FUNCTION trans ( value : IN BIT_VECTOR (0 TO 1) ) ; RETURN BIT_VECTOR IS CASE value IS WHEN "0000" => RETURN "1100" ; WHEN "0101" => RETURN "0001" ; WHEN OTHERS => RETURN "1111" ; END CASE ; END FUNCTION trans ; IN ( 5 ) 3.5.2 OVERLOADED FUNCTION VHDL 3-20 max 3-20 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; PACKAGE packexp IS -- FUNCTION max( a,b IN STD_LOGIC_VECTOR) -- RETURN STD_LOGIC_VECTOR FUNCTION max( a,b IN BIT_VECTOR) --

40 VHDL RETURN BIT_VECTOR FUNCTION max( a,b IN INTEGER ) RETURN INTEGER END -- PACKAGE BODY packexp IS FUNCTION max( a,b IN STD_LOGIC_VECTOR) -- RETURN STD_LOGIC_VECTOR IS IF a > b THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION max; -- FUNCTION FUNCTION max( a,b IN INTEGER) -- RETURN INTEGER IS IF a > b THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION max; -- FUNCTION FUNCTION max( a,b IN BIT_VECTOR) -- RETURN BIT_VECTOR IS IF a > b THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION max; -- FUNCTION END; -- PACKAGE BODY -- max LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE WORK.packexp.ALL ENTITY axamp IS PORT(a1,b1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); a2,b2 : IN BIT_VECTOR(4 DOWNTO 0); a3,b3 : IN INTEGER 0 TO 15; c1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); c2 : OUT BIT_VECTOR(4 DOWNTO 0); c3 : OUT INTEGER 0 TO 15); END; ARCHITECTURE bhv OF axamp IS c1 <= max(a1,b1); -- max( a,b IN STD_LOGIC_VECTOR) c2 <= max(a2,b2); -- max( a,b IN BIT_VECTOR) c3 <= max(a3,b3); -- max( a,b IN INTEGER) END;

3 VHDL VHDL 3-21 + VHDL IEEE STD_LOGIC_UNSIGNED "+" "-" "*" "=" ">=" "<=" ">" "<" "/=" "AND" "MOD" INTEGRE STD_LOGIC STD_LOGIC_VECTOR 3-21 Synopsys STD_LOGIC_UNSIGNED STD_LOGIC_UNSIGNED UNSIGNED IEEE.STD_LOGIC_ARITH MAXIUM 3-21 LIBRARY IEEE ; -- USE IEEE.std_logic_1164.all ; USE IEEE.std_logic_arith.all ; PACKAGE STD_LOGIC_UNSIGNED is function "+" (L : STD_LOGIC_VECTOR ; R : INTEGER) return STD_LOGIC_VECTOR ; function "+" (L : INTEGER; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR ; function "+" (L : STD_LOGIC_VECTOR ; R : STD_LOGIC ) return STD_LOGIC_VECTOR ; function SHR (ARG : STD_LOGIC_VECTOR ; COUNT : STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR ;... end STD_LOGIC_UNSIGNED ; LIBRARY IEEE ; -- use IEEE.std_logic_1164.all ; use IEEE.std_logic_arith.all ; package body STD_LOGIC_UNSIGNED is function maximum (L, R : INTEGER) return INTEGER is begin if L > R then return L; else return R; end if; end; function "+" (L : STD_LOGIC_VECTOR ; R : INTEGER) return STD_LOGIC_VECTOR is Variable result : STD_LOGIC_VECTOR (L range) ; Begin result := UNSIGNED(L) + R ; 41

42 VHDL return std_logic_vector(result) ; end ;... end STD_LOGIC_UNSIGNED + USE STD_LOGIC_UNSIGNED STD_LOGIC_VECTOR STD_LOGIC 4 VHDL 3-22 3-16 3-22 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; -- ENTITY cnt4 IS PORT Clk : IN STD_LOGIC ; q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ); END cnt4; ARCHITECTURE one OF cnt4 IS PROCESS ( clk ) IF clk'event AND clk = '1' THEN IF q=15 THEN -- = q <= "0000" ; ELSE q <= q + 1 ; -- + END IF ; END IF ; END PROCESS ; END one ; q = 15 q 15 q<=q + 1 + 1 USE IEEE.STD_LOGIC_UNSIGNED.ALL

3 VHDL 43 3.5.3 PROCEDURE VHDL PROCEDURE PROCEDURE PROCEDURE IS [ ] BIGIN END PROCEDURE -- -- 1. IN OUT INOUT IN 3-23 PROCEDURE pro1 (VARIABLE a, b : INOUT REAL) ; PROCEDURE pro2 CONSTANT a1 : IN INTEGER VARIABLE b1 : OUT INTEGER ) ; PROCEDURE pro3 (SIGNAL sig : INOUT BIT) ; pro1 a b pro2 IN OUT pro3 sig INOUT BIT IN OUT INOUT IN INOUT OUT 2. WAIT WAIT

44 VHDL IN INOUT Wait 3-24 PROCEDURE prg1(variable value:inout BIT_VECTOR(0 TO 7)) IS CASE value IS WHEN "0000" => value: "0101" ; WHEN "0101" => value: "0000" ; WHEN OTHERS => value: "1111" ; END CASE ; END PROCEDURE prg1 ; value 3-25 PROCEDURE comp ( a, r : IN REAL; m : IN INTEGER ; v1, v2: OUT REAL) IS VARIABLE cnt : INTEGER ; v1 := 1.6 * a ; v2 := 1.0 ; Q1 : FOR cnt IN 1 TO m LOOP v2 := v2 * v1 ; EXIT Q1 WHEN v2 > v1; END LOOP Q1 ASSERT (v2 < v1 ) REPORT "OUT OF RANGE" SEVERITY ERROR ; END PROCEDURE comp ; -- -- -- v2 > v1 LOOP -- comp a r m v2 v1 comp LOOP v2 v2 r EXIT REPORT 3.5.4 OVERLOADED PROCEDURE

3 VHDL 3-26 PROCEDURE calcu ( v1, v2 : IN REAL ; SIGNAL out1 : INOUT INTEGER) ; PROCEDURE calcu ( v1, v2 : IN INTEGER ; SIGNAL out1 : INOUT REAL) ;... calcu (20.15, 1.42, signl) ; -- calcu calcu (23 320 sign2 ) -- calcu... 45 v1 v2 out1 INOUT v1 v2 out1 OUT INOUT 3-26 3.6 LIBRARY VHDL VHDL VHDL VHDL USE USE VHDL IEEE IEEE IEEE IEEE 1076 Synopsys STD_LOGIC_UNSIGNED VHDL

46 VHDL WORK IEEE LIBRARY USE LIBRARY LIBRARY LIBRARY IEEE ; IEEE 1. VHDL h IEEE IEEE VHDL IEEE IEEE STD_LOGIC_1164 NUMERIC_BIT NUMERIC_STD STD_LOGIC_1164 IEEE IEEE Synopsys STD_LOGIC_ARITH STD_LOGIC_SIGNED STD_LOGIC_UNSIGNED EDA Synopsys IEEE STD_LOGIC_1164 STD_LOGIC_ARITH STD_LOGIC_SIGNED STD_LOGIC_UNSIGNED IEEE IEEE VHDL STD_LOGIC_1164 VHDL h STD VHDL STANDARD TEXTIO / STD VHDL VHDL STD VHDL IEEE LIBRARY STD USE STD.STANDARD.ALL ; h WORK WORK VHDL WORK VHDL VHDL WORK PC VHDL

3 VHDL VHDL WORK VHDL VHDL h VITAL VITAL VHDL VHDL VITAL_TIMING VITAL_PRIMITIVES VITAL IEEE VHDL VITAL IEEE FPGA/CPLD ispexpert Compiler 12 VHDL VHDL FPGA/CPLD VITAL EDA FPGA/CPLD DATAIO GENERICS DATAIO Synopsys VHDL EDA WORK Synplicity Synplify ( 12 ) EDA 2 VHDL VHDL 3-22 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; IEEE STD_LOGIC_1164 STD_LOGIC_UNSIGNED VHDL USE LIBRARY USE 47

48 VHDL VHDL USE USE USE USE. USE..ALL USE USE USE USE IEEE.STD_LOGIC_1164.ALL ; IEEE STD_LOGIC_1164 VHDL ALL 3-27 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.STD_ULOGIC ; USE IEEE.STD_LOGIC_1164.RISING_EDGE ; STD_LOGIC_1164 RISING_EDGE STD_ULOGIC USE 3.7 PACKAGE VHDL VHDL VHDL h h VHDL 4

3 VHDL h VHDL h STD_LOGIC_1164 STD_LOGIC STD_LOGIC_VECTOR PACKAGE IS -- END PACKAGE BODY IS -- END 3-21 STD_LOGIC_UNSIGNED 1. VHDL 3-28 PACKAGE pacl IS -- TYPE byte IS RANGE 0 TO 255 ; -- byte SUBTYPE nibble IS byte RANGE 0 TO 15 ; -- nibble CONSTANT byte_ff : byte := 255 ; -- byte_ff SIGNAL addend : nibble ; -- addend COMPONENT byte_adder -- PORT( a, b : IN byte ; c : OUT byte ; overflow : OUT BOOLEAN ) ; END COMPONENT ; FUNCTION my_function (a : IN byte) Return byte ; -- END pacl ; -- pacl byte nibble byte byte_ff nibble addend 49

50 VHDL USE LIBRARY WORK USE WORK.pacl.ALL ; ENTITY... ARCHITHCYURE...... WORK LIBRARY WORK USE 3-29 WORK 3-29 PACKAGE seven IS SUBTYPE segments is BIT_VECTOR(0 TO 6) ; TYPE bcd IS RANGE 0 TO 9 ; END seven ; USE WORK.seven.ALL ; ENTITY decoder IS PORT (input: bcd; drive : out segments) ; END decoder ; ARCHITECTURE simple OF decoder IS WITH input SELECT drive <= B"1111110" WHEN 0, B"0110000" WHEN 1, B"1101101" WHEN 2, B"1111001" WHEN 3, B"0110011" WHEN 4, B"1011011" WHEN 5, B"1011111" WHEN 6, B"1110000" WHEN 7, B"1111111" WHEN 8, B"1111011" WHEN 9, B"0000000" WHEN OTHERS ; END simple ; 4 BCD 7 VHDL seven segments bcd 7 decoder WORK USE 2. USE 3-28

3 VHDL h STD_LOGIC_1164 STD_LOGIC_1164 IEEE IEEE VHDL 0 1 Z X STD_LOGIC_1164 STD_LOGIC STD_LOGIC_VECTOR FPGA/CPLD h STD_LOGIC_ARITH STD_LOGIC_ARITH IEEE Synopsys STD_LOGIC_1164 UNSIGNED SIGNED SMALL_INT h STD_LOGIC_UNSIGNED STD_LOGIC_SIGNED STD_LOGIC_UNSIGNED STD_LOGIC_SIGNED Synopsys IEEE INTEGER STD_LOGIC STD_LOGIC_VECTOR STD_LOGIC_VECTOR INTEGER STD_LOGIC_SIGNED STD_LOGIC_ARITH STD_LOGIC_UNSIGNED STD_LOGIC_SIGNED IEEE VHDL VHDL h STANDARD TEXTIO STANDARD TEXTIO STD STANDARD STANDARD VHDL USE TEXTIO USE STD.TEXTIO.ALL TEXTIO TEXTIO VHDL 51 3.8 CONFIGURATION

52 VHDL VHDL VHDL VHDL VHDL VHDL CONFIGURATION OF IS END 3-30 nand 3-30 LIBRARY IEEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY nand IS PORT (a : IN STD_LOGIC ; b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END ENTITY nand ; ARCHITECTURE one OF nand IS c <= NOT (a AND b) ; END ARCHITECTURE one ; ARCHITECTURE two OF nand IS c <= 1 WHEN (a = 0 )AND(b = 0 ) ELSE 1 WHEN (a = 0 )AND(b = 1 ) ELSE 1 WHEN (a = 1 )AND(b = 0 ) ELSE 0 WHEN (a = 1 )AND(b = 1 ) ELSE 0 ; END ARCHITECTURE two CONFIGURATION second OF nand IS FOR two END FOR END second ;

3 VHDL CONFIGURATION first OF nand IS FOR one END FOR END first ; 53 3-30 second nand two first nand one 3-30 nand nand 3-31 3-30 nand RS nand two nand 3-31 LIBRARY LEEE; USE LEEEE.STD_LOGIC_1164.ALL ; ENTITY rs1 IS PORT ( r : IN STD_LOGIC ; s : IN STD_LOGIC ; q : OUT STD_LOGIC ; qf : OUT STD_LOGIC ; END rs1 ; ARCHITECTURE rsf OF rs1 IS COMPONENT nand PORT ( a : IN STD_LOGIC ; b : IN STD_LOGIC ; c : OUT STD_LOGIC ; END COMPONENT ; U1: nand PORT MAP ( a => s, b => qf, c => q ) ; U2: nand PORT MAP ( a => q, b => r, c => qf ) ; END rsf ; CONFIGURATION sel OF rs1 IS FOR rsf FOR u1, u2 : nand USE ENTITY WORK.nand( two ) ; END FOR END FOR END sel ; WORK 3-1 ENTITY 3-2 3-3 VHDL

54 VHDL 3-4 PROCESS PROCESS 3-5 VHDL 3-6 3-7 8 74LS373 D CLOCK OE Q 3-8 1 ENTITY buf3s IS -- PORT (input : IN STD_LOGIC ; -- enable : IN STD_LOGIC ; -- output : OUT STD_LOGIC ) ; -- END buf3x ; 2 ENTITY mux21 IS -- 2 1 PORT (in0, -- 0 in1, -- 1 sel : IN STD_LOGIC; -- output : OUT STD_LOGIC); -- END mux21 ; 3-9 VHDL 3-10 VHDL ENTITY dlatch IS PORT( d, cp : IN STD_LOGIC ; q, qn : BUFFER STD_LOGIC ) ; END dlatch ; ARCHITECTURE one OF dlatch IS SINGAL n1, n2 : STD_LOGIC ; n1<= (NOT d) NAND cp ; n2<= d NAND cp ;q <= qn NAND n1 ; qn <= q NAND n2 ; END one ; 3-11 VHDL ENTITY ENTITY SN74LS20 IS

3 VHDL PORT ( I1A, I1B, I1C, I1D : IN STD_LOIGC ; I2A, I2B, I2C, I2D : IN STD_LOIGC ; O1, O2 : OUT STD_LOGIC ) ; END SN74LS20 ; ARCHITECTURE struc OF SN74LS20 IS O1 <= NOT (I1A AND I1B AND I1C AND I1D) ; O2 <= NOT (I1A AND I1B AND I1C AND I1D) ; END struc ; 3-12 VHDL 3-13 BLOCK BLOCK 3 3-14 55

4 VHDL 55 4 VHDL VHDL VHDL VHDL VHDL VHDL VHDL (Data Objects Objects) (Variables) (Signals) (Constants) (Data Types Types) (Operands) (Operators) 4.1 VHDL VHDL VHDL VHDL (Literal) 1. h 5 678 0 156E2(=15600) 45_234_287 (=45234287) h 188.993 88_670_551.453_909(=88670551.453909) 1.0 44.99E-2(=0.4499) 1.335 0.0 h # # 0

56 VHDL... SIGNAL d1,d2,d3,d4,d5, : INTEGER RANGE 0 TO 255; d1 <= 110#170# ; d2 <= 16#FE# ; d3 <= 2#1111_1110#; -- ( 170) -- ( 254) -- ( 254) d4 <= 8#376# ; -- ( 254) d5 <= 16#E#E1 ; -- ( 2#1110000# 224)... h (VHDL ) 60s (60 ) 100m (100 ) k ( ) 177A (177 ) 2 ASCII 'R' 'a' '*' 'Z' 'U' '0' '11' '-' 'L' TYPE STD_ULOGIC IS ( 'U' 'X' '0' '1' 'W' 'L' 'H' '-' ) (1) "ERROR" "Both S and Q equal to 1" "X" "BB$CC" (2) Bit "B" "O" "X" h B 0 1 Bit h O 3 (BIT) h X (0 F) 4 data1 <= B"1_1101_1110" data2 <= O"15" data3 <= X"AD0" -- 9 -- 6 -- 12 data4 <= B"101_010_101_010" -- 12

data5 <= "101_010_101_010" data6 <= "0AD0" 4 VHDL -- X -- B 57 3 VHDL h 26 a z A Z 0 9 _ h h _ h VHDL 93 h \74LS373\ \Hello World\ h ( ) \IRDY#\ \C/BE\ \A or B\ h 1987 VHDL Decoder_1 FFT Sig_N Not_Ack State0 Idle _Decoder_1 -- 2FFT Sig_#N Not-Ack RyY_RST_ data BUS return 4. -- -- # -- - -- _ -- -- ( )

58 VHDL m 3 SIGNAL a b : BIT_VECTOR (0 TO 3) ; SIGNAL m : INTEGER RANGE 0 TO 3 ; SIGNAL y z : BIT ; y <= a(m) ; z <= b(3) ; 5 -- -- ( ) ( ) TO DOWNTO TO (2 TO 8) DOWNTO (8 DOWNTO 2) SIGNAL a z : BIT_VECTOR (0 TO 7) ; SIGNAL b : STD_LOGIC_VECTOR (4 DOWNTO 0) ; SIGNAL c : STD_LOGIC_VECTOR (0 TO 4) ; SIGNAL e : STD_LOGIC_VECTOR (0 TO 3) ; SIGNAL d : STD_LOGIC ;... z(0 TO 3) <= a(4 TO 7) ; -- z 0 <=a(4) z 1 <=a(5)... z(4 TO 7) <= a(0 TO 3) ; b(2) <= '1'; b(3 DOWNTO 0) <= "1010"; -- b 3 <='1' b 2 <='0'... c(0 TO 3) <= "0110"; c(2) <= d ; c <= b ; -- c(0 TO 4)<=b(4 DOWNTO 0) c 0 <=b(4) c 1 <=b(3)... e <= c ; -- e <= c 0 TO 3 ; -- e <= c 1 TO 4 ; -- 4.2 VHDL VHDL (Data Objects) (VARIABLE) (CONSTANT) (SIGNAL)

4 VHDL VHDL GND VCC VHDL VHDL VHDL ( VHDL ) VHDL VHDL FPGA/CPLD 59 4.2.1 (VARIABLE) VHDL VHDL VARIABLE := VARIABLE a : INTEGER ; VARIABLE b, c : INTEGER := 2 ; VARIABLE d : STD_LOGIC ; a b c 2 d

60 VHDL := := 4-1 4-1 VARIABLE x y : REAL ; VARIABLE a b : BIT_VECTOR( 0 TO 7 ) ; x := 100.0 ; -- x y := 1.5+x ; -- y a := b ; a := "1010101" ; -- a a (3 TO 6) := ( '1' '1' '0' '1') ; -- a (0 TO 5) := b (2 TO 7) ; a (7) := '0' ; -- 4-1 a b 8 8 a (0) a (1) a (7) b (0) b (1) b (7) VHDL 93 SHARED VARIABLE fre: BOOLEAN := true VHDL 4.2.2 (SIGNAL) VHDL ABEL REG NODE SIGNAL := VHDL

4 VHDL (Port) SIGNAL temp : STD_LOGIC := 0 ; SIGNAL flaga flagb : BIT ; SIGNAL data : STD_LOGIC_VECTOR(15 DOWNTO 0 ) ; SIGNAL a : INTEGER RANGE 0 TO 15; temp STD_LOGIC BIT flaga flagb STD_LOGIC_VECTOR 16 a 0 15 VHDL TYPE four IS ( 'X', '0', '1', 'Z' ) SIGNAL s1 : four SIGNAL s2 : four := 'X' SIGNAL s3 : four := '1' four TYPE four STD_LOGIC s1 VHDL LEFT most 'X' ( ) s2 'X' s3 '1' VHDL <= 61

62 VHDL ( ) <= ( 8 ) <= <= := := x <= 9 ; y <= x ; z <= x AFTER 5ns ; 5ns x z AFTER AFTER δ δ VHDL ( ) 4-2... SIGNAL a b c y z: INTEGER... PROCESS (a b c) y <= a * b ; z <= c x ; y <= b END PROCESS ;... a b c y b y b ( ) 4-3 ARCHITECTURE fun1 OF adder_h IS

4 VHDL sum <= a XOR b ; carry <= a AND b ; END ARCHITECTURE fun1 63 a b sum carry 9 9-8 9-9 9-25 4.2.3 (CONSTANT) CONSTANT := CONSTANT fbus : BIT_VECTOR := "010115" ;-- CONSTANT Vcc : REAL := 5.0 ; CONSTANT dely : TIME := 25ns ; -- -- VHDL (file) (Access) 4-4 4-4 PACKAGE t IS CONSTANT rst : STD_LOGIC ; END PACKAGE t PACKAGE BODY t IS CONSTANT rst : STD_LOGIC := '0' ; END PACKAGE BODY t ; 4-4 rst

64 VHDL 4.3 VHDL 4.2 (TYPES) VHDL ( ) VHDL VHDL VHDL VHDL BIT VHDL 1. (Scalar Type) h h h h 2. (Composite Type) (Array) (Record) 3. (Access Type) 4. (Files Type) VHDL VHDL VHDL STANDARD STD_LOGIC_1164 VHDL VHDL

4 VHDL VHDL VHDL REAL TIME FILE ( ) 65 4.3.1 VHDL VHDL VHDL STANDARD VHDL USE 1. (BOOLEAN) STANDARD TYPE BOOLEAN IS (FALSE TRUE) FALSE( ) TRUE( ) BOOLEAN a b IF (a>b) TRUE FALSE 1 0 2 (BIT) 1 0 VHDL BIT STANDARD TYPE BIT IS ( '0', '1' ) 3 (BIT_VECTOR) BIT STANDARD : TYPE BIT_VECTOR IS ARRAY (Natural Range <> ) OF BIT ; SIGNAL a : BIT_VECTOR(7 TO 0) ; a 8 a(7) a(0) 4. (CHARACTER) 'A' 'B' 'b'

66 VHDL STANDARD TYPE CHARACTER IS ( NUL SOH STX ETX EOT ENQ ACK BEL, BS HT LF VT FF CR SO SI, DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FSP GSP RSP USP, ' ' '!' '"' '#' '$' '%' '&' ''', '(' ')' '*' '+' ',' '-' '.' '/', '0' '1' '2' '3' '4' '5' '6' '7', '8' '9' ':' ';' '<' '=' '>' '?', '@' 'A' 'B' 'C' 'D' 'E' 'F' 'G', 'H' 'I' 'J' 'K' 'L' 'M' 'N' 'O', 'P' 'Q' 'R' 'S' 'T' 'U' 'V' 'W', 'X' 'Y' 'Z' '[' '\' ']' '^' '_', '`' 'a' 'b' 'c' 'd' 'e' 'f' 'g', 'h' 'i' 'j' 'k' 'l' 'm' 'n' 'o', 'p' 'q' 'r' 's' 't' 'u' 'v' 'w', 'x' 'y' 'z' '{' ' ' '}' '~' DEL ) ; VHDL 5. (INTEGER) + * / VHDL 2147483647 2147483647 32 VHDL INTEGER VHDL Integer VHDL RANGE VHDL SIGNAL typei : INTEGER RANGE 0 TO 15 ; typei 0 15 16 4 typei 2 0 77459102 10E4

4 VHDL 16#D2# 8#720# 2#11010010# 67 6. (NATURAL) (POSITIVE) STANDARD SUBTYPE NATURAL IS INTEGER RANGE 0 TO INTEGER'HIGH ; SUBTYPE POSITIVE IS INTEGER RANGE 1 TO INTEGER'HIGH ; 7. (REAL) VHDL 1.0E38 1.0E38 VHDL VHDL 1.0 0.0 65971.333333 65_971.333_3333 8#43.6#e+4 43.6E 4 8. (STRING) VARIABLE string_var : STRING (1 TO 7 ) ; string_var := "a b c d" 9. (TIME) VHDL 55 ms 20 ns STANDARD TYPE time IS RANGE 2147483647 TO 2147483647 units fs ; -- VHDL ps = 1000 fs ; -- ns = 1000 ps ; -- us = 1000 ns ; -- ms = 1000 us ; -- sec = 1000 ms ; --

68 VHDL min = 60 sec ; hr = 60 min ; end units ; 10. (SEVERITY LEVEL) -- -- VHDL NOTE( ) WARNING( ) ERROR( ) FAILURE( ) TYPE severity_level IS (note warning error failure) ; 11. (1) (2) REAL (3) Aceess (4) File RAM ROM 4.3.2 IEEE IEEE STD_LOGIC_1164 STD_LOGIC STD_LOGIC_VECTOR 1. STD_LOGIC IEEE STD_LOGIC_1164 STD_LOGIC TYPE STD_LOGIC IS 'U' 'X' '0' '1' 'Z' 'W' 'L' 'H' '-' ) ; -- -- -- 0 -- 1 -- -- -- 0 -- 1 -- LIBRARY IEEE; USE IEEE.STD_LOIGC_1164.ALL;

4 VHDL STD_LOGIC BIT STD_LOGIC BIT 0 1 IEEE STD_LOGIC BIT STD_LOGIC STD_LOGIC_1164 STD_LOGIC AND NAND OR NOR XOR NOT BIT STD_LOGIC STD_LOGIC STD_LOGIC 0 1 Z VHDL 2. (STD_LOGIC_VECTOR) STD_LOGIC_VECTOR TYPE STD_LOGIC_VECTOR IS ARRAY ( NATURAL RANGE <> ) OF STD_LOGIC ; STD_LOGIC_VECTOR STD_LOGIC_1164 STD_LOGIC STD_LOGIC_VECTOR ARRAY 4-5 CPU 4-5... TYPE t_data IS ARRAY(7 DOWNTO 0) OF STD_LOGIC; -- SIGNAL databus memory : t_data ; -- databus,memory CPU : PROCESS -- CPU VARIABLE rega : t_data ; -- rega... databus <= rega; -- 8 END PROCESS CPU -- CPU MEM : PROCESS -- RAM... databus <= memory ; END PROCESS MEM... STD_LOGIC_VECTOR 69

70 VHDL STD_LOGIC 4.3.3 VHDL Synopsys IEEE STD_LOGIC_ARITH h (UNSIGNED) h (SIGNED) h (SMALL_INT) STD_LOGIC_ARITH TYPE UNSIGNED IS array (NATURAL range < >) OF STD_LOGIC ; TYPE SIGNED IS ARRAY (NATURAL range < >) OF STD_LOGIC ; SUBTYPE SMALL_INT IS INTEGER RANGE 0 TO 1 ; LIBRARY IEEE ; USE IEEE.STD_LOIGC_ARITH.ALL ; UNSIGNED SIGNED UNSIGNED SIGNED IEEE NUMERIC_STD NUMERIC_BIT UNSIGNED SIGNED NUMERIC_STD STD_LOGIC NUMERIC_BIT BIT STD_LOGIC_ARITH NUMBER_STD NUMERIC_BIT STANDARD STD_LOGIC_VECTOR UNSIGNED SIGNED 1. (UNSIGNED TYPE) UNSIGNED 8 UNSIGNED'("1000") UNSIGNED 4 15 8 255 0 UNSIGNED VARIABLE var : UNSIGNED(0 TO 10) ;

SIGNAL sig : UNSIGNED(5 TO 0) ; 4 VHDL 71 var 11 var(0) var(10) sig 6 sig(5) 2. (SIGNED TYPE) SIGNED SIGNED'("0101") +5 5 SIGNED'("1011") 5 var SIGNED VARIABLE var SIGNED(0 TO 10) ; var 11 var(0) 4.3.4 VHDL (Enumeration Types) (Interger Types) (Array Types) (Record Types) (Time Types) (Real Types) TYPE SUBTYPE 1. TYPE TYPE TYPE IS OF Type IS TYPE OF BIT STD_LOGIC INTEGER TYPE st1 IS ARRAY ( 0 TO 15 ) OF STD_LOGIC ; TYPE week IS (sun mon tue wed thu fri sat) ; TYPE byt IS STD_LOGIC(15 TO 0) ;--

72 VHDL st1 16 STD_LOGIC sun = 1010 ;,TYPE VHDL STD_LOGIC VHDL (SIGNAL VARIABLE CONSTANT) TYPE v1 8 byte TYPE byte IS ARRAY(7 DOWNTO 0) of BIT VARIABLE v1 : byte ; --v1 byte colour TYPE colour IS (Red Green Yellow Blou Violet);... a <= colour (Red) ; 2. SUBTYPE -- Red a SUBTYPE TYPE SUBTYPE SUBTYPE IS RANGE TYPE TYPE VHDL TYPE SUBTYPE digits IS INTEGER RANGE 0 to 9 ; INTEGER digits INTEGER 10 2 SUBTYPE SUBTYPE dig1 IS STD_LOGIC_VECTOR(7 DOWNTO 0) ; SUBTYPE dig3 IS ARRAY(7 DOWNTO 0) of STD_LOGIC;-- STANDARD (Natural type) (Positive type) INTEGER

4 VHDL 73 4.3.5 VHDL VHDL TYPE m_state IS ( state1 state2 state3 state4 state5 ) ; SIGNAL present_state next_state : m_state ; present_state next_state m_state state1 state5 VHDL BIT (BOOLEAN) (CHARACTER) STD_LOGIC BIT 0 1 0 1 0 1 4-6 TYPE my_logic IS ( 1 Z U 0 ) ; SIGNAL s1 : my_logic ; s1 <= Z ; TYPE STD_LOGIC IS ( U X 0 1 Z W L H - ) ; SIGNAL sig : STD_LOGIC ; sig <= Z ; ( ) 0 1 3 state1 = 000 state2 = 001 state3 = 010 state4 = 011 state5 = 100 state1 < state2 < state3 < state4 < state5 9

74 VHDL 4.3.6 VHDL VHDL h h VHDL RANGE TYPE percent IS RANGE 100 TO 100 ; 8 1 7 4-7 TYPE num1 IS range 0 to 100 -- 7 TYPE num2 IS range 10 to 100 -- 7 TYPE num3 IS range -100 to 100 -- 8 SUBTYPE num4 IS num3 RANGE 0 to 6 -- 3 4.3.7 ( ) ) VHDL VHDL 0 TO 7 8 15 DOWNTO 0 16 VHDL

4 VHDL TYPE IS ARRAY ( )OF 75 TYPE stb IS ARRAY (7 DOWNTO 0) of STD_LOGIC ; stb 8 7 6 5 4 3 2 1 0 stb(7) stb(6) stb(0) TYPE x is (low high) ; TYPE data_bus IS ARRAY (0 TO 7 x) of BIT ; x data_bus 9 BIT TYPE IS ARRAY ( RANGE <>)OF <> <> < > 4-8 TYPE Bit_Vector IS Array (Natural Range <>)OF BIT VARIABLE va Bit_Vector (1 to 6) -- 1 6 4-9 TYPE Real_Matrix IS ARRAY (POSITIVE RANGE <>) of RAEL ; VARIABLE Real_Matrix_Object : Real_Matrix (1 TO 8) ; -- 4-10 TYPE Log_4_Vector IS ARRAY (NATURAL RANGE <>, POSITIVE RANGE<>) OF Log_4 ; VARIABLE L4_Object : Log_4_Vector (0 TO 7 1 TO 2) ;-- 4-11 4-11 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;

76 VHDL ENTITY regfile IS PORT ( q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); d : IN STD_LOGIC_VECTOR (7 DOWNTO 0); addr : IN STD_LOGIC_VECTOR (3 DOWNTO 0); we, clk : IN STD_LOGIC); END regfile; ARCHITECTURE behave OF regfile IS TYPE rf_type IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL rf : rf_type (15 DOWNTO 0); PROCESS (clk) IF RISING_EDGE(clk) THEN IF we = '1' THEN rf(conv_integer(addr)) <= d; END IF; END IF; END PROCESS; q <= rf(conv_integer(addr)); END behave; 8 RAM RAM 16 16 4.3.8 4-1 4-11 RTL TYPE IS RECORD... : ; : ; END RECORD [ ]; 4-12 TYPE GlitchDataType IS RECORD -- GlitchDataType

4 VHDL 77 SchedTime : TIME ; -- SchedTime GlitchTime : TIME ; -- GlitchTime SchedValue : STD_LOGIC ; -- SchedValue CurrentValue : STD_LOGIC ; -- CurrentValue END RECORD ; OTHERS OTHERS 4-13 4-13 TYPE RegName IS (AX BX CX DX) ; TYPE Operation IS RECORD Mnemonic : STRING (1 TO 10) ; OpCode : BIT_VECTOR(3 DOWNTO 0) ; Op1 Op2 Res : RegName ; END record ; VARIABLE Instr1 Instr2: Operation ;... Instr1 := ("ADD AX BX" "0001" AX BX AX) ; Instr2 := ("ADD AX BX" "0010" others => BX) ; VARIABLE Instr3 : Operation ; Instr3.Mnemonic := "MUL AX BX" ; Instr3.Op1 := AX ; Operation Mnemonic 4 OpCode Op1 Op2 Res Op1 Op2 Res Instr1 Operation "ADD AX BX" 4 "0001" AX BX AX BX AX AX Instr3.Mnemonic := "MUL AX BX" ; "MUL AX BX" Instr3 Mnemonic (. )

78 VHDL 4.3.9 VHDL 1. 4-14 PACKAGE defs IS SUBTYPE short IS INTEGER RANGE 0 TO 15 ; END defs ; USE WORK.defs.ALL ; ENTITY cnt4 IS PORT (clk : IN BOOLEAN ; P : INOUT short) ; END ENTITY cnt4 ARCHITECTURE behv OF cnt4 IS PROCESS (clk) IF clk AND clk EVENT THEN P <= P + 1 ; END IF ; END PROCESS ; END behv ; 4-2 4-14 4 2 defs short 0 15 P short + P 1 VHDL + PLD I/O P P PLD I/O 4-2 4-14 RTL + 4-15 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ; ENTITY cnt4 IS

4 VHDL PORT (clk : IN STD_LOGIC ; p : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0) ) END cnt4 LIBRARY dataio ; USE dataio.std_logic_ops.all ARCHITECTURE behv OF cnt4 IS PROCESS (clk) IF clk = 1 AND clk EVENT THEN p <= To_Vector(2,To_Integer(p)+1) ; END IF END PROCESS ; END behv ; 79 dataio DATAIO STD_LOGIC_ops To_Vector( NTEGER STD_LOGIC_VECTOR) To_Integer( STD_LOGIC_VECTOR INTEGER) + 1 STD_LOGIC_VECTOR EDA 4-14 VHDL VHDL 4-16 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY amp IS PORT ( a1 a2 : IN BIT_VECTOR(3 DOWNTO 0); c1 c2,c3 : IN STD_LOGIC_VECTOR (3 DOWNTO 0); b1 b2 b3 : INTEGER RANGE 0 TO 15; d1,d2,d3,d4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END amp;... d1 <= TO_STDLOGICVECTOR(a1 AND a2); --(1)... d2 < = CONV_STD_LOGIC_VECTOR(b1,4) WHEN CONV_INTEGER(b2)=9 else CONV_STD_LOGIC_VECTOR(b3,4); --(2)

80 VHDL... d3 < = c1 WHEN CONV_INTEGER(c2)= 8 ELSE c3; --(3)... d4 < = c1 WHEN c2 = 8 else c3; --(4), (1) IEEE.STD_LOGIC_1164, : FUNCTION TO_STDLOGICVECTOR( s : BIT_VECTOR) RETURN STD_LOGIC_VECTOR; STD_LOGIC_VECTOR IEEE.STD_LOGIC_UNSIGNED : FUNCTION CONV_INTEGER(arg: STD_LOGIC_VECTOR) RETURN INTEGER; FUNCTION CONV_STD_LOGIC_VECTOR(arg: INTEGER;size INTEGER) (2) RETURN STD_LOGIC_VECTOR 3 (4) STD_LOGIC_UNSIGNED "=" STD_LOGIC_VECTOR 4-17 CONV_INTEGER( ) 3-8 4-17 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY decoder3to8 IS PORT ( input: IN STD_LOGIC_VECTOR (2 DOWNTO 0); output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END decoder3to8; ARCHITECTURE behave OF decoder3to8 IS PROCESS (input) output <= (OTHERS => '0'); output(conv_integer(input)) <= '1'; END PROCESS; END behave; 4-18 FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0' ) RETURN BIT ; FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0' ) RETURN BIT_VECTOR ; FUNCTION To_bitvector ( s : std_ulogic_vector ; xmap : BIT := '0' ) RETURN BIT_VECTOR ;

4 VHDL 81 To_bitvector FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0' ) RETURN BIT_VECTOR IS ALIAS sv : std_logic_vector(s'length-1 DOWNTO 0 ) IS s ; VARIABLE result : BIT_VECTOR(s'LENGTH-1 DOWNTO 0 ); FOR i IN result'range LOOP CASE sv(i) IS WHEN '0' 'L' => result(i) := '0'; WHEN '1' 'H' => result(i) := '1'; WHEN OTHERS => result(i) := xmap; END CASE ; END LOOP ; RETURN result ; END ; To_bitvector std_logic_vector BIT_VECTOR STANDARD STD_LOGIC_1164 Vector INTEGER EDA 2. VHDL ( ) ( ) h ( ) h h 4-19 4-19 VARIABLE Data_Calc Param_Calc : INTEGER ;... Data_Calc := INTEGER(74.94 * REAL(Param_Calc) ) ;

82 VHDL 4.4 VHDL VHDL (Operands) (Operators) VHDL 4.4.1 VHDL 4-1 (Logical Operator) (Relational Operator) (Arithmetic Operator) (Sign Operator) (Overloading Operator) AND OR NAND NOR XOR XNOR NOT BIT BOOLEAN STD_LOGIC_1164 STD_LOGIC AND OR NAND NOR XOR XNOR AND OR XOR A and B and C and D (A or B) xor C VHDL h h VHDL ( 4-1 ) BIT STD_LOGIC ABEL-HDL 4-2 ** ABS NOT NOT

4 VHDL 83 4.4.2 4-1 VHDL + & * ( ) / ( ) MOD REM SLL BIT SRL BIT SLA BIT SRA BIT ROL BIT ROR BIT ** ABS = /= < > <= >= AND BIT BOOLEAN STD_LOGIC OR BIT BOOLEAN STD_LOGIC NAND BIT BOOLEAN STD_LOGIC NOR BIT BOOLEAN STD_LOGIC XOR BIT BOOLEAN STD_LOGIC XNOR BIT BOOLEAN STD_LOGIC NOT BIT BOOLEAN STD_LOGIC + 4-2 VHDL NOT ABS ** * / MOD REM +( ) ( ) + & SLL SLA SRL SRA ROL ROR = /= < <= > >= AND OR NAND NOR XOR XNOR VHDL AND( ) OR( ) NAND( ) NOR(

84 VHDL ) XOR( ) XNOR NOT( ) ( ) BIT BOOLEAN STD_LOGIC BIT_VECTOR STD_LOGIC_VECTOR 4-2 NOT 4-20 SIGNAL a b c : STD_LOGIC_VECTOR (3 DOWNTO 0) SIGNAL d e f g : STD_LOGIC_VECTOR (1 DOWNTO 0) SIGNAL h I j k : STD_LOGIC SIGNAL l m n o p : BOOLEAN... a<=b AND c ; -- b c a a b c -- 4 d<=e OR f OR g ; -- OR h<=(i NAND j)nand k -- NAND l<=(m XOR n)and(o XOR p); -- h<=i AND j AND k ; -- AND h<=i AND j OR k ; -- a<=b AND e ; -- b e h<=i OR l ; -- i STD_LOGIC l... -- BOOLEAN 4-3 BIT 4-3 a b NOT a a AND b a OR b a XOR b a NAND b a NOR b a XNOR b 0 0 1 0 0 0 1 1 1 0 1 1 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 1 0 1 1 0 0 0 1 4-3 1 TRUE 0 FALSE BOOLEAN ( STD_LOGIC_VECTOR) a b c d AND2 XOR 4-3 4-21 OR2 e

4 VHDL a[0] output[0] 4-3 4-4 b[0] 4-21 4-22 a[1] output[1] 4-21 b[1] a[2] STD_LOGIC 4-22 output[2] b[2] a[3] output[3] STD_LOGIC_VECTOR 4-4 b[3] 4-4 4-22 85 AND2 X 4 4-21 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ; ENTITY logical_ops_1 IS PORT (a b c d : IN STD_LOGIC ; E: OUT STD_LOGIC); END logical_ops_1 ; ARCHITECTURE example OF logical_ops_1 IS SIGNAL tmp: STD_LOGIC; e <= (a AND b) OR tmp; -- tmp <= c XOR d; -- END ARCHITECTURE example; 4-22 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ; ENTITY logical_ops_2 IS PORT ( a b : IN STD_LOGIC_VECTOR (0 TO 3) ; output : OUT STD_LOGIC_VECTOR (0 TO 3) ) ; END logical_ops_2 ; ARCHITECTURE example OF logical_ops_2 IS output <= a AND b ; END ARCHITECTURE example ; 4.4.3 (BOOLEAN) TRUE FALSE VHDL 4-1 = ( ) /= ( ) > ( )

86 VHDL < ( ) >= ( ) <= ( ) VHDL VHDL a b (a= b) TRUE (a /= b) FALSE ( ) VHDL BOOLEAN TRUE TRUE < <= > >= VHDL '1' > '0' TRUE > FALSE a > b ( a=1 b=0) TO DOWNTO q (1011) (101011) (101011) 0 VHDL TRUE '1' = '1' "101" = "101" "1" > "011" "101" < "110" STD_LOGIC_ARITH UNSIGNED UNSIGNED UNSIGNED' "1" < UNSIGNED' "011" TRUE (= /=) 4-23 a[0] b[0] a[1] b[1] 4-24 a[2] b[2] 4 a[3] b[3] 4-23 = 4-24 >= XOR X 4 NOR4 4-5 4-23 a = b output

4 VHDL 4-23 4-5 4-24 4-6 4-24 3 4-23 b[0] a[0] b[1] a[1] 87 b[2] a[2] b[3] a >= b output a[3] 4-6 4-24 4-23 ENTITY relational_ops_1 IS PORT ( a b : IN BIT VECTOR (0 TO 3) ; m : OUT BOOLEAN) ; END relational_ops_1 ; ARCHITECTURE example OF relational_ops_1 IS output <= (a = b) ; END example ; 4-24 ENTITY relational_ops_2 IS PORT (a b : IN INTEGER RANGE 0 TO 3 ; m : OUT BOOLEAN) ; END relational_ops_2 ; ARCHITECTURE example OF relational_ops_2 IS output <= (a >= b) ; END example ; 4.4.4 4-1 17 4-4

88 VHDL 4-4 1 (Adding operators) +( ) ( ) &( ) 2 (Multiplying operators) * / MOD REM 3 (Sign operators) +( ) ( ) 4 (Miscellaneous ** ABS 5 operators) (Shift operators) SLL SRL SLA SRA ROL ROR 1. VHDL VHDL 4 VHDL 4-25 VARIABLE a b c,d e,f : INTEGER RANGE 0 TO 255 ;... a := b + c ; d := e f ;... 4-26... PROCEDURE adding_e (a : IN INTEGER ; b : INOUT INTEGER ) IS... b := a + b ;... a[0] b[0] a[1] b[1] a[2] b[2] ( ) 4-27 3 4-7 4-27 OR2 XOR AND4 XOR AND2 NOR2 4-7 4-27 NXOR NAND2 c[0] c[1] c[2]

4 VHDL PACKAGE example_arithmetic IS TYPE small_int IS RANGE 0 TO 7 ; END example_arithmetic ; USE WORK.example_arithmetic.ALL ; ENTITY arithmetic IS PORT (a b : IN SMALL_INT ; c : OUT SMALL_INT) ; END arithmetic ; ARCHITECTURE example OF arithmetic IS c <= a + b ; END example ; 89 2. & VH & DL VHDL ;'0'&'1' 01 4-28 SIGNAL a d : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL b c g : STD_LOGIC_VECTOR (1 DOWNTO 0) ; SIGNAL e : STD_LOGIC_VECTOR (2 DOWNTO 0) ; SIGNAL f h I : STD_LOGIC ;... a <= NOT b & NOT c ; -- 4 d <= NOT e & NOT f ; -- 4 g <= NOT h & i ; -- 2 a <= '1'&'0'&b(1)&e(2) ; -- 4 '0'&c <= e ; --... IF a & d = "10100011" THEN... - IF 3. * ( ) / ( ) MOD( ) RED( ) VHDL ( ) 13 8 8 8

90 VHDL + 1 ( 13 ) MOD RED 2 MOD RED 4-29 SIGNAL a b c d e f g h : INTEGER RANGE 0 TO 15 ; a <= b*4 ; -- a 15 c <= d/4 ; e <= f MOD 4 ; g <= h REM 4 ; 4-30 VARIABLE c : Real c:= 12.34 * ( 234.4/43.89 ) ; -- c 0 15 (* / MOD REM) 2 2 ( ) MAX+plus II * / 2 x * 8 MAX+plus II LPM FUNDATION FPGA Express / MOD REM 2 * MAX+plus II MOD REM 4 + + z := x*( y) 5. ** ABS VHDL (**) VHDL 2 4-31

SIGNAL a b : INTEGER RANGE 8 to 7 ; SIGNAL c : INTEGER RANGE 0 to 15 ; SIGNAL d : INTEGER RANGE 0 to 3 ; a <= ABS(b) ; c <= 2 ** d ; 4 VHDL 91 MAX+plus II ABS ** FUNDATION FPGA Express ** 2 6. (OTHERS => X ) SIGNAL d1,d2 e : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL f: STD_LOGIC_VECTOR(4 DOWNTO 0);... d1 < = (OTHERS = >'0'); d1 < = "000000000",,, (OTHERS => X ) OTHERS d2 < = (1 = >'1',4 = >'1', OTHERS = >'0'); d2 1 4 '1', '0' (OTHERS => X ) d2 : f < = (1 = > e(3),3 = > e(5), OTHERS = > e(1) ); ( a 5 ): f < = e(1) & e(5) & e(1) & e(3) & e(1) ; f < = f(4) & f(3) & f(2) & f(1) & f(0) ; (OTHERS => X) & 7. SLL SRL SLA SRA ROL ROR VHDL 93 1987 VHDL 93 BIT BOOLEAN EDA STD_LOGIC_VECTOR INTEGER INTEGER INTEGER SLL SRL SLL ROL

92 VHDL ROR SLA SRA 4-32 4-33 4-34 4-32... VARIABLE shifta : STD_LOGIC_VECTOR(3 DOWNTO 0) := ('1','0','1','1'); --... shifta SLL 1 -- ('0' '1' '1' '0') -- 1 shifta SLL 3 -- ('1' '0' '0' '0') -- 3 shifta SLL 3 -- shifta SRL 3 shifta SRL 1 -- ('0' '1' '0' '1') shifta SRL 3 -- ('0' '0' '0' '1') shifta SRL 3 -- shifta SLL 3 shifta SLA 1 -- ('0' '1' '1' '1') shifta SLA 3 -- ('1' '1' '1' '1') shifta SLA 3 -- shifta SRA 3 shifta SRA 1 -- ('1' '1' '0' '1') shifta SRA 3 -- ('1' '1' '1' '1') shifta SRA 3 -- shifta SLA 3 shifta ROL 1 -- ('0' '1' '1' '1') shifta ROL 3 -- ('1' '1' '0' '1') shifta ROL 3 -- shifta ROR 3 shifta ROR 1 -- ('1' '1' '0' '1') shifta ROR 3 -- ('0' '1' '1' '1') shifta ROR 3 -- shifta ROL 3... 4-33 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ; ENTITY shift1 IS PORT ( a b : IN STD_LOGIC_VECTOR (7 DOWNTO 0) ; out1 out2 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ) ; END shift1 ; ARCHITECTURE example OF shift1 IS out1 <= a SLL 2 ; out2 <= b ROL 2 END example ;

4 VHDL 93 4-34 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ; ENTITY shift1 IS PORT (a b : IN STD_LOGIC_VECTOR (7 DOWNTO 0 ) ; out1 out2 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ) ; END shift1 ; ARCHITECTURE example OF shift1 IS out1 <= a(5 DOWNTO 0) & "00" ; out2 <= b(5 DOWNTO 0) & b(7 DOWNTO 6) END example; 4-35 SLL STD_LOGIC_UNSIGNED CONV_INTEGER 3-8 4-35 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY decoder3to8 IS port ( input: IN STD_LOGIC_VECTOR (2 DOWNTO 0); output: OUT BIT_VECTOR (7 DOWNTO 0)); END decoder3to8; ARCHITECTURE behave OF decoder3to8 IS output <= "00000001" SLL CONV_INTEGER(input); END behave; ( ) 4.4.5 VHDL

94 VHDL STD_LOGIC_UNSIGNED Synopsys STD_LOGIC_ARITH STD_LOGIC_UNSIGNED STD_LOGIC_SIGNED SINGNED UNSIGNED STD_LOGIC INTEGER INTEGER STD_LOGIC STD_LOGIC_VECTOR 3 3.5 3.6 3.7 4-1 VHDL 16 0FA 10 12F 8 789 8 356 2 0101010 74HC245 \74HC574\ CLR/RESET \IN 4/SCLK\ D100 4-2 (1) (2) (3) (4) + BIT BOOLEAN (5) VHDL (**) (6) = /= > < (7) 4-3 4-4 AGE function CONV_INTEGER(ARG: AGE) return INTEGER; + SIGNAL a c : AGE;... c <= a + 20; 4-5 16 16 A= [A15 A0] B=[B15 B0] D E F A=B D=1 A>B E=1 A<B F=1 4-6 VHDL

5 VHDL 95 5 VHDL (Sequential Statements) (Concurrent Statements) VHDL ( ) (Process) (Function) (Procedure) VHDL VHDL VHDL VHDL VHDL h h h h h h 5.1

96 5 VHDL VHDL 5.1.1 <= = VHDL ( ) ( ) ( ) D VHDL ( 9 ) := <= 5-1 5-1 SIGNAL s1,s2 : STD_LOGIC; SIGNAL svec : STD_LOGIC_VECTOR (0 TO 7);... PROCESS ( s1,s2 ) VARIABLE v1,v2 : STD_LOGIC

v1 := '1' ; v2 := '1' ; s1 <= '1' ; s2 <= '1' ; svec(0) <= v1; svec(1) <= v2; svec(2) <= s1; svec(3) <= s2; v1 := '0' ; v2 := '0' ; s2 <= '0' ; svec(4) <= v1; svec(5) <= v2; svec(6) <= s1; svec(7) <= s2; END PROCESS ; 97 5 VHDL -- v1 1 -- v2 1 -- s1 1 -- s2 -- -- v1 1 svec(0) -- v2 1 svec(1) -- s1 1 svec(2) -- s2 '0' svec(3) -- v1 0 -- v2 0 -- s2 -- '0' '1' -- v1 0 svec(4) -- v2 0 svec(5) -- s1 1 svec(6) -- s2 0 svec(7) 5.1.2 1. 5-2 5-2 VARIABLE a b STD_LOGIC ; SIGNAL c1 : STD_LOGIC_VECTOR (1 TO 4); a := '1' b := '0' c1 := "1100" a b c1 2. ( ) ( ) 5-3 5-3

98 5 VHDL SIGNAL a b STD_LOGIC_VECTOR (0 TO 3); SIGNAL i INTEGER RANGE 0 TO 3 ; SIGNAL y z STD_LOGIC;... -- a <= " 1010 " ; b <= " 1000 " ; a (I) <= y ; -- b (3) <= z ; -- 3. ( 1 TO( DOWNTO) 2) TO DOWNTO 5-4 5-4 VARIABLE a b STD_LOGIC_VECTOR (1 TO 4); a (1 TO 2) := "10" -- a(1) :='1' a(2) := '0' a (1 To 4) := " 1011" 4. 5-5 SIGNAL a, b, c, d STD_LOGIC SIGNAL s STD_LOGIC_VECTOR (1 TO 4);... VARIABLE e, f STD_LOGIC VARIABLE g STD_LOGIC_VECTOR (1 TO 2); VARIABLE h : STD_LOGIC_VECTOR (1 TO 4); s <= ('0' '1' '0' '0') (a, b, c, d) <= s ; --... -- (3=>e, 4=>f 2 =>g(1) 1=>g(2) ) := h -- a <= '0' b <= '1' c <= '0' d <= '0' g(2) = h(1) g(1) = h(2) e = h(3) f = h(4)

5 VHDL 5.2 99 h IF h CASE h LOOP h NEXT h EXIT 5.2.1 IF IF IF IF Then END IF IF Then ELSE END IF -- IF -- IF IF Then -- IF ELSIF Then... ELSE END IF IF BOOLEAN IF TRUE FALSE IF (TRUE) (THEN) END IF IF (FALSE) IF IF 5-6

100 5-6 k1 : IF (a>b) THEN output <= '1' ; END IF k1; 5 VHDL k1 (a>b) TRUE output 1 IF IF FALSE END IF ELSE IF IF IF 2 5-7 FUNCTION and_func (x,y : IN BIT ) RETURN BIT IS IF x='1' AND y='1' THEN RETURN '1'; ELSE RETURN '0'; END IF END and_func ; IF BOOLEAN 5-8 5-8 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY control_stmts IS PORT (a, b, c: IN BOOLEAN; output: OUT BOOLEAN); END control_stmts; ARCHITECTURE example OF control_stmts IS PROCESS (a, b, c) VARIABLE n: BOOLEAN; IF a THEN n := b; ELSE n := c; END IF; output <= n; END PROCESS; END example; 5-8 5-1 a

5 VHDL IF ELSIF ( ) c 5-2 2 1 VHDL a 5-9 p1 p2 b output 5-1 5-8 5-9 SIGNAL a, b, c, p1, p2, z : BIT ;... IF (p1 ='1') THEN z <= a ; -- (p1 ='1') ELSIF (p2 ='0') THEN z <= b ; -- (p1 ='0') AND (p2 ='0') ELSE z <= c ; -- (p1 ='0') AND (p2 ='1') END IF; 101 5-2 2 1 5-9 IF IF-THEN-ELSIF 5-10 8-3 5-1 5-10 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY coder IS PORT ( din : IN STD_LOGIC_VECTOR(0 TO 7); output : OUT STD_LOGIC_VECTOR(0 TO 2) ); END coder; ARCHITECTURE behav OF coder IS SIGNAL SINT : STD_LOGIC_VECTOR(4 DOWNTO 0); PROCESS (din) IF (din(7)='0') THEN output <= "000" ; --(din(7)='0') ELSIF (din(6)='0') THEN output <= "100" ; --(din(7)='1')and(din(6)='0') ELSIF (din(5)='0') THEN

102 5 VHDL output <= "010" ; --(din(7)='1')and(din(6)='1')and(din(5)='0') ELSIF (din(4)='0') THEN output <= "110" ; ELSIF (din(3)='0') THEN output <= "001" ; ELSIF (din(2)='0') THEN output <= "101" ; ELSIF (din(1)='0') THEN output <= "011" ; ELSE output <= "111" ; END IF END PROCESS END behav; 5-1 8-3 din0 din1 din2 din3 din4 din5 din6 din7 output0 output1 output2 x x x x x x x 0 0 0 0 x x x x x x 0 1 1 0 0 x x x x x 0 1 1 0 1 0 x x x x 0 1 1 1 1 1 0 x x x 0 1 1 1 1 0 0 1 x x 0 1 1 1 1 1 1 0 1 x 0 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 x VHDL 5-10 output <= "111" (in (7) ='1') AND (in (6) ='1') AND (in (5) ='1') AND (in (4) ='1') AND(in (3) ='1') AND (in (2) ='1') AND (in (1) ='1') AND (in (0) ='0' ) 5-1 5.2.2 CASE CASE CASE CASE IS When => When =>... END CASE CASE

5 VHDL CASE ( => THEN ) [ ] h 4 h (2 TO 4) 2 3 4 h 3 5 3 5 h CASE (1) (2) CASE OTHERS OTHERS OTHERS STD_LOGIC STD_LOGIC_VECTOR 1 0 Z X (3) CASE (4) CASE CASE 5-11 CASE 4 1 VHDL 5-11 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY mux41 IS PORT (s1, s2 : IN STD_LOGIC; a, b, c, d : IN STD_LOGIC; z : OUT STD_LOGIC); END ENTITY mux41 ARCHITECTURE activ OF mux41 IS SIGNAL s : STD_LOGIC_VECTOR (1 DOWNTO 0); s <= s1 & s2 ; PROCESS (s, a, b, c, d) - s s1 s2 CASE s IS WHEN "00" => z<= a ; WHEN "01" => z<= b ; 103

104 5 VHDL WHEN "10" => z<= c ; WHEN "11" => z<= d ; WHEN OTHERS => z<= 'X' ;-- X END CASE END PROCESS End activ s1 s2 d c b a D C B A S1 S0 5-3 4 1 z 5-11 STD_LOGIC_VECTOR s VHDL 00 01 10 11 STD_LOGIC 5-3 WHEN OTHERS => z<= 'X' X STD_LOGIC 5-12 4 1 IF CASE 4 4 1 5-12 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY mux41 IS PORT (s4 s3, s2 s1 : IN STD_LOGIC; z4 z3, z2 z1 : OUT STD_LOGIC); END mux41 ARCHITECTURE activ OF mux41 IS SIGNAL sel : INTEGER RANGE 0 TO 15; PROCESS (sel s4 s3 s2 s1 ) sel<= 0 ; -- IF (s1 ='1') THEN sel <= sel+1 ; ELSIF (s2 ='1') THEN sel <= sel+2 ; ELSIF (s3 ='1') THEN sel <= sel+4 ; ELSIF (s4 ='1') THEN sel <= sel+8 ; ELSE NULL; -- END IF ; z1<='0' ; z2<='0'; z3<='0'; z4<='0'; -- CASE sel IS WHEN 0 => z1<='1' ; -- sel=0 WHEN 1 3 => z2<='1' ; -- sel 1 3 WHEN 4 To 7 2 => z3<='1'; -- sel 2 4 5 6 7 WHEN OTHERS => z4<='1' ; -- sel 8 15 END CASE

END PROCESS END activ 5 VHDL 105 5-12 IF-THEN-ELSIF s4 s3 s2 s1 4 sel 5-13 CASE 5-13 SIGNAL value : INTEGER RANGE 0 TO 15; SIGNAL out1 : STD_LOGIC ;... CASE value IS -- WHEN END CASE... CASE value IS WHEN 0 => out1<= '1' ; -- value2 15 WHEN 1 => out1<= '0' ; END CASE... CASE value IS WHEN 0 TO 10 => out1<= '1'; -- 5 10 WHEN 5 TO 15 => out1<= '0'; END CASE IF CASE CASE IF CASE CASE IF CASE IF IF-THEN-ELSLF ( ) CASE 5-14 VHDL opcode CASE IF-THEN 5-14 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY alu IS PORT( a, b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); opcode: IN STD_LOGIC_VECTOR (1 DOWNTO 0); result: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END alu; ARCHITECTURE behave OF alu IS CONSTANT plus : STD_LOGIC_VECTOR (1 DOWNTO 0) := b"00"; CONSTANT minus : STD_LOGIC_VECTOR (1 DOWNTO 0) := b"01"; CONSTANT equal : STD_LOGIC_VECTOR (1 DOWNTO 0) := b"10";

106 5 VHDL CONSTANT not_equal: STD_LOGIC_VECTOR (1 DOWNTO 0) := b"11"; PROCESS (opcode,a,b) CASE opcode IS WHEN plus => result <= a + b; -- a b WHEN minus => result <= a - b; -- a b WHEN equal => -- a b IF (a = b) THEN result <= x"01"; ELSE result <= x"00"; END IF; WHEN not_equal => -- a b IF (a /= b) THEN result <= x"01"; ELSE result <= x"00"; END IF; END CASE; END PROCESS; END behave; 5.2.3 LOOP LOOP LOOP (1) LOOP [ LOOP ] LOOP END LOOP [ LOOP ] ( EXIT ) LOOP 5-15 5-15... L2 : LOOP a := a+1; EXIT L2 WHEN a >10 ; END LOOP L2;... -- a 10 EXIT a>10 a := a+1 (2) FOR_LOOP [LOOP ] FOR IN LOOP END LOOP [LOOP ]

5 VHDL FOR LOOP LOOP LOOP LOOP 1 5-4 5-16 5-16 8 VHDL 5-16 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY p_check IS PORT ( a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); y : OUT STD_LOGIC ); END p_check ARCHITECTURE opt OF p_check IS SIGNAL tmp STD_LOGIC PROCESS(a) tmp <='0'; FOR n IN 0 TO 7 LOOP tmp <= tmp XOR a(n); END LOOP ; y <= tmp; END PROCESS; END opt; 5-17 LOOP 5-17 SIGNAL a, b, c : STD_LOGIC_VECTOR (1 TO 3);... FOR n IN 1 To 3 LOOP a(n) <= b(n) AND c(n); END LOOP; a(1)<=b(1) AND c(1); a(2)<=b(2) AND c(2); a(3)<=b(3) AND c(3); LOOP LOOP (3) WHILE_LOOP 107

108 5 VHDL [ ] WHILE LOOP END LOOP [ ] FOR_LOOP WHILE_LOOP a=0 a>b TRUE FALSE END LOOP 5-18 5-18 Shift1 : PROCESS (inputx) VARIABLE n : POSITIVE := 1; L1 : WHILE n<=8 LOOP -- <= outputx(n)<=inputx(n + 8) n := n+1; END LOOP L1; END PROCESS Shift1; a[0] a[1] a[2] a[3] out1[3] out1[2] out1[1] out1[0] 5-5 5-19 WHILE_LOOP n 9 NEXT EXIT 5-19 5-20 a[0] a[1] a[2] 5-5 5-6 5-19 5-20 out1[2] out1[1] out1[0] 5-6 5-20 5-19 ENTITY LOOP_stmt IS PORT (a: IN BIT_VECTOR (0 TO 3); out1: OUT BIT_VECTOR (0 TO 3)); END LOOP_stmt; ARCHITECTURE example OF LOOP_stmt IS PROCESS (a) VARIABLE b : BIT; b := '1';

5 VHDL FOR i IN 0 TO 3 LOOP b := a(3-i) AND b; out1(i) <= b; END LOOP; END PROCESS; END example; 109 5-20 ENTITY while_stmt IS PORT (a: IN BIT_VECTOR (0 TO 3); out1: OUT BIT_VECTOR (0 TO 3)); END while_stmt; ARCHITECTURE example OF while_stmt IS PROCESS (a) VARIABLE b: BIT; VARIABLE i: INTEGER; i := 0; WHILE i < 4 LOOP b := a(3-i) AND b; out1(i) <= b; END LOOP; END PROCESS; END example; 5-20 WHILE_LOOP WHILE LOOP 5.2.4 NEXT NEXT LOOP NEXT NEXT LOOP -- -- NEXT LOOP WHEN -- LOOP NEXT LOOP NEXT LOOP LOOP LOOP LOOP WHEN NEXT TRUE NEXT

110 5 VHDL LOOP NEXT WHEN LOOP 5-21 5-21... L1 : FOR cnt_value IN 1 TO 8 LOOP s1 : a(cnt_value) := '0'; NEXT WHEN (b=c); s2 : a(cnt_value + 8 ):= '0'; END LOOP L1; 5-21 NEXT (b=c) TRUE NEXT L1 cnt_value 1 s1 s2 NEXT 5-22 5-22... L_x : FOR cnt_value IN 1 TO 8 LOOP s1 : a(cnt_value):= '0'; k := 0; L_y : LOOP s2 : b(k) := '0'; NEXT L_x WHEN (e>f); s3 : b(k+8) := '0'; k := k+1; NEXT LOOP L_y ; NEXT LOOP L_x ; e>f TRUE NEXT L_x L_x cnt_value 1 s1 FALSE s3 k 1 5.2.5 EXIT EXIT NEXT LOOP EXIT EXIT EXIT LOOP -- -- EXIT LOOP WHEN -- 5.2.4 NEXT NEXT LOOP LOOP LOOP LOOP EXIT LOOP LOOP NEXT LOOP EXIT LOOP

5 VHDL 5-22 a b EXIT 5-23 SIGNAL a, b : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL a_less_then_b : Boolean;... a_less_then_b <= FALSE ; -- FOR i IN 1 DOWNTO 0 LOOP IF (a(i)='1' AND b(i)='0') THEN a_less_then_b <= FALSE ; -- a > b EXIT ; ELSIF (a(i)='0' AND b(i)='1') THEN a_less_then_b <= TRUE ; -- a < b EXIT; ELSE NULL; END IF; END LOOP; -- i=1 LOOP NULL ELSE a b 1 TRUE FALSE a b 111 5.3 WAIT ( ) WAIT (Suspension) WAIT WAIT WAIT ON -- -- WAIT UNTIL -- WAIT FOR -- ( 0 1 1 0 ) 5-24 WAIT 5-24 SIGNAL s1,s2 : STD_LOGIC;... PROCESS

112... WAIT ON s1,s2 END PROCESS 5 VHDL WAIT s1 s2 PROCESS VHDL WAIT WAIT (1) (2) WAIT 5-25 (a) (b) 5-25 (a) WAIT_UNTIL (b) WAIT_ON... LOOP Wait until enable ='1'; Wait on enable;... EXIT WHEN enable ='1'; END LOOP; 5-25 enable 1 enable 0 enable WAIT_UNTIL ( VHDL ) WAIT_UNTIL WAIT UNTIL =Value -- (1) WAIT UNTIL EVENT AND =Value; -- (2) WAIT UNTIL NOT STABLE AND =Value; -- (3) clock WAIT ( 5.7 ) WAIT UNTIL clock ='1'; WAIT UNTIL rising_edge(clock) ; WAIT UNTIL NOT clock STABLE AND clock ='1'; WAIT UNTIL clock ='1' AND clock EVENT; 5-26 a 4 4

5-26... PROCESS WAIT UNTIL clk ='1'; ave <= a; WAIT UNTIL clk ='1'; ave <= ave + a; WAIT UNTIL clk ='1'; ave <= ave + a; WAIT UNTIL clk ='1'; ave <= (ave + a)/4 ; END PROCESS ; 5 VHDL 113 5-27 LOOP WAIT 5-27 PROCESS rst_loop : LOOP WAIT UNTIL clock ='1' AND clock EVENT; -- NEXT rst_loop WHEN (rst='1'); -- rst x <= a ; -- WAIT UNTIL clock ='1' AND clock EVENT; -- NEXT rst_loop When (rst='1'); -- rst y <= b ; -- END LOOP rst_loop ; END PROCESS; 5-27 rst WAIT 5-28 4 DATA(0 TO 3) NEW_CORRECT_PARITY PARITY_OK 5-28 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL; ENTITY Pari IS PORT( CLOCK : IN STD_LOGIC; SET_PARITY : IN STD_LOGIC; NEW_CORRECT_PARITY : IN STD_LOGIC; DATA : IN STD_LOGIC_VECTOR(0 TO 3); PARITY_OK : OUT BOOLEAN ); END Pari;

114 5 VHDL ARCHITECTURE behav OF Pari IS SIGNAL CORRECT_PARITY : STD_LOGIC; PROCESS(CLOCK) VARIABLE TEMP : STD_LOGIC; IF CLOCK EVENT AND CLOCK ='1' THEN IF SET_PARITY ='1' THEN First: CORRECT_PARITY <= NEW_CORRECT_PARITY; END IF; TEMP := '0'; FOR I IN DATA RANGE LOOP TEMP := TEMP XOR DATA(i); END LOOP; Second PARITY_OK <= (TEMP = CORRECT_PARITY); END IF; END PROCESS; END behav; 5-28 5-6 RTL 5-28 NEW_CORRECT_PARITY SET_PARITY 5-7 WAIT D CORRECT_PARITY First PARITY_OK Second TEMP TEMP NEW_CORRECT_PARITY SET_PARITY D0 Q0 FD11 MUX21 A B O S DATA[0] DATA[3] DATA[1] DATA[2] CLOCK D0 Q0 FD11 PARITY_OK 5-7 5-28 RTL 5-29 VHDL 8 5-29 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;

115 5 VHDL ENTITY shifter IS PORT ( data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); shift_left: IN STD_LOGIC; shift_right: IN STD_LOGIC; clk: IN STD_LOGIC; reset : IN STD_LOGIC; mode : IN STD_LOGIC_VECTOR (1 DOWNTO 0); qout : BUFFER STD_LOGIC_VECTOR (7 DOWNTO 0) ); END shifter; ARCHITECTURE behave OF shifter IS SIGNAL enable: STD_LOGIC; PROCESS WAIT UNTIL (RISING_EDGE(clk) ); -- IF (reset = '1') THEN qout <= "00000000"; ELSE CASE mode IS WHEN "01" => qout <= shift_right & qout(7 DOWNTO 1);-- WHEN "10" => qout <= qout(6 DOWNTO 0) & shift_left; -- WHEN "11" => qout <= data; -- WHEN OTHERS => NULL; END CASE; END IF; END PROCESS; END behave; WAIT 5.4 VHDL VHDL ( ) ( ) ( )

116 5 VHDL ( ) 1. [([ => ] { [ => ] }) ] (1) IN INOUT (2) (3) IN INOUT 5-30 5-8 swap ( ) swap 5-30 PACKAGE data_types IS -- SUBTYPE data_element IS INTEGER RANGE 0 TO 3 -- TYPE data_array IS ARRAY (1 TO 3) OF data_element; END data_types USE WORK.data_types.ALL; -- data_types ENTITY sort IS PORT ( in_array : IN data_array ; out_array : OUT data_array); END sort; ARCHITECTURE exmp OF sort IS PROCESS (in_array) -- data_types PROCEDURE swap(data : INOUT data_array; -- swap data low high low, high : IN INTEGER ) IS VARIABLE temp : data_element ; -- IF (data(low) > data(high)) THEN --

117 5 VHDL temp := data(low) ; data(low) := data(high); data(high) := temp ; END IF END swap ; -- swap VARIABLE my_array : data_array ; -- my_array -- my_array := in_array ; -- swap(my_array, 1, 2); -- my_array 1 2 data low high swap(my_array, 2, 3); -- 2 3 swap(my_array, 1, 2); -- 1 2 out_array <= my_array ; END Process ; END exmp ; [4:5] in_array[2:7] [2:3] [2:7] [6:7] swap_temp4 < < [1:0] [4:5] 0 [1:0] [2:3] 1 [1:0] [6:7] 0 1 [1:0] [1:0] < [1:0] [1:0] 0 [1:0] 1 [1:0] [1:0] out_array_1[1:0] out_array[2:7] [2:3] 0 [1:0] [1:0] [1:0] 0 1 [1:0] out_array_2[1:0] [4:5] 1 [1:0] swap_data_3[1:0] [6:7] [1:0] 0 1 [1:0] 5-8 5-30 RTL 5-31 5-31 ENTITY sort4 is GENERIC (top : INTEGER :=3); PORT (a, b, c, d : IN BIT_VECTOR (0 TO top); ra, rb, rc, rd : OUT BIT_VECTOR (0 TO top)); END sort4; ARCHITECTURE muxes OF sort4 IS PROCEDURE sort2(x, y : INOUT BIT_VECTOR (0 TO top)) is VARIABLE tmp : BIT_VECTOR (0 TO top); IF x > y THEN tmp := x; x := y; y := tmp; END IF; END sort2; PROCESS (a, b, c, d)

118 5 VHDL VARIABLE va, vb, vc, vd : BIT_VECTOR(0 TO top); va := a; vb := b; vc := c; vd := d; sort2(va, vc); sort2(vb, vd); sort2(va, vb); sort2(vc, vd); sort2(vb, vc); ra <= va; rb <= vb; rc <= vc; rd <= vd; END PROCESS; END muxes; 2 5.5 (RETURN) RETURN; RETURN -- -- END 5-31 RS REPORT 5-31 PROCEDURE rs (SIGNAL s, r : IN STD_LOGIC ; SIGNAL q, nq : INOUT STD_LOGIC) IS IF ( s ='1' AND r ='1') THEN REPORT "Forbidden state : s and r are quual to '1'"; RETURN ; ELSE q <= s AND nq AFTER 5 ns ; nq <= s AND q AFTER 5 ns ; END IF ; END PROCEDURE rs ; s r 1 IF RETURN

5 VHDL 5-32 opt opran opran a AND b a OR b 5-32 FUNCTION opt (a, b, opr :STD_LOGIC) RETURN STD_LOGIC IS IF (opr ='1') THEN RETURN (a AND b); ELSE RETURN (a OR b) ; END IF ; END FUNCTION opt ; opr a b rtn_valu 5-8 opt 119 5-8 rtn_valu 5.6 (NULL) NULL NULL CASE NULL 5-33 CASE NULL 5-33 CASE Opcode IS WHEN "001" => tmp := rega AND regb ; WHEN "101" => tmp := rega OR regb ; WHEN "110" => tmp := NOT rega ; WHEN OTHERS => NULL ; END CASE ; CPU "001" "101" "110" CPU EDA MAXPLUS II NULL

120 5 VHDL NULL WHEN OTHERS => tmp := rega ; 5.7 5.7.1 (ATTRIBUTE) VHDL VHDL h h h h h h VHDL ( ) VHDL ( ) 5-2 LEFT RIGHT HIGH LOW RANGE REVERS RANGE LENGTH EVENT STABLE ' 5-1 1. EVENT clock EVENT clock δ clock 0 1 1 0 IF BOOLEAN TRUE FALSE clock EVENT clock EVENT AND clock='1'

5 VHDL 5-2 LEFT[(n)] n RIGHT[(n)] n HIGH[(n)] n LOW[(n)] n LENGTH[(n)] ( ) n STRUCTURE[(n)] 'STURCTURE TRUE BEHAVIOR 'BEHAVIOR TRUE POS(value) value VAL(value) value SUCC(value) value PRED(value) value LEFTOF(value) value RIGHTOF(value) value EVENT TRUE FALSE ACTIVE TRUE FALSE LAST_EVENT LAST_VALUE LAST_ACTIVE DELAYED[(time)] STABLE[(time)] TRUE QUIET[(time)] TRUE TRANSACTION BIT ( 0 1 ) RANGE[(n)] n n REVERSE_RANGE[( n)] n n h 'LEFT 'RIGHT 'LENGTH 'LOW h 'POS 'VAL 'SUCC 'LEFTOF 'RIGHTOF h 'ACTIVE 'EVENT 'LAST_ACTIVE 'LAST_EVENT 'LAST_VALUE 121

122 5 VHDL h 'DELAYED 'STABLE 'QUIET 'TRANSACTION h 'RANGE 'REVERSE_RANGE clock clock TRUE δ clock 1 clock ='1' TRUE TRUE TRUE clock ='1' δ clock 0 clock 5-34 5-34 PROCESS (clock) IF (clock EVENT AND clock ='1' ) THEN Q <= DATA ; END IF ; END PROCESS; 5-34 VHDL IF TRUE Q <= DATA Q clock (clock EVENT AND clock ='0') STABLE EVENT TRUE (NOT clock STABLE AND clock ='1') (clock EVENT AND clock ='1') NOT(clock STABLE AND clock ='1') VHDL BIT clock 1 0 clock EVENT AND clock ='1' clock STD_LOGIC (clock='1') = TRUE δ clock '0' RISING EDGE (clock) RISING EDGE ( ) VHDL IEEE

IF RISING EDGE (clock) THEN 5 VHDL WAIT UNTIL RISING EDGE (clock) 123 EVENT STABLE VHDL EVENT IF WAIT 2 'RANGE[(n)] 'REVERSE RANGE[(n)] 5-2 RANGE REVERSE RANGE 5-35 5-35... SIGNAL range1 : IN STD LOGIC VECTOR (0 TO 7)... FOR i IN range1'range LOOP... 5-35 FOR LOOP FOR i IN 0 TO 7 LOOP range1 RANGE range1 REVERSE RANGE (7 DOWNTO 0) 3. VHDL LEFT RIGHT HIGH LOW 5-2 5-36... PROCESS (clock, a, b); TYPE obj IS ARRAY (0 TO 15) OF BIT ; SIGNAL ele1, ele2, ele3, ele4: INTEGER ; ele1 <= obj RIGNT ; ele2 <= obj LEFT ; ele3 <= obj HIGH ; ele4 <= obj LOW ;... ele1 ele2 ele3 ele4 0 15 0 15

124 5 VHDL 5-37 'LOW 'HIGH 5-9 5-9 5-37 LIBRARY IEEE;--PARITY GENERATOR USE IEEE.STD_LOGIC_1164.ALL; ENTITY parity IS GENERIC (bus_size : INTEGER := 8 ); PORT (input_bus : IN STD_LOGIC_VECTOR(bus_size-1 DOWNTO 0); even_numbits, odd_numbits : OUT STD_LOGIC ) ; END parity ; ARCHITECTURE behave OF parity IS PROCESS (input_bus) VARIABLE temp: STD_LOGIC; temp := '0'; FOR i IN input_bus'low TO input_bus'high LOOP temp := temp XOR input_bus( i ) ; END LOOP ; odd_numbits <= temp ; even_numbits <= NOT temp; END PROCESS; END behave; 4 LENGTH 5-38... TYPE arry1 ARRAY (0 TO 7) OF BIT VARIABLE wth: INTEGER;...

wth1: =arry1 LENGTH; -- wth1 = 8... 5 VHDL 125 5. ATTRIBUTE : ; ATTRIBUTE OF : IS ; VHDL EDA Synplify synplify.attributes LIBRARY synplify; USE synplicity.attributes.all; DATA I/O VHDL pinnum 5-39 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY cntbuf IS PORT( Dir: IN STD_LOGIC; Clk,Clr,OE: IN STD_LOGIC; A,B: INOUT STD_LOGIC_VECTOR (0 to 1); Q: INOUT STD_LOGIC_VECTOR (3 downto 0) ); ATTRIBUTE PINNUM : STRING; ATTRIBUTE PINNUM OF Clk: signal is "1"; ATTRIBUTE PINNUM OF Clr: signal is "2"; ATTRIBUTE PINNUM OF Dir: signal is "3"; ATTRIBUTE PINNUM OF OE: signal is "11"; ATTRIBUTE PINNUM OF A: signal is "13,12"; ATTRIBUTE PINNUM OF B: signal is "19,18"; ATTRIBUTE PINNUM OF Q: signal is "17,16,15,14"; END cntbuf; Synopsys FPGA Express synopsys.attributes VHDL 5.7.2 (TEXTIO) VHDL IC VHDL

126 5 VHDL VHDL VHDL STD.TEXTIO STD.TEXTIO VHDL VHDL ModelSim STD.TEXTIO type LINE is access string; type TEXT is file of string; type SIDE is (right, left); subtype WIDTH is natural; file input : TEXT open read_mode is "STD_INPUT"; file output : TEXT open write_mode is "STD_OUTPUT"; STD.TEXTIO READ READLINE WRITE WRITELINE VHDL STD.TEXTIO 5-40... component counter8 port ( CLK: in STD_LOGIC; RESET: in STD_LOGIC; CE, LOAD, DIR: in STD_LOGIC; D N: in INTEGER range 0 to 255; COUNT: out INTEGER range 0 to 255 ); end component;... file RESULTS: TEXT open WRITE_MODE is "results.txt";... procedure WRITE_RESULTS ( CLK : STD_LOGIC; RESET : STD_LOGIC; CE : STD_LOGIC; LOAD : STD_LOGIC; DIR : STD_LOGIC; DIN : INTEGER;

5 VHDL COUNT : INTEGER ) is variable V_OUT : LINE; begin -- write(v_out, now, right, 16, ps); write(v_out, CLK, right, 2); write(v_out, RESET, right, 2); write(v_out, CE, right, 2); write(v_out, LOAD, right, 2); write(v_out, DIR, right, 2); write(v_out, DIN, right, 257); -- write(v_out, COUNT, right, 257); writeline(results,v_out); end WRITE_RESULTS;... 127 8 VHDL WRITE_RESULTS results.txt 5.7.3 ASSERT ASSERT( ) VHDL ASSERT TRUE FALSE ASSERT REPORT SEVERITY [SEVERITY_LEVEL] 5-41 ASSERT NOT (S= '1' AND R= '1') REPORT "Both values of signals S and R are equal to '1'" SEVERITY ERROR; SEVERITY SEVERITY_LEVEL SEVERITY_LEVEL NOTE WARNING ERROR FAILURE ASSERT

128 5 VHDL ASSERT 5.7.4 REPORT REPORT ASSERT REPORT ; REPORT SEVERITY SEVERITY_LEVEL; 5-42 WHILE counter <= 100 LOOP IF counter > 50 THEN REPORT "the counter is over 50"; END IF;... END LOOP; VHDL 1993 REPORT ASSERT FALSE ASSERT 1987 REPORT 5.7.5 (Resolution) 5-43 package RES_PACK is function RES_FUNC(DATA: in BIT_VECTOR) return BIT; subtype RESOLVED_BIT is RES_FUNC BIT; end; package body RES_PACK is function RES_FUNC(DATA: in BIT_VECTOR) return BIT is begin for I in DATA'range loop if DATA(I) = '0' then return '0'; end if; end loop; return '1'; end; end; USE work.res_pack.all; ENTITY WAND_VHDL is PORT(X, Y: in BIT; Z: out RESOLVED_BIT); END WAND_VHDL;

5 VHDL ARCHITECTURE WAND_VHDL OF WAND_VHDL IS begin Z <= X; Z <= Y; end WAND_VHDL; 129 VHDL 5-1 3 VHDL 1 Signal A, EN : std_logic; Process (A, EN) Variable B : std_logic; Begin if EN = 1 then B <= A; end if; end process; 2 Architecture one of sample is variable a, b, c : integer; begin c <= a + b; end; 3 library ieee; use ieee.std_logic_1164.all; entity mux21 is port ( a, b : in std_logic; sel : in std_logic; c : out std_logic;); end sam2; architecture one of mux21 is begin if sel = '0' then c := a; else c := b; end if; end two; 5-2 1 2 5-3 (1) (2)

130 5 VHDL (3) ASSERT (4) VHDL (5) (6) 5-4 CASE IF 3-8 5-5 WAIT 5-6 5-10 f_adder cin cout VHDL 5-7 5 M1 M0 (M1 M0) (0 0) 19 (M1 M0) (0 1) 4 (M1 M0) (1 0) 10 (M1 M0) (1 1) 6 5-10 5-6

6 VHDL 131 6 VHDL VHDL VHDL 6-1 6-1 VHDL 6-1 h Concurrent Signal Assignments h (Process Statements) h (Block Statements)

132 VHDL h (Selected Signal Assignments h (Component Instantiations) h (Generate Statements) h (Concurrent Procedure Calls) ARCHITECTURE OF IS END ARCHITECTURE VHDL 6.1 VHDL VHDL VHDL VHDL

6 VHDL IF WAIT 6-1 4 in1(3 DOWNTO 0) 1 out1(3 DOWNTO 0) 1 6-1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt10 IS PORT clr : IN STD_LOGIC; in1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); out1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END cnt10 ARCHITECTURE actv OF cnt10 IS PROCESS in1 clr IF (clr ='1' OR in1 = "1001") THEN out1 <= "0000" ; -- 9 out1 0 ELSE -- 1 out1 <= in1 + 1 ;-- + + END IF -- STD_LOGIC_UNSIGNED END PROCESS ; END actv ; 133 in1[0] in1[1] in1[2] in1[3] clr NOT AND4 OR2 ADDER ADDER41 A0 S0 A1 S1 A2 S2 A3 S3 B0 VCC S0=0 : => Z[3..0] = A[3..0) S0=1 : => Z[3..0] = B[3..0] 1 0 A0 A1 A2 A3 B0 B1 B2 B3 S0 Z0 Z1 Z2 Z3 MUX42 out1[0] out1[1] out1[2] out1[3] 6-2 6-1 cnt10 6-1 6-2 ADDER 1 4 A(3 DOWNTO 0)+B0=S(3 DOWNTO 0) B0=1 MUX42 6-2 6-2 1 1

134 VHDL 6-2 6-1 WAIT 6-3 6-2 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt10 IS PORT ( clr : IN STD_LOGIC ; Clk : IN STD_LOGIC ; Cnt : Buffer STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END cnt10 ARCHITECTURE actv OF cnt10 IS PROCESS WAIT UNTIL clk'event AND clk = '1' ; -- clk IF ( clr ='1' OR cnt = 9 ) THEN cnt <= "0000" ; ELSE cnt <= cnt+ 1 ; END IF ; END PROCESS ; END actv ; D0 Q0 out1[0] clr NOT AND4 OR2 ADDER ADDER41 A0 S0 A1 S1 A2 S2 A3 S3 B0 VCC S0=0 : => Z[3..0] = A[3..0) S0=1 : => Z[3..0] = B[3..0] 1 0 A0 A1 A2 A3 B0 B1 B2 B3 S0 Z0 Z1 Z2 Z3 MUX42 FD11 D0 Q0 FD11 D0 Q0 FD11 D0 Q0 out1[1] out1[2] out1[3] clk FD11 6-3 cnt10 ( 4 D ) 6-2 6-3 6-2 4 D 1

6 VHDL 4 4 D BUFFER b1 a1 6-3 inc 4 NOR2 clk rst rst NOT NAND2 s0 clk current_state current_state 6-4 6-3 PACKAGE mtype IS TYPE state_t IS (s0, s1, s2, s3); -- END mtype; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE WORK.mtype.ALL; -- ENTITY s4_machine IS PORT(clk, inc, a1, b1 : IN STD_LOGIC ; rst : IN BOOLEAN ; out1: OUT STD_LOGIC) ; END ENTITY s4_machine; ARCHITECTURE activ OF s4_machine IS SIGNAL current_state, next_state: state_t ; sync: PROCESS(clk, rst) -- IF (rst) THEN -- current_state <= s0; ELSIF (clk EVENT AND clk ='1') THEN -- current_state <= next_state; END IF; END PROCESS sync; fsm: PROCESS(inc current_state, a1, b1) -- out1 <= a1; D_FF D D C C Q Q MUX21 S B A out1 NAND3 135 6-4 4

136 VHDL next_state <= s0; IF (inc = '1') THEN CASE current_state IS WHEN s0 => next_state <= s1; WHEN s1 => next_state <= s2; out1 <= b1; WHEN s2 => next_state <= s3; WHEN s3 => NULL ; END CASE; END IF; END PROCESS fsm; END activ; 6-4 3 3 3 6-4... a_out <= a WHEN (ena) ELSE 'Z' ; b_out <= b WHEN (enb) ELSE 'Z' ; c_out <= c WHEN (enc) ELSE 'Z' ; PRO1 PROCESS (a_out) bus_out <= a_out ; END PROCESS ; PRO2 PROCESS (b_out) bus_out <= b_out ; END PROCESS ; PRO3 PROCESS (c_out) bus_out <= c_out ; END PROCESS ;... 3 6-5 ena enb enc a b c 9 9- a_out OT11 b_out OT11 30 9-31 6-5 6-4 c_out OT11 bus_out

6 VHDL 137 6.2 a y b c z d 6-6 2 6-5 6-5... b1 : BLOCK SIGNAL s : BIT ; s <= a AND b ; b2 : BLOCK SIGNAL s : BIT ; s <= c AND d ; b3 : BLOCK z <= s ; END BLOCK b3 ; END BLOCK b2 ; y <= s ; END BLOCK b1; -- b1 -- b1 s -- b1 s -- b2 b1 -- b2 s -- b2 s -- s b2 -- s b1 6-6 2 3

138 VHDL 6.3 h h h 6.3.1 VHDL <= 6-6 6-6 ARCHITECTURE curt OF bc1 IS SIGNAL s1 : STD_LOGIC ; output1 <= a AND b ; output2 <= c + d ; B1 : BLOCK SIGNAL e, f, g, h : STD_LOGIC ; g <= e OR f ; h <= e XOR f ; END BLOCK B1 s1 <= g ; END ARCHITECTURE curt 6.3.2

<= WHEN ELSE WHEN ELSE... 6 VHDL 139 IF = TRUE IF ELSE WHEN CASE 5-9 5-2 6-7 6-7... z <= a WHEN p1 = '1' ELSE b WHEN p2 = '1' ELSE c ;... p1 p2 1 z a 6.3.3 WITH SELECT <= WHEN WHEN... WHEN CASE CASE CASE WITH CASE

140 VHDL 6-8 6-7 a b c data1 data2 dataout 6-8 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY decoder IS PORT ( a b c : IN STD_LOGIC; data1 data2 : IN STD_LOGIC; dataout : OUT STD_LOGIC ); END decoder; ARCHITECTURE concunt OF decoder IS SIGNAL instruction : STD_LOGIC_VECTOR(2 DOWNTO 0) instruction <= c & b & a ; WITH instruction SELECT dataout <= data1 AND data2 WHEN "000" data1 OR data2 WHEN "001" data1 NAND data2 WHEN "010" data1 NOR data2 WHEN "011" data1 XOR data2 WHEN "100" data1 XNOR data2 WHEN "101" 'Z' WHEN OTHERS ; END concunt ; a b c data1 6-9 data2 4 1 6-7 6-8 DECODER 6-9... WITH selt SELECT muxout <= a WHEN 0 1, -- 0 1 b WHEN 2 TO 5, -- 2 3 4 5 DECODER a b c d_out d1 d2 dataout

... 6 VHDL c WHEN 6, d WHEN 7, 'Z' WHEN OTHERS ; 141 6.4 6-10 6-10... PROCEDURE adder(signal a, b :IN STD_LOGIC ; -- adder SIGNAL sum : OUT STD_LOGIC );... adder(a1 b1 sum1) ; --... -- a1 b1 sum1 a b sum PROCESS( c1 c2) ; -- Adder(c1 c2 s1) ; -- c1 c2 s1 END PROCESS ; -- a b sum 1 0 6-11 check 1 check error TRUE 6-11 PROCEDURE check(signal a : IN STD_LOGIC_VECTOR; -- SIGNAL error : OUT BOOLEAN ) IS -- VARIABLE found_one : BOOLEAN := FALSE ; -- FOR i IN a'range LOOP -- a IF a(i) = '1' THEN -- a '1' IF found_one THEN -- found_one TRUE '1' ERROR <= TRUE; -- '1' found_one TRUE

142 VHDL RETURN; -- END IF; Found_one := TRUE; -- a '1' End IF; End LOOP; -- a error <= NOT found_one; -- '1' error TRUE END PROCEDURE check 6-12... CHBLK BLOCK SIGNAL s1: STD_LOGIC_VECTOR (0 TO 0); -- SIGNAL s2: STD_LOGIC_VECTOR (0 TO 1); SIGNAL s3: STD_LOGIC_VECTOR (0 TO 2); SIGNAL s4: STD_LOGIC_VECTOR (0 TO 3); SIGNAL e1, e2, e3, e4: Boolean; Check (s1, e1); -- s1 e1 Check (s2, e2); -- s2 e2 Check (s3, e3); -- s3 e3 Check (s4, e4); END BLOCK;... -- s4 e4 s2[1] s2[0] s3[0] s3[2] s3[1] e2 e3 s4[0] s4[1] s4[2] s4[3] s1[0] e4 e1 6-8 CHBLK 6-8

6 VHDL 143 6.5 VHDL VHDL FPGA Verilog IP FPGA IP COMPONENT IS GENERIC PORT END COMPONENT -- PORT MAP [ =>]... -- PORT MAP

144 VHDL => PORT MAP PORT MAP 6-13/14 u1 a x 2 b 6-9 u2 3 c y 6-13 d 6-13 6-9 ord41 6-13 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY nd2 IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC ); END nd2; ARCHITECTURE nd2behv OF nd2 IS y <= a NAND b; END nd2behv ; 6-14 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY ord41 IS PORT ( a1 b1 c1 d1 : IN STD_LOGIC; z1 : OUT STD_LOGIC ); END ord41; ARCHITECTURE ord41behv OF ord41 IS COMPONENT nd2 PORT ( a, b : IN STD_LOGIC ; c : OUT STD_LOGIC) ; END COMPONENT ; SIGNAL x, y : STD_LOGIC ; u1 : nd2 PORT MAP (a1, b1, x) ; -- u2 : nd2 PORT MAP (a => c1, c => y, b => d1); -- u3 : nd2 PORT MAP (x, y, c => z1) ; -- END ARCHITECTURE ord41behv u3 z

6 VHDL 6.6 145 GENERIC map PORT MAP( ) 3-5 6-15 PORT MAP( ) GENERIC 6-15 addern adders 6-10 addern addern 16 U1 U2 addern 8 6-10 6-15 LIBRARY IEEE; -- USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_arith.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; ENTITY addern IS PORT (a, b: IN STD_LOGIC_VECTOR; result: out STD_LOGIC_VECTOR); END addern; ARCHITECTURE behave OF addern IS result <= a + b; END; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_arith.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; ENTITY adders IS GENERIC(msb_operand: INTEGER := 15; msb_sum: INTEGER :=15); PORT(b: IN STD_LOGIC_VECTOR (msb_operand DOWNTO 0); result: OUT STD_LOGIC_VECTOR (msb_sum DOWNTO 0)); END adders; ARCHITECTURE behave OF adders IS COMPONENT addern PORT ( a, b: IN STD_LOGIC_VECTOR; result: OUT STD_LOGIC_VECTOR); END COMPONENT; SIGNAL a: STD_LOGIC_VECTOR (msb_sum /2 DOWNTO 0);

146 VHDL SIGNAL twoa: STD_LOGIC_VECTOR (msb_operand DOWNTO 0); twoa <= a & a; U1: addern PORT MAP (a => twoa, b => b, result => result); U2: addern PORT MAP (a=>b(msb_operand downto msb_operand/2 +1), b=>b(msb_operand/2 downto 0), result => a); END behave; 6-10 6-15 6.7 [ ] FOR IN GENERATE END GENERATE [ ] [ ] IF GENERATE Begin END GENERATE [ ] (1) FOR IF (2) (3) Copy

6 VHDL (4) FOR LOOP FOR LOOP 147 TO DOWNTO -- 1 TO 5 -- 5 DOWNTO 1 6-16 VHDL ATTRIBUTE RANGE 6-11 6-16... COMPONENT comp PORT (x : IN STD_LOGIC y : OUT STD_LOGIC ); END COMPONENT ; SIGNAL a, b : STD_LOGIC_VECTOR (0 TO 7)... gen : FOR i IN a RANGE GENERATE u1: comp PORT MAP (x => a(i) y => b(i) ) ; END GENERATE gen,... FOR_GENERATE 8 a[0] COMP INPUT OUTPUT b[0] a[1] a[7] COMP INPUT OUTPUT... COMP INPUT OUTPUT b[1] b[7] 6-12 74373 74373 6-11 8 74LS373/74HC373 74373 6-12 D1 D8 Q1 Q8 OEN

148 VHDL OEN=1 Q8 Q1 OEN=0 Q8~Q1 G G=1 D8 D1 74373 8 G=0 74373 8 74373 6-13 74373 1 Latch 2 2-2 latch.vhd 6-17 74373 6-17 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY SN74373 IS -- SN74373 PORT (D : IN STD_LOGIC_VECTOR( 8 DOWNTO 1 ); -- 8 OEN : IN STD_LOGIC; G : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(8 DOWNTO 1)); -- 8 END ENTITY SN74373; ARCHITECTURE one OF SN74373 IS COMPONENT Latch PORT ( D, ENA : IN STD_LOGIC; Q : OUT STD_LOGIC ); END COMPONENT; SIGNAL sig_mid : STD_LOGIC_VECTOR( 8 DOWNTO 1 ); GeLatch : FOR inum IN 1 TO 8 GENERATE -- 2-2 1 -- FOR_GENERATE -- 8 1 Latchx : Latch PORT MAP(D(iNum),G,sig_mid(iNum)); -- END GENERATE; Q <= sig_mid WHEN OEN =0 ELSE -- "ZZZZZZZZ"; -- OEN=1 Q(8)~Q(1) END ARCHITECTURE one; ARCHITECTURE two OF SN74373 IS SIGNAL sigvec_save : STD_LOGIC_VECTOR(8 DOWNTO 1); PROCESS(D, OEN, G sigvec_save) IF OEN = '0' THEN Q <= sigvec_save; ELSE Q <= "ZZZZZZZZ"; END IF; IF G = '1' THEN Sigvec_save <= D; END IF; END PROCESS; END ARCHITECTURE two 6-17 -- IF (1)

6 VHDL VHDL two ARCHITECTURE two ARCHITECTURE one 2-2 ENTITY Latch (2) COMPONENT 2-2 ENTITY Latch VHDL COMPONENT COMPONENT Latch Latch one COMPONENT VHDL VHDL Latch (3) FOR_GENERATE GeLatch inum 1~8 8 (4) Latchx : Latch PORT MAP ( D(iNum), G, sig_mid(inum) ); inum D2 D Q Latchx Latch D D(iNum) ENA G Q sig_mid(inum) inum 1~8 Latch 1~8 8 8 Latch D(1)~D(8) sig_mid(1) ~sig_mid(8) 8 Latch 6-17 one 6-12 D7 D D8 D FOR_GENERATE OEN D LATCH D Q ENA LATCH LATCH D Q ENA LATCH D Q ENA LATCH LATCH D1 D3 D4 D5 D6 G FOR_GENERATE 6-18 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY d_ff IS PORT ( d, clk_s : IN STD_LOGIC ; q : OUT STD_LOGIC ; ENA LATCH D Q ENA LATCH D ENA ENA ENA Q Q Q OT11 OT11 OT11 OT11 OT11 OT11 OT11 OT11 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 149 6-13 SN74373

150 VHDL nq : OUT STD_LOGIC ); END ENTITY d_ff; ARCHITECTURE a_rs_ff OF d_ff IS bin_p_rs_ff : PROCESS(CLK_S) IF clk_s = '1' AND clk_s'event THEN q <= d ; nq <= NOT d; END IF; END PROCESS; END ARCHITECTURE a_rs_ff; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY cnt_bin_n is GENERIC (n : INTEGER := 4); PORT (q : OUT STD_LOGIC_VECTOR (0 TO n-1); in_1 : IN STD_LOGIC ); END ENTITY cnt_bin_n; ARCHITECTURE behv OF cnt_bin_n IS COMPONENT d_ff PORT(d, clk_s : IN STD_LOGIC; Q, NQ : OUT STD_LOGIC); END COMPONENT d_ff; SIGNAL s : STD_LOGIC_VECTOR(0 TO n); s(0) <= in_1; q_1 : FOR i IN 0 TO n-1 GENERATE dff : d_ff PORT MAP (s(i+1), s(i), q(i), s(i+1)); END GENERATE; END ARCHITECTURE behv; q0 q1 i=0 i=1 D0 Q0 D0 Q0 clk clk s(0) FD11 s(1) nq... qn-1 i=n-1 D0 Q0 clk FD11 FD11 s(2) s(n) nq nq 6-14 n IF_GENERATE IF_GENERATE FOR_GENERATE

6 VHDL 6-14 n n D n FOR_GENERATE IF_GENERATE 6-18 VHDL 6-1 CASE WITH_SELECT 6-2 WHEN_ELSE PROCESS a b c d IF a= '0' AND b='1' THEN next1 <= "1101" ELSIF a='0' THEN next1 <= d ELSIF b='1' THEN next1 <= c ELSE Next1 <= "1011" END IF END PROCESS 6-3 VHDL ARCHITECTURE one OF com1 VARIABLE a b c clock STD_LOGIC ; pro1 PROCESS IF NOT clock ' EVENT AND clock = '1' THEN x <= a xor b or c END IF; END PROCESS; END; 6-4 VHDL WITH_SELECT_WHEN 4 16 1 16 4 1 6-5 STD_LOGIC_UNSIGNED 6-6 6-7 1 VHDL (1) 1 1 6-15 h_suber diff s_out sub_in (2) 6-1 (3) 1 8 ( x y - sun_in = diffr) 151

152 VHDL 6-15 6-7 6-1 X y sub_in diffr sub_out 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 6-8 6-15 3 D VHDL 6-15 6-8

7 VHDL 153 7 VHDL VHDL VHDL RTL RTL VHDL 7.1 VHDL 7-1 8 VHDL 7-2 8 ABEL-HDL 7-1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY cunter_up IS PORT( reset, clock : IN STD_LOGIC; counter : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END; ARCHITECTURE behv of cunter_up IS

154 VHDL SIGNAL cnt_ff: UNSIGNED(7 DOWNTO 0); PROCESS (clock,reset,cnt_ff) IF reset='1' THEN cnt_ff <= X"00" ; ELSIF (clock='1' AND clock'event) THEN cnt_ff <= cnt_ff + 1 ; END IF; END PROCESS; counter <= STD_LOGIC_VECTOR(cnt_ff); END ARCHITECTURE behv 7-2 MODULE counter_up Clock,reset, PIN ; Counter7..counter0 PIN ISTYPE 'COM' ; Cnt_ff7..cnt_ff0 NODE ISTYPE 'REG' ; Counter = [counter7..counter0]; Cnt = [cnt_ff7..cnt_ff0]; EQUATIONS Cnt.CLK = clock ; Cnt.AR = reset ; Cnt := cnt.fb + 1 ; Counter = cnt ; END counter_up 7-1 7-2 8 7-2 ABEL-HDL 8 'REG' 8 'COM' cnt.clk = clcok CLK cnt 8 clock cnt.ar = reset reset cnt AR cnt := cnt.fb + 1.FB 1 cnt 7-2 PLD ABEL 7-1

7 VHDL ABEL- HDL ELSIF (clock ='1' AND clock EVENT) THEN VHDL VHDL 7-2 cnt.clk=clock ABEL-HDL VHDL VHDL VHDL VHDL VHDL VHDL Verilog-HDL RTL VHDL VHDL VHDL VHDL VHDL VHDL Cadence Synplicity Synopsys Viewlogic EDA VHDL 155 7.2 RTL RTL RTL VHDL RTL

156 VHDL 7-3 7-3 ENTITY \74LS18\ IS PORT( I0_A, I0_B, I1_A, I1_B, I2_A : IN STD_LOGIC; I2_B I3_A I3_B : IN STD_LOGIC; O_A : OUT STD_LOGIC; O_B : OUT STD_LOGIC ); END \74LS18\; ARCHITECTURE model OF \74LS18\ IS O_A <= NOT ( I0_A AND I1_A AND I2_A AND I3_A ) AFTER 55 ns ; O_B <= NOT ( I0_B AND I1_B AND I2_B AND I3_B ) AFTER 55 ns ; END model; 7.3 VHDL VHDL VHDL 7-4 ARCHITECTURE STRUCTURE OF COUNTER3 IS COMPONENT DFF PORT(CLK, DATA: IN BIT; Q: OUT BIT); END COMPONENT; COMPONENT AND2 PORT(I1, I2: IN BIT; O: OUT BIT); END COMPONENT; COMPONENT OR2 PORT(I1, I2: IN BIT; O: OUT BIT);

7 VHDL END COMPONENT; COMPONENT NAND2 PORT(I1, I2: IN BIT; O: OUT BIT); END COMPONENT; COMPONENT XNOR2 PORT(I1, I2: IN BIT; O: OUT BIT); END COMPONENT; COMPONENT INV PORT(I: IN BIT; O: OUT BIT); END COMPONENT; SIGNAL N1, N2, N3, N4, N5, N6, N7, N8, N9: BIT; u1: DFF PORT MAP(CLK, N1, N2); u2: DFF PORT MAP(CLK, N5, N3); u3: DFF PORT MAP(CLK, N9, N4); u4: INV PORT MAP(N2, N1); u5: OR2 PORT MAP(N3, N1, N6); u6: NAND2 PORT MAP(N1, N3, N7); u7: NAND2 PORT MAP(N6, N7, N5); u8: XNOR2 PORT MAP(N8, N4, N9); u9: NAND2 PORT MAP(N2, N3, N8); COUNT(0) <= N2; COUNT(1) <= N3; COUNT(2) <= N4; END STRUCTURE; 157 VHDL VHDL VHDL EDA EDA VHDL EDA EDA VHDL 7-1 VHDL 7-2 VHDL 7-3 VHDL 7-4 2 8

158 VHDL 8 Simulation VHDL VHDL EDA FPGA VHDL VHDL VHDL VHDL EDA SRAM FPGA VHDL VHDL VHDL 12 13 8.1 VHDL VHDL EDA

8 159 VHDL VHDL VHDL VHDL VHDL VHDL (1) DEBUG ModelSim Active-VHDL VHDL (2) C VHDL 8-1 8-1 VHDL VHDL VHDL VHDL VHDL Mentor Graphics Renoir Xilinx Foundation Series EDA VHDL VHDL VHDL VHDL VHDL

160 VHDL VHDL VHDL LIBRARY USE VHDL VHDL VHDL FPGA/CPLD PLD VHDL VHDL VHDL VHDL VHDL VHDL VHDL REPORT ASSERT VHDL EDA VHDL VHDL MAX+PLUSII SNF PC VHDL Model Technology ModelSim Aldec Active-VHDL ModelSim V-System/ Windows Windows 8-1 VHDL EDA MAX+PLUSII EPF10K10LC84 MAX+PLUSII SNF VHDL 8-2 EPF10K10LC84 8-2 VHDL 8-1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY and1 IS PORT(aaa,bbb : IN STD_LOGIC; ccc: OUT STD_LOGIC); END and1; ARCHITECTURE one OF and1 IS ccc <= aaa AND bbb; END;

8 161 8-2 LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY TRIBUF_and1 IS GENERIC ( ttri: TIME := 1 ns; ttxz: TIME := 1 ns; ttzx: TIME := 1 ns); PORT ( in1 : IN std_logic; oe : IN std_logic; y : OUT std_logic); END TRIBUF_and1; ARCHITECTURE behavior OF TRIBUF_and1 IS PROCESS (in1, oe) IF oe'event THEN IF oe = '0' THEN y <= TRANSPORT 'Z' AFTER ttxz; ELSIF oe = '1' THEN y <= TRANSPORT in1 AFTER ttzx; END IF; ELSIF oe = '1' THEN y <= TRANSPORT in1 AFTER ttri; ELSIF oe = '0' THEN y <= TRANSPORT 'Z' AFTER ttxz; END IF; END PROCESS; END behavior; LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE work.tribuf_and1; ENTITY and1 IS PORT ( aaa : IN std_logic; bbb : IN std_logic; ccc : OUT std_logic); END and1; ARCHITECTURE EPF10K10LC84_a3 OF and1 IS SIGNAL gnd : std_logic; SIGNAL vcc : std_logic; SIGNAL n_8, n_9, n_10, n_11, n_12, a_a4_aout, n_14, n_15, n_16, n_17, n_18, n_20, n_22 : std_logic; COMPONENT TRIBUF_and1 GENERIC (ttri, ttxz, ttzx: TIME); PORT (in1, oe : IN std_logic; y : OUT std_logic); END COMPONENT;

162 VHDL gnd <= '0'; vcc <= '1'; PROCESS(aaa, bbb) ASSERT aaa /= 'X' OR Now = 0 ns REPORT "Unknown value on aaa" SEVERITY Warning; ASSERT bbb /= 'X' OR Now = 0 ns REPORT "Unknown value on bbb" SEVERITY Warning; END PROCESS; TRIBUF_2: TRIBUF_and1 GENERIC MAP (ttri => 2600 ps, ttxz => 4500 ps, ttzx => 4500 ps) PORT MAP (IN1 => n_8, OE => vcc, Y => ccc); DELAY_3: n_8 <= TRANSPORT n_9; XOR2_4: n_9 <= n_10 XOR n_14; OR1_5: n_10 <= n_11; AND1_6: n_11 <= n_12; DELAY_7: n_12 <= TRANSPORT a_a4_aout AFTER 2500 ps; AND1_8: n_14 <= gnd; DELAY_9: a_a4_aout <= TRANSPORT n_15 AFTER 500 ps; XOR2_10: n_15 <= n_16 XOR n_22; OR1_11: n_16 <= n_17; AND2_12: n_17 <= n_18 AND n_20; DELAY_13: n_18 <= TRANSPORT bbb AFTER 4800 ps; DELAY_14: n_20 <= TRANSPORT aaa AFTER 4300 ps; AND1_15: n_22 <= gnd; END EPF10K10LC84_a3; VHDL VHDL VHDL 8.2 VHDL VHDL FPGA/CPLD VHDL FPGA/CPLD FPGA/CPLD VHDL 8-2 VHDL

8 163 8.2.1 VHDL δ δ VHDL VHDL δ VHDL z <= x XOR y AFTER 5ns 5ns x XOR y 5ns x XOR y 5ns z x y z <= x XOR y x XOR y δ z FPGA/CPLD VHDL 8.2.2 VHDL PCB ASIC z <= TRANSPORT x AFTER 10 ns; TRANSPORT

164 VHDL AFTER 8.3 d VHDL δ δ δ δ 8.4 VHDL TEXTIO VHDL 4 4 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADDER4 IS PORT ( a, b : IN INTEGER RANGE 0 TO 15; c : OUT INTEGER RANGE 0 TO 15 ); END ADDER4; ARCHITECTURE one OF ADDER4 IS c <= a + b; END one;

8 165 h VHDL ENTITY SIGGEN IS PORT ( sig1 : OUT INTEGER RANGE 0 TO 15; sig2 : OUT INTEGER RANGE 0 TO 15 ); END; ARCHITECTURE Sim OF SIGGEN IS sig1 <= 10, 5 AFTER 200 ns, 8 AFTER 400 ns; sig2 <= 3, 4 AFTER 100 ns, 6 AFTER 300 ns; END; 8-2 ModelSim SIGGEN ADDER4 VHDL 8-2 SIGGEN ENTITY BENCH IS END; ARCHITECTURE one OF BENCH IS COMPONENT ADDER4 PORT ( a, b : integer range 0 to 15; c : OUT INTEGER RANGE 0 TO 15 ); END COMPONENT; COMPONENT SIGGEN PORT ( sig1 : OUT INTEGER RANGE 0 TO 15; sig2 : OUT INTEGER RANGE 0 TO 15 ); END COMPONENT; SIGNAL a, b, c : INTEGER RANGE 0 TO 15; U1 : ADDER4 PORT MAP (a, b, c); U2 : SIGGEN PORT MAP (sig1=>a, sig2=>b); END; a b c ModelSim 8-3 h

166 VHDL ModelSim force force force < > < > [< >][, < > < > ] [-repeat < >] force a 0 force b 0 0, 1 10 8-3 BENCH 0 b 0 0 10 1 force clk 0 0, 1 15 repeat 20 clk 20 ADDER4 ModelSim force a 10 0, 5 200, 8 400 force b 3 0, 4 100, 6 300 Run Run 500 8-3 ModelSim 12 VHDL 8.5 VHDL VHDL Test Bench VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL Test Bench VHDL /

8 167 8.4 VHDL VHDL 8 Library IEEE; use IEEE.std_logic_1164.all; entity counter8 is port CLK CE LOAD DIR RESET: in STD_LOGIC; DIN: in INTEGER range 0 to 255; COUNT: out INTEGER range 0 to 255 ); end counter8; architecture counter8_arch of counter8 is begin process (CLK, RESET) variable COUNTER: INTEGER range 0 to 255; begin if RESET='1' then COUNTER := 0; elsif CLK='1' and CLK'event then if LOAD='1' then COUNTER := DIN; Else if CE='1' then if DIR='1' then if COUNTER =255 then COUNTER := 0; Else COUNTER := COUNTER + 1; end if; else if COUNTER =0 then COUNTER := 255; Else COUNTER := COUNTER - 1; end if; end if; end if; end if; end if; COUNT <= COUNTER; end process; end counter8_arch; Entity testbench is end testbench; Architecture testbench_arch of testbench is File RESULTS: TEXT open WRITE_MODE is "results.txt"; Component counter8 port ( CLK: in STD_LOGIC; RESET: in STD_LOGIC; CE, LOAD, DIR: in STD_LOGIC; DIN: in INTEGER range 0 to 255; COUNT: out INTEGER range 0 to 255 );

168 VHDL end component; shared variable end_sim : BOOLEAN := false; signal CLK, RESET, CE, LOAD, DIR: STD_LOGIC; signal DIN: INTEGER range 0 to 255; signal COUNT: INTEGER range 0 to 255; procedure WRITE_RESULTS ( CLK CE LOAD LOAD RESET : STD_LOGIC; DIN COUNT : INTEGER ) is Variable V_OUT : LINE; Begin write(v_out, now, right, 16, ps); -- write(v_out, CLK, right, 2); write(v_out, RESET, right, 2); write(v_out, CE, right, 2); write(v_out, LOAD, right, 2); write(v_out, DIR, right, 2); write(v_out, DIN, right, 257); --write outputs write(v_out, COUNT, right, 257); writeline(results,v_out); end WRITE_RESULTS; begin UUT: COUNTER8 port map (CLK => CLK,RESET => RESET, CE => CE, LOAD => LOAD, DIR => DIR, DIN => DIN, COUNT => COUNT ); CLK_IN: process Begin if end_sim = false then CLK <= '0'; Wait for 15 ns; CLk <='1'; Wait for 15 ns; Else Wait; end if; end process; STIMULUS: process Begin RESET <= '1'; CE <= '1'; -- DIR <= '1'; -- DIN <= 250; -- LOAD <= '0'; -- wait for 15 ns; RESET <= '0'; wait for 1 us; CE <= '0'; -- wait for 200 ns; CE <= '1';

8 169 wait for 200 ns; DIR <= '0'; wait for 500 ns; LOAD<= '1'; wait for 60 ns; LOAD <= '0'; wait for 500 ns; DIN <= 60; DIR <= '1'; LOAD<= '1'; wait for 60 ns; LOAD<= '0'; wait for 1 us; CE <= '0'; wait for 500 ns; CE <= '1'; wait for 500 ns; end_sim :=true; wait; end process; WRITE_TO_FILE: WRITE_RESULTS(CLK,RESET,CE,LOAD,DIR,DIN,COUNT); End testbench_arch; 8-4 8 8-4 Active-VHDL 8.6 VHDL VHDL VHDL PLI

170 VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL 8051 PIC16C5X 80386 VHDL IP PCI 8-5 89C51 VHDL VHDL VHDL VHDL PSPICE VHDL PSPICE PSPICE VHDL VHDL VHDL VHDL Internet FSF VHDL 8-1 8-2 δ 8-3 VHDL VHDL 8-4 VHDL 8-5 VHDL

9 171 9 VHDL Synthesis VHDL FPGA/CPLD ASIC EDA VHDL VHDL VHDL VHDL VHDL VHDL 16 16 PLD 1 VHDL VHDL VHDL 9.1 VHDL EDA VHDL VHDL / /

172 VHDL VHDL VHDL Speed Area Density VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL EDA VHDL VHDL FPGA/CPLD EDA MAX+PLUSII HDL HDL / VHDL

9 VHDL VHDL VHDL VHDL VHDL VHDL IEEE EDA VHDL VHDL EDA EDA Synopsys Design Compiler FPGA Express FPGA CompilerII Synplicity Synplify Candence Synergy Mentor Graphics AutologicII DATA I/O Synario Viewlogic Workview Office Altera MAX+plusII VHDL FPGA Express Synopsys FPGA/CPLD VHDL/Verilog FPGA/CPLD FPGA/CPLD VHDL EDIF EDIF EDA PLD EDA EDIF 200 VHDL ADDER4.VHD FPGA Express isplsi1032 Export EDIF ADDER4.EDF Lattice ISPDS+ FPGA/CPLD EDIF EDA VHDL EDIF V CC GND MAX+plusII EDIF EDA Lattice ISPDS+ 5.0 Altera EDIF MAX+plusII Lattice MAX+plusII EDA EDIF Lattice EDA Altera FPGA Express Synplify EDIF Workview Office EDIF VHDL VHDL 173

174 VHDL 9.2 VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL 32 VHDL VHDL VHDL VHDL / CPLD FPGA VHDL EDA

9 9.3 175 VHDL VHDL 1 WAIT IF h h IF_THEN IF_THEN_ELSE h h IF IF h IF True h IF ELSE ELSIF 9.3.1 (1) 9-1 9-1 PROCESS (clk_a, clk_b) IF (clk_a'event AND clk_a ='1' ) THEN a <= b;

176 VHDL END IF; IF (clk_b'event AND clk_b ='1' ) THEN c <= b; END IF; END PROCESS; -- (2) 9-2 ELSE 9-2 PROCESS (clock) IF(clock'EVENT AND clock ='1') THEN sig <= b; ELSE sig <= c; -- END IF; END PROCESS; ELSE sig <= c; (3) IF 9-3 9-3 PROCESS (clock) VARIABLE edge_var, any_var: BIT; IF (clock'event AND clock ='1') THEN edge_signal <= x; -- edge_var := y; -- any_var := edge_var; -- END IF; any_var := edge_var; -- END PROCESS; (4) IF NOT(clock'EVENT AND clock ='1') THEN... (5) 9-4 IF ELSE gate data 9-4 PROCESS (gate,data) IF (gate = '1') THEN q <= data; END IF; END PROCESS;

9 177 (6) 9-5 9-5 FUNCTION my_func(data, gate : BIT) RETURN BIT IS VARIABLE s1: BIT; IF (gate = '1') THEN s1 := data; END IF; RETURN s1; END;... q <= my_func (data, gate);... (7) 9-6 I B A H 9-1 9-6 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT ( CLK,C,J,K : IN STD_LOGIC; A,H : OUT STD_LOGIC ); END EXAP ; ARCHITECTURE behav OF EXAP IS SIGNAL I,B : STD_LOGIC; PROCESS (CLK) IF ( CLK'EVENT AND CLK='1') THEN B <= C; A <= B; H <= I; I <= J XOR K; END IF; END PROCESS ; END behav; 9-7 9-2 9-7 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT (CLK,C,J,K : IN STD_LOGIC; A,H : OUT STD_LOGIC ); END EXAP ;

178 VHDL ARCHITECTURE behav OF EXAP IS SIGNAL I,B : STD_LOGIC; PROCESS (CLK) IF ( CLK'EVENT AND CLK='1') THEN B <= C; I <= J XOR K; END IF; END PROCESS ; A <= B; H <= I; END behav; J K D I Q D H Q H J K D H Q H CLK C CLK D B Q D A Q A C D A Q A 9-1 9-6 9-2 9-7 (8) 9-8 9-8 x <= '1'; IF x='1' x 9-8 9-3 9-8 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT ( clk,a,b : IN STD_LOGIC; y : OUT STD_LOGIC ); END EXAP ; ARCHITECTURE behav OF EXAP IS SIGNAL x : STD_LOGIC; PROCESS WAIT UNTIL CLK ='1' ; x <= '0'; y <= '0'; IF a = b THEN x <= '1';

179 9 END IF; IF x='1' THEN y <= '1' ; END IF ; END PROCESS ; END behav; 9-8 x x 9-4 9-9 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT ( clk,a,b : IN STD_LOGIC; y : OUT STD_LOGIC ); END EXAP ; ARCHITECTURE behav OF EXAP IS PROCESS VARIABLE x : STD_LOGIC; WAIT UNTIL CLK ='1' ; x := '0'; y <= '0'; IF a = b THEN x := '1'; END IF; IF x='1' THEN y <= '1' ; END IF ; END PROCESS ; END behav; a a=b D Q D Q y a a=b D Q y b b CLK CLK 9-3 9-8 9-4 9-9

180 VHDL 9.3.2 IF_THEN WAIT PROCESS (clk) IF clk='1' THEN y <= a; ELSE END IF; END PROCESS; -- VHDL y y ABEL-HDL ABEL-HDL ELSE 0 9-10 9-10 PROCESS (clk) IF clk='1' THEN y <= a; ELSE y <= b; END IF; END PROCESS; 9-10 2 1 IF IF CASE 9-11 PROCESS (clk) IF clk='1' THEN ELSE y <= a; END IF; END PROCESS; 9-12 PROCESS (clk) IF clk='0' THEN -- --

y <= a; END IF; END PROCESS; 9 -- 181 9-13 clk'event AND clk='1' 9-13 PROCESS (clk) IF clk'event AND clk='1' THEN y <= a; END IF; END PROCESS; 9-14 STD_LOGIC rising_edge( ) 9-14 SIGNAL clk STD-LOGIC... PROCESS (clk) IF rising_edge(clk) THEN y <= a; END IF; END PROCESS; WAIT 9-15 WAIT a y y 9-15 PROCESS WAIT UNTIL clk'event AND clk='1' y <= a; END PROCESS; VHDL WAIT WAIT 9-16 IF 9-16 PROCESS (clk, a, b) IF clk='1' THEN y <= a AND b; END IF; END PROCESS;

182 VHDL 9-17 IF 9-17 ARCHITECTURE dataflow OF latch IS PROCEDURE my_latch( SIGNAL clk,a,b : IN Boolean; SIGNAL y : OUT Boolean) IF clk='1' THEN y <= a AND b; END IF; END; Latch_1: my_latch (clock,input1,input2,outputa); Label_2: my_latch (clock,input1,input2,outputb); END dataflow; 9-18 Y 9-18 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT ( b, a : IN STD_LOGIC; clk : BOOLEAN; Y1 : OUT STD_LOGIC ); END EXAP ; ARCHITECTURE behav OF EXAP IS SIGNAL Y : STD_LOGIC; Y <= a AND b WHEN clk ELSE Y; Y1 <= Y ; END behav; clk='1' AND clk 'EVENT 9-5 9-18 9-19 9-18 ELSE 9-19

9 ARCHITECTURE concurrent OF my_register IS Y <= a AND b WHEN clk='1' AND clk'event; END concurrent; 183 9-18 1076-1993 VHDL 1076-1987 9.3.3 9-20 9-6 9-6 9-20 9-20 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT (clk,d : IN STD_LOGIC; ena : IN BOOLEAN; -- ena q1 : OUT STD_LOGIC ); END EXAP ; ARCHITECTURE behav OF EXAP IS SIGNAL q : STD_LOGIC; PROCESS(clk,ena) IF (clk='1' AND clk'event) AND ena THEN q <= d; END IF; q1 <= q ; END PROCESS; END behav; 9-21 9-21 IF clk='1' AND clk'event THEN IF ena THEN -- ena

184 VHDL q <= d; END IF; END IF; 9.3.4 9-22 9-7 9-22 PROCESS(clk) IF clk='1' AND clk'event THEN IF set='1' THEN y <= '1'; -- '1' TRUE ELSE y <= a AND b; END IF; END IF; END PROCESS; set/reset / reset='0' FALSE y TRUE/FALSE / 9.3.5 9-7 9-22 9-8 9-23

9 VHDL / / PLD 9-23 9-23 -- BOOLEAN LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT (clk,reset : IN STD_LOGIC; a,b : IN BOOLEAN; Y1 OUT BOOLEAN ); END EXAP ; ARCHITECTURE behav OF EXAP IS SIGNAL Y : BOOLEAN; PROCESS (clk,reset) IF reset='1' THEN y <= FALSE; ELSIF clk='1' AND clk'event THEN y <= a AND b; END IF; END PROCESS; Y1 <= Y; END behav; VHDL PLD VHDL 9-24 185 9-9 9-24 9-24 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT (clk,reset,preset : IN STD_LOGIC; a,b : IN STD_LOGIC; Y1 : OUT STD_LOGIC ); END EXAP ; ARCHITECTURE behav OF EXAP IS

186 VHDL SIGNAL Y :STD_LOGIC; PROCESS (clk, reset, preset) IF reset='1' THEN y <='0'; -- 0 ELSIF preset='1' THEN y <='1'; ELSIF rising_edge(clk) THEN y <= a AND b; END IF; END PROCESS; Y1 <= Y; END behav; 9-24 9-9 -- 1 9-24 9-23 9-24 9.4 9-25 9-25 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.All; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY exmp IS PORT ( clock, reset : IN STD_LOGIC; and_b, or_b, nor_b : OUT STD_LOGIC ); END exmp; ARCHITECTURE rtl OF exmp IS PROCESS VARIABLE count : STD_LOGIC_VECTOR(2 DOWNTO 0); WAIT UNTIL clock'event AND clock ='1'; IF (reset = '1') THEN count := "000"; ELSE count := count + 1; END IF; and_b <= count(2) AND count(1) AND count(0); or_b <= count(2) OR count(1) OR count(0); nor_b <= count(2) XOR count(1) XOR count(0); END PROCESS; END rtl;

9 9-25 3 9-10 6 D 3 count count 3 9-25 3 WAIT 187 D0 Q0 and_b clock FD11 D0 Q0 or_b D0 Q0 FD11 D0 Q0 FD11 D0 Q0 FD11 nor_b reset FD11 D0 Q0 FD11 B A S max21 9-10 9-25 3 WAIT IF 9-26 WAIT 9-26 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.All; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY exmp IS PORT( clock, reset : IN STD_LOGIC; and_b, or_b, xor_b : OUT STD_LOGIC); END exmp; ARCHITECTURE rtl OF exmp IS SIGNAL count : STD_LOGIC_VECTOR(2 DOWNTO 0); PROCESS -- WAIT UNTIL clock'event AND clock ='1'; IF (reset = '1') THEN Count <= "000"; ELSE Count <= count + 1; END IF; END PROCESS; PROCESS(count) --

188 VHDL and_b <= count(2) AND count(1) AND count(0); or_b <= count(2) OR count(1) OR count(0); xor_b <= count(2) XOR count(1) XOR count(0); END PROCESS; END rtl; D0 Q0 and_b I3 reset FD11 B A S D0 Q0 or_b D0 Q0 FD11 xor_b clock FD11 9-11 9-26 9-11 9-26 3 9-26 IF WAIT IF WAIT 9-27 cond a(0) a (1) a (2) a (4) 4 output cond a 4 9-27 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.All; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY exmp IS PORT ( clk : IN STD_LOGIC; cond : IN INTEGER RANGE 0 TO 3; a : IN STD_LOGIC_VECTOR(0 to 3); output : OUT STD_LOGIC); END exmp; ARCHITECTURE activ OF exmp IS SIGNAL s_cond : INTEGER RANGE 0 TO 3;

9 PROCESS WAIT UNTIL clk'event AND clk ='1'; s_cond <= cond; END PROCESS; PROCESS (a, s_cond) output <= a(s_cond); END PROCESS; END activ; 189 9-12 9-27 9-28 p1 p2 temp temp l_b 9-12 9-27 a p1 p2 D Q D Q q temp l_b 9-13 9-28 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.All; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY latch2 IS PORT(p1, p2, a : IN STD_LOGIC; q : OUT STD_LOGIC ); 9-13 9-28

190 VHDL END latch2; ARCHITECTURE activ OF latch2 IS SIGNAL temp, l_b: STD_LOGIC; PROCESS(p1, a, l_b) IF (p1 = '1') THEN temp <= a AND l_b; -- END IF; END PROCESS; PROCESS(p2, temp) IF(p2 = '1') THEN l_b <= NOT temp; -- END IF; END PROCESS; q <= l_b; END activ; 9.5 6 6-4 FPGA/CPLD CPU VHDL Lattice 1000 2000 isplsi Xilinx FPGA Z 9-29 1 9-29... IF (condition) THEN out_val <= in_val; ELSE out_val <= 'Z'; -- Z END IF;... Z Z RETURN out_val <= 'Z' AND in_val

IF in_val = 'Z' THEN... 9 191 IF FALSE THEN... 'Z' VHDL 'Z' VHDL 'Z' STD_LOGIC 'Z' s_a < = 'Z'; s_b < = 'z'; -- -- 'Z' IEEE STD_LOGIC 9-14 9-30 4 IF IF 9-30 9-14 9-14 4 OT11 8 IF IF 9-30 IF IF 9-31 4 WHEN-ELSE 9-14 9-31 9-30 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;

192 VHDL ENTITY tristate2 IS port ( input3, input2, input1, input0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); output : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END tristate2 ; ARCHITECTURE multiple_drivers OF tristate2 IS PROCESS(enable,input3, input2, input1, input0 ) IF enable(3) = '1' THEN output <= input3 ; ELSE output <=(OTHERS => 'Z'); END IF ; IF enable(2) = '1' THEN output <= input2 ; ELSE output <=(OTHERS => 'Z'); END IF ; IF enable(1) = '1' THEN output <= input1 ; ELSE output <=(OTHERS => 'Z'); END IF ; IF enable(0) = '1' THEN output <= input0 ; ELSE output <=(OTHERS => 'Z'); END IF ; END PROCESS; END multiple_drivers; 9-31 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY tristate2 IS port ( input3, input2, input1, input0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); output : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END tristate2 ; ARCHITECTURE multiple_drivers OF tristate2 IS output <= input3 WHEN enable(3) = '1' ELSE (OTHERS => 'Z'); output <= input2 WHEN enable(2) = '1' ELSE (OTHERS => 'Z'); output <= input1 WHEN enable(1) = '1' ELSE (OTHERS => 'Z'); output <= input0 WHEN enable(0) = '1' ELSE (OTHERS => 'Z'); END multiple_drivers; 9-32 9-32 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY tris IS port ( three_s,clk, input : IN STD_LOGIC; cnd : IN BOOLEAN ; output : OUT STD_LOGIC );

9 END tris ; ARCHITECTURE mul OF tris IS PROCESS(three_s,clk, input ) IF (three_s = '0') THEN output <= 'Z'; ELSIF (clk ='1' AND clk'event) THEN IF (cnd) THEN output <= input; END IF; END IF; END PROCESS; END mul; 193 9-15 9-32 9-32 9-15 9-15 9-33 three_s temp 9-16 9-33 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY latch_3s IS PORT( clk, three_s, input : IN STD_LOGIC ; output : OUT STD_LOGIC; cnd : IN BOOLEAN ); END latch_3s; ARCHITECTURE activ OF latch_3s IS SIGNAL temp: STD_LOGIC; PROCESS(clk, cnd, input) IF (clk ='1' AND clk EVENT) THEN IF (cnd) THEN temp <= input; END IF;

194 VHDL END IF; END PROCESS; PROCESS(three_s, temp) IF (three_s = '0') THEN output <= 'Z'; ELSE output <= temp; END IF; END PROCESS; END ARCHITECTURE activ; 9-34 three_s cnd 9-17 input clk INOUT enable OT11 -- 9-34 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY bidir IS PORT (input_val, enable, other_sig : IN STD_LOGIC; output_val : OUT STD_LOGIC; bidir_port : INOUT STD_LOGIC) ; END bidir ; ARCHITECTURE tri_state OF bidir IS bidir_port <= input_val WHEN enable = '1' ELSE 'Z'; output_val <= bidir_port XOR other_sig ; END tri_state; B A S MUX21 D Q D_FF I1 OT11 output 9-16 9-33 9-17 9-34 9.6 VHDL

9 Area Optimize Or Density Optimize 9-35 9-36 9-18 9-19 9-35 9-36 9-36 9-35 9-35 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY SHARE IS PORT(A,B,C,D :IN STD_LOGIC_VECTOR (3 DOWNTO 0); SEL : IN STD_LOGIC ; OPUT : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END SHARE ; ARCHITECTURE BEHAVE OF SHARE IS SIGNAL OUT1 : STD_LOGIC_VECTOR (3 DOWNTO 0); PROCESS (A,B,C,D,SEL) IF (SEL='1') THEN OUT1 <= A+B; ELSE OUT1 <= C+D ; END IF; OPUT <= OUT1; END PROCESS; END BEHAVE ; 9-36 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY SHARE IS PORT(A,B,C,D :IN STD_LOGIC_VECTOR (3 DOWNTO 0); SEL : IN STD_LOGIC ; OPUT : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END SHARE ; ARCHITECTURE BEHAVE OF SHARE IS SIGNAL OUT1,F,G : STD_LOGIC_VECTOR (3 DOWNTO 0); PROCESS (A,B,C,D,SEL) IF (SEL='1') THEN F <= A; G <=B; ELSE F <= C ;G <=D; END IF; OPUT <= F+G; END PROCESS; 195

196 VHDL END BEHAVE ; VHDL VHDL 9-35 9-19 SEL SEL C[3:0] D[3:0] + 0 OPUT[3:0] C[3:0] A[3:0] 0 1 f[3:0] + OPUT[3:0] 1 A[3:0] B[3:0] + OPUT[3:0] D[3:0] B[3:0] 0 1 g[3:0] 9-18 9-35 9-19 9-36 9-1 VHDL VHDL 9-2 9-3 VHDL 9-4 FPGA CPLD VHDL 9-5 7 LED ( ) 4 0 1 14 15 7 0 1 9 A B C D E F 9-6 16 9-7 RS T JK VHDL 9-8 8 9-20 (1) [d7..d0] : 8 (2) dataout 9-20 9-8

(3) datain 9 (4) clock (5) clken (6) clr (7) s/l 9-1 4014 dataout(0)~ dataout(7) 0 dataout 7 dataout = dataout 7 Clken Clock Datai clr s/l n 9-1 8 d0 d n dataout 0 dataout n 1 X 0 1 0 1 0 1 X 0 1 1 1 0 1 X 0 1 0 0 1 1 X 0 1 1 1 1 1 0 0 0 X 0 dataout n 1 1 1 0 0 X 1 dataout n 1 1 X 0 X X dataout 0 dataout n X X X 1 X X 0 0 0 X X 0 X X 197 9-8

198 VHDL 10 FSM VHDL VHDL CPU h VHDL h h VHDL h VHDL CPU CPU CPU h CPU CPU CPU CPU h CPU CPU CPU 2 ns CPU

10 FSM 199 ms 10.1 Mealy Moore VHDL 1 TYPE ARCHITECTURE ARCHITECTURE...IS TYPE states IS (st0, st1, st2, st3); -- SIGNAL current_state, next_state: states; --...... ; 2 next_state current_state next_state 3 next_state next_state

200 4 VHDL 5 3 4 10-1 REG COM 10-1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY s_machine IS PORT ( clk,reset : IN STD_LOGIC; state_inputs : IN STD_LOGIC_VECTOR (0 TO 1); comb_outputs : OUT STD_LOGIC_VECTOR (0 TO 1) ); END s_machine; ARCHITECTURE behv OF s_machine IS TYPE states IS (st0, st1, st2, st3); -- states SIGNAL current_state, next_state: states; REG PROCESS (reset,clk) -- IF reset = '1' THEN current_state <= st0; -- ELSIF clk='1' AND clk'event THEN current_state <= next_state; -- END IF; END PROCESS; -- current_state COM COM PROCESS(current_state, state_inputs) -- CASE current_state IS -- WHEN st0 => comb_outputs <= "00"; -- "00" IF state_inputs = "00" THEN -- "00" next_state <= st0; -- REG st0 ELSE next_state <= st1; -- REG st1 END IF; WHEN st1 => comb_outputs <= "01";-- st1 "01" IF state_inputs = "00" THEN -- "00" next_state <= st1; -- REG st1 ELSE next_state <= st2; -- REG st2 END IF;

10 FSM 201 WHEN st2 => comb_outputs <= "10"; -- IF state_inputs = "11" THEN next_state <= st2; ELSE next_state <= st3; END IF; WHEN st3 => comb_outputs <= "11"; IF state_inputs = "11" THEN next_state <= st3; ELSE next_state <= st0; -- REG st0 END IF; END case; END PROCESS; -- next_state REG END behv; reset state_inputs clk PROCESS REG 10-2 AD574 comb_outputs REG REG st0 st1 st2 st3 state_inputs REG current_state COM current_state state_inputs REG FSM: next_state s_machine current_state PROCESS COM 10-1 s_machine 10-1 AD574 X comb_outputs CE CS RC K12/8 A0 0 X X X X X 1 X X X 1 0 0 X 0 12 1 0 0 X 1 8 state_inputs 1 0 1 1 X 12 1 0 1 0 0 8 1 0 1 0 1 4 4 0

202 VHDL 10-1 current_state REG COM next_state COM REG 3 clk reset 10-1 current_state next_state VHDL 10-1 PROCESS REG CLK current_state next_state CS I.C. : AD574 A0 RC K12/8 STSTUS D[11:0] FSM: AD574 PROCESS COM LOCK PROCESS LATCH Q[11:0] 10-3 AD574 10-2 A/D AD574 AD574 10-2 10-3 10-1 10-1 LATCH 12 REGL COM AD574 6 LOCK st3 st4 10-2 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY AD574 IS PORT (D :IN STD_LOGIC_VECTOR(11 DOWNTO 0); --AD574 CLK,STATUS : IN STD_LOGIC; --CLK STATUS CS,A0,RC,K12/8 : OUT STD_LOGIC; --CS A0 12 A/D 12 --RC A/D K12/8 12 8 Q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));-- A/D END AD574; ARCHITECTURE behav OF AD574 IS TYPE states IS (st0, st1, st2, st3,st4,st5); -- SIGNAL current_state, next_state: states :=st0 ; SIGNAL REGL : STD_LOGIC_VECTOR(11 DOWNTO 0);--A/D

10 FSM 203 SIGNAL LOCK : STD_LOGIC; -- K12/8 <= '1'; -- 12 COM: PROCESS(current_state,STATUS) -- CASE current_state IS WHEN st0 => CS<='1';A0<='0';RC<='0';LOCK<='0'; next_state <= st1;--ad574 st0 st1 WHEN st1=> CS<='0';A0<='0';RC<='0';LOCK<='0'; next_state <= st2; -- 12 WHEN st2=> CS<='0';A0<='0';RC<='0';LOCK<='0'; IF (STATUS='1') THEN next_state <= st2; -- ELSE next_state <= st3; -- END IF ; WHEN st3=> CS<='0';A0<='0';RC<='1';LOCK<='0'; next_state <= st4; -- RC 12 WHEN st4=> CS<='0';A0<='0';RC<='1';LOCK<='1'; next_state <= st5; -- WHEN st5=> CS<='1';A0<='1';RC<='1';LOCK<='0'; next_state <= st0; -- AD574 WHEN OTHERS => next_state <= st0; -- END CASE ; END PROCESS COM ; REG PROCESS (CLK) IF ( CLK'EVENT AND CLK='1') THEN current_state <= next_state; -- CLK END IF; END PROCESS REG; -- current_state COM LATCH PROCESS (LOCK) -- LOCK 12 REGL IF LOCK='1' AND LOCK'EVENT THEN REGL <= D ; END IF; END PROCESS ; Q <= REGL; -- REGL Q END behav; 10-3 3 REG FUNC1 FUNC2 10-3 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY system IS PORT (clock: IN STD_LOGIC; a: IN STD_LOGIC; d: OUT STD_LOGIC); END system; ARCHITECTURE moore OF system IS SIGNAL b, c: STD_LOGIC;

204 VHDL -- 1 FUNC1: PROCESS (a, c) b <= FUNC1(a, c); -- c END PROCESS; FUNC2: PROCESS (c) d <= FUNC2(c); END PROCESS; REG: PROCESS (clock) IF clock='1' AND clock'event THEN c <= b; -- b END IF; END PROCESS; END moore; -- 2 -- D FUNC2 -- 10-4 10-3 FUNC2 10-4 10-3 2 2 FSMs OE START ALE EOC RST PROCESS COM ADC ADC_NEXT_STATE ADC_CURRENT_STATE PROCESS REG AD_STATE PROCESS REG DATA_LOCK 8 DIN ENABLE CLK ADC_END ADC_DATA 8 ADDRES_CNT CLK PROCESS REG RAM_NEXT_STATE PROCESS COM 13 PROCESS REG WRIT_STATE RAM_CURRENT_STATE RAM_WRITE COUNTER CS ADDRESS RAM_DIN RD ADDA 13 8 1 1 ADDRES_PLUS 10-5 10-4 FPGA/CPLD

10 FSM 205 FUNC1 FUNC2 10-4 FPGA CPLD ADC0809 SRAM 6264 6 ( 10-5 ) 1 ADC0809 ADC AD_STATE DATA_LOCK ADC RST ST0 ENABLE 6264 A/D ST2 A/D START ST4 EOC 0 1 ST5 OE LOCK DATA_LOCK 0809 8 ADC_DATA ST7 A/D ADC_END 6264 AD_STATE 2 SRAM 6264 WRIT_STATE RAM_WRITE COUNTER WRIT_STATE AD_STATE WRIT_STATE ADC START_WRITE (ADDRES_CNT = "1111111111111") A/D ENABLE=0 RST ADDRES_CNT A/D ENABLE=1 WRITE1 A/D ADC_END=1 SRAM WRITE2 ADDRES_CNT 13 ADC_DATA 8 6264 ADC_DATA WRITE3 WR=0 6264 A/D COUNTER RST WRITE_END A/D CLK A/D A/D ENABLE A/D ADC_END LOCK ADDRES_PLUS ADC WRIT_STATE DATA_LOCK COUNTER 10-5 10-4 9-7 ISPEXPERT MAXPLUS-II EDA 10-4 LIBRARY IEEE;

206 VHDL USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SRAM IS PORT ( --ADC0809 DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);--0809 CLK,EOC: IN STD_LOGIC; --CLK EOC RST: IN STD_LOGIC; -- ALE: OUT STD_LOGIC; -- 0809 START: OUT STD_LOGIC; -- 0809 OE: OUT STD_LOGIC; -- 0809 ENABLE PIN 9 ADDA: OUT STD_LOGIC; --0809 --SRAM 6264 CS: OUT STD_LOGIC; --6264 RD,WR: OUT STD_LOGIC; --6264 / RAM_DIN: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --6264 ADDRESS: OUT STD_LOGIC_VECTOR(12 DOWNTO 0));-- END SRAM ; ARCHITECTURE behav OF SRAM IS --A/D TYPE AD_STATES IS (ST0, ST1, ST2, ST3, ST4,ST5,ST6,ST7) ; TYPE WRIT_STATES IS (START_WRITE,WRITE1, WRITE2, WRITE3, WRITE_END); --SRAM SIGNAL RAM_CURRENT_STATE, RAM_NEXT_STATE: WRIT_STATES ; SIGNAL ADC_CURRENT_STATE, ADC_NEXT_STATE: AD_STATES ; --0809 SIGNAL ADC_END : STD_LOGIC; SIGNAL LOCK : STD_LOGIC; -- SIGNAL ENABLE : STD_LOGIC; -- A/D SIGNAL ADDRES_PLUS: STD_LOGIC; --SRAM 1 -- SIGNAL ADC_DATA: STD_LOGIC_VECTOR(7 DOWNTO 0); --SRAM SIGNAL ADDRES_CNT: STD_LOGIC_VECTOR(12 DOWNTO 0); ADDA <= '1'; -- ADDA=1 ADDB=0 ADDC=0 A/D IN-1 RD <= '1'; -- SRAM,,RD -- ADC0809 --A/D ADC: PROCESS(ADC_CURRENT_STATE,EOC,ENABLE,RST) IF (RST='1') THEN ADC_NEXT_STATE <= ST0; -- ELSE CASE ADC_CURRENT_STATE IS WHEN ST0 => ALE<='0'; START<='0'; OE<='0'; LOCK<='0'; ADC_END<='0'; --A/D IF (ENABLE='1') THEN ADC_NEXT_STATE<=ST1;-- ELSE ADC_NEXT_STATE <= ST0; -- END IF; WHEN ST1 => ALE<='1'; START<='0'; OE<='0';

10 FSM 207 LOCK<='0'; ADC_END<='0'; ADC_NEXT_STATE <= ST2; -- WHEN ST2 => ALE<='1'; START<='1'; OE<='0'; LOCK<='0'; ADC_END<='0'; ADC_NEXT_STATE <= ST3; -- A/D START WHEN ST3 => ALE<='1'; START<='1'; OE<='0'; LOCK<='0'; ADC_END<='0'; -- IF (EOC='0') THEN ADC_NEXT_STATE <= ST4; ELSE ADC_NEXT_STATE <= ST3; -- END IF ; WHEN ST4 => ALE<='0'; START<='0'; OE<='0'; LOCK<='0'; ADC_END<='0'; IF (EOC='1') THEN ADC_NEXT_STATE<=ST5;-- ELSE ADC_NEXT_STATE <= st4; -- END IF ; WHEN ST5 => ALE<='0'; START<='1'; OE<='1'; LOCK<='0'; ADC_END<='0'; ADC_NEXT_STATE <= ST6; -- OE WHEN ST6 => ALE<='0'; START<='0'; OE<='1'; LOCK<='1'; ADC_END<='1'; ADC_NEXT_STATE <= ST7; -- WHEN ST7 => ALE<='0'; START<='0'; OE<='1'; LOCK<='1'; ADC_END<='1'; ADC_NEXT_STATE <= ST0; -- 6264 A/D WHEN OTHERS => ADC_NEXT_STATE<=ST0; -- END CASE ; END IF END PROCESS ADC ; AD_STATE: PROCESS (CLK) --A/D IF ( CLK'EVENT AND CLK='1') THEN ADC_CURRENT_STATE <= ADC_NEXT_STATE;-- END IF; END PROCESS AD_STATE ; -- current_state DATA_LOCK: PROCESS (LOCK) -- LOCK ADC_DATA IF LOCK='1' AND LOCK'EVENT THEN ADC_DATA <= DIN ; END IF; END PROCESS DATA_LOCK; -- SRAM WRIT_STATE: PROCESS (CLK,RST) -- SRAM IF RST='1' THEN RAM_CURRENT_STATE <= START_WRITE;-- ELSIF ( CLK'EVENT AND CLK='1') THEN RAM_CURRENT_STATE <= RAM_NEXT_STATE; -- END IF; END PROCESS WRIT_STATE ; RAM_WRITE:PROCESS(RAM_CURRENT_STATE,ADC_END, ADDRES_CNT, ADC_DATA) --SRAM

208 VHDL CASE RAM_CURRENT_STATE IS WHEN START_WRITE => CS<='1'; WR <='1';ADDRES_PLUS<='0' ; IF (ADDRES_CNT = "1111111111111") -- THEN ENABLE <='0'; --SRAM A/D RAM_NEXT_STATE <= START_WRITE ; ELSE ENABLE <='1'; --SRAM A/D RAM_NEXT_STATE <= WRITE1 ; END IF; WHEN WRITE1 => CS<='1'; WR <='1'; ENABLE <='1'; ADDRES_PLUS<='0' ; -- A/D IF (ADC_END='1') THEN RAM_NEXT_STATE <= WRITE2;-- ELSE RAM_NEXT_STATE <= WRITE1 ; -- A/D END IF ; WHEN WRITE2 => CS<='0'; WR <='1'; -- SRAM ENABLE <='0'; -- A/D ADDRES_PLUS<='0' ; ADDRESS<=ADDRES_CNT ; -- 13 RAM_DIN <= ADC_DATA; -- 8 SRAM RAM_NEXT_STATE <= WRITE3; -- WHEN WRITE3 => CS<='0'; WR <='0'; -- ENABLE <='0'; -- A/D ADDRES_PLUS<='1'; -- 1 1 RAM_NEXT_STATE <= WRITE_END; -- WHEN WRITE_END => CS<='1'; WR <='1'; ENABLE <='1'; -- A/D ADDRES_PLUS <='0'; -- 1 RAM_NEXT_STATE <= START_WRITE; -- WHEN OTHERS => RAM_NEXT_STATE <= START_WRITE; END CASE ; END PROCESS RAM_WRITE; COUNTER: PROCESS(ADDRES_PLUS, RST) -- 1 IF (RST='1') THEN ADDRES_CNT <= (OTHERS=>'0' ;-- ELSIF ( ADDRES_PLUS'EVENT AND ADDRES_PLUS='1') THEN ADDRES_CNT <= ADDRES_CNT + 1; END IF; END PROCESS COUNTER; END behav; 10-4 SRAM

10 FSM 209 IF-THEN-ELSE IF-THEN-ELSE IF clk='1' THEN y <= a; END IF; clk='0' Y ELSE IF clk='1' THEN y <= a; ELSE Y<=b END IF; ELSE IF current_state =st0 THEN a <= '1'; ELSIF current_state =st1 THEN b <= '1'; ELSE c <= '1'; --current_state =st2 END IF; st0 st2 st3 a b c st0 st2 st3 a b c st0 st1 st2 a b c 3 a <= '0'; b <= '0'; c <= '0'; IF current_state =st0 THEN a <= '1'; ELSIF current_state =st1 THEN b <= '1'; ELSE c <= '1'; END IF; VHDL VHDL

210 VHDL VHDL VHDL 10.2 1 AD574 10-2 CS A0 RC LK1 LK2 STATE0 1 1 1 0 0 STATE1 0 0 0 0 0 STATUS=0 STATE2 STATE2 0 0 1 0 0 AD574 8 STATE3 0 0 1 1 0 LK1 8 STATE4 0 1 1 0 0 AD574 4 STATE5 0 1 1 0 1 LK2 4 10-1 AD574 10-2 6 STATE0 STATE5 11100 00000 00100 00110 01100 01101 8 4 LK1 LK2 10-5 10-5 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY AD574 IS PORT ( D : IN STD_LOGIC_VECTOR(11 DOWNTO 0); CLK,STATUS : IN STD_LOGIC; CS,A0,RC,K128 : OUT STD_LOGIC; LK1 LK2 : OUT STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); END AD574; ARCHITECTURE behav OF AD574 IS

10 FSM 211 SIGNAL CRURRENT_STATE,NEXT_STATE: STD_LOGIC_VECTOR(4 DOWNTO 0 ); CONSTANT STATE0 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11100" ; CONSTANT STATE1 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000" ; CONSTANT STATE2 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00100" ; CONSTANT STATE3 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00110" ; CONSTANT STATE4 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "01100" ; CONSTANT STATE5 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "01101" ; SIGNAL REGL : STD_LOGIC_VECTOR(11 DOWNTO 0); SIGNAL LOCK : STD_LOGIC;... 2 6 3 10-6... SIGNAL CRURRENT_STATE,NEXT_STATE: STD_LOGIC_VECTOR(2 DOWNTO 0 ); CONSTANT ST0 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000" ; CONSTANT ST1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001" ; CONSTANT ST2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010" ; CONSTANT ST3 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011" ; CONSTANT ST4 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100" ; CONSTANT ST5 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "101" ;... FPGA CS A0 RC LK1 LK2 10-3 3 STATE0 100000 000 STATE1 010000 001 STATE2 001000 010 STATE3 000100 011 STATE4 000010 100 STATE5 000001 101 10-7 10-7... SIGNAL CRURRENT_STATE,NEXT_STATE: STD_LOGIC_VECTOR(1 DOWNTO 0 ); CONSTANT ST0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00" ; CONSTANT ST1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01" ; CONSTANT ST2 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11" ;

212 VHDL CONSTANT ST3 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10" ;... 4 onehot encoding n n 1 0 6 6 10-3 FPGA CPLD FPGA/CPLD VHDL 10.3 10-4 st0 000 st1 001 st2 010 st3 011 st4 100 10-2 6 st5 101 st0 st1 st2 st3 st4 st5 undefined1 110 undefined2 111 3 8 10-4 2 6 10-2 10-8 10-8... TYPE states IS (st0, st1, st2, st3 undefined1 undefined2 undefined3 undefined4); SIGNAL current_state, next_state: states;...

10 FSM 213 COM PROCESS(current_state, state_inputs) -- CASE current_state IS --... WHEN OTHERS => next_state <= st0; END case; 10-8 OTHERS st0 10-5 6 58 64 n m = 2 n 1 '1' '0' 1 '1' '1' '1' alarm 10-2 6 10-9 10-9... alarm <= (st0 AND (st1 OR st2 OR st3 OR st4 OR st5)) OR (st1 AND (st0 OR st2 OR st3 OR st4 OR st5)) OR (st2 AND (st0 OR st1 OR st3 OR st4 OR st5)) OR (st3 AND (st0 OR st1 OR st2 OR st4 OR st5)) OR (st4 AND (st0 OR st1 OR st2 OR st3 OR st5)) OR (st5 AND (st0 OR st1 OR st2 OR st3 OR st4)) ; 10-1 VHDL ( 1110010) 1 0 I/O xi zo xi

214 VHDL 1110010 zo 1 1 11 111 1110 11100 111001 1110010 8 10-2 a b output clk 5 S0 S1 S2 S3 S4 [b a]=0 clk 1 [b a]=1 clk 1 [b a]=2 0 [b a]=3 S0 1 (1) (2) VHDL (3) VHDL (4) VHDL 10-3 10-4 SRAM 6264 13 13.17 10-4 10-2 10-5 10-6 10-7 VHDL a /="010" b='1' st0 a = "010" st1 lock <= '0' out1<="001" a='1' AND b='1' AND c='1' b='0' lock <='0' out1<="010" lock<='0' out1<="000" c='0' st2 st4 c='1' lock<='0' out1<="111" st3 lock<='1' out1<="100" 10-7 10-6

11 215 EDA FPGA/CPLD DSP FPGA VHDL FIR IIR 11.1 FPGA FFT DSP DSP FIR 5-6 8 8 FIR 11-1 FPGA DSP FIR DSP 8 FIR FPGA MSPS ASIC FIR MIPS 8 104 832 30 8 16 101 1616 8 FIR 24 103 2472 32 105 3360 FIR FPGA

216 VHDL FPGA 32 8 FIR 100 11-1 1 FIR 2 FPGA Million Samples Per Second MSPS) 3 DSP FPGA DSP Million Instructions Per Second MIPS FPGA 8 8 FIR 104MSPS DSP 832MIPS DSP 100MIPS DSP DSP DSP 32 11-1 FPGA FIR 11-1 16 8 FIR 11-1 16 8 FIR 50-MHz DSP 133-MHz CPU 50-MHz DSP 4 50-MHzCPU DSP EPF8820A-2 3/4 EPF81500A-2 3/5 ALTERA FPGA 8000 FPGA FPGA EPF81500A-2 DSP 67 11-2 11-2 11-2 FPGA DSP 1/3 133-MHz CPU 3.0 50-MHz DSP 2.8 FPGA EPF8820A-2 1.0 11-1 16 8 FIR

11 11.2 FIR 217 FIR / H N 1 n= 0 ( z) = h( n) z n y N 1 ( n) h( m) x( n m) = m= 0 ( ) ( ) x n h n n x ( n) 1 z 1 z 1 z 1 z 1 z h ( 0) h ( 1) h ( 2) h ( 3) h ( 4) h ( N 2) h ( N 1) y( n) y( n) n ( ) 11-2 h n h n ( ) ( M n) h( n) h = = n,,, M M y M ( n) h( k) x( n k) = k =0

218 VHDL ( n) x 1 z 1 z 1 z 1 z 1 z 1 z 1 z 1 z M 1 M M M = k 0 2 2 M 2 h( k ) x( n k) + h x n + h( k) x( n k) = k = + 1 2 M 1 M 1 M M = k= 0 2 2 k = 0 2 2 h( k ) x( n k) + h x n + h( M k) x( n M + k) y M 1 2 M k = 0 2 M 2 ( n) h( k) [ x( n k) + x( n M + k) ] + h x n = M ( n) h ( 0) h ( 1) h ( 2) h ( 3) h ( M 2 1) h( M 2) y ( n) 11-3 x 1 z 1 z 1 z 1 z 1 z 1 z 1 z 1 z 1 z y( n) h ( 0) h ( 1) h ( 2) h ( 3) h [( M 3) 2] h[ ( M 1) 2] 11-4 y ( M 1) 2 ( n) h( k )[ x( n k) + x( n M + k) ] = k= 0

11 H d ( e jω ) N 1 ( ) ( ) n= 0 jω H e = h n e ( ) jωn jω ( ) H e d jω H e n h d jω jωn ( n) H d ( e ) e dω 1 = 2 π π π d h d ( ) ( H e jω ) ( n) d h d ( h n) h( n) 219 ( h d n) ( ) n ω n h d ( ) h d ( n) h ( n) ω( n) h ( n) = d ω( n) = R ( n) N 1 2 n π 2 N 1 ( ω n) = 1 cos R ( n) ( ω n) = 0.54 0.46cos R ( n) N 2πn N 1 N 2πn 4ωn ω n = 0.42 0.5cos + 0.08cos R N N 1 1 ( ) ( n) N

220 VHDL FIR 1 FIR 11-2 11-3 11-4 11-5 11-4, M M 11-3 FIR FIR 2 11-5 FIR 11-5 FIR

11 11-2 11-6 FIR N 8 FIR N 8 8 FPGA 3 FPGA FIR N N N A B N Q N B = 1 2 i B( i) ( B i) B i i= 0 221 11-6 N 1 N 1 i Q = A B = A 2 B i= 0 i ( i) = 2 A B( i) i= 0 11-6 N ROM ROM 11-7 ( n i) h( i) Q i = x 11-7 FIR FIR

222 VHDL ROM N FIR FIR 11-8 FIR N N W y N 1 ( n) h( m) x( n m) = m= 0 y N 1 W 1 W 1 N = 1 i m= 0 i= 0 i= 0 m= 0 i i ( n) x( n m) 2 h( m) = 2 h( m) x( n m) W 1 N 1 i= 0 m= 0 i ( n) = 2 x( n m) h( m) y 11-12 i W 1 i= 0 i 11-12 2 ( ) ( ) i i x n m h m N 1 W ( ) i ( ) ( ) i 11-8 Q m h m x n m 1 W FIR N 1 m= 0

11 223 1KHz 10KHz 11 FIR h(n) 11-3 11-3 11 FIR 11-3 h n 1024 h(0) h(10) 0 0 00H 00000000 FIR h(1) h(9) 0.0468 47.923 30H 00110000 h(1) h(9) 0.0468 47.923 30H 00110000 h(2) h(8) 0.1010 103.424 67H 01100111 h(3) h(7) 0.1515 155.136 9bH 10011011 1 8 h(4) h(6) 0.1872 191.692 c0h 11000000 h(5) 0.2001 204.902 cdh 11001101 FIR 8 8 9 9 clk_regbt<=not clk and clk_en; -- clk_reg<=not clk and not clk_en; -- process(clk,res) begin if(res='1')then -- counter<=0; count_bt<=0; elsif(clk'event and clk='1')then -- if(counter<8)then -- 8 clk_en<='1'; -- counter<=counter+1; -- count_bt<=count_bt-1; -- else -- 9 ounter<=0; count_bt<=0; clk_en<='0'; end if; end if; end process; clk res counter count_bt counter 9 count_bt clk_regbt clk_reg clk_regbt clk_reg

224 VHDL clk res 8 count_bt clk_en clk_en clk_en clk_regbt clk_reg not clk clk clk_en 11-9 11-9 process(clk_reg,clr,res) begin if(res='1' or clr='1')then -- for I in 0 to 10 loop reg_xn(i)<="00000000"; end loop; elsif(clk_reg'event and clk_reg='0')then -- for I in 10 to 1 loop reg_xn(i)<=reg_xn(i-1); end loop; reg_xn(0)<=data_xn; -- end if; end process; reg_xn 11 8 clk_reg x reg_xn(10)

11 reg_xn(0) data_xn clk_reg 1 8 3 1 8 h(n) x(n) process(clk) begin if(clk'event and clk='0')then -- for I in 0 to 10 loop -- if (reg_hn(i)(count_bt)='1')then -- 1 add_xn(i)<=reg_xn(i); -- reg_xn(i) else -- 1 end if; end loop; end if; end process; add_xn(i)<="00000000"; -- "00000000" clk clk_regbt clk_regbt clk clk clk_regbt 11-9 clk_regbt reg_hn add_xn reg_xn reg_hn h(n) add_xn h(n) x(n) count_bt reg_hn(i)(count_bt) reg_hn i+1 count_bt h(i) count_bt count_bt 7 0 8 h(i) 8 x(i) 4 11-10 11-10 225

226 VHDL W 1 i= 0 i 11-12 2 N 1 i = x( n m) h( m) i m= 0 Q 11-8 i Q i i 2 process(clk_regbt,clk_reg,clr,set) begin if(clr= 1 or set= 1 ) then -- sum <= (OTHERS =>'0'); data_yn <= (OTHERS =>'0'); elsif(clk_reg= 1 )then -- data_yn<=result(18 downto 11); -- sum<=(others =>'0'); -- elsif(clk_regbt='1')then -- -- sum91<=add_xn(0)+add_xn(1); sum92<=add_xn(2)+add_xn(3); sum93<=add_xn(4)+add_xn(5); sum94<=add_xn(6)+add_xn(7); sum101<=sum91+sum92; sum102<=sum93+sum94; sum11<=sum101+sum102; sum<=result+sum11; -- else result<=sum(17 downto 0)& 0 ; -- end if; end process; W 1 N 1 i= 0 m= 0 ( ) i 2 p m i ( p m) i ( ) ( ) i i x n m h m 8 FIR h n ( )

11 227 FIR 6 1 h( n) FPGA FPGA process(clk) begin if(clk event and clk= 1 )then if(pcount<pmax & 0 )then pcount:=pcount+ 1 ; if(pcount<pmax)then clkout<= 0 ; else clkout<= 1 ; end if; else pcount:=0; end if; end if; end process; - -- -- 1 -- -- 0 -- -- pmax 1/2 clkout 1/2 clkout 50% 2 h( n) process(set,enter,mode) begin if(set<='1')then if(mode="00")then reg_hn(0)<="00000001"; reg_hn(10)<="00000001"; -- -- -- --

228 VHDL reg_hn(9)<="00110000"; reg_hn(1)<="00110000"; reg_hn(2)<="01100111"; reg_hn(8)<="01100111"; reg_hn(3)<="10011011"; reg_hn(7)<="10011011"; reg_hn(4)<="11000000"; reg_hn(6)<="11000000"; reg_hn(5)<="11001101"; elsif(mode="01")then -- if(enter= 1 )then -- reg_hn(addr_hn)<=data_hn; -- h( n) end if; end if; end if; end process; ( ) h n reg_hn ( ) h n 0 mode="00" h n FIR ( ) 1 mode="01" addr_hn data_hn addr_hn addr_hn set EDA FIR A/D 8 A/D AD574 ADC0809 FIR FPGA EPF10K20-TC144 FIR A/D DAC0832 13 FPGA 11 8 8 FIR FIR

11 11.3 IIR 229 FIR IIR FPGA IIR FIR IIR IIR FIR IIR 5~10 IIR IIR IIR FPGA 1 IIR a + a z + a z 1 2 0 1 2 ( z) = 1 2 1 b0 z b1 z H 11-13 II 11-11 n X(n) Y(n) n IIR d( n) = X ( n) + b d( n 1) + b Y ( n) = d( n) a 0 0 + d( n 1) a 1 2 ( n 2) + d( n 2) a 2 11-14 5 6 FPGA 2 ROM VHDL ROM IIR y 11-15 n = a0xn + a1xn 1 + a2xn 2 + b0 yn 1 + b1 yn 2 11-11 II {X n } Y N ai bi {X(N)} b 2 X(n) <1 X(n)

230 VHDL b 1 k k 0 x n = xn 2 x n 11-16 K = 1 k X(N) b-k 0 5bit F k k k k k k k k k k F( xn, xn 1, xn 2, yn 1, yn 2 ) a0xn + a1xn 1 + a2xn 2 + b0 yn 1 + b1 yn 2 = 11-17 b 1 k k k k k k 0 0 0 0 0 y n = 2 F( xn, xn 1, xn 2, yn 1, yn 2 ) F( xn, xn 1, xn 2, yn 1, yn 2 ) 11-18 k = 1 F 32 32*b ROM 11-12 ROM xn SR1 SR2 k x n k xn 1 k xn 2 y n SR3 k yn 1 y k n 2 SR4 k x n k xn 1 ROM k xn 2 k yn 1 k yn 2 FPGA FIR ROM ROM ROM 11-12 ROM 3 ROM ROM IIR y 11-19 n = a0xn + a1xn 1 + a2xn 2 + b0 yn 1 + b1 yn 2

11 {X n } Y N ai bi {X(N)} b 2 X(n) <1 X(n) 231 b 1 k k 0 x n = xn 2 x n 11-20 K = 1 k X(N) b-k 0 5bit F k k k k k k k k k k F( xn, xn 1, xn 2, yn 1, yn 2 ) a0xn + a1xn 1 + a2xn 2 + b0 yn 1 + b1 yn 2 = 11-21 k k k k k k k k k k F( a0, a1, a2, b0, b1 ) xna0 + xn 1a1 + xn 2a2 + yn 1b0 + yn 2b1 = 11-22 b 1 k k k k k k 0 0 0 0 0 y n = 2 F( a0, a1, a2, b0, b1 ) F( a0, a1, a2, b0, b1 ) 11-23 k = 1 11-19 X(n) X(n-1) X(n-2) Y(n-2) Y(n-1) k a 0 X k a 1 X k a 2 X k b 1 X k b 0 X Y(n) a 0 0 0 0 0 a1, a2, b0,, b 0 1 11-13 0 0 0 0 0 F ( a, a, a, b, ) =0 0 1 2 0 b1

232 VHDL b 1 k k k k k k y n = 2 F( a0, a1, a2, b0, b1 ) 11-24 k = 1 8 *1 8 11-13 X N FPGA A/D 2 1 6 8 Y N X n-1 X n-2 X n X n-1 Y N ->Y(N-1),Y(N-1)->Y(N-2) 1 Y N <1 k k k k k =max{ F a, a, a, b, b )} 11-25 ( 0 1 2 0 1 k k k k k =min{ F a, a, a, b, b )} 11-26 ( 0 1 2 0 1 y n b α 1 K = 1 2 k β k = 1 k 2 = 1 y < α β y(n) <1 S n S > α β α = 4 0.1913 = 1. 5652 β = 0.3695 0.1958 = 0.5653 S = α β = 2. 1305 Q5 2 VHDL CLR RES counter clk_en

11 count_bt Clk_en 8 process(clk,clr,res) begin if(clr='1' or res='1')then - counter<=0; count_bt<=0; elsif(clk'event and clk='1')then if(counter<8)then clk_en<='1'; -- 0-7 counter<=counter+1; -- count_bt<=count_bt+7; -- 1 else counter<=0; count_bt<=0; clk_en<='0'; end if end if; end process; 8 *1 8 clr,res data_yn data_yntemp 8 process(clk_regbt,clk_reg,clr,res)--adder begin if(clr='1' or res='1') then - sum<= OTHERS =>'0' ; data_yn<= OTHERS =>'0' ; elsif(clk_reg='1')then data_yn<=result(14 downto 7); -- 8 data_yntemp<=result(14 downto 7); sum<= OTHERS =>'0' ; elsif(clk_regbt='1')then sum<=result+add_xn(0)+add_xn(1)+add_xn(2) -add_yn(0)-add_yn(1);-- else result<=sum(14 downto 0)&'0';-- 2 end if; end process; 8 *1 8 11-24 process(clk)-- get the addend begin if(clk'event and clk='0')then if (reg_an(0)(count_bt)='1')then add_xn(0)<=reg_xn(0); else add_xn(0)<="00000000"; end if; --a0 count_bt x(n) if (reg_an(1)(count_bt)='1')then add_xn(1)<=reg_xn(1); else add_xn(1)<="00000000"; 233

234 VHDL end if; if (reg_an(2)(count_bt)='1')then add_xn(2)<=reg_xn(2); else add_xn(2)<="00000000"; end if; if (reg_bn(0)(count_bt)='1')then add_yn(0)<=reg_yn(0); else add_yn(0)<="00000000"; end if; if (reg_bn(1)(count_bt)='1')then add_yn(1)<=reg_yn(1); else add_yn(1)<="00000000"; end if; end if; end process; A/D X N X n X n-1 X n-1 X n-2 Y N ->Y(N-1),Y(N-1)->Y(N-2). process(clk_en) begin if(clk_en'event and clk_en='0')then data_xn<=ad_data; end if; end process; process(clk_reg,clr,res) begin if(res='1' or clr='1')then - reg_xn(0)<="00000000"; reg_xn(1)<="00000000"; reg_xn(2)<="00000000"; reg_yn(0)<="00000000"; reg_yn(1)<="00000000"; elsif(clk_reg'event and clk_reg='0')then reg_xn(2)<=reg_xn(1); -- X(N-1)->X(N-2) reg_xn(1)<=reg_xn(0) --X(N)->Y(N-1); reg_xn(0)<=data_xn reg_yn(1)<=reg_yn(0); reg_yn(0)<=data_yntemp; end if; end process; end; 11-1 FPGA DSP 11-2 VHDL FIR

12 VHDL 235 12 VHDL VHDL VHDL EDA VHDL / EDA VHDL EDA VHDL VHDL VHDL VHDL CPU VHDL VHDL ASIC FPGA CPLD VHDL EDA VHDL VHDL VHDL EDA IP FPGA/CPLD ASIC PLD 3 EDA PC FPGA CPLD ASIC EDA / 12.1 ispvhdl VHDL isplsi VHDL VHDL isplsi VHDL PC VHDL Model Technology ModelSim VHDL Verilog VHDL Synplicity Synplify VHDL Verilog Lattice ispexpert Compiler EDA

236 VHDL ` ispvhdl isplsi EDA 12-1 12-1 ModelSim PE/Plus 4.7h Synplify VHDL VHDL Verilog UltraEdit ispexpert Compiler ispds+ 1998 EDA 12.1.1 isplsi isplsi CPLD Lattice 1 5 isplsi isplsi 1K/2K/2KE/3K/5K/6K/8K isplsi 2KE/5K/8K 1998 2.5V isplsi1k/e Lattice E 2 CMOS 64 192 91 125MHz ISP Daisy Chain Download isplsi2ke SupperFast 200MHz 32 128 isplsi3k 125MHz 12-1 isplsi EDA isplsi5k SuperWide 32 64 68 isplsi5kv Lattice 3.3V isp PLD 256 512 1.2 2.4 PLD 125MHz JTAG I/O 5V 3.3V 2.5V isplsi8k SuperBig CPLD 480 840 720 1152 25000 43750 PLD ModelSim Synplify ispexpert Compiler ModelSim 12.1.2 ispvhdl 1 ModelSim ModelSim Model Technology VHDL Verilog Model Technology Mentor Graphics ModelSim RTL Functional Gate-Level RTL VHDL VHDL

12 VHDL VHDL VHDL ModelSim VHDL IEEE 1076-1987 IEEE 1076-1993 ModelSim Verilog IEEE 1364-1995 Open Verilog ModelSim SDF 1.0 2.0 2.1 VITAL 2.2b VITAL 95 2 Synplify Synplify FPGA CPLD Synplicity Synplicity Cadence Synplify Verilog VHDL Synplify VHDL Verilog Synplify FSM Synplify HDL Synplify RTL Technology RTL Synplify VHDL RTL VHDL Synplify Actel Altera Lattice Lucent Philips QuickLogic Vantis(AMD) Xilinx Synplify VHDL 1076-1993 Verilog 1364-1995 3 ispexpert Compiler ispexpert Compiler Lattice Fitter EDA EDIF ispexpert Compiler Lattice isplsi1k/2k/3k/5k/6k VHDL Verilog EDIF ispexpert Compiler EDIF PLA LAF VHDL Viewlogic Synopsys Synplicity Aldec VeriBest OrCAD Cadence Mentor Graphics Exemplar Logic EDA Lattice isplsi2ke isplsi5kv isplsi8k 237 12.1.3 ispvhdl 4 VHDL isplsi 4 VHDL 12-1

238 VHDL ` LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY Cnt4b IS PORT ( CLK : IN STD_LOGIC ; Q : BUFFER INTEGER RANGE 0 TO 15 ) ; END Cnt4b ; ARCHITECTURE one OF Cnt4b IS PROCESS ( CLK ) IF CLK'EVENT AND CLK = '1' THEN IF Q = 15 THEN Q <= 0 ; ELSE Q <= Q + 1 ; END IF; END IF ; END PROCESS ; END one ; DOS Windows D D D:\ISPEXAM 1 VHDL Cnt4b.vhd Windows 98 Synplicity Synplify Synplify Synplify 12-10 File New HDL File File Save 12-2 ModelSim Directory D:\ISPEXAM Cnt4b.vhd Synplify VHDL Tools Syntax Check 12-10 3 Synplify Cnt4b.vhd /

12 VHDL 2 ModelSim Cnt4b.vhd 239 Windows Model Tech ModelSim ModelSim (1) ModelSim File Directory 12-2 D:\ISPEXAM 12-3 WORK (2) Library New WORK WORK WORK 12-3 WORK WORK 3 WORK ( ) (3) File Compile VHDL 12-4 Cnt4b.vhd Compile Cnt4b.vhd Done Cnt4b WORK Cnt4b one WORK (4) File Simulate Simulate a Design 12-5 Entity 12-4 12-5 VHDL

240 VHDL ` Cnt4b (5) View Wave Wave 12-6 (6) Signals Add to Waveform Signals in Region Cnt4b clk q 12-6 (7) Transcript ModelSim force clk 0 0, 1 50 repeat 100 Enter 100 ns 0 ns 0 50 ns 1 100 ns (8) Wave Run Run 100 ns Run ModelSim 8 3 Synplify Cnt4b.vhd VHDL Synplify (1) Synplify 12-10 File New Project OK 12-10 Unsaved Project 12-6 12-7 D:\ISPEXAM CNT4.prj File Save 12-7 D:\ISPEXAM 12-7 Work

12 VHDL CNT4.prj D:\ISPEXAM CNT4.prj 12-10 D:\ISPEXAM\CNT4.prj CNT4.prj (2) D:\ISPEXAM\CNT4.prj ( 12-10) Add Add Source Files 12-8 Cnt4b.vhd ADD Cnt4b.vhd Source Work Cnt4b.vhd [VHDL] 241 Synplify VHDL ADD VHDL 12-8 Cnt4b.vhd (3) Change 12-10 Change Target Set Device Options 12-9 Technology 12-10 Lattice 12-9 isplsi OK Lattice isplsi 12-9 Altera FLEX10K EDIF / (4) Run Synplify Cnt4.prj Cnt4b.vhd D:\ISPEXAM Cnt4b.edf EDIF 12-10 Done View Log

242 VHDL ` (5) HDL Analyst RTL View 12-11 RTL VHDL HDL Analyst Technology View 4 ispexpert Compiler Cnt4b.edf Lattice ispexpert Compiler JED (1) Windows Lattice Semiconduct or ispexpert Compiler (2) Project New Create New 12-10 Project 12-11 RTL

( 12-12) EDIF Reader Settings EDIF Reader 13 Vendor Synplicity Synplify EDIF OK EDF Project Update Cnt4b.laf (4) Assign Device 12 VHDL 12-13 Synplify EDF Device Selection 12-14 Settings 12- isplsi1032e- 70LJ84 OK 12-12 243 (3) Create New Project D:\ISPEXAM Cnt4b.edf OK ispexpert Compiler Synplify Cnt4b.edf ispexpert Compiler Cnt4b.edf ispexpert Compiler 12-14

244 VHDL ` Lattice isplsi Synplify (5) Assign Pin Locations ispexpert Compiler 12-15 Unassigned CLK Q(0)..Q(3) 12-15 CLK I/O7 33 12-1 Pin Location Assignment 12-15 Save Pin Assignments Q(2) I/O18(PIN 47) Q(3) I/O19(PIN 48).ppn Read Pin File 12-1 CLK I/O7 (PIN 33) Q(0) I/O16(PIN 45) Q(1) I/O17(PIN 46) 12-1 Unassigned Assigned Pins I/O 1 2 12-1 1 GW48 NO.5 4 4 PIO19 PIO16 1 8 CLK PIO7 8 1 PIO19 PIO16 PIO7 isp1032e 1 isplsi1032e PIO19 PIO16 PIO7 48 47 46 45 33 FLEX10K20 1 (6) ispexpert Compiler Assign Pin Locations Tools Compile Compile ispexpert Compiler Cnt4b.laf

12 VHDL Cnt4b.jed Cnt4b.jed isp1032e (7) Interfaces VHDL Writer ispds+ VHDL Cnt4b.vhd Cnt4b (8) ModelSim Cnt4b.vhd Cnt4b.vhd 5 Cnt4b.jed ispexpert Compiler Tools ispdcd LSC ISP Daisy Chain Download 12-16 12-16 Cnt4b.jed isplsi1032e ISP Configuration Scan Board SCAN Lattice ISP 12-16 1032E 1032E Browse Cnt4b.jed Command Run Operation Cnt4b PASS 1 6 VHDL Lattice Lattice ispexpert Compiler Macro Library Macro VHDL Lattice I/O 600 isplsi6000 RAM Lattice Lattice Synplify Lattice Lattice Lattice components LIBRARY LATTICE; USE LATTICE.COMPONENTS.ALL ; 245

246 VHDL ` Lattice ispexpert System manuals Lattice Synplify isplsi isplsi RTL Synplify VHDL RTL View Technology View VHDL 12.2 Altera MAX+plus II VHDL MAX+plus II EDA MAX+plus II VHDL Verilog EDIF MAX+plusII MAX+plusII EDIF VHDL Verilog MAX+plusII EDA Synopsys Cadence Synplicity Mentor Viewlogic Exemplar Model Technology MAX+plusII APEX20K Altera FPGA/CPLD 1 Cnt4.vhd 12-5 Cnt4.vhd 4 VHDL File New 12-17 Text Editor file OK Untitled - Text Editor 12-17 New 12-2 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY CNT4 IS PORT ( CLK : IN STD_LOGIC ; Q : BUFFER INTEGER RANGE 0 TO 15) ; END ; ARCHITECTURE one OF CNT4 IS PROCESS (CLK) IF CLK'EVENT AND CLK = '1' THEN Q <= Q + 1 ; END IF; END PROCESS ; END ;

12 VHDL File Save 12-18 Directories D:\MAXVS\GUIDE File Name Cnt4.vhd OK D:\MAXVS\GUIDE MAX+plusII.VHD VHDL.TDF AHDL.V Verilog Cnt4 Cnt4 File Create Default Symbol MAX+plusII 12-19 247 Cnt4 MAX+plusII Cnt4.vhd Cnt4 12-20 12-19 Cnt4.vhd 2 Decl7s.vhd Decl7s.vhd 7 4 7 Decl7s.vhd 1. Cnt4.vhd 12-18 Cnt4.vhd 12-20 D:\MAXVS\GUIDE 12-3 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY DecL7S IS PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; LED7S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END ; ARCHITECTURE one OF DecL7S IS

248 VHDL ` PROCESS( A ) CASE A(3 DOWNTO 0) IS WHEN "0000" => LED7S <= "00111111" ; -- X 3F 0 WHEN "0001" => LED7S <= "00000110" ; -- X 06 1 WHEN "0010" => LED7S <= "01011011" ; -- X 5B 2 WHEN "0011" => LED7S <= "01001111" ; -- X 4F 3 WHEN "0100" => LED7S <= "01100110" ; -- X 66 4 WHEN "0101" => LED7S <= "01101101" ; -- X 6D 5 WHEN "0110" => LED7S <= "01111101" ; -- X 7D 6 WHEN "0111" => LED7S <= "00000111" ; -- X 07 7 WHEN "1000" => LED7S <= "01111111" ; -- X 7F 8 WHEN "1001" => LED7S <= "01101111" ; -- X 6F 9 WHEN "1010" => LED7S <= "01110111" ; -- X 77 10 WHEN "1011" => LED7S <= "01111100" ; -- X 7C 11 WHEN "1100" => LED7S <= "00111001" ; -- X 39 12 WHEN "1101" => LED7S <= "01011110" ; -- X 5E 13 WHEN "1110" => LED7S <= "01111001" ; -- X 79 14 WHEN "1111" => LED7S <= "01110001" ; -- X 71 15 WHEN OTHERS => NULL ; END CASE ; END PROCESS ; END ; 3 TOP.GDF TOP.GDF 1 2 Cnt4.vhd Decl7s.vhd File New 12-17 Graphic Editor File OK Graphic Editor Graphic Editor 12-21 (1) Graphic Editor 12-22 Enter Symbol Symbol Name VHDL 12-21

12 VHDL OK Symbol Files Cnt4 Decl7s Symbol Libraries d:\maxvs\guide VHDL VHDL VHDL OK 12-21 Cnt4 Decl7s INPUT OUTPUT prim 12-22 e:\maxplus2\max2lib\prim Symbol Files INPUT OUTPUT Symbol Name INPUT OUTPUT MAX+plusII INPUT OUTPUT (2) 12-21 / / 12-21 LED7S[7..0] 8 Options Line Style (3) / INPUT OUTPUT TOP.GDF CLK 8 LED7S[7..0] 12-21 LED7S[7..0] VHDL LED7S7 LED7S0 LED7S7 AHDL VHDL LED7S 7 12-22 8 12-21 File Save TOP.GDF 249

250 VHDL `, File Name 4 TOP.GDF CLK PIN 23 PIO13 8 TOP.GDF LED7S7 PIN 38 PIO23 D8 LED7S6 PIN 78 PIO46 g Project LED7S5 PIN 73 PIO45 f LED7S4 PIN 72 File Project Set Project to PIO44 e LED7S3 PIN 71 PIO43 d Current File LED7S2 PIN 70 PIO42 c TOP LED7S1 PIN 67 PIO41 b LED7S0 PIN 66 PIO40 a Assign Device Device Family FLEX10K Devices EPF10K10LC84-3 2 OK II MAX+plus Compiler 12-23 START Assign Pin/Locatio n/chip Node 12-2 12-23 Name Pin: Add LED7S[7..0] LED7S7 LED7S6 LED7S0 8 12-2 OK GW48 1 NO.6 CLK 8

12 VHDL LED7S7 D8 LED7S6 LED7S0 PIO46 PIO40 7, MAX+plus II Compiler 12-23 VHDL 12-23 Interfaces VHDL Netlist Reader Settings VHDL 87 87 VHDL Assign Global Project Logic Synthesis Area Optimize Speed CPLD MAX Device Synthesis Options Define Synthesis Style Style Normal Minimization Full Slow Slew Rate I/O 7128S XOR Synthesis 251 OK Assign Global Project Device Options Security Bit Enable JTAG Suport JTAG OK Compiler Start Fitter rpt 5 TOP MAX+plusII File New New Waveform Editor file 12-17 OK 12-24 Node Enter Nodes from SNF 12-24 12-25 List

252 VHDL ` => OK CLK 7 LED7S[7..0] Cnt4:1 Q File Save top.scf SNF CLK CLK Value CLK CLK 4 12-25 12-25 OK OPTIONS Grid Size 12-26 12-24 Simulator MAX+plusII 200ns 12-26 Simulator 12-27 Start 12-28 0 errors 0 warnings 12-29 12-27

12-29 12 VHDL File End Time 5 s OK MAX+plusII Simulator Simulator End Time 5 s File Open Open Waveform Editor Files Files top.scf 0 1 X Z INV G 6 TOP 12-23 MAX+plus II Programmer Programmer ( 12-30) FPGA GW48 1 FLEX10K 10K10 Configure 10K10 Configuration Complete 6 6 8 8 1 0 F 7 VHDL GDF 253 12-28 12-29 TOP

254 VHDL ` 12-30 FPGA Configure CPLD EPM7128S Program Configure CLK 42 1/2 10K10 42 Clock1 Clock1 8Hz 4Hz 2Hz 1Hz File Open Open Graphic Editor top.gdf Assign Pin/Location/Pin CLK Pin 42 Change OK MAX+plusII Compiler Start MAX+plus II MAX+plusII FLEX ISP MAX ByteBlaster ByteBlaster Programmer Options Hardware Setup Hardware Type ByteBlaster OK 12-30 12.3 MAX+plus II Synplify EDA VHDL Synopsys FPGA Express Synplicity Synplify VHDL MAX+plusII VHDL EDA VHDL IP EDA MAX+plus II Synplify Synplify VHDL MAX+plus II MAX+plusII TOP TOP Cnt4 Decl7s Cnt4 EDA Synplify 12-2

12 VHDL CNTS Synplify File New HDL File OK 12-1 CNTS Cnt4 d:\maxvs\guide CNTS.VHD File New Project OK Synplify-[Unsaved Project] File Save Save as CNTS.PRJ Add CNTS.VHD Add Change Target EPF10K10 OK Run EDIF CNTS.EDF Altera MAX+plus II CNTS.ACF d:\maxvs\guide Synplify Synplify.PRJ MAX+plus II File Project Name Hierarchies Project Name Show Only Tops of Files EDF CNTS.EDF VHDL EDF Interfaces CNTS.EDF File Create Default Symbol top.gdf cnts Cnt4 top.gdf MAX+plusII File Project Name top.gdf Compiler Compiler EPF10K10 Settings Interfaces EDIF Netlist Reader Vendor Synplicity Customize >> LMF #1 MAX+plus II8.0 OK Compiler Start Programmer 255 / 10K10 1 Synplify VHDL 2 MAX+plusII EDF Project File 3 MAX+plusII Interfaces EDIF Netlist Reader Settings EDA Synplicity 4 MAX+plusII 5 MAX+plusII 1 6 EDA

256 VHDL ` 12.4 Xilinx Foundation VHDL Foundation Series Xilinx EDA XC3000A/L XC3100A/L XC4000E/L/EX/XL/XV/XLA XC5200 XC9500 C9500XL Spartan SpartanXL Virtex Foundation Foundation Project Manager Xilinx Synopsys FPGA Express Foundation Series EDA Synopsys FPGA Express Foundation VHDL Verilog HDL IP JTAG CPLD FPGA Foundation 12.4.1 Foundation Foundation HDL hhdl Flow h 12-31 (1) Xilinx (2) Options Create Netlist 12-31

12 VHDL (3) Logic Simulator (4) Translate Map Place & Route Timing Configure (5) (6) 12-32 HDL (7) HDL 12-32 Foundation 12-31 12-32 HDL HDL 257 12.4.2 VHDL VHDL 4 ADDER4b Foundation 1 ADDER4b HDL ADDER4b D \XLINSAM Foundation 12-33 12-33 Foundation Create a New Project OK

258 VHDL ` 12-34 ADDER4b HDL OK File New Project New Project 2 HDL ADDER4b.VHD ADDER4b.VHD (1) HDL Foundation HDL HDL Editor 12-35 Create Empty OK HDL 12-4 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_ARITH.ALL ; ENTITY ADDER4b IS PORT ( a, b : IN INTEGER RANGE 0 TO 15 ; c : OUT INTEGER RANGE 0 TO 31 ) ; END ADDER4b ; ARCHITECTURE one OF ADDER4b IS c <= a + b ; END one ; (2) 12-4 HDL VHDL File Save ADDER4b.VHD ADDER4b.VHD (3) Project Add to Project ADDER4b.VHD HDL Foundation ADDER4b.VHD 12-34 12-35 HDL

12 VHDL VHDL HDL Add to Project VHDL Foundation ADDER4b.VHD Synthesis Check Syntax 3 ADDER4b.VHD ADDER4b (1) 259 Foundation 12-36 Version Versions Version 12-36 Version ver1 ver2 ver3 (2) ADDER4b / ADDER4b / 12-36 Edit Synthesis/Implementation Constraints Speed Area 12-36 Run 12-36 Run 12-37 Pad Loc P P5 5 FPGA 2 XCS10 XCS30 12-37 Global Buffer I/O CLK CLK DONT USE CLK Global Buffer DONT USE

260 VHDL ` ( 12-38 ) Foundation Versions Ver1-SPARTAN- S05PC84-3 Edit Constraints 12-37 12-37 OK Foundation 2. (1) Foundation (2) Signal Add Signals 12-39 Singal Selection Add Waveform Viewer 0 12-37 12-39 Ctrl Add Waveform Viewer 0 Close

12 VHDL Component Selection for Waveform Viewer 12-39 A3, A0 B3, B0 C4, C0 A3, A0 A3 A2 A1 A0 Add Close (3) Waveform Edit 12-45 12-38 Test Vector State Selection 12-3 Test Vector State Selection 12-3 Low High Unkn_X High_Z Del Bus Bus Bus State 12-40 Test Vector State Selection High A3, A0 B3, B0 12-40 Bus 12-40 261

262 VHDL ` Bus (4) 12-41 Simulation Step Tools 50ns 12-41 5 ADDER4b (1) Foundation 12-41 Options 12-42 Options (2) 12-42 Optional Targets Produce Timing Simulation Data Produce Configuration Data OK 12-43 (3) 12-41 / 12-42

12 VHDL 12-43 Run Flow Engine 12-44 Foundation Flow Engine 12-4 Running Completed 12-44 Configure Completed 263 6 Foundation 12-44 12-45 ADDER4b 12-43

264 VHDL ` 7 Hardware Debugger Parallel GW48 1 Download Download Design 12-4 Xilinx CPLD Translate Map Xilinx FPGA XC95108 Place & Route 1 Timing Configure b 2 CPLD 8 XC9500 Project Manager Implementation Options Options XC9500 Edit Template 12-45 ADDER4b Slew Rate 12-1 12.2 TOP VHDL Cnt4.vhd Decl7s.vhd TOP.VHD

13 VHDL 265 13 VHDL EDA VHDL 19 VHDL EDA EDA EDA EDA Xilinx XILINX University Program EDA Workshop Altera University Program EDA Design Laboratory Package FPGA/CPLD RS232 VGA MAX+plusII 1 GW48-CK EDA GW48-CK GW48-CK VHDLDEMO VHDL MAX+plusII EPF10K10 2 EDA 12 2 13.1 8 13-1 8 13-1 counter.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY counter IS PORT (d : IN STD_LOGIC_VECTOR (7 DOWNTO 0);--8

266 VHDL ld, ce, clk, rst : IN std_logic; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END counter; ARCHITECTURE behave OF counter IS SIGNAL count : STD_LOGIC_VECTOR (7 DOWNTO 0); PROCESS (clk, rst) IF rst = '1' THEN count <= (OTHERS =>'0');-- 0 ELSIF RISING_EDGE(clk) THEN --... IF ld = '1' THEN count <= d; -- 1, ELSIF ce = '1' THEN count <= count + 1;--, END IF; END IF; END PROCESS; q <= count; END behave; 13-1,d(7 DOWNTO 0) 8 ;ld ce clk rst 13-1 ld --, 1 -- 13-1 13-1 GW48-CK 1 13-1 counter.vhd, MAX+plusII, EPF10K10LC84 2 1 NO.0 d(7 DOWNTO 0)->PIO15 13-2 13-2 ~PIO8;q(7 DOWNTO 0)-> PIO47~PIO40;ce->PIO7;ld->PIO6;rst->PIO5;clk->CLOCK0;3 1 PIO 10K10 MAX+PLUSII 12.3 4 CLOCK0 1Hz 5 8

13 VHDL ce 7 ld 6 0 rst 8 7 16 2/ 1 8 D8~D1 13-1-1 MAX+plusII 13-1 13-1-2 13-1 13-1-3 13-2 13-1 GENERIC 1 13-2 GENERIC (width : INTEGER := 1) 1 13-2 13-2 2 2 8 GW48 NO.0 13-2 counter1.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; ENTITY counter1 IS GENERIC (width : INTEGER := 4); -- 4 PORT (clk, rst : IN STD_LOGIC; up, down, load : IN STD_LOGIC; data : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0); q : BUFFER STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END counter1; ARCHITECTURE behave OF counter1 IS PROCESS (clk, rst) VARIABLE delta : STD_LOGIC_VECTOR (width-1 DOWNTO 0); IF rst = '1' THEN q <= (OTHERS => '0'); ELSIF RISING_EDGE(clk) THEN IF (load = '1') THEN q <= data; ELSIF (up = '1' OR down = '1') THEN IF (up = '1') THEN delta :=(0 => '1', OTHERS => '0'); ELSE delta := (OTHERS => '1'); END IF; q <= q + delta; END IF; END IF; END PROCESS; END behave; 267 13.2 13-3 IF-THEN-ELSE

268 VHDL nmi, float, int peripheral CONV_STD_LOGIC_VECTOR(X Y) 13-3 13-3 interrupt.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY interrupt IS GENERIC(msb: INTEGER := 15); PORT( nmi, float, int, peripheral: IN STD_LOGIC; flush_cache: OUT STD_LOGIC; goto_addr: OUT STD_LOGIC_VECTOR (msb DOWNTO 0) ); END interrupt; ARCHITECTURE behave OF interrupt IS CONSTANT nop: INTEGER :=0; -- nop=0 CONSTANT nmi_addr: integer := 16#C5AA#; -- CONSTANT float_addr: integer := 16#CA522#;-- CONSTANT int_addr: integer := 16#CB4A#; -- CONSTANT periph_addr: integer :=16#CD2C#; -- PROCESS (nmi, float, int, peripheral) VARIABLE address : INTEGER; flush_cache <= '0'; IF nmi = '1' THEN address := nmi_addr; -- ELSIF float = '1' THEN address := float_addr; flush_cache <= '1'; -- ELSIF int = '1' THEN address := int_addr; flush_cache <= '1'; -- ELSIF peripheral = '1' THEN address := periph_addr; -- ELSE address := nop; -- 0 END IF; -- address msb+1 goto_addr <= CONV_STD_LOGIC_VECTOR(address, msb+1); END PROCESS; END behave; 13-2-1 13-3 16 GW48-CK NO.5 4 3 2 1 nmi, float, int, peripheral D1 flush_cache 4 3 2 1 goto_addr 13-2-2 13-3 MCS51 5 13-3 VHDL

13 VHDL 13.3 SRAM 269 SRAM SRAM 13-4 SRAM 4 2 8 2 16X8bit SRAM WRITE wr='0' IF_THEN wr wr='0' cs='0' AND rd='1' 8 din adr RAM (rd='0' and cs='0' and wr='1') SRAM adr RAM dout 13-3 13-4 13-4 GENERIC SRAM k w MAX+PLUSII EDA 13-4 12.3.4 MAX+PLUSII EPF10K10 13-4 sram.vhd LIBRARY IEEE; --16X8bitSRAM USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity sram is GENERIC(k: INTEGER := 8; --8 w: INTEGER := 4); --4 16 port (rd, wr, cs: in Std_logic; -- adr: in Std_logic_vector(w-1 downto 0); --4 din: in Std_logic_vector(k-1 downto 0); --8 dout: out Std_logic_vector(k-1 downto 0));--8 end sram; architecture behav of sram is subtype word is Std_logic_vector(k-1 downto 0); -- MAX+PLUSII type memory is array(0 to 2 ** w-1) of word; signal sram : memory; signal adr_in :INTEGER; begin adr_in <=conv_integer(adr);

270 VHDL WRITE process( wr,cs,adr_in,din,rd) -- WRITE begin if wr='0' then if cs='0' AND rd='1' then sram(adr_in)<=din; end if; end if; end process; READ process(rd,cs,adr_in,wr) -- READ begin if (rd='0' and cs='0' and wr='1') then dout <= sram(adr_in); dout <=(others=>'z'); end if ; end process; else end behav; GW48-CK 1 SRAM SRAM.EDF, EPF10K10LC84 2 NO.1 din(7 DOWNTO 0)->PIO7~PIO0;dout(7 DOWNTO 0)->PIO31~PIO24; adr(3 DOWNTO 0)->PIO11~pIO8;cs->PIO12;rd->PIO48;wr->PIO49;3 4 0 cs= 0 3 1 16 2/ 1 8 2 30 8 7 wr rd 8/ 7 RAM 8 13-3-1 13-4 wr 13.4 13-5 8 8 clk push='1' pop='0' 8 din(7 downto 0) push='0' pop='1' dout(7 downto 0) empty='1' pushfull='1' C 13-5 stack.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity stack is generic (n: INTEGER := 8; -- k: INTEGER := 8); --

271 13 VHDL port(rst, clk: in Std_logic; push, pop: in Std_logic; empty, fullpop: out Std_logic; din: in Std_logic_vector(n-1 downto 0 ); dout: out Std_logic_vector(n-1 downto 0 )); end stack; architecture alg of stack is signal num,c: integer range 0 to k-1; function to_bit (b: in boolean) return Std_logic is begin case b is -- MAX+PLUSII case IF return when true => return'1'; when false => return'0'; end case; end to_bit; begin empty <= to_bit(c = 0); fullpop <= to_bit(c = k - 1); process type type_stack is array (natural range k-1 downto 0) of Std_logic_vector (n-1 downto 0 ); variable s: type_stack; begin wait until clk'event and clk ='1'; if rst = '1' then c <= 0; elsif push = '1' and pop = '0' then s( k-1 downto 1):= s( k-2 downto 0); s(0):= din; c <= c + 1; elsif pop = '1' and push = '0' then dout <= s(0); s( k-2 downto 0):= s( k-1 downto 1); c <= c - 1; end if; end process; end alg; GW48-CK 13-4-1 13-5 FIFO GW48-CK 13.5 8 CPLD

272 VHDL 4 4 8 4 13-4 4 8 4 VHDL 13-6 ADDER4B.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADDER4B IS -- 4 PORT ( CIN : IN STD_LOGIC ; -- A : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; --4 B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; --4 S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ; --4 COUT : OUT STD_LOGIC ); -- END ADDER4B ; ARCHITECTURE behav OF ADDER4B IS SIGNAL SINT : STD_LOGIC_VECTOR(4 DOWNTO 0) ; SIGNAL AA,BB : STD_LOGIC_VECTOR(4 DOWNTO 0) ; AA<='0'&A ; -- 4 5 BB<='0'&B ; -- 4 5 SINT <= AA + BB + CIN ; S <= SINT(3 DOWNTO 0) ; COUT <= SINT(4) ; END behav ; 4 8 13-7 ADDER8B.vhd LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY ADDER8B IS PORT ( CIN : IN STD_LOGIC ; A : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; B : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ; COUT : OUT STD_LOGIC ); END ADDER8B ;

13 VHDL ARCHITECTURE struc OF ADDER8B IS COMPONENT ADDER4B -- ADDER4B PORT ( CIN : IN STD_LOGIC; A : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ; COUT : OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL CARRY_OUT : STD_LOGIC; -- 4 U1 : ADDER4B -- 4 U1 PORT MAP(CIN=>CIN, A=>A(3 DOWNTO 0), B=>B(3 DOWNTO 0), S=>S(3 DOWNTO 0), COUT=>CARRY_OUT ) ; U2 : ADDER4B -- 4 U2 PORT MAP(CIN=>CARRY_OUT, A=>A(7 DOWNTO 4),B=>B(7 DOWNTO 4), S=>S(7 DOWNTO 4), COUT=>COUT ) ; END struc ; 273 CIN A[7..0] B[7..0] A[7..0] B[7..0] A[3..0] B[3..0] A[7..4] B[7..4] ADDER4B CIN S[3..0] A[3..0] COUT B[3..0] ADDER4B CIN S[3..0] A[3..0] COUT B[3..0] S[3..0] S[7..4] S[7..0] S[7..0] COUT 13-4 8 GW48-CK NO.1 1 A[7..0] PIO7 PIO0; B[7..0] PIO15 PIO8; S[7..0] PIO23 PIO16 8 A B 2 1 4 3 6 4 5 4 PIO39 D8 8 CIN PIO49 13-5-1 8 8 0 13.6 8

274 VHDL PLD ROM 8 8 1 0 13-5 13-5 ARICTL START PIO49 CLK START ARICTL CLK CLKOUT START RSTALL ARIEND ARIEND GND A[7..0] B[7..0] SREG8B CLK LOAD DIN[7..0] QB DTBOUT[15..8] ANDSD[7..0] ADDER8B CIN S[7..0] A[7..0] COUT B[7..0] DTBIN[7..0] DTBIN8 ABIN DIN[7..0] ANDARITH DOUT[7..0] ANDSD[7..0] DTBIN[8..0] CLK CLR D[8..0] REG16B Q[15..0] DTBOUT[15..0] DTBOUT[15..0] 13-5 8 8 16 A[7..0] SREG8B ARICTL CLK 8 SREG8B 1 ANDARITH 8 B[7..0] 8 16 REG16B 8 0 8 ARICTL ARIEND REG16B 8 100MHz 80ns 12MHz MCS-51 8 4 s 13-8 ANDARITH.vhd LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY ANDARITH IS -- PORT ( ABIN : IN STD_LOGIC; --

13 VHDL DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; --8 DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;--8 END ANDARITH ; ARCHITECTURE behav OF ANDARITH IS PROCESS(ABIN, DIN) FOR I IN 0 TO 7 LOOP -- 8 1 DOUT(I) <= DIN(I) AND ABIN ; -- END LOOP ; END PROCESS ; END behav; 13-9 REG16B.vhd LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY REG16B IS -- 16 PORT (CLK : IN STD_LOGIC ; -- CLR : IN STD_LOGIC ; -- D : IN STD_LOGIC_VECTOR(8 DOWNTO 0) ; -- 8 Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --16 END REG16B; ARCHITECTURE behav OF REG16B IS SIGNAL R16S : STD_LOGIC_VECTOR(15 DOWNTO 0);--16 PROCESS(CLK, CLR) IF CLR = '1' THEN R16S <= OTHERS =>'0' ;-- ELSIF CLK'EVENT AND CLK = '1' THEN -- R16S(6 DOWNTO 0) <= R16S(7 DOWNTO 1);-- 8 R16S(15 DOWNTO 7) <= D ; -- 8 END IF ; END PROCESS ; Q <= R16S ; END behav ; 13-10 SREG8B.vhd LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY SREG8B IS -- 8 PORT ( CLK : IN STD_LOGIC; LOAD : IN STD_LOGIC ; DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); QB : OUT STD_LOGIC ); END SREG8B; ARCHITECTURE behav OF SREG8B IS SIGNAL REG8 : STD_LOGIC_VECTOR(7 DOWNTO 0); PROCESS (CLK, LOAD) IF CLK'EVENT AND CLK = '1' THEN IF LOAD = '1' THEN REG8 <= DIN; -- ELSE REG8(6 DOWNTO 0) <= REG8(7 DOWNTO 1);-- 275

276 VHDL END IF; END IF; END PROCESS; QB <= REG8(0); -- END behav; 13-11 ARICTL.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ARICTL IS -- PORT ( CLK : IN STD_LOGIC; START : IN STD_LOGIC; CLKOUT : OUT STD_LOGIC; RSTALL : OUT STD_LOGIC; ARIEND : OUT STD_LOGIC ); END ARICTL; ARCHITECTURE behav OF ARICTL IS SIGNAL CNT4B : STD_LOGIC_VECTOR(3 DOWNTO 0); RSTALL <= START; PROCESS(CLK, START) IF START = '1' THEN CNT4B <= "0000"; -- ELSIF CLK'EVENT AND CLK = '1' THEN IF CNT4B < 8 THEN -- 8 8 CNT4B <= CNT4B + 1; END IF; END IF; END PROCESS; PROCESS(CLK, CNT4B, START) IF START = '0' THEN IF CNT4B < 8 THEN -- CLKOUT <= CLK; ARIEND <= '0'; ELSE CLKOUT <= '0'; ARIEND <= '1'; -- END IF; ELSE CLKOUT <= CLK; ARIEND <= '0'; END IF; END PROCESS; END behav; 13-12 MULTI8X8.vhd LIBRARY IEEE; -- 8 USE IEEE.STD_LOGIC_1164.ALL; ENTITY MULTI8X8 IS PORT ( CLK : IN STD_LOGIC; START : IN STD_LOGIC; -- A : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; --8 B : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; --8 ARIEND : OUT STD_LOGIC; -- DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) );--16 END MULTI8X8 ; ARCHITECTURE struc OF MULTI8X8 IS

13 VHDL COMPONENT ARICTL -- PORT ( CLK : IN STD_LOGIC; START : IN STD_LOGIC; CLKOUT : OUT STD_LOGIC; RSTALL : OUT STD_LOGIC; ARIEND : OUT STD_LOGIC ); END COMPONENT; COMPONENT ANDARITH -- PORT ( ABIN : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; COMPONENT ADDER8B -- 8 PORT (CIN : IN STD_LOGIC; A : IN STD_LOGIC_VECTOR(7 DOWNTO 0); B : IN STD_LOGIC_VECTOR(7 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); COUT : OUT STD_LOGIC ); END COMPONENT; COMPONENT SREG8B -- 8 PORT ( CLK : IN STD_LOGIC; LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); QB : OUT STD_LOGIC ); END COMPONENT; COMPONENT REG16B -- 16 PORT ( CLK : IN STD_LOGIC; CLR : IN STD_LOGIC ; D : IN STD_LOGIC_VECTOR(8 DOWNTO 0) ; Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END COMPONENT; SIGNAL GNDINT : STD_LOGIC ; SIGNAL INTCLK : STD_LOGIC ; SIGNAL RSTALL : STD_LOGIC; SIGNAL QB : STD_LOGIC; SIGNAL ANDSD : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL DTBIN : STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL DTBOUT : STD_LOGIC_VECTOR(15 DOWNTO 0); DOUT <= DTBOUT ; GNDINT <= '0'; U1 : ARICTL PORT MAP( CLK=> CLK, START=> START, CLKOUT => INTCLK, RSTALL=> RSTALL, ARIEND=> ARIEND ) ; U2 : SREG8B PORT MAP( CLK=> INTCLK, LOAD=> RSTALL, DIN=> B, QB=> QB ) ; U3 : ANDARITH PORT MAP( ABIN=> QB, DIN=> A, DOUT=> ANDSD); U4 : ADDER8B PORT MAP(CIN => GNDINT, A => DTBOUT(15 DOWNTO 8), B => ANDSD, S => DTBIN(7 DOWNTO 0), COUT => DTBIN(8) ) ; U5 : REG16B PORT MAP(CLK => INTCLK, CLR => RSTALL, D => DTBIN, Q => DTBOUT ) ; END struc ; GW48-CK NO.1 ARIEND PIO39(D8) CLK Clock0 START 8 PIO49 B[7..0] PIO7 PIO0 2 1 8 A[7..0] 277

278 VHDL PIO15 PIO8 4 3 8 DOUT[15..0] PIO31 PIO16 1 2 1 4 4 ( 2 1) 2 4 3 4 4 ( 4 3) 3 clock0 4 8 8 8 5 13-6-1 4 13-6-2 8 4 13.7 8 VHDL tabletennis MAX+PLUSII ball clk board 1 cou4 cou10 mway sound 13-13 ball.vhd library ieee; -- use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ball is port(clk:in std_logic; -- clr:in std_logic; -- way:in std_logic; -- en:in std_logic; -- ballout:out std_logic_vector(7 downto 0));-- end ball; architecture ful of ball is signal lamp:std_logic_vector(9 downto 0); begin process(clk,clr,en) begin if(clr='1') then lamp<="1000000001"; -- elsif en='0' then elsif (clk'event and clk='1') then-- if(way='1') then -- lamp(9 downto 1)<=lamp(8 downto 0);

13 VHDL lamp(0)<='0'; else -- lamp(8 downto 0)<=lamp(9 downto 1); lamp(9)<='0'; end if; end if; ballout<=lamp(8 downto 1); end process; end; 13-14 ballctrl.vhd library ieee; -- use ieee.std_logic_1164.all; entity ballctrl is port(clr:in std_logic;-- bain bbin:in std_logic;-- serclka:in std_logic;-- serclkb:in std_logic;-- clk:in std_logic;-- bdout:out std_logic;-- serve:out std_logic;-- serclk:out std_logic;-- ballclr:out std_logic;-- ballen:out std_logic);-- end ballctrl; architecture ful of ballctrl is signal bd ser:std_logic; begin bd<=bain or bbin; ser<=serclka or serclkb; serclk<=ser;-- bdout<=bd; -- process(clr,clk,bd) begin if(clr='1' ) then -- serve<='1'; -- ballclr<='1'; -- else -- if(bd='1')then -- ballclr<='1'; -- if(ser='1') then -- ballen<='1'; -- serve<='0'; -- else ballen<='0'; -- serve<='1'; -- end if; else ballclr<='0'; -- end if; end if; end process; end; 13-15 board.vhd library ieee; -- 279

280 VHDL use ieee.std_logic_1164.all; entity board is port (ball:in std_logic;-- net:in std_logic; -- counclk serclk bclk:in std_logic;-- serve:in std_logic;-- couclk:out std_logic;-- serclk:out std_logic);-- '1' end board; architecture ful of board is begin process(bclk,net) begin if(net='1')then -- counclk serclk serclk<='0'; couclk<='0'; elsif(bclk'event and bclk='1')then -- if(serve='1')then serclk<='1';-- else -- if(ball='1') then serclk<='1';-- else serclk<='0'; couclk<='1';-- end if; end if; end if; end process; end; 13-16 cou10.vhd library ieee; -- use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cou10 is port(clk,clr:in std_logic; cout:out std_logic; qout:out std_logic_vector(3 downto 0)); end cou10; architecture ful of cou10 is signal qqout:std_logic_vector(3 downto 0); begin process(clr,clk) begin if(clr='1') then qqout<="0000"; cout<='0'; elsif(clk'event and clk='1') then if(qqout>"1000") THEN qqout<="0000"; cout<='1'; else qqout<=qqout+'1'; cout<='0'; end if; end if; qout<=qqout; end process; end; 13-17 cou4.vhd library ieee; --

13 VHDL use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cou4 is port(clk,clr:in std_logic; cout:out std_logic; qout:out std_logic_vector(3 downto 0)); end cou4; architecture ful of cou4 is signal qqout:std_logic_vector(3 downto 0); begin process(clr,clk) begin if(clr='1') then qqout<="0000"; cout<='0'; elsif(clk'event and clk='1') then if(qqout>"0010")then qqout<="0000"; cout<='1'; else qqout<=qqout+'1'; cout<='0'; end if; end if; qout<=qqout; end process; end; 13-18 mway.vhd library ieee; -- use ieee.std_logic_1164.all; entity mway is port(servea serveb:in std_logic;-- way:out std_logic); -- end mway; architecture ful of mway is begin process(servea,serveb) begin if(servea='1') then way<='1'; -- elsif(serveb='1') then way<='0'; -- end if; end process; end; 13-19 sound.vhd library ieee; -- use ieee.std_logic_1164.all; entity sound is port (clk:in std_logic;-- sig:in std_logic;-- en:in std_logic;-- sout:out std_logic);-- end sound; architecture ful of sound is begin sout<=clk and (not sig) and en;-- end; 281

282 VHDL 13-20 tabletennis.vhd library ieee;-- use ieee.std_logic_1164.all; entity tabletennis is port(bain,bbin,clr,clk,souclk:in std_logic; ballout:out std_logic_vector(7 downto 0); countah,countal,countbh,countbl:out std_logic_vector(3 downto 0); lamp,speaker:out std_logic); end; architecture ful of tabletennis is component sound port (clk,sig,en:in std_logic;sout:out std_logic); end component; component ballctrl port(clr,bain,bbin,serclka,serclkb,clk:in std_logic; bdout,serve,serclk,ballclr,ballen:out std_logic); end component; component ball port(clk,clr,way,en:in std_logic; ballout:out std_logic_vector(7 downto 0)); end component; component board port (ball,net,bclk,serve:in std_logic; couclk,serclk:out std_logic); end component; component cou10 port(clk,clr:in std_logic;cout:out std_logic; qout:out std_logic_vector(3 downto 0)); end component; component cou4 port(clk,clr:in std_logic; cout:out std_logic; qout:out std_logic_vector(3 downto 0)); end component; component mway port(servea,serveb:in std_logic; way:out std_logic); end component; signal net,couclkah,couclkal,couclkbh,couclkbl,cah,cbh way, serve,serclka,serclkb,serclk,ballclr,bdout,ballen:std_logic; signal bbll:std_logic_vector( 7 downto 0); begin net<=bbll(4); uah:cou4 port map (couclkah,clr,cah,countah); ual:cou10 port map (couclkal,clr,couclkah,countal); ubh:cou4 port map (couclkbh,clr,cbh,countbh); ubl:cou10 port map (couclkbl,clr,couclkbh,countbl); ubda:board port map (bbll(0),net,bain,serve,couclkal,serclka); ubdb:board port map (bbll(7),net,bbin,serve,couclkbl,serclkb); ucpu:ballctrl port map (clr,bain,bbin,serclka,serclkb, clk,bdout,serve,serclk,ballclr,ballen);

13 VHDL uway:mway port map (serclka,serclkb,way); uball: ball port map (clk,ballclr,way,ballen,bbll); usound:sound port map(souclk,ballen,bdout,speaker); ballout<=bbll; lamp<=clk; end; GW48-CK 1 EDA MAX+PLUSII EPF10K10-PC84 10K10 bain->16 bbin->5 ballout 0..7 ->25,24,23,22,21,19,18,17 clk->42 clr->11 countah(0..3)- >39,47,48,49 countbh(0..3)->66,67,70,71 countal(0..3)- >35,36,37,38 countbl(0..3)->61,62,64,65 lamp->79 souclk->83 speaker->3 2 NO.3 clock5 1024Hz clock1 4Hz 8 1 3/2 7/6 13-7-1 283 13.8 CHK 1 0 CLR 13-6 8 13-6 A B VHDL 13-21 CHK.vhd LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CHK IS PORT( DIN : IN STD_LOGIC ; -- CLK, CLR : IN STD_LOGIC ; -- / D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --8 AB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); -- END CHK; ARCHITECTURE behav OF CHK IS SIGNAL Q : INTEGER RANGE 0 TO 8 ; DIN CLK D[7..0] AB[3..0]

284 VHDL PROCESS( CLK, CLR ) IF CLR = '1' THEN Q <= 0 ; ELSIF CLK'EVENT AND CLK='1' THEN -- CASE Q IS WHEN 0=> IF DIN = D(7) THEN Q <= 1 ; ELSE Q <= 0 ; END IF ; WHEN 1=> IF DIN = D(6) THEN Q <= 2 ; ELSE Q <= 0 ; END IF ; WHEN 2=> IF DIN = D(5) THEN Q <= 3 ; ELSE Q <= 0 ; END IF ; WHEN 3=> IF DIN = D(4) THEN Q <= 4 ; ELSE Q <= 0 ; END IF ; WHEN 4=> IF DIN = D(3) THEN Q <= 5 ; ELSE Q <= 0 ; END IF ; WHEN 5=> IF DIN = D(2) THEN Q <= 6 ; ELSE Q <= 0 ; END IF ; WHEN 6=> IF DIN = D(1) THEN Q <= 7 ; ELSE Q <= 0 ; END IF ; WHEN 7=> IF DIN = D(0) THEN Q <= 8 ; ELSE Q <= 0 ; END IF ; WHEN OTHERS => Q <= 0 ; END CASE ; END IF ; END PROCESS ; PROCESS( Q ) -- IF Q = 8 THEN AB <= "1010" ; -- A ELSE AB <= "1011" ; -- B END IF ; END PROCESS ; END behav ; GW48-CK DIN PIO10 CLR PIO8 CLK PIO9 8 D[7..0] PIO7 PIO0 AB[3..0] PIO43 PIO40 7 1 NO.8 2 2 1 2 3 4 3 2 4 8 7 B 5 6(CLK) 8 8 7 B A B 13-8-1 13-8-2 13.9 13-7 LCNT8 8

13 VHDL LD 13-7 D 13-22 13-23 13-22 : LCNT8.vhd LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY LCNT8 IS -- 8 PORT ( CLK, LD : IN STD_LOGIC; -- / D : IN INTEGER RANGE 0 TO 255 ; --8 CAO : OUT STD_LOGIC ) ; -- END LCNT8 ; ARCHITECTURE behav OF LCNT8 IS SIGNAL COUNT : INTEGER RANGE 0 TO 255 ;--8 PROCESS( CLK ) IF CLK'EVENT AND CLK = '1' THEN IF LD = '1' THEN COUNT <= D; --LD ELSE COUNT <= COUNT + 1; -- END IF; END IF; END PROCESS; PROCESS( COUNT ) IF COUNT = 255 THEN CAO <= '1'; -- ELSE CAO <= '0'; END IF; END PROCESS; END behav; 13-23 : LCNT8.vhd LIBRARY IEEE; -- USE IEEE.STD_LOGIC_1164.ALL; ENTITY PULSE IS PORT ( CLK : IN STD_LOGIC; -- A B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);--8 PSOUT : OUT STD_LOGIC ); -- END PULSE; ARCHITECTURE mixed OF PULSE IS COMPONENT LCNT8 PORT ( CLK, LD : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CAO : OUT STD_LOGIC ); END COMPONENT; SIGNAL CAO1, CAO2 : STD_LOGIC; SIGNAL LD1, LD2 : STD_LOGIC; SIGNAL PSINT : STD_LOGIC; 285

286 VHDL U1 : LCNT8 PORT MAP( CLK => CLK, LD => LD1, D => A, CAO => CAO1 ); U2 : LCNT8 PORT MAP( CLK => CLK, LD => LD2, D => B, CAO => CAO2 ); PROCESS(CAO1, CAO2) -- IF CAO1 = '1' THEN PSINT <= '0'; ELSIF CAO2'EVENT AND CAO2 = '1' THEN PSINT <= '1' ; END IF ; END PROCESS; LD1 <= NOT PSINT ; LD2 <= PSINT ; PSOUT <= PSINT ; END mixed; GW48-CK 65536Hz 8 CLK B[7..0] PIO15 PIO8 4 3 D[7..0] 4 3 8 A[7..0] PIO7 PIO0 2 1 A 2 1 PSOUT -- NO.1 CLK clock0 Speaker( 1032E 5 Pin 5; EPF10K10 3 Pin 3) 2 1 ( 2 1) 4 3 ( 4 3) F=12MHz 6MHz 3MHz clk9 CLK CLK LD 13-9-1 13-23 13-8 13-9-1 13-8 (1) 13-24 B LCNT8 (2) EDA CLK CAO HALF FOUT CAO LCNT8 CLK LD D[7..0] PSOUT (3) CLK HALF FOUT CAO VCC PRN D Q CLRN 13-7

13 VHDL (4) HALF 1 HALF (5) FOUT D C HALF HALF FOUT (6) 13-24 : PULSE1.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY PULSE1 IS PORT ( CLK : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); FOUT : OUT STD_LOGIC ); END PULSE1; ARCHITECTURE behav OF PULSE1 IS SIGNAL COUNT : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL COMPIN : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL HALF, CAO, PDFF,LOAD : STD_LOGIC; LOAD <= CAO ; PROCESS( CLK, LOAD, D ) IF CLK'EVENT AND CLK = '1' THEN IF LOAD = '1' THEN COUNT <= D; ELSE COUNT <= COUNT + 1 ; END IF; END IF; END PROCESS; COMPIN(6 DOWNTO 0) <= D(7 DOWNTO 1); COMPIN(7) <= '1'; PROCESS( COUNT, COMPIN ) IF COUNT = 255 THEN CAO <= '1'; ELSE CAO <= '0' ; END IF; IF COUNT = COMPIN THEN HALF <= '1'; ELSE HALF <= '0'; END IF; END PROCESS; PROCESS(CAO, HALF) IF HALF = '1' THEN PDFF <= '0'; ELSIF CAO'EVENT AND CAO = '1' THEN PDFF <= '1'; END IF; END PROCESS; FOUT <= PDFF; END behav; 287 13.10 CPU MCU EDA

288 VHDL 13-9 (1) 13-9 SPEAKERA 13.10 clk 12MHz SPEAKERA SPKOUT D 1/2 SPEAKERA clk 11 Tone[10..0] SPKOUT Tone[10..0] SPKOUT TONETABA Tone[10..0]=1036 "3" 2 13-9 TONETABA SPEAKERA SPEAKER TONETABA NOTETABS 13 Index[3..0] NOTETABS clk 4Hz CLK12MHz CLK8Hz clk ToneIndex[3..0] TONETABA Tone[10..0] SPEAKERA clk Tone[10..0] 13 13-9 TONETABA 4 Index[3..0] Index[3..0] 16 TONETABA Index[3..0] ToneIndex[3..0] NOTETABS NOTETABS 8 138 4Hz 0.25 1 4 NOTETABS VHDL 3 4 1 3 1036 SPEAKERA 1 NOTETABS 4Hz VHDL : 13-25 : Songer.VHD LIBRARY IEEE ; -- USE IEEE.STD_LOGIC_1164.ALL ; SpkS SPKOUT

289 13 VHDL ENTITY Songer IS PORT ( CLK12MHZ : IN STD_LOGIC ; -- CLK8HZ : IN STD_LOGIC ; -- CODE1: OUT INTEGER RANGE 0 TO 15 ; -- HIGH1: OUT STD_LOGIC; -- SPKOUT: OUT STD_LOGIC ) ; -- END; ARCHITECTURE one OF Songer IS COMPONENT NoteTabs PORT ( clk : IN STD_LOGIC ; ToneIndex : OUT INTEGER RANGE 0 TO 15 ) ; END COMPONENT ; COMPONENT ToneTaba PORT ( Index : IN INTEGER RANGE 0 TO 15 ; CODE : OUT INTEGER RANGE 0 TO 15 ; HIGH : OUT STD_LOGIC ; Tone : OUT INTEGER RANGE 0 TO 16#7FF# ) ; END COMPONENT ; COMPONENT Speakera PORT ( clk: IN STD_LOGIC ; Tone: IN INTEGER RANGE 0 TO 16#7FF# ;--11 SpkS: OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL Tone : INTEGER RANGE 0 TO 16#7FF# ; SIGNAL ToneIndex : INTEGER RANGE 0 TO 15 ; -- U1 U2 U3 u1 : NoteTabs PORT MAP (clk=>clk8hz, ToneIndex =>ToneIndex ) ; u2 : ToneTaba PORT MAP (Index=>ToneIndex, Tone=>Tone, CODE=>CODE1, HIGH=>HIGH1 ) ; u3 : Speakera PORT MAP(clk=>CLK12MHZ,Tone=>Tone, SpkS=>SPKOUT ); END; 13-26 : ToneTaba.VHD LIBRARY IEEE ; -- USE IEEE.STD_LOGIC_1164.ALL ; ENTITY ToneTaba IS PORT (Index : IN INTEGER RANGE 0 TO 15 ; -- CODE : OUT INTEGER RANGE 0 TO 15 ; -- HIGH : OUT STD_LOGIC; -- Tone : OUT INTEGER RANGE 0 TO 16#7FF# );-- -- END ; ARCHITECTURE one OF ToneTaba IS Search : PROCESS(Index) CASE Index IS -- -- CODE HIGH WHEN 0 => Tone <= 2047 ; CODE <= 0 ; HIGH <= '0' ; WHEN 1 => Tone <= 773 ; CODE <= 1 ; HIGH <= '0' ; WHEN 2 => Tone <= 912 ; CODE <= 2 ; HIGH <= '0' ;

290 VHDL WHEN 3 => Tone <= 1036 ; CODE <= 3 ; HIGH <= '0' ; WHEN 5 => Tone <= 1197 ; CODE <= 5 ; HIGH <= '0' ; WHEN 6 => Tone <= 1290 ; CODE <= 6 ; HIGH <= '0' ; WHEN 7 => Tone <= 1372 ; CODE <= 7 ; HIGH <= '0' ; WHEN 8 => Tone <= 1410 ; CODE <= 1 ; HIGH <= '1' ; WHEN 9 => Tone <= 1480 ; CODE <= 2 ; HIGH <= '1' ; WHEN 10 => Tone <= 1542 ; CODE <= 3 ; HIGH <= '1' ; WHEN 12 => Tone <= 1622 ; CODE <= 5 ; HIGH <= '1' ; WHEN 13 => Tone <= 1668 ; CODE <= 6 ; HIGH <= '1' ; WHEN 15 => Tone <= 1728 ; CODE <= 1 ; HIGH <= '1' ; WHEN OTHERS => NULL ; END CASE ; END PROCESS ; END ; 13-27 : Speakera.VHD LIBRARY IEEE ; -- USE IEEE.STD_LOGIC_1164.ALL ; ENTITY Speakera IS PORT ( clk : IN STD_LOGIC ; -- Tone : IN INTEGER RANGE 0 TO 16#7FF# ;-- SpkS : OUT STD_LOGIC ) ; -- END ; ARCHITECTURE one OF Speakera IS SIGNAL PreCLK : STD_LOGIC ; SIGNAL FullSpkS : STD_LOGIC ; DivideCLK : PROCESS(clk) VARIABLE Count4 : INTEGER RANGE 0 TO 15 ; PreCLK <= '0' ; -- CLK 11 PreCLK CLK 11 IF Count4 > 11 THEN PreCLK <= '1' ; Count4 := 0; ELSIF clk'event AND clk='1' THEN Count4 := Count4 + 1; END IF; END PROCESS ; GenSpkS : PROCESS(PreCLK, Tone) VARIABLE Count11 : INTEGER RANGE 0 TO 16#7FF# ; IF PreCLK'EVENT AND PreCLK = '1' THEN -- 11 IF Count11 = 16#7FF# THEN Count11 := Tone; -- FullSpkS <= '1'; --11 FullSpkS ELSE Count11 := Count11 + 1; -- FullSpkS <= '0' ; END IF; END IF; END PROCESS; DelaySpkS : PROCESS(FullSpkS) -- VARIABLE Count2 : STD_LOGIC ; -- IF FullSpkS'EVENT AND FullSpkS = '1' THEN

13 VHDL Count2 := NOT Count2 ; IF Count2 = '1' THEN SpkS <= '1'; ELSE SpkS <= '0' ; END IF; END IF ; END PROCESS ; END ; 13-28 : NoteTabs.VHD LIBRARY IEEE ; -- USE IEEE.STD_LOGIC_1164.ALL ; ENTITY NoteTabs IS PORT ( clk : IN STD_LOGIC ; -- ToneIndex : OUT INTEGER RANGE 0 TO 15 ) ; -- END; ARCHITECTURE one OF NoteTabs IS SIGNAL Counter : INTEGER RANGE 0 TO 138 ; -- CNT8 : PROCESS(clk) IF Counter = 138 THEN Counter <= 0 ; ELSIF (clk'event AND clk='1') THEN Counter <= Counter + 1; END IF ; END PROCESS ; Search : PROCESS(Counter) CASE Counter IS -- WHEN 00 => ToneIndex <= 3; -- 3 WHEN 01 => ToneIndex <= 3; -- 4 WHEN 02 => ToneIndex <= 3; WHEN 03 => ToneIndex <= 3; WHEN 04 => ToneIndex <= 5; -- 5 WHEN 05 => ToneIndex <= 5; -- 3 WHEN 06 => ToneIndex <= 5; WHEN 07 => ToneIndex <= 6; -- 6 -- WHEN 136 => ToneIndex <= 0; -- WHEN 137 => ToneIndex <= 0; WHEN 138 => ToneIndex <= 0; WHEN OTHERS => NULL; END CASE; END PROCESS; -- END; GW48-CK CLK12MHz clock9 12MHz 12MHz clock9 12MHz Clock2 4Hz CLK8Hz clock2 4Hz 291 SPKOUT Speaker( 1) CODE1 PIO19 16 HIGH1 PIO36 SOF NO.1

292 VHDL 13-10-1 (1) 4 ToneIndex (2) NOTETABA (3) NOTETABA 9 512 13.11 RS232 VHDL FPGA/CPLD RS232 EDA PC RS232 FPGA/CPLD 1 FPGA/CPLD 13.10 ToneTaba.vhd Speakera.vhd, 13-30 TOP.VHD; 2 RS232 13-31 SEND.VHD 13-29 TOPTOP.VHD; 3 C PC SEND.C SEND.EXE 13-29 : TOPTOP.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY TOPTOP IS -- RS232 PORT ( CLK12MHZ : IN STD_LOGIC; CODE1 : OUT INTEGER RANGE 0 TO 15; HIGH1 : OUT STD_LOGIC; RXD : IN STD_LOGIC; D : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); SPKOUT : OUT STD_LOGIC ); END; ARCHITECTURE one OF TOPTOP IS COMPONENT SEND PORT(SYSCLK,RXD : IN STD_LOGIC; D : OUT STD_LOGIC_VECTOR(10 DOWNTO 0 ) ; KEY : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ) ); END COMPONENT; COMPONENT TOP PORT(CLK12MHZ : IN STD_LOGIC; INDEX1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CODE1 : OUT INTEGER RANGE 0 TO 15; SPKOUT,HIGH1 : OUT STD_LOGIC );

13 VHDL END COMPONENT; SIGNAL SEL : STD_LOGIC_VECTOR(7 DOWNTO 0); u1 : SEND PORT MAP(SYSCLK=>CLK12MHZ, RXD=>RXD,D=>D,KEY=>SEL); u2 : TOP PORT MAP(CLK12MHZ=>CLK12MHZ,CODE1=>CODE1, HIGH1=>HIGH1,SPKOUT=>SPKOUT,INDEX1=>SEL ); END; 13-30 : TOP.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY TOP IS -- PORT ( CLK12MHZ : IN STD_LOGIC; INDEX1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CODE1 : OUT INTEGER RANGE 0 TO 15; HIGH1, SPKOUT : OUT STD_LOGIC ); END; ARCHITECTURE one OF TOP IS COMPONENT ToneTaba PORT ( Index : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CODE : OUT INTEGER RANGE 0 TO 15; HIGH : OUT STD_LOGIC; Tone : OUT INTEGER RANGE 0 TO 16#7FF# ); END COMPONENT; COMPONENT Speakera PORT ( clk : IN STD_LOGIC; Tone : IN INTEGER RANGE 0 TO 16#7FF#; SpkS : OUT STD_LOGIC ); END COMPONENT; SIGNAL Tone2 : INTEGER RANGE 0 TO 16#7FF#; u1 : ToneTaba PORT MAP (Index=>Index1, Tone=>Tone2, CODE=>CODE1, HIGH=>HIGH1); u2 : Speakera PORT MAP (clk=>clk12mhz,tone=>tone2, SpkS=>SPKOUT ); END; 13-31 : SEND.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SEND IS PORT ( SYSCLK, RXD : IN STD_LOGIC; D : OUT STD_LOGIC_VECTOR(10 DOWNTO 0 ) ; KEY : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ) ); END SEND; ARCHITECTURE BEHAV OF SEND IS SIGNAL B : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL R : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL J : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL FRXD,GT,GTCLR,CCLK,GATE : STD_LOGIC; 293

294 VHDL S1: PROCESS (SYSCLK,GT) IF GT='0' THEN J <= (OTHERS=>'0',2=>'1',1=>'0'); ELSIF ( SYSCLK'EVENT AND SYSCLK='1') THEN IF J = "0000000110101000" THEN J <= (OTHERS=>'0'); ELSE J <= J + 1 ; END IF; END IF; END PROCESS; S2: PROCESS (J) IF J= "0000000110101000" THEN CCLK <= '0' ; ELSE CCLK <= '1'; END IF; END PROCESS; GATE <= GT AND CCLK ; S3: PROCESS (GATE,GTCLR) IF GTCLR = '1' THEN R <= "0001"; ELSIF ( GATE'EVENT AND GATE='1') THEN R <= R + 1 ; END IF; END PROCESS; S4: PROCESS (GATE,R) IF R = "1001" THEN GTCLR <= NOT GATE ; ELSE GTCLR <= '0'; END IF; END PROCESS; S5: PROCESS (GATE,RXD,B) IF ( GATE'EVENT AND GATE='1') THEN B(9 DOWNTO 0) <= B(8 DOWNTO 0) & RXD; END IF; END PROCESS; D(9 DOWNTO 0) <= B(9 DOWNTO 0); FRXD <= NOT RXD; S6: PROCESS (FRXD,GTCLR) IF GTCLR='1' THEN GT <= '0'; ELSIF ( FRXD'EVENT AND FRXD='1') THEN GT <= '1' ; END IF; END PROCESS; S7: PROCESS( B(8 DOWNTO 5) ) CASE B(8 DOWNTO 5) IS WHEN "0000" => KEY(0) <= '1' ; WHEN "0100" => KEY(1) <= '1' ; WHEN "1000" => KEY(2) <= '1' ; WHEN "0110" => KEY(3) <= '1' ; WHEN "1010" => KEY(4) <= '1' ; WHEN "0110" => KEY(5) <= '1' ;

13 VHDL WHEN "1110" => KEY(6) <= '1' ; WHEN "1001" => KEY(7) <= '1' ; WHEN OTHERS => KEY <= (OTHERS=>'0') ; END CASE; END PROCESS; END BEHAV; GW48-CK FSIN 1 GW48-CK RS232 PC 1 COM1 2 12MHZ CLOCK9 3 CLK12MHZ->3 RXD- >53 D(0..10)- >17,18,70,67,66,65,6 4,62,61,25,59, PC ASCII SPKOUT->3, ;4 NO.5 JMCU 5 MAX+PLUSII SENDSONG 13-10 8 TOPTOP 10K10 6 SEND.EXE PC 0 2 3 4 5 6 7 8 PC GW48 GW48 PC ASCII 0 2 3 4 5 6 7 8 GW48 13-11-1 SENDSONG VHDL C [I] RST [I] CLK [O]TSTEN [O]Load [O]CLR_CNT CLK DIN[31..0] GND Load DIN[31..0] CLK RST TESTCTL TSTEN CLR_CNT Load REG32B DOUT[31..0] DOUT[31..0] CLK CLR ENA CLK CLR ENA CLK CLR ENA CLK CLR ENA CLK CLR ENA CLK CLR ENA CLK CLR ENA CLK CLR ENA CNT10 CQ[3..0] CARRY_OUT CNT10 CQ[3..0] CARRY_OUT CNT10 CQ[3..0] CARRY_OUT CNT10 CQ[3..0] CARRY_OUT CNT10 CQ[3..0] CARRY_OUT CNT10 CQ[3..0] CARRY_OUT CNT10 CQ[3..0] CARRY_OUT CNT10 CQ[3..0] CARRY_OUT DIN[3..0] DIN[7..4] 295 DIN[11..8] DIN[15..12] DIN[19..16] DIN[23..20] DIN[27..24] DIN[31..28] 13-11

296 VHDL 13.12 13-10 13-35 8 TESTCTL 8 CNT10 32 REG32B (1) TESTCTL TSTEN 1 CNT10 ENA TSTEN Load 1 32 REG32B 7 CLR_CNT 1 13-11 D CLK CLK 1Hz TSTEN 1 Load CLR_CNT 13-11 TSTEN 1 Load 0.5 CLR_CNT TIMING SIMULATION 2 REG32B 32 BCD Load REG32B REG32B 7 3 CNT10 13-10 ENA 8 VHDL 13-32 CNT10.VHD LIBRARY IEEE ; -- USE IEEE.STD_LOGIC_1164.ALL ; ENTITY CNT10 IS PORT (CLK : IN STD_LOGIC ; -- CLR : IN STD_LOGIC ; -- ENA : IN STD_LOGIC ; -- CQ : OUT INTEGER RANGE 0 TO 15 ; -- 4 CARRY_OUT : OUT STD_LOGIC ) ; -- END CNT10 ; ARCHITECTURE behav OF CNT10 IS SIGNAL CQI : INTEGER RANGE 0 TO 15 ;

13 VHDL PROCESS(CLK, CLR, ENA) IF CLR = '1' THEN CQI <= 0; -- ELSIF CLK'EVENT AND CLK = '1' THEN IF ENA = '1' THEN IF CQI < 9 THEN CQI <= CQI + 1 ; ELSE CQI <= 0 ; END IF -- 9 END IF ; END IF ; END PROCESS ; PROCESS(CQI) IF CQI = 9 THEN CARRY_OUT <= '1' ; -- ELSE CARRY_OUT <= '0' ; END IF; END PROCESS ; CQ <= CQI ; END behav ; 13-33 REG32B.VHD LIBRARY IEEE ; --32 USE IEEE.STD_LOGIC_1164.ALL ; ENTITY REG32B IS PORT ( Load : IN STD_LOGIC ; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ; DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ) ; END REG32B ; ARCHITECTURE behav OF REG32B IS PROCESS(Load, DIN) IF Load'EVENT AND Load='1' THEN DOUT<=DIN ; -- END IF; END PROCESS; END behav; 13-34 TESTCTL.VHD LIBRARY IEEE ; -- USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY TESTCTL IS PORT (CLK : IN STD_LOGIC ; -- 1Hz TSTEN : OUT STD_LOGIC ; -- CLR_CNT : OUT STD_LOGIC ; -- Load : OUT STD_LOGIC ); -- END TESTCTL ; ARCHITECTURE behav OF TESTCTL IS SIGNAL Div2CLK : STD_LOGIC ; PROCESS( CLK ) IF CLK'EVENT AND CLK = '1' THEN -- 1Hz Div2CLK <= NOT Div2CLK ; 297

298 VHDL END IF ; END PROCESS ; PROCESS (CLK, Div2CLK) IF CLK='0' AND Div2CLK='0' THEN CLR_CNT<='1';-- ELSE CLR_CNT <= '0' ; END IF; END PROCESS; Load <= NOT Div2CLK ; TSTEN <= Div2CLK ; END behav ; 13-35 FREQTEST.VHD LIBRARY IEEE; -- USE IEEE.STD_LOGIC_1164.ALL; ENTITY FREQTEST IS PORT ( CLK : IN STD_LOGIC; FSIN : IN STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END FREQTEST; ARCHITECTURE struc OF FREQTEST IS COMPONENT TESTCTL PORT(CLK : IN STD_LOGIC; TSTEN : OUT STD_LOGIC; CLR_CNT : OUT STD_LOGIC; Load : OUT STD_LOGIC ); END COMPONENT; COMPONENT CNT10 PORT(CLK : IN STD_LOGIC; CLR : IN STD_LOGIC; ENA : IN STD_LOGIC; CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CARRY_OUT : OUT STD_LOGIC ); END COMPONENT; COMPONENT REG32B PORT ( Load : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; SIGNAL Load1, TSTEN1, CLR_CNT1 : STD_LOGIC; SIGNAL DTO1 : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL CARRY_OUT1 : STD_LOGIC_VECTOR(6 DOWNTO 0); U1 : TESTCTL PORT MAP(CLK => CLK, TSTEN => TSTEN1, CLR_CNT => CLR_CNT1, Load => Load1 ); U2 : REG32B PORT MAP( Load => Load1, DIN => DTO1,DOUT => DOUT); U3 : CNT10 PORT MAP(CLK => FSIN,CLR => CLR_CNT1,ENA => TSTEN1, CQ => DTO1(3 DOWNTO 0),CARRY_OUT => CARRY_OUT1(0) ); U4 : CNT10 PORT MAP(CLK => CARRY_OUT1(0), CLR => CLR_CNT1, ENA => TSTEN1, CQ => DTO1(7 DOWNTO 4), CARRY_OUT => CARRY_OUT1(1) ); U5 : CNT10 PORT MAP( CLK => CARRY_OUT1(1), CLR => CLR_CNT1, ENA => TSTEN1, CQ => DTO1(11 DOWNTO 8), CARRY_OUT => CARRY_OUT1(2) ); U6 : CNT10 PORT MAP( CLK => CARRY_OUT1(2), CLR => CLR_CNT1, ENA => TSTEN1, CQ => DTO1(15 DOWNTO 12), CARRY_OUT => CARRY_OUT1(3)); U7 : CNT10 PORT MAP( CLK => CARRY_OUT1(3), CLR => CLR_CNT1,

13 VHDL ENA => TSTEN1, CQ => DTO1(19 DOWNTO 16), CARRY_OUT => CARRY_OUT1(4) ); U8 : CNT10 PORT MAP( CLK => CARRY_OUT1(4),CLR => CLR_CNT1, ENA => TSTEN1, CQ => DTO1(23 DOWNTO 20), CARRY_OUT => CARRY_OUT1(5) ); U9 : CNT10 PORT MAP( CLK => CARRY_OUT1(5),CLR => CLR_CNT1, ENA => TSTEN1, CQ => DTO1(27 DOWNTO 24), CARRY_OUT => CARRY_OUT1(6) ); U10 : CNT10 PORT MAP( CLK => CARRY_OUT1(6),CLR => CLR_CNT1, ENA => TSTEN1, CQ => DTO1(31 DOWNTO 28) ); END struc; 299 GW48-CK CLK 1Hz Clock1 FSIN Clock0 8 DOUT[31..0] PIO47 PIO16 NO.0 Clock0 13-12-1 13.13 PC FPGA 13.11 PC RXD TXD 89C2051 1 2-13 FPGA 13.12 13.12 FREQTEST.VHD 13-36 FREQTEST.VHD P1 DINOUT INOUT 13-12 13-36 FSEND.ASM PC FTEST.C FTEST.EXE FPGA 1Hz-50MHz 89C2051 PC PC FPGA PC FPGA 13-36 FREQTEST.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FREQTEST IS PORT (CLK FSIN P37 : IN STD_LOGIC; DINOUT : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); SEL : IN STD_LOGIC_VECTOR(2 DOWNTO 0); DATAOUT : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) END FREQTEST; ARCHITECTURE struc OF FREQTEST IS COMPONENT TESTCTL

300 VHDL PORT ( CLK : IN STD_LOGIC; TSTEN : OUT STD_LOGIC; CLR_CNT : OUT STD_LOGIC; Load : OUT STD_LOGIC ); END COMPONENT; COMPONENT CNT10 PORT(CLK : IN STD_LOGIC; CLR : IN STD_LOGIC; ENA : IN STD_LOGIC; CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CARRY_OUT : OUT STD_LOGIC ); END COMPONENT; COMPONENT REG32B PORT(Load : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; SIGNAL TSTEN1 CLR_CNT1 Load1 K1,K2,K3 : STD_LOGIC; SIGNAL DTO1 DOUT : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL CARRY_OUT1 : STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL CLOCK1,CLOCK2,CLOCK3 : STD_LOGIC; SIGNAL DATA : STD_LOGIC_VECTOR(11 DOWNTO 0); SIGNAL DAT : STD_LOGIC_VECTOR(7 DOWNTO 0); U1 : TESTCTL PORT MAP( CLK => CLK, TSTEN => TSTEN1, CLR_CNT => CLR_CNT1, Load => Load1 ); U2 : REG32B PORT MAP( Load => Load1, DIN => DTO1,DOUT => DOUT); U3 : CNT10 PORT MAP(CLK => FSIN,CLR => CLR_CNT1,ENA => TSTEN1, CQ => DTO1(3 DOWNTO 0),CARRY_OUT => CARRY_OUT1(0) ); U4 : CNT10 PORT MAP(CLK => CARRY_OUT1(0), CLR => CLR_CNT1, ENA => TSTEN1, CQ => DTO1(7 DOWNTO 4), CARRY_OUT => CARRY_OUT1(1) ); U5 : CNT10 PORT MAP( CLK => CARRY_OUT1(1), CLR => CLR_CNT1, ENA => TSTEN1, CQ => DTO1(11 DOWNTO 8), CARRY_OUT => CARRY_OUT1(2) ); U6 : CNT10 PORT MAP( CLK => CARRY_OUT1(2), CLR => CLR_CNT1, ENA => TSTEN1, CQ => DTO1(15 DOWNTO 12), CARRY_OUT => CARRY_OUT1(3)); U7 : CNT10 PORT MAP( CLK => CARRY_OUT1(3), CLR => CLR_CNT1, ENA => TSTEN1, CQ => DTO1(19 DOWNTO 16), CARRY_OUT => CARRY_OUT1(4) ); U8 : CNT10 PORT MAP( CLK => CARRY_OUT1(4),CLR => CLR_CNT1, ENA => TSTEN1, CQ => DTO1(23 DOWNTO 20), CARRY_OUT => CARRY_OUT1(5) ); U9 : CNT10 PORT MAP( CLK => CARRY_OUT1(5),CLR => CLR_CNT1, ENA => TSTEN1, CQ => DTO1(27 DOWNTO 24), CARRY_OUT => CARRY_OUT1(6) ); U10 : CNT10 PORT MAP( CLK => CARRY_OUT1(6),CLR => CLR_CNT1, ENA => TSTEN1, CQ => DTO1(31 DOWNTO 28) ); Sch : PROCESS(SEL) CASE SEL IS WHEN "000" => DINOUT <= DOUT(7 DOWNTO 0);K1 <='0'; K2 <='0'; K3 <='0'; WHEN "001" => DINOUT <= DOUT(15 DOWNTO 8);K1 <='0'; K2 <='0'; K3 <='0';

13 VHDL WHEN "010" => DINOUT <= DOUT(23 DOWNTO 16);K1 <='0'; K2 <='0'; K3 <='0'; WHEN "011" => DINOUT <= DOUT(31 DOWNTO 24);K1 <='0'; K2 <='0'; K3 <='0'; WHEN "100" => DAT <= DINOUT; K1 <='1' ; WHEN "101" => DAT <= DINOUT; K2 <='1' ; WHEN "110" => DAT <= DINOUT; K3 <='1' ; WHEN OTHERS => K1 <='0'; K2 <='0'; K3 <='0'; END CASE; END PROCESS; CLOCK1<=K1 AND P37 ; CLOCK2<=K2 AND P37 ; CLOCK3<=K3 AND P37 ; KK1: PROCESS(CLOCK1) IF CLOCK1'EVENT AND CLOCK1 = '1' THEN DATA( 3 DOWNTO 0) <= DAT(7 DOWNTO 4); END IF; END PROCESS; KK2: PROCESS(CLOCK2) IF CLOCK2'EVENT AND CLOCK2 = '1' THEN DATA( 7 DOWNTO 4) <= DAT(7 DOWNTO 4); END IF; END PROCESS; KK3: PROCESS(CLOCK3) IF CLOCK3'EVENT AND CLOCK3 = '1' THEN DATA( 11 DOWNTO 8) <= DAT(7 DOWNTO 4); END IF; END PROCESS; DATAOUT <= DATA ; END struc; GW48-CK 1 NO.5 13-12 2 P37->25;SEL(0..2)->23,22,21;DINOUT(0..7)->39,47,48,49, 50,51,52,53 13-12 3 sendfre FREQTEST 4 5 5 DOS sendfre mcucom ftest.exe PC FPGA 6 PC PC 13-13-1 FPGA ADC0809 30 PC PC 301 13.14 VGA FPGA VGA VGA

302 VHDL 640X480/60Hz R G B HS VS HS VS CRT CRT X=0 Y=1 480 CRT VS=1 CRT X=0 Y=0 HS VS 13-12 13-12 HS VS 13-12 T1 6 s T2 26 s T3 CRT R G B VS=0 HS=0 CRT 26µs HS=1 6µs T4 480 13-13 3 6 1 1 2 2 1 2 3 1 1 2 2 R 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 13-13 13-37 13-37 COLOR.VHD LIBRARY IEEE ; -- USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY COLOR IS PORT ( CLK, MD : IN STD_LOGIC ; -- / HS, VS, R, G, B : OUT STD_LOGIC); -- / END COLOR ; ARCHITECTURE behav OF COLOR IS SIGNAL HS1, VS1, FCLK, CCLK : STD_LOGIC ; SIGNAL MMD : STD_LOGIC_VECTOR(1 DOWNTO 0) ; -- SIGNAL FS : STD_LOGIC_VECTOR (3 DOWNTO 0) ;

13 VHDL SIGNAL CC : STD_LOGIC_VECTOR(4 DOWNTO 0); -- / SIGNAL LL : STD_LOGIC_VECTOR(8 DOWNTO 0); -- / SIGNAL GRBX : STD_LOGIC_VECTOR(3 DOWNTO 1) ; --X SIGNAL GRBY : STD_LOGIC_VECTOR(3 DOWNTO 1) ; --Y SIGNAL GRBP : STD_LOGIC_VECTOR(3 DOWNTO 1) ; SIGNAL GRB : STD_LOGIC_VECTOR(3 DOWNTO 1) ; GRB(2) <= (GRBP(2) XOR MD) AND HS1 AND VS1 ; GRB(3) <= (GRBP(3) XOR MD) AND HS1 AND VS1 ; GRB(1) <= (GRBP(1) XOR MD) AND HS1 AND VS1 ; PROCESS( MD ) IF MD'EVENT AND MD = '0' THEN IF MMD = "10" THEN MMD <= "00" ; ELSE MMD <= MMD + 1; END IF -- END IF ; END PROCESS ; PROCESS( MMD ) IF MMD = "00" THEN GRBP <= GRBX ; -- ELSIF MMD = "01" THEN GRBP <= GRBY ; -- ELSIF MMD = "10" THEN GRBP <= GRBX XOR GRBY;-- ELSE GRBP <= "000" ; END IF ; END PROCESS ; PROCESS( CLK ) IF CLK'EVENT AND CLK = '1' THEN -- 12MHz 13 IF FS = 24 THEN FS <= "0000" ; ELSE FS <= FS + 1 ; END IF ; END IF ; END PROCESS ; FCLK <= FS(2) ; PROCESS( FCLK ) IF FCLK'EVENT AND FCLK = '1' THEN IF CC = 48 THEN CC <= "00000"; ELSE CC <= CC + 1 ; END IF; END IF ; END PROCESS ; CCLK <= CC(4) ; PROCESS( CCLK ) IF CCLK'EVENT AND CCLK = '0' THEN IF LL = 481 THEN LL <= "000000000" ; ELSE LL <= LL + 1 ; END IF ; END IF ; END PROCESS ; PROCESS( CC,LL ) IF CC > 23 THEN HS1 <= '0' ; -- 303

304 VHDL ELSE HS1 <= '1' ; END IF ; IF LL > 479 THEN VS1 <= '0' ; -- ELSE VS1 <= '1' ; END IF ; END PROCESS ; PROCESS(CC, LL) IF CC < 3 THEN GRBX <= "111" ; -- ELSIF CC < 6 THEN GRBX <= "110" ; ELSIF CC < 9 THEN GRBX <= "101" ; ELSIF CC < 12 THEN GRBX <= "100" ; ELSIF CC < 15 THEN GRBX <= "011" ; ELSIF CC < 18 THEN GRBX <= "010" ; ELSIF CC < 21 THEN GRBX <= "001" ; ELSE GRBX <= "000" ; END IF; IF LL < 60 THEN GRBY <= "111" ; -- ELSIF LL < 120 THEN GRBY <= "110" ; ELSIF LL < 180 THEN GRBY <= "101" ; ELSIF LL < 240 THEN GRBY <= "100" ; ELSIF LL < 300 THEN GRBY <= "011" ; ELSIF LL < 360 THEN GRBY <= "010" ; ELSIF LL < 420 THEN GRBY <= "001" ; ELSE GRBY <= "000"; END IF ; END PROCESS; HS <= HS1 ; VS <= VS1 ; R <= GRB(2) ; G <= GRB(3) ; B <= GRB(1) ; END behav ; GW48-CK NO.1 CLK CLOCK9 12MHz MD PIO49 KEY8 PIO49 6 1 2 1 2 1 2 13-14-1 VGA 13-14-2 VGA 13.15 A/D CPLD/FPGA A/D ADC0809 GW48-CK AD574A CPLD FPGA ADC0809 CPLD/FPGA A/D

13 VHDL ADC0809 8 A/D 100µs 13-14 8 IN0 IN7 ADDA ADDB ADDC ADDC 8 ALE 3 EOC 8 EOC START OE CLK ADC 500kHz A/D A/D EOC EOC OE [D0..D7] 13-15 ADC0809 ADCINT, [D0..D7] ADC0809 PIO23 PIO16 [QQ0..QQ7] 7 CK D3 8 8 7 PIO40 PIO47 ST clock0 ALE STA( START) IN0-7 EOC PIO33 PIO34 EOC PIO8 OE ADDA IN3 IN4 IN5 IN6 IN7 START EOC OE CLOCK VCC REF+ GND D1 START ADD-CBA OE [D7..D0] LOCK ALE 1 2 3 4 5 6 7 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 IN2 ADD-CBA 13-14 0809/0832 ADC0809 IN1 IN0 ADDA ADDB ADDC ALE D7 D6 D5 D4 D0 REF- D2 ADC0809 CLOCK PIO35 PIO32 305 A/D [D7..D0] 8 [IN0..IN7] ADD-C/B/A ALE A/D START 1(AIN1_VR1) 0809 IN1 OE EOC EOC 0809 ST 13-15 A/D ADC0809 VHDL * ADC0809 GW48- REF+ REF- ADC0809 /CS /WR1 AGND DIN3 DIN2 DIN1 DIN0 VREF RFB DGND OE EOC DAC0832 1 2 3 4 5 6 7 8 9 10 +5V 20 19 18 17 16 15 14 13 12 11 VCC ILE /WR2 /XFER DIN4 DIN5 DIN6 DIN7 IOUT2 IOUT1

306 VHDL 13-38 ADCINT.VHD LIBRARY IEEE ; --0809 USE IEEE.STD_LOGIC_1164.ALL ; ENTITY ADCINT IS PORT (DD : IN STD_LOGIC_VECTOR(7 DOWNTO 0);--8089 A/D ST,EOC : IN STD_LOGIC;-- ST EOC A/D ALE, STA : OUT STD_LOGIC ; -- ALE -- STA(START) OE, ADDA : OUT STD_LOGIC; -- OE ADDA QQ : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));-- END ADCINT ; ARCHITECTURE behav OF ADCINT IS SIGNAL QQQ : STD_LOGIC_VECTOR(7 DOWNTO 0) ; SIGNAL DK,CLR : STD_LOGIC ; -- DK A/D ADDA <= '1' ; -- IN1 OE <= NOT EOC ; CLR <= NOT EOC ; PROCESS (EOC) IF EOC='1' AND EOC'EVENT THEN QQQ <= DD ; -- A/D EOC END IF; END PROCESS ; PROCESS (CLR,ST) IF CLR='1' THEN DK <= '0'; -- D DK ELSIF ST='1' AND ST'EVENT THEN DK <= '1' ; -- ST DK 1 END IF; END PROCESS; ALE <= DK ; STA <= DK ; QQ <= QQQ ; END behav ; ADC0809 VHDL 13-39 D CLK DD ST START STA 13-39 ADCINT.VHD LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY ADCINT IS PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; CLK,EOC : IN STD_LOGIC ; OE, ADDA : OUT STD_LOGIC ; ALE, START : OUT STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ; -- QQ : OUT INTEGER RANGE 15 DOWNTO 0); -- 4 END ADCINT ; ARCHITECTURE behav OF ADCINT IS -- TYPE states IS (st0, st1, st2, st3, st4, st5, st6, st7) ;

13 VHDL SIGNAL current_state, next_state: states :=st0 ; SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0) ; SIGNAL LOCK : STD_LOGIC ; -- ADDA <= '1' ; -- IN1 PRO: PROCESS(current_state,EOC) -- CASE current_state IS WHEN st0=> QQ<=0 ; ALE<='0' ; START<='0' ; OE<='0' ; LOCK<='0' ; next_state<=st1; -- st0 st1 0809 WHEN st1=> QQ<=1 ; ALE<='1' ; START<='0' ; OE<='0' ; LOCK<='0' ; next_state<=st2; -- ALE 001 0809 WHEN st2=> QQ<=2 ; ALE<='1' ; START<='1' ; OE<='0' ; LOCK<='0' ; next_state <= st3 ; -- START WHEN st3=> QQ<=3; ALE<='1';START<='1';OE<='0';LOCK<='0';-- IF (EOC='0') THEN next_state <= st4; -- ELSE next_state <= st3 ; -- st3 END IF ; WHEN st4=> QQ<=4 ; ALE<='0' ; START<='0' ; OE<='0' ; LOCK<='0' ; IF (EOC='1') THEN next_state<=st5; --EOC 0 1 ELSE next_state <= st4 ; -- END IF ; WHEN st5=> QQ<=4 ; ALE<='0' ; START<='1' ; OE<='1' ; LOCK<='0' ; next_state <= st6 ; -- OE WHEN st6=> QQ<=5 ; ALE<='0' ; START<='0' ; OE<='1' ; LOCK<='1' ; next_state <= st7 ; -- START LOCK WHEN st7=> QQ<=6 ; ALE<='0' ; START<='0' ; OE<='1' ; LOCK<='1' ; next_state <= st0 ; -- WHEN OTHERS => next_state <= st0 ; END CASE ; END PROCESS PRO ; PRO PROCESS (CLK) -- IF ( CLK'EVENT AND CLK='1') THEN Current_state <= next_state ; -- END IF ; END PROCESS PRO;-- Current_state PRO PROCESS (LOCK) -- LOCK -- 8 IF LOCK='1' AND LOCK'EVENT THEN REGL <= D ; END IF; END PROCESS ; Q <= REGL; END behav; 13-16 GW48-CK NO.5A NO.5 GW48 1 A/D 0809 OE PIO35 0809 307

308 VHDL A/D PIO35 0809 2 0809 EOC PIO8 0809 0809 NO.5A 0809 CLOCK 750kHz 3 clock0 4 VR1 8 7 AD 13-16 13-15-1 ISPVHDL MAX+PLUSII 13.16 D/A D/A PLD D/A DAC0832 8 D/A 1µs 13-14 DAC0832 FPGA/CPLD 2 NO.5C 8 PIO24 PIO31 5V DAC0832 1 ILE PIN 19 5V 2 /WR1 /WR2 PIN 2 18 1 2 3 /XFER(PIN 17) 4 VREF PIN 8 10V 5 RFB PIN 9 6 IOUT1/ IOUT2 PIN 11 12 1 2 DAC0832 D/A 2 NO.5C 7 AGND/DGND PIN 3 10 VHDL 64 ( ) 13-40 DAC.VHD 10V

309 13 VHDL LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DAC IS PORT(CLK : IN STD_LOGIC; --D/A DD : OUT INTEGER RANGE 255 DOWNTO 0; -- DISPDATA : OUT INTEGER RANGE 255 DOWNTO 0);-- END; ARCHITECTURE DACC OF DAC IS SIGNAL Q : INTEGER RANGE 63 DOWNTO 0 ; SIGNAL D : INTEGER RANGE 255 DOWNTO 0 ; PROCESS(CLK) IF (CLK'EVENT AND CLK = '1') THEN -- Q <= Q + 1; END IF; END PROCESS; PROCESS(Q) CASE Q IS --64 WHEN 00=> D<=255 ; WHEN 01=> D<=254 ; WHEN 02=> D<=252 ; WHEN 03=> D<=249 ; WHEN 04=> D<=245 ; WHEN 05=> D<=239 ; WHEN 06=> D<=233 ; WHEN 07=> D<=225 ; WHEN 08=> D<=217 ; WHEN 09=> D<=207 ; WHEN 10=> D<=197 ; WHEN 11=> D<=186 ; WHEN 12=> D<=174 ; WHEN 13=> D<=162 ; WHEN 14=> D<=150 ; WHEN 15=> D<=137 ; WHEN 16=> D<=124 ; WHEN 17=> D<=112 ; WHEN 18=> D<= 99 ; WHEN 19=> D<= 87 ; WHEN 20=> D<= 75 ; WHEN 21=> D<= 64 ; WHEN 22=> D<= 53 ; WHEN 23=> D<= 43 ; WHEN 24=> D<= 34 ; WHEN 25=> D<= 26 ; WHEN 26=> D<= 19 ; WHEN 27=> D<= 13 ; WHEN 28=> D<= 8 ; WHEN 29=> D<= 4 ; WHEN 30=> D<= 1 ; WHEN 31=> D<= 0 ; WHEN 32=> D<= 0 ; WHEN 33=> D<= 1 ; WHEN 34=> D<= 4 ; WHEN 35=> D<= 8 ; WHEN 36=> D<= 13 ; WHEN 37=> D<= 19 ; WHEN 38=> D<= 26 ; WHEN 39=> D<= 34 ; WHEN 40=> D<= 43 ; WHEN 41=> D<= 53 ; WHEN 42=> D<= 64 ; WHEN 43=> D<= 75 ; WHEN 44=> D<= 87 ; WHEN 45=> D<= 99 ; WHEN 46=> D<=112 ; WHEN 47=> D<=124 ; WHEN 48=> D<=137 ; WHEN 49=> D<=150 ; WHEN 50=> D<=162 ; WHEN 51=> D<=174 ; WHEN 52=> D<=186 ; WHEN 53=> D<=197 ; WHEN 54=> D<=207 ; WHEN 55=> D<=217 ; WHEN 56=> D<=225 ; WHEN 57=> D<=233 ; WHEN 58=> D<=239 ; WHEN 59=> D<=245 ; WHEN 60=> D<=249 ; WHEN 61=> D<=252 ; WHEN 62=> D<=254 ; WHEN 63=> D<=255; WHEN OTHERS => NULL ; END CASE; END PROCESS; DD <= D; -- D/A DISPDATA <= D; -- D/A CLK -- END; GW48-CK NO.5C NO.5

310 VHDL (1) CLK clock0 DAC0832 (2) JP2 D/A JP1 clock0 4096Hz 0832 D/A D/A (3) clock0 4Hz 8 7 DAC0832 AOUT 13-16-1 0832 clock0 JP2 1 0 13.17 MCS-51 CPLD CPLD ALE P2 P0 FPGA/CPLD CPLD PSEN WR / RD A15--A8 A7-A0 A7-A0 8 8 / RAM A15--A8 A7-A0 8 13-17 MCS-51 13.17.1 FPGA/CPLD (1) 13-17 MCS-51 / MOV@DPTR A MOV A @DPTR (2) PLD I/O 13-18 DECOER 19 I/O FPGA/CPLD ( 13-18

13 VHDL 14 GWDVP ) (3) (4) FPGA/CPLD SRAM ROM 311 FPGA/CPLD READY WR RD WR RD P2 8 DECODER WR_ENABLE1 WR_ENABLE2 WR_ENABLE1 LATCH_OUT1 8 AD_CS DATOUT1 8031 8 P2 P0 8 ALE 8 RD_ENABLE WR_ENABLE2 LATCH_OUT2 8 DATOUT2 ALE LATCH_ADDRES I1 P0 8 8 LATCH1 LATCH_IN1 8 DATAIN1 DMA FPGA/CPLD A/D SRAM SRAM 13-18 CPLD/FPGA MCS-51 FPGA/CPLD 13-17 MCS-51 ALE 8 CPLD/FPGA LATCH_ADDRES ALE 8 P0 8 P2 PSEN ROM P0 PSEN P2 P0 8 8 ALE P0 8 FPGA/CPLD MOV A @DPTR RD P0 13-18 LATCH_IN1 A A FPGA/CPLD MOV @DPTR A WR DPTR 8 8 8 P2 P0 WR, A

312 VHDL 13.17.2 FPGA/CPLD PLD FPGA/CPLD 89C2051 97C2051 Z84 PIC16C5X 13-18 VHDL VHDL 13-41 MCS51.VHD LIBRARY IEEE; -- MCS51 FPGA/CPLD USE IEEE.STD_LOGIC_1164.ALL; ENTITY MCS51 IS PORT ( -- 8031 P0 : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- / P2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- 8 RD WR : IN STD_LOGIC; -- ALE : IN STD_LOGIC; -- READY : IN STD_LOGIC; -- AD_CS : OUT STD_LOGIC; -- A/D DATAIN1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- LATCH1 : IN STD_LOGIC; -- DATOUT1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- 1 DATOUT2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- 2 END MCS51; ARCHITECTURE behav OF MCS51 IS SIGNAL LATCH_ADDRES : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL LATCH_OUT1 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL LATCH_OUT2 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL LATCH_IN1 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL WR_ENABLE1 : STD_LOGIC; SIGNAL WR_ENABLE2 : STD_LOGIC; PROCESS( ALE ) -- 8 IF ALE'EVENT AND ALE = '0' THEN LATCH_ADDRES <= P0; -- ALE P0 8 END IF; -- LATCH_ADDRES END PROCESS; PROCESS( P2,LATCH_ADDRES ) -- WR 1 IF (LATCH_ADDRES="11110101") AND (P2="01101111") THEN WR_ENABLE1 <= WR ; -- ELSE WR_ENABLE1 <= '1'; END IF; -- END PROCESS; PROCESS( WR_ENABLE1 ) -- 1

13 VHDL IF WR_ENABLE1'EVENT AND WR_ENABLE1 = '1' THEN LATCH_OUT1 <= P0; END IF; END PROCESS; PROCESS( P2,LATCH_ADDRES ) -- WR 2 IF (LATCH_ADDRES="11110011") AND (P2="00011111") THEN WR_ENABLE2 <= WR ; -- ELSE WR_ENABLE2 <= '1'; END IF -- END PROCESS; PROCESS( WR_ENABLE2 ) -- 2 IF WR_ENABLE2'EVENT AND WR_ENABLE2 = '1' THEN LATCH_OUT2 <= P0; END IF; END PROCESS; PROCESS( P2,LATCH_ADDRES,READY,RD ) -- 8031 PLD IF (LATCH_ADDRES="01111110") AND (P2="10011111") AND (READY='1') AND (RD='0') THEN P0 <= LATCH_IN1 ; -- P0 ELSE P0 <= "ZZZZZZZZ" ; END IF -- P0 END PROCESS; PROCESS( LATCH1 ) IF LATCH1'EVENT AND LATCH1 = '1' THEN LATCH_IN1 <= DATAIN1; END IF; END PROCESS; -- CPLD PROCESS( LATCH_ADDRES ) -- A/D IF (LATCH_ADDRES="00011110") THEN AD_CS <= '0' -- A/D ELSE AD_CS <= '1' END IF -- A/D END PROCESS; DATOUT1 <= LATCH_OUT1 ; DATOUT2 <= LATCH_OUT2 ; END behav; CPLD 8031 VHDL 8031 8031 #5AH LATCH_OUT1 MOV A #5AH MOV DPTR #6FF5H MOVX @DPTR,A READY 8031 LATCH_IN1 MOV DPTR #9F7EH MOVX A @DPTR 13-17-1 8031 ADC0809 DAC0832 8031 3 15 8 313

314 VHDL DAC0832 8031 13.18 PS/2 PS/2 PS/2 VHDL FPGA/CPLD PS/2 PS/2 FPGA/CPLD 1 NO.5B PS/2 VHDL 13-42 kb2pc1.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY kb2pc1 IS PORT (SYSCLK : IN STD_LOGIC; RESET : IN STD_LOGIC; KBCLK : IN STD_LOGIC; KBDATA : IN STD_LOGIC; PDATA : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ); PARITY : OUT STD_LOGIC; DTOE : BUFFER STD_LOGIC); END kb2pc1; ARCHITECTURE one OF kb2pc1 IS SIGNAL CoState : STD_LOGIC_VECTOR( 1 DOWNTO 0 ); SIGNAL SPData : STD_LOGIC_VECTOR( 8 DOWNTO 0 ); SIGNAL Start Swto02 RecvEN : STD_LOGIC; SIGNAL Cnt8 : INTEGER RANGE 0 TO 15; Str1 : PROCESS( RESET, KBCLK, KBDATA, Start, CoState ) IF RESET = '1' THEN Start <= '0'; ELSIF KBCLK'EVENT AND KBCLK = '0' THEN IF CoState = "00" AND KBDATA = '0' THEN Start <= '1'; END IF; END IF; END PROCESS; Str2 : PROCESS( RESET, KBCLK, KBDATA, Start, CoState ) IF RESET = '1' THEN Swto02 <= '0'; ELSIF KBCLK'EVENT AND KBCLK = '1' THEN IF CoState = "00" AND Start = '1' AND KBDATA = '0' THEN Swto02 <= '1'; END IF; END IF; END PROCESS; ChState : PROCESS( RESET, SYSCLK, CoState, Swto02 ) IF RESET = '1' THEN CoState <= "00"; ELSIF SYSCLK'EVENT AND SYSCLK = '1' THEN IF Swto02 = '1' THEN CoState <= "01"; ELSIF Cnt8 = 9 THEN CoState <= "10";

13 VHDL END IF; END IF; END PROCESS; Recv : PROCESS( RESET, KBCLK, KBDATA, CoState ) IF RESET = '1' THEN Cnt8 <= 0; SPData <= "000000000"; ELSIF KBCLK'EVENT AND KBCLK = '0' THEN IF CoState = "01" THEN IF Cnt8 /= 9 THEN SPData( 7 DOWNTO 0 ) <= SPData(8 DOWNTO 1); SPData(8) <= KBDATA; Cnt8 <= Cnt8 + 1; END IF; END IF; END IF; END PROCESS; RecvEnd : PROCESS( RESET, KBCLK, RecvEN, CoState ) IF RESET = '1' THEN DTOE <= '0'; ELSIF KBCLK'EVENT AND KBCLK = '1' THEN IF Cnt8 = 9 AND CoState = "01" THEN DTOE <= '1'; END IF; END IF; END PROCESS; PARITY <= SPDATA(8); PDATA <= SPDATA(7 DOWNTO 0); END; 315 13.19 7 LED 7 LED 12 12.2 3 13-43 7 4 7 16 13-19 13-43 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY DECLED IS PORT ( CLK : IN STD_LOGIC ; DOUT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); --7 END DECLED ; ARCHITECTURE behav OF DECLED IS SIGNAL CNT4B : STD_LOGIC_VECTOR(3 DOWNTO 0);-- 4 PROCESS(CLK) - 4 IF CLK'EVENT AND CLK = '1' THEN CNT4B <= CNT4B + 1; -- CLK 1

316 VHDL END IF; END PROCESS; PROCESS(CNT4B) CASE CNT4B IS -- CASE_WHEN WHEN "0000" => DOUT <= "0111111"; -- 0 WHEN "0001" => DOUT <= "0000110"; -- 1 WHEN "0010" => DOUT <= "1011011"; -- 2 WHEN "0011" => DOUT <= "1001111"; -- 3 WHEN "0100" => DOUT <= "1100110"; -- 4 WHEN "0101" => DOUT <= "1101101"; -- 5 WHEN "0110" => DOUT <= "1111101"; -- 6 WHEN "0111" => DOUT <= "0000111"; -- 7 WHEN "1000" => DOUT <= "1111111"; -- 8 WHEN "1001" => DOUT <= "1101111"; -- 9 WHEN "1010" => DOUT <= "1110111"; -- A WHEN "1011" => DOUT <= "1111100"; -- B WHEN "1100" => DOUT <= "0111001"; -- C WHEN "1101" => DOUT <= "1011110"; -- D WHEN "1110" => DOUT <= "1111001"; -- E WHEN "1111" => DOUT <= "1110001"; -- F WHEN OTHERS => DOUT <= "0000000"; -- END CASE; END PROCESS; END behav; NO.6 CLK clock1 1 0~F NO.6 1 a b c d e f g I/O40~I/O46 CLK 7 13-19-1 13-19-2 26 26 7 26 g f e d c b a DOUT(6) DOUT(5) DOUT(4) DOUT(3) DOUT(2) DOUT(1) DOUT(0) 13-19 7 LED e f g a d b c

14 317 14 97 EDA 14.1 (1) 0.1Hz 70MHz (2) (3) 0.1 s 1s 0.01 s (4) 1 99 14.1.1 14-1 Tpr CNT1 CNT2 CNT1 CLK Fs CNT2 CLK 14-1 isplsi Fxe Fx D Q CNT1 CNT2 CNT1 CNT2 Fx

318 VHDL Fs Tpr Nx Ns Fx / Nx = Fs / Ns (14-1) Fx = ( Fs / Ns ) Nx (14-2) Fx Fxc Fs Fx Tpr Fx Nx Fs Ns et 1 Fx/Nx = Fs / Ns (14-3) Fxe / Nx = Fs / (Ns+ et) (14-4) Fx = (Fs / Ns) Nx (14-5) Fxe = [Fs / (Ns+ et )] Nx (14-6) Fxe Fxe = Fxe-Fx Fxe (14-5) (14-6) 14-7 et 1 Fxe Fxe = et Ns et Ns = Fxe Fxe 1 Ns 1 Ns (14-7) (14-8) (14-9) (14-10) Ns = Tpr Fs (14-11) (1) (2) Tpr Fs Ns (3) Fs/Fs (4) 14.1.2 VHDL 14-2 1. /

14 CONTRL FIN CONTRL FSD CONTRL CLR (1) TF=0 CONTRL CLR (2) CONTRL START CONT1 CONT2 (3) CONTRL START CONT1 CONT2 Fs (4) CONTRL EEND ADRB ADRA CONT1 CONT2 319 CHEKF FINPUT CHOICE START CLR/TRIG FSTD FCH CHKF FIN FOUT CHOIS I_35 CONTRL FIN CLK1 START EEND CLR CLK2 FSD CLRC I_34 ADRA ADRB CONT1 OO0 OO1 CLK OO2 CLR OO3 A OO4 B OO5 OO6 OO7 I_33 B0 B1 B2 B3 B4 B5 B6 B7 TF EEND CONTRL2 FIN PUL START ENDD CLR I_31 CLK2 FSD CNL PUL GATE CLKOUT I_32 END CONT2 OO0 OO1 CLK OO2 CLR OO3 A OO4 B OO5 OO6 OO7 I_4 A0 A1 A2 A3 A4 A5 A6 A7 2 14-3 D START FIN Q FIN CLK1 FSD CLK2 EEND D START FIN FIN CLK1 FSD CLK2 3 14-2 CONT1/CONT2 32 8 4 32 14-2 4 14-4 (CONTRL2) 50% FIN CLR START 14-4 CONTRL2 PUL

320 VHDL GATE PUL FSD (1) CONTRL2 CLR (2) GATE CNL CONT2 (3) CONTRL2 PUL CONT2 (4) CONTRL2 PUL CONT2 (5) CONT2 14-3 CONTRL2 CONTRL2 PUL PUL PUL ENDD PUL CONTRL2 CONT2 N1 CONT2 N2 FIN START VCC VCC VCC D Q D Q D C CLR CONTRL2 GT QQ2 PL QQ3 END 14-4 = N1 N1+N2 100% C C Q PUL ENDD 14.1.3 VHDL VHDL 13-1 CNT1 CNT2 counter.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT IS PORT (A, B, CLK, CLR: IN STD_LOGIC; OO: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); Q: OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );

END CNT; ARCHITECTURE behav OF CNT IS 14 SIGNAL CNT : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); PROCESS(CLK, CLR) IF CLR = '1' THEN CNT <= (OTHERS =>'0'); ELSIF CLK'EVENT AND CLK = '1' THEN CNT <= CNT + 1; END IF; END PROCESS; PROCESS(A, B) END behav; SEL(0) <= A; SEL(1) <= B; IF SEL = "00" THEN OO <= CNT(7 DOWNTO 0); ELSIF SEL = "01" THEN OO <= CNT(15 DOWNTO 8); ELSIF SEL = "10" THEN OO <= CNT(23 DOWNTO 16); ELSIF SEL = "11" THEN OO <= CNT(31 DOWNTO 24); ELSE END PROCESS; Q <= CNT; 13-2 FCH FIN.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FIN IS OO <= "00000000"; END IF; PORT ( CHKF, FIN, CHOIS : IN STD_LOGIC; END FIN; ARCHITECTURE rtl OF FIN IS FOUT : OUT STD_LOGIC ); FOUT <= (FIN AND CHOIS) OR (CHKF AND NOT CHOIS); END rtl; 13-3 CONTRL CONTRL.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CONTRL IS PORT ( FIN, START, CLR, FSD : IN STD_LOGIC; CLK1, EEND, CLK2, CLRC : OUT STD_LOGIC ); 321

322 VHDL END CONTRL; ARCHITECTURE mix OF CONTRL IS SIGNAL QQ1 : STD_LOGIC; PROCESS(FIN, CLR, START) IF CLR = '1' THEN Q1 <= '0'; ELSIF FIN'EVENT AND FIN = '1' THEN QQ1 <= START; END IF; END PROCESS; CLRC <= CLR; EEND <= QQ1; CLK1 <= FIN AND QQ1; CLK2 <= FSD AND QQ1; END mix; 13-4 CONTRL2 CONTRL2.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CONTRL2 IS PORT ( FIN, START, CLR : IN STD_LOGIC; END CONTRL2; ENDD, PUL : OUT STD_LOGIC ); ARCHITECTURE behav OF CONTRL2 IS SIGNAL QQ : STD_LOGIC_VECTOR(3 DOWNTO 1); SIGNAL A0, B0, C0, F2 : STD_LOGIC; SIGNAL S : STD_LOGIC_VECTOR(1 DOWNTO 0); S(0) <= QQ(3); S(1) <= QQ(2); PROCESS(START, S) IF START = '1' THEN F2 <= FIN; ELSE F2 <= NOT FIN; IF S = 2 THEN PUL <= '1'; ELSE PUL <= '0'; END IF; END IF; IF S = 3 THEN ENDD <= '1'; ELSE ENDD <= '0'; END PROCESS; END IF; A0 <= F2 AND QQ(1); B0 <= NOT A0; C0 <= NOT F2; PROCESS(C0, CLR)

IF CLR = '1' THEN 14 QQ(1) <= '0'; ELSIF C0'EVENT AND C0 = '1' THEN QQ(1) <= '1'; END IF; END PROCESS; PROCESS(A0, CLR) IF CLR = '1' THEN QQ(2) <= '0'; ELSIF A0'EVENT AND A0 = '1' THEN QQ(2) <= '1'; END IF; END PROCESS; PROCESS(B0, CLR) IF CLR = '1' THEN QQ(3) <= '0'; ELSIF B0'EVENT AND B0 = '1' THEN QQ(3) <= '1'; END IF; END PROCESS; END behav; 13-5 GATE GATE.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY GATE IS PORT (CLK2, FSD, CNL, PUL : IN STD_LOGIC; END GATE; ARCHITECTURE behav OF GATE IS CLKOUT : OUT STD_LOGIC ); PROCESS(CLK2, PUL, FSD, CNL) IF CNL = '0' THEN CLKOUT <= CLK2; ELSE END PROCESS; END behav; CLKOUT <= PUL AND FSD; END IF; 14-2 323 14.1.4 14-5 89C51

324 VHDL isplsi1032e 89C51 1032E 7 LED 60MHz 1.1 10-8 8 (1) 14-5 7PIN 8 4094 89C51 P1.0 8 4094 PIN15 P1.1 PIN2 P1.2 PIN3 8 4014 (2) FSTD 60MHz (3) FINPUT AMPL FIN (4) STADF CHEKF VCC P10 P11 P12 P13 P14 P15 P16 P17 P33 P32 P35 P34 EA X1 X2 RST P37 P36 12MHz 1 2 3 4 5 6 7 8 13 12 15 14 31 19 18 9 17 16 C2 AT89C51 33p C1 33p 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 10 11 30 10k R1 P00 P01 P02 P03 P04 P05 P06 P07 P20 P21 P22 P23 P24 P25 P26 P27 RXD TXD ALE E1 RST VCC + A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 P30 P31 P32 P33 P34 P35 P36 P37 11 12 13 14 15 16 17 18 26 27 28 29 30 31 32 33 34 LATTICE ISPLSI1032E PLCC84 END TF CHOICE START CLR/TRIG EEND ADRB ADRA 35 36 37 38 39 40 41 67 84 3 60MHz VCC FSTD 1 2 FINPUT CHEKF 61 VCC 4 2MHz STADF P10 P11 P12 P13 P14 FIN DS AMPL 14-5 14.1.5 (1) TF P31 TF = 0 TF = 1 (2) CLR/TRIG P34 TF = 0 TF = 1 CLR/TRIG CONT2 (3) END P3.0 END = 1 (4) CHOICE P3.2 / CHOICE = 1 CHOICE = 0 (5) START P3.3 TF = 0

14 START=1 TF = 1 START START=0 START=1 (6) EEND P3.5 EEND = 0 (7) ADRA ADRB AD = [ADRB ADRA] AD=0 1 2 3 P0 P2 8 8 4 8 325 14.2 VHDL 14-6 EDA FPGA CPLD ROM/RAM A/D D/A P3.1 KEY1 FPGA/CPLD 1 GWDVP GWDVP GW48-CK 1 GW48-CK 10 2 GWDVP GW48-CK FPGA/CPLD GW48-CK GWDVP FPGA/CPLD 3 GWDVP FPGA/CPLD GW48-CK 2 14-6 93C46 P3.0 AT89C51 KEY2 GWDVP 50MHz 12MHZ KEY3 CON1 KEY4 CD4053 CD4053 FPGA/CPLD CD4053 1 89C51 FPGA/CPLD KEY5 KEY6 27C512/62256 AD574J KEY7 CON2 KEY8 DAC0832 DAC0832 14-6 GWDVP 356 356 356 356 356 D1 D2 D3 D4 D5 D6 D7 D8 CD4051 CD4052

326 VHDL ROM/RAM 13 13.17 A/D DMA 2 8 8 P3.0 P3.1 2 A/D D/A 3 ROM/RAM GWDVP 4053 DMA ROM/RAM FPGA/CPLD 27C512 W27E512 27C256 27C128 27C64 28C64 28E64 6264 62256 4 FPGA/CPLD 48 GWDVP FPGA/CPLD isplsi1032 isplsi1048 isplsi3256 EPM7128S EPF10K10 EPF10K20 EPF10K30 EPF6016 XCS10 XC95108 5 D/A ADC0832 ROM/RAM 8 6 A/D AD574 AD674 AD1674-10V +10V 12 +10V 1 /10us LM356 4052 FPGA/CPLD 7 EEPROM 93C46 8 GWDVP 8 8 16 8 14-1 13 13.13 RS232 PC 89C51 ISP1032E VHDL 14-2 93C46 2 GWDVP 93C46 VHDL FPGA 93C46

327 1 EDA 1 GW48 EDA EDA VHDL GW48-CK (1) GW48-CK ASIC Lattice Xilinx Altera Vantis Atmel Cypress PLD isp CPLD/FPGA (2) PC DSP 2.5V 1.8V FPGA/CPLD 5V FPGA Altera EPF10K 10KA 10KE 1K 2K 20K GW48 FPGA/CPLD (5V 3.3V 1.5V 1.8V) FPGA CPLD (3) GW48 I/O LG I/O CPLD/FPGA I/O / (4) 2 GW48 1.1 GW48-CK 1-1 GW48-CK EDA SW9

328 VHDL 1. 2. PLD 3. FPGA CPLD 1)SW9 12 2 14 NO.3 SW9 SWG9 3 NO.3 SWG9 A JP1B 2)B2 FPGA/CPLD CPLD FPGA 3 3) J3B/J3A GWDVP GW48 J3A J3B FPGA/CPLD +5V FPGA/CPLD ByteBlasterMV 4) J2 J2 EDA CPLD/FPGA J2 B2 ASIC PLD CPLD/FPGA 5) 1~ 8 SW9 2 6) 1~8/D1~D16 2 7) JP1A/JP1B/JP1C JP1C CLOCK0 CLOCK0 1Hz 50MHz 14 JP1B JP1B 2Hz 1024Hz 12MHz JP1A CLOCK4 CLOCK7 CLOCK8 CLOCK4 CLOCK7 CLOCK8 JP1A/B 3 8) S1 JP1B SPEAKER PIO50 9) J7 PS/2 GW48

J4 50MZH 1 2 3 4 5 6 7 8 J5 JS6 JVCC 329 1 EDA J3A VGA J3B ByteBlaster ByteBlasterMV PS/2 JV2 JS5 B8 RS-232 GND +12V GND -12V +5V D8 D7 D6 D5 D4 D3 D2 D1 S1 C38 K1 JMCU J6 VGA B3 J1 2 1 RS-232 B4 J8 EDA J7 B2 SWG9 CPLD/FPGA J2 CON2 ASIC CON1 SW10 J10 ADC0809 AD1674/574A Clock0 J11 SW9 IN0 AIN0 IN1 AIN1 1-1 GW48-CK D9 D10 D11 D12 D13 D14 D15 D16 JP2 JP1A JP1B JP1C VR1 AOUT 8 7 6 5 4 3 2 1

330 VHDL PS/2 NO.5B 10 J6 VGA VGA VGA VGA NO.2 (11) NO.5B 12) J8 RS-232 PC PC FPGA/CPLD FPGA/CPLD PC NO.5B JMCU P3.0 P3.1 PIO31 PIO30 PC RS232 P3.0 P3.1 JMCU 13)AOUT/JP2 D/A NO.5C D/A AOUT JP2 JP2 1 D/A D/A WR PIO36 2 D/A D/A WR PIO36 3 0 to +5 D/A 0 +12V 4-5 to +5 D/A -12V +12V 5 0 1 D/A D/A 12 14) ADC0809/AIN0/AIN1 AIN0 AIN1 A/D ADC0809 IN0 IN1 ADC0809 ADC0809, NO.5A 0809 0809 0809 JP2 A/D 15) JP2 JP2 A/D A/D ENABLE(9) PIO35 A/D A/D ENABLE(9) 0 0809 JP2 EOC(7) PIO36 ADC0809 16) VR1/AIN1 VR1 0V~+5V 0809 IN1 AIN1 AIN1 VR1 IN1

331 1 EDA VR1 0809 25 IN1 17) AD574 AD574 A/D AD574 18) AIN0 LM311 D/A A/D 19)SW10 AT89C2051 (20)JS5/JS6 COMMON 5-VENDORs 21) J4 1-1 (22) 1032E SW9 NO.1 GW48 1032E I/O31~28 27~24 23~20 19~16 4 4 I/O 7 1023E16 FPGA/CPLD 0000 0001 0010... 1100 1101 1110 1111 0 1 2... C D E F D16 D15 4 1 1032E PIO0~PIO15 4 16 1 1 2..9 A..F I/O GW48 PIO 2 (25) FPGA/CPLD GW48 JV2 2.5V 1.8V JVCC I/O 3.3V(VCCIO) 5V VCC 5V VCC EP1K30/50/100 EPF10K30E/50E JVCC VCCIO JV2 +2.5V 5V VCC 1.2 1-2 (1 1-2a 16 7 7 7 7 a b c d e f g D C B A D A PIO19~16 PIO19 D 18 C 17 B

332 VHDL 16 A (2 1-2b (3 1-2c 16 8421 4 2 1 16 0000~1111 ^H0 ^HF 1 4 2 (4 7 7 1-5 NO.2 PIO46-PIO40 g f e d c b a PIO46 PIO45..PIO40 7 g f e d c b a (5 1-2d 20ms (6 NO.5 NO.5A NO.5B NO.5C 5 7 1-2e NO.3 1-2

333 1 EDA 8 7 6 5 4 3 2 1 D8 D7 D6 D5 D4 D3 D2 D1 PIO19-PIO16 PIO23-PIO20 PIO27-PIO24 PIO31-PIO28 PIO35-PIO32 PIO39-PIO36 PIO43-PIO40 PIO47-PIO44 SPEAKER FPGA/CPLD PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 D16 D15 D14 D13 D12 D11 PIO7--PIO2 PIO11-PIO8 PIO15-PIO12 8 7 6 5 4 3 HEX 2 HEX 1 NO.0 1-3 NO.0 1-4 NO.1

334 VHDL 1-5 NO.2 8 7 6 5 4 3 2 1 PIO19-PIO16 PIO23-PIO20 PIO27-PIO24 PIO31-PIO28 PIO35-PIO32 PIO39-PIO36 PIO43-PIO40 PIO47-PIO44 D8 D7 D6 D5 D4 D3 D2 D1 FPGA/CPLD PIO15 PIO14 PIO13 PIO12 PIO11 PIO10 PIO9 PIO8 PIO15-PIO8 PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 PIO1 D9 D16 D15 D14 D13 D12 D11 D10 PIO0 SPEAKER 8 7 6 5 4 3 2 1 NO.3 1-6 NO.3

335 1 EDA 1-7 NO.4 8 7 6 5 4 3 2 1 PIO19-PIO16 PIO23-PIO20 PIO27-PIO24 PIO31-PIO28 PIO35-PIO32 PIO39-PIO36 PIO43-PIO40 PIO47-PIO44 D8 D7 D6 PIO15 PIO14 PIO13 D5 PIO12 D4 PIO11 D3 PIO10 D2 PIO9 D1 PIO8 D16 D15 D14 D13 D12 D11 D10 D9 SPEAKER FPGA/CPLD PIO15-PIO8 PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 PIO1 PIO0 8 7 6 5 4 3 2 1 NO.5 1-8 NO.5

336 VHDL 1-9 NO.6 8 7 6 5 4 3 2 1 PIO19-PIO16 PIO23-PIO20 PIO27-PIO24 PIO31-PIO28 PIO35-PIO32 PIO39-PIO36 D8 PIO47 D7 PIO46 D6 PIO45 D5 PIO44 D16 D15 D14 D13 D12 D11 D9 D4 PIO43 D3 PIO42 D2 PIO41 D1 PIO40 SPEAKER FPGA/CPLD PIO47-PIO40 PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 PIO0 8 7 6 5 4 3 2 1 NO.7 1-10 NO.7

337 1 EDA 1-11 NO.8 1-12 NO.9

338 VHDL D8 D7 D6 D5 D4 D3 D2 D1 D16 D15 D14 D13 D12 D11 D10 D9 ADEN ADEOC COMP DAWR COMM JP2(5/6) 21 20 19 18 8 15 14 17 7 25 22 9 6 1 3 5 7 9 11 13 15 17 19 JP2 2 4 6 8 10 12 14 16 18 20 EU1 (24) (23) C29 103 ADC0809 PIO35 PIO8 FPGA/CPLD PIO23 PIO22 PIO21 PIO20 PIO19 PIO18 PIO17 PIO16 PIO8 msb2-1 2-2 2-3 2-4 2-5 2-6 2-7 lsb2-8 EOC ADD-A ADD-B ADD-C ALE ENABLE START PIO39-PIO36 PIO43-PIO40 PIO47-PIO44 PIO37 PIO38 DA0--+5 DA-5--+5 PIO32 102 C30 PIO33 PIO35 PIO34 750KHZA CLOCK 750KHZA 10 IN-0 IN-1 ref(+) ref(-) 12 16 26 27 1 +5V 2 FIT AIN0 AIN1 0 VCC 10K VR1 NO.5A SPEAKER 8 7 6 5 4 3 2 1 JP2(1/2,3/4) 8 7 6 5 4 3 2 1 PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 PIO1 PIO0 1-13 NO.5A

4 J7 PIO46 5 PS/2 PIO45 1 3 FPGA/CPLD 339 1 EDA D8 D7 D6 D5 D4 D3 D2 D1 PC D16 D15 D14 D13 D12 D11 D10 PIO39-PIO36 PIO43-PIO40 PIO47-PIO44 D9 5 3 2 12MHZA B4 PIO11 PIO12 PIO13 PIO14 RS-232 EU3 SPEAKER 10 9 8 7 6 5 4 3 2 1 GND P35 P34 P33 P32 X1 X2 P31 P30 RST P37 P10 P11 P12 P13 P14 P15 P16 P17 VCC 11 12 13 14 15 16 17 18 19 20 PIO15 PIO24 PIO25 PIO26 PIO27 PIO28 PIO29 PIO30 PIO31 8 7 6 5 4 3 2 1 VCC AT89C2051 NO.5B 8 7 6 5 4 3 2 1 PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 PIO1 PIO0 1-14 NO.5B

340 VHDL 1-15 NO.B 8 7 6 5 4 3 2 1 D8 D7 D6 D5 D4 D3 D2 D1 PIO15 PIO14 PIO13 PIO12 PIO11 PIO10 PIO9 PIO8 D16 D15 D14 D13 D12 D11 D10 D9 8 7 6 5 4 3 2 1 FPGA/CPLD DA-5--+5 1 103 0 DA0--+5 COMM JP2 6 PIO19-PIO16 PIO23-PIO20 PIO35-PIO32 PIO43-PIO40 PIO47-PIO44 PIO38 JP2(9,10) DAC0832 EU2 DAWR WR1 5 2 FB 9 PIO15-PIO8 PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 PIO1 PIO0 PIO24 PIO25 PIO26 PIO27 PIO28 PIO29 PIO30 PIO31 4 16 15 14 13 7 6 5 D0 D1 D2 D3 D4 D5 D6 D7 IOUT1 11 IOUT2 12 /CS WR2 XFER A GND D GND 1 18 17 3 10 VREF 8 VCC 20 +5 VCC PIO37 NO.5C 10K 102 FIT 5.1K 5.1K 7 TL082/2 R72 5.1K +12 51pFC27 8 2 1 3 4 2 TL082/1 3 LM311-12 COMP JP2(COMP) +5 AOUT AIN0 10K +12 8 4-12 VCC 1-16 NO.5C

341 1 EDA 1.3 GW48

342 VHDL * * * * ** * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

343 1 EDA

344 VHDL

VHDL 344 2 FPGA CPLD LATTICE 128-PIN PQFP/TQFP PLSI1048/C/E isplsi1048/c/e I/O59 GND I/O60 I/O61 I/O62 I/O63 I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 IN7 IN8 GND VCC GOE1 IN9 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 IN10 I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 I/O78 I/O79 I/O80 I/O81 I/O82 I/O83 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 I/O87 I/O86 I/O85 I/O84 GND 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 IN11 Y0 VCC GND ISPEN RESET SDI/IN0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O11 I/O10 GND I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 I/O18 I/O19 31 32 56 I/O20 I/O21 I/O22 I/O23 MODE/IN1 IN2 VCC GND SDO/IN3 IN4 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 GOE0 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 57 58 59 60 61 62 64 63 65 66 67 GND I/O36 I/O40 I/O41 I/O39 I/O38 I/O37 68 69 70 71 72 73 74 75 76 I/O42 I/O43 I/O44 I/O45 I/O46 77 78 79 81 80 82 83 84 85 I/O47 SCLK/IN5 Y3 Y2 GND VCC Y1 IN6 I/O48 86 87 88 89 90 91 92 93 94 95 96 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 I/O58 2-1 LATTICE isplsi1048c/e

FPGA/CPLD 345 I/O39 I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 GND IN6 I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 I/O56 LATTICE 84-PIN PLCC PLSI1032/E isplsi1032/e IN7 I/O63 I/O59 I/O58 I/O57 I/O62 I/O61 I/O60 Y0 VCC GND ISPEN RESET SDI/IN0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O8 I/O9 I/O7 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 MODE/IN1 GND SDO/IN2 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 IN3/SCLK I/O31 Y3 Y2 GND VCC Y1 IN4 IN5 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 12 13 14 15 16 17 18 19 20 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 2-2 LATTICE isplsi1032e I/O22/SGCK2 I/O21 I/O20 I/O19 I/O18 I/O17 I/O16 I/O15 I/O9 I/O14 I/O13 I/O10/TDI I/O12/TMS I/O11/TCK I/O8/PGCK1 I/O7/SGCK1 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I/O60 I/O59 I/O58 I/O57 I/O56 I/O55 I/O54/PGCK4 I/O53 I/O52/SGCK4(DOUT) I/O51(DIN) I/O50 I/O49 I/O48 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 I/O39/PGCK3 I/O38 I/O37/SGCK3 I/O36 I/O35 I/O34 I/O33 I/O32 I/O31 I/O30 I/O29(/INIT) I/O28 I/O27 I/O26 I/O25(/LDC) I/O24(HDC) I/O23/PGCK2 XCS05/XL XCS10/XL GND VCC CCLK GND VCC /PROGRAM VCC DONE GND GND VCC N.C. VCC MODE GND N.C. VCC GND VCC VCC GND GND O/TDO 84-PIN PLCC XILINX 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 12 13 14 15 16 17 18 19 20 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 2-3 XILINX XCS10/05

VHDL 346 I/O24 I/O23 I/O22 I/O21 I/O20 I/O19 I/O18 I/O17 I/O16 I/O15 I/O14 I/O11 I/O13 I/O12 I/O10/GCK3 I/O9 I/O8/GCK2 I/O7/GCK1 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I/O69 I/O67 I/O66 I/O65 I/O64 I/O63 I/O62/GTS2 I/O60 I/O61/GTS1 I/O59/GSR I/O58 I/O57 I/O56 I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I/O35 I/O34 I/O33 I/O32 I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 XC95108PC84 XC9572PC84 84-PIN PLCC XILINX GND VCCINT GND GND VCCINT GND GND GND VCCIO VCCIO VCCINT TMS TDO TDI TCK 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 12 13 14 15 16 17 18 19 20 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 2-4 XILINX XC95108/72-PC84 ATMEL 84-PIN PLCC ATF1508AS EPM7160S EPM7128S EPM7096S EPM7064S ALTERA I/O63 I/O62 I/O61 TDO I/O60 I/O59 I/O58 I/O57 I/O56 I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 IO47 I/O46 I/O45 TCK I/O44 I/O43 I/O42 I/O41 I/O40 I/O38 I/O39 I/O37 I/O36 I/O35 I/O34 I/O33 I/O32 I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 I/O23 I/O22 I/O21 I/O20 I/O19 I/O18 I/O17 I/O16 I/O15 TMS I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 TDI Note: Pin 6,39,46 and 79 are no-connect pins I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 IN4/OE2/GCLK2 IN3/GCLRn IN2/OE1 IN1/GCLK1 VCCIO VCCIO VCCIO VCCINT VCCIO VCCIO VCCIO VCCINT on EPM7096S and EPM7160S GND GND GND GND GND GND GND GND 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 12 13 14 15 16 17 18 19 20 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 2-5 ALTERA EPM7128S-PC84

FPGA/CPLD 347 I/O21 I/O20 I/O22 I/O23 I/O24 I/O38 I/O37 I/O36 I/O35 I/O34 I/O33 ntrst I/O32 I/O19 I/O18 I/O17 I/O16 I/O15 I/O14 I/O13 VCCINT DEV_OE DEV_CLRn GCLCK1 IN1 IN4 TMS TDO TDI I/O6/DATA1 I/O5/DATA2 I/O4/DATA3 I/O3/DATA4 I/O2/DATA5 I/O1/DATA6 I/O0/DATA7 I/O45/CLKUSR TCK I/O47/CS I/O46/nCS I/O49/nRS I/O48/nWS nceo CONF_DONE nstatus MSEL1 MSEL0 DATA0 DCLK nce I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 nconfig IN2 GCLK2 IN3 GNDINT I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O39 I/O40 I/O41 GNDINT INIT_DONE I/O42/RDYnBSY I/O43 I/O44 GNDINT VCCINT VCCINT GNDINT VCCINT VCCINT GNDINT VCCINT ALTERA EPF10K10LC84 FLEX 84-PIN PLCC 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 12 13 14 15 16 17 18 19 20 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 2-6 ALTERA EPF10K10-PC84 LATTICE 44-PIN PLCC isplsi2032/e PLSI1016/E isplsi1016/e I/O2 I/O1 I/O0 SDI/IN0 ISPEN VCC Y0 I/O31 I/O30 I/O3 I/O4 I/O5 I/O6 I/O7 GND SDO/IN1 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 SCLK/Y2 VCC Y1/RESET MODE/IN2 I/O15 I/O16 I/O17 I/O18 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 IN3 GND I/O23 I/O22 I/O21 I/O20 I/O19 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 44 43 42 41 40 2-7 208PIN-PQFP FPGA * 2-8 LATTICE isplsi1016

VHDL 348 RDYnBSY ALTERA 144-PIN TQFP 77 EPF10K30A 69 68 67 66 INPUT3 "CLOCK2" INPUT4 I/O94 I/O95 GCLOCK2 I/O60 "CLOCK1" "CLOCK8" INPUT1 INPUT2 GCLOCK1 "CLOK0" 93 92 91 90 89 88 87 86 85 84 83 82 I/O81 I/O80 I/O79 31 30 29 28 27 26 70 71 72 73 74 "CLOCK10" "CLOCK7" "CLOCK6" 65 64 63 61 62 VCCIO GNDIO VCCIO GNDINT GNDINT VCCINT VCCINT GNDIO VCCIO GNDIO I/O78 I/O77 I/O76 I/O75 I/O59 I/O58 I/O57 I/O56 I/O55 I/O54 "CLOCK5" "CLOCK4" "CLOCK3" "CLOCK9" "SPKER" 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EPF10K20 Total User I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GNDIO GNDIO GNDIO GNDIO GNDINT GNDINT GNDINT VCCIO VCCIO VCCIO VCCIO VCCINT VCCINT VCCINT VCCINT DEV_OE DEV_CLRn TMS DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 TDI nrs nws CS ncs DATA7 DATA6 nce DCLK nconfig nstatus MSEL1 MSEL0 I/O I/O I/O I/O GNDINT GNDIO INIT_DONE I/O I/O I/O I/O I/O CLKUSR VCCINT VCCIO TDO nceo CONF_DONE TCK 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2-9 ALTERA EPF10K20-TQ144 **

FPGA/CPLD 349 I/O I/O I/O "CLOCK10" PGCK3,I/O112 SGCK3,I/O111 110 109 108 I/O107 I/O106 I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 (INIT)I/O97 I/O96 95 I/O94 93 92 91 90 89 88 87 86 (HDC)I/O85 PGCK2,I/O84 83,SGCK2 82 81 I/O80, I/O79,TCK I/O78,TDI I/O77,PGCK1 I/O76 I/O54,PGCK4 I/O53 "CLOCK9" "CLOCK8" "CLOCK6" "CLOCK5" "CLOCK2" "CLOCK1" "CLOCK0" (DOUT)SGCK4,I/O52 (DIN)I/O51 "SPKER" I/O50 I/O49 48 47 46 45 44 43 42 I/O41 I/O40 39 38 37 36 35 I/O34 I/O33 I/O32 31 30 29 28 I/O27 I/O26 25 24 23 22 I/O21 I/O20 19 18 17 16 15 I/O14 I/O13 I/O12 11 10 9 8 I/O7 I/O6 I/O5 I/O0 I/O4 I/O3 I/O1 I/O2 I/O I/O I/O "CLOCK7" "CLOCK4" "CLOCK3" I/O 75 74 73 72 71 70 I/O69 I/O68 I/O67 I/O66 I/O65 I/O64 I/O63 62 61 60 59 I/O58 I/O57 I/O56 I/O55 VCC Don't Connect (LDC) GND VCC GND GND GND DONE O,TDO GND GND GND I/O GND,SGCK1 VCC VCC CCLK GND GND VCC GND PROGRAM VCC MODE GND Don't Connect GND VCC GND GND GND 138 144-PIN TQFP XCS30/XL XCS20/XL XCS10/XL XILINX TMS VCC 77 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 144 143 142 141 140 139 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2-10 XILINX XCS30-TQ144

350 VHDL 2-11 LATTICE isplsi3256/a/av-pq160 * GW48 2-7 208PIN-PQFP EP1K100 EPF10K30E EPF10K50E EPF10K100E EPF6016 ** VCCIO VCCINT GND 2-9 TQ144 ALTERA I/O EPF10K10 EPF10K20 EP1K30 VCCINT=2.5V VCCIO=3.3V EP1K50 VCCINT=2.5V VCCIO=3.3V GW48-CK

FPGA/CPLD 351 1 VHDL Reference Guide, Xilinx Inc. San Jose USA 1998. 2 DATA I/O INC. Synario Design Automation VHDL Reference Lattice Semiconductor Redmond Washington USA 1999 3 VHDL Language Reference Guide, Aldec Inc. Henderson NV USA 1999. 4 Lattice Inc. DATA BOOK Lattice Semiconductor Incorporation Redmond Washington USA 1999 5 Xilinx Inc. DATA BOOK Xilinx Incorporation San Jose USA 1999. 6 Altera Corporation DATA BOOK Altera Corporation San Jose CA 95134 USA 1999. 7 Vantis Corporation DATA BOOK Vantis Corporation Sunnyval CA 94088 USA 1998 8. VHDL. 2000. 9... 1996. 10.. VHDL... 1997. 11.. VHDL. 1999. 12. VHDL 1998

GW48-CK EDA 1) J3B/J3A J4 50MZH 1 2 3 4 5 6 7 8 J5 JS6 JVCC J3A VGA J3B ByteBlaster ByteBlasterMV PS/2 JV2 ASIC GWDVP GW48 J3A J3B FPGA/CPLD 1 5V FPGA CPLD 2 5V FPGA/CPLD EP1K30/50/100 EPF10K30E 2.5V ByteBlasterMV GW48 FPGA CPLD J3B 10 ByteBlasterMV (2) FPGA/CPLD GW48 5V 1 JV2 2.5V 1.8V 2 JVCC I/O 3.3V(VCCIO) 5V VCC 5V VCC EP1K30/50/100 EPF10K30E/50E JVCC VCCIO JV2 +2.5V 5V VCC 3 3 VCCIO JS5 B8 RS-232 GND +12V GND -12V +5V D8 D7 D6 D5 D4 D3 D2 D1 S1 C38 K1 JMCU J6 VGA B3 J1 2 1 RS-232 B4 J8 EDA J7 B2 SWG9 CPLD/FPGA J2 CON2 CON1 SW10 J10 ADC0809 AD1674/574A Clock0 J11 SW9 IN0 AIN0 D9 D10 D11 D12 D13 D14 D15 D16 JP2 IN1 AIN1 JP1A JP1B JP1C VR1 AOUT 8 7 6 5 4 3 2 1

GW48-CK EDA 1) J3B/J3A J4 50MZH 1 2 3 4 5 6 7 8 J5 JS6 JVCC J3A VGA J3B ByteBlaster ByteBlasterMV PS/2 JV2 ASIC GWDVP GW48 J3A J3B FPGA/CPLD 1 5V FPGA CPLD 2 5V FPGA/CPLD EP1K30/50/100 EPF10K30E 2.5V ByteBlasterMV GW48 isplsi3256a 10 ByteBlaster (2) FPGA/CPLD GW48 5V 1 JV2 2.5V 1.8V 2 JVCC I/O 3.3V(VCCIO) 5V VCC 5V VCC EP1K30/50/100 EPF10K30E/50E JVCC VCCIO JV2 +2.5V 5V VCC 3 3 VCCIO JS5 B8 RS-232 GND +12V GND -12V +5V D8 D7 D6 D5 D4 D3 D2 D1 S1 C38 K1 JMCU J6 VGA B3 J1 2 1 RS-232 B4 J8 EDA J7 B2 SWG9 CPLD/FPGA J2 CON2 CON1 SW10 J10 ADC0809 AD1674/574A Clock0 J11 SW9 IN0 AIN0 D9 D10 D11 D12 D13 D14 D15 D16 JP2 IN1 AIN1 JP1A JP1B JP1C VR1 AOUT 8 7 6 5 4 3 2 1