5 28-3D IC Low-Cost and TSV-free Monolithic 3D-IC with Heterogeneous Integration of Logic, Memory and Sensor Analogy Circuitry for Internet of Things 綉 3D IC (MOSFET) 40 50% 3D IC 3D IC IO(ultra-wide-IO) 6T SRAM ReRAM 3D IC 3D IC Abstract For the first time, a CO 2 far-infrared laser annealing (CO 2 -FIR-LA) technology was developed as the activation solution to enable highly heterogeneous integration without causing device degradation for TSV-free monolithic 3DIC. This process is capable to implement small-areasmall-load vertical connectors, gate-first high-k/metal gate MOSFETs and non-al metal interconnects. Such a far-infrared laser annealing exhibits excellent selective activation capability that enables performance-enhanced stacked sub-40nm UTB-MOSFETs (Ion-enhanced over 50 %). Unlike TSV-based 3D-IC, this 3D Monolithic IC enables ultra-wide-io connections between layers to achieve high bandwidth with less power consumption. A test chip with logic circuits,
NANO COMMUNICATION 23 No. 2-3D IC 29 6T SRAM, ReRAM, sense amplifiers, analog amplifiers and gas sensors was integrated to confirm the superiority in heterogeneous integration of proposed CO 2 -FIR-LA technology. This chip demonstrates the most variable functions above reported 3D Monolithic ICs. This CO 2 -FIR-LA based TSV-free 3D Monolithic IC can realize low cost, small footprint, and highly heterogeneous integration for Internet of Things. Keywords Monolithic 3DIC Far-infrared Ray Laser Annealing IC 3D IC (1) (2) (3) ( 1.a) 3D IC (~600 ) ( ) ( ) ( =10.6µm) (400 ) 3D IC 40 1 (a) 3DIC (b) 3D IC
5 30 I on 50 % 6T SRAM ReRAM 40nm 3D IC n/p SRAM ( ) / ( ) ( 1.b) ReRAM 3.1 6T-SRAM 2 n/p 216/178 A/ m ( Vd =1V) 88/92 mv/dec 2014 IEDM / ( 3a) 1.8um ( 3b) 6T-SRAM( 3C) 4 2 40nm n/p I d -V g 6T-SRAM / 6T-SRAM 150mV (V DD ) 0.5V 3.2 ( ) 1 ( 5d) 3 8 6 6(e) 100mV 7 3 (a) ( ) ( ) (b)0.18 m and (c) a 6T SRAM cell hold-snm
NANO COMMUNICATION 23 No. 2-3D IC 31 4 (a) 6T-SRAM array 6T-SRAM (b) hold, (c) read and (d) write (VDD = 1.0V, 0.7V and 0.5V) 7(e) (0.7V) (2.6V) ( 8)SET/RESET 3.3 3D-IC ( 9) twostage Differential Pair Single-ended Rail-to-rail Output Stage Unit Gain Bandwidth (GBW) khz IoT 10 3D-IC 3D IC 3D [1] Jo de Boeck, IoT: the Impact of Things, VLSI Tech. Dig., T82, 2015. [2] T. Yamauchi et al., Automotive Low Power Technology for IoT Society, VLSI Tech. Dig.,T80, 2015. 5 (a) (b) (c) (d) (e) Vdd=1V 3 8.
5 32 6 (a) (b) Sub-block (c) (d) (e) Vdd=1V 7 (a) (b) Sub-block (c) (d) (e) Vdd=0.7V 8 TiN(5nm)/HfO2(6nm)/Ti(5nm) 2.0V set/rest 9 Schematics of (a) (b) (c) (c) / [3] Y. F. Tsai et al., Design Space Exploration for 3-D Cache, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 4, pp. 444-455, Apr. 2008. [4] M.-F. Chang et al., Embedded 1Mb ReRAM in 28nm
NANO COMMUNICATION 23 No. 2-3D IC 33 Read Current-Sampling-Based Sense Amplifier for Small- Cell-Current Nonvolatile Memory, IEEE Journal of Solid-State Circuits, vol. 48, no. 3, pp. 864-877, March 2013. [7] M.-F. Chang et al., A 28nm 256Kb 6T-SRAM with 280mV Improvement in VMIN Using a Dual-Split- Control Assist Scheme IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 314-315, Feb. 2015. 10 (a),, SiO 2 /SiNx,,, and SnO 2 /Au (b) CMOS with 0.27-to-1V Read Using Swing-Sampleand-Couple Sense Amplifier and Self-Boost- Write- Termination Scheme, IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 332-333, Feb. 2014. [5] P.-F. Chiu et al., Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM with Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications, IEEE Journal of Solid-State Circuits, vol. 47, no. 6, pp. 1483-1496, June 2012. [8] C.-H. Shen et al., Heterogeneously Integrated sub- 40nm Low-power epi-like Ge/Si Monolithic 3D-IC with stacked SiGeC Ambient Light Harvester, IEDM Tech. Dig., p. 3.6, 2014. [9] C.-H. Shen et al., Monolithic 3D Chip Integrated with 500ns NVM, 3ps Logic Circuits and SRAM, IEDM Tech. Dig., p. 9.3, 2013. [10] L. Pasini et al., High Performance low temperature activated devices and Optimization Guidelines for 3D VLSI Integration of FD, TriGate, FinFET on Insulator, VLSI Tech. Dig.,T50, 2015. [11] K. Usuda et al., High-Performance Tri-Gate Poly-Ge Junction-Less P- and N-MOSFETs Fabricated by Flash Lamp Annealing Process, IEDM Tech. Dig., p.16.6, 2014. [6] M.-F. Chang et al., An Offset-Tolerant Fast-Random- 1 Comparison of monolithic 3D-IC technology ] 9 [