( ) 2005 2 27
1 70 :SSI(Small Scale Integration), 1 10,MSI (Medium Scale Integration),,, 80 LSI(Large Scale Integration),, 16,Motoral M68000(7 ),Intel 80286 (12.5 ),80386 (27.5 ) 90 : VLSI(Very Large Scale Integration), 32,80486, 100 ;98 Pentium III 1000 ULSI(Ultra LSI), GLSI(Giant LSI) SOC/SOPC : Intel Prescott ( Pentium 4E), 2GHz Pentium-M
SOC
SOPC
(ALTERA StartixII)
FIFO M512 RAM FIR DSP DDR PCI PCI-X SSTL-3 SSTL- 2HSTL-1 HSTL-2 LCDS Hyper I/O IOEs M-RAM DSP M4K RAM 9-76 STRIDIX
Evolution of Integration Density and Minimum Feature Size, as seen in the early 1980s
The integration density between the memory chips and logic chips Adapted from Mlynek, Daniel J
Moore s s Law in Microprocessors
Transition to Automation and Regular Structures Intel 4004 ( 71)( Intel 8080 Intel 8085 Intel 8286 Intel 8486 Courtesy Intel Design Methods 13
Pentium 3 & Alpha 21264 0.18µm,6M,CMOS 0.18,0.25,0.35µm,6M,CMOS Transistors: 28.1M 15.2M die size: 106 mm 2 210,210,314 mm 2
Pentium 4 Pentium 4 42M transistors / 1.3-1.8GHz / 49-55W L=0.18µm Pentium 4 Northwood 55M transistors / 2-2.5GHz L=0.13µm
Moore s s Law in Microprocessors 1000 100 2X growth in 1.96 years! Transistors (MT) 10 1 0.1 0.01 0.001 8085 8086 8080 4004 8008 386 286 486 P6 Pentium proc 1970 1980 1990 2000 2010 Year Adapted from Irwin & Nayaranan s Slides from PSU. Copyright 2002 J. Rabaey et al."
Die Size Growth 100 Die size grows by 14% to satisfy Moore s Law Die size (mm) 10 8080 8008 4004 386 8085 8086 286 486 P6 Pentium proc ~7% growth per year ~2X growth in 10 years 1 1970 1980 1990 2000 2010 Year Adapted from Irwin & Nayaranan s Slides from PSU. Copyright 2002 J. Rabaey et al."
Evolution in DRAM Chip Capacity Kbit capacity/chip 100000000 10000000 1000000 100000 10000 1000 100 64 10 256 1,000 4,000 1.6-2.4 µm 16,000 1.0-1.2 µm human memory human DNA 4X growth every 3 years! book page 64,000 0.7-0.8 µm 256,000 0.5-0.6 µm 1,000,000 4,000,000 0.35-0.4 µm 16,000,000 0.13 µm 0.18-0.25 µm 64,000,000 0.1 µm 1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010 Year 0.07 µm encyclopedia 2 hrs CD audio 30 sec HDTV Adapted from Irwin & Nayaranan s Slides from PSU. Copyright 2002 J. Rabaey et al."
Adapted from Irwin & Nayaranan s Slides from PSU. Copyright 2002 J. Rabaey et al."
3~30GHz
Power will be a major problem Power (Watts) 100000 10000 1000 100 10 1 0.1 8085 8086286 386 486 4004 80088080 Pentium proc 18KW 5KW 1.5KW 500W 1971 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive
Adapted from Irwin & Nayaranan s Slides from PSU. Copyright 2002 J. Rabaey et al."
SOC SOPC 1. 2. 3. EDA SOC 4. SOPC 5. IC 6. 7.
SIA(Semiconductor Industry Association) Roadmap Year 1999 2002 2005 2008 2011 2014 Feature size (nm) 180 130 100 70 50 35 Logic trans/cm 2 6.2M 18M 39M 84M 180M 390M Cost/trans (mc) 1.735.580.255.110.049.022 #pads/chip 1867 2553 3492 4776 6532 8935 Clock (MHz) 1250 2100 3500 6000 10000 16900 Chip size (mm 2 ) 340 430 520 620 750 900 Wiring levels 6-7 7 7-8 8-9 9 10 Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5 High-perf pow (W) 90 130 160 170 175 183
1. Transistors are smaller and denser 1999-2014: 180nm to 35nm 1999-2014: 6.2 to 390 M logic Trans/cm 2 Chip areas are larger 1999-2014:340 to 900mm 2 Clock 1999-2014: 1250 to 16900Mhz power 1999-2014:90 to 183W Interconnects are dense 1999-2014 :6 to 10 wiring levels
30~60%
Cache
SOC SOPC 1. 2. 3. EDA SOC 4. SOPC 5. IC 6. 7.
2 (50~70%,0.35um)
2
2 ASIC (0.8um--1,0.5um- -5,0.35um-->10 )
SOC SOPC 1. 2. 3. EDA SOC 4. SOPC 5. IC 6. 7.
3 EDA SOC Single Pass, Physical Synthesis Floorplanning IP SOC
SOC SOPC 1. 2. 3. EDA SOC 4. ASIC 5. IC 6. 7.
4 ASIC 1985 Xillinx XC2000 PLC CLB PRR PIO 400~500MHz 0.09-0.18 m 6-9 SOPC FPGA DSP MCU RAM PCI XILINX Virtex-II Pro,Altera Stratix
ASIC
SOC SOPC 1. 2. 3. EDA SOC 4. SOPC 5. IC 6. 7.
5 IC (Embeded System) (, ): DSP,,RAM,ROM., (Cable Modem, 1G ): (Mpeg Decoder Encoder, STB, IA ATI R420
5 IC IC
We must,but,but
MOS transistor scaling (2003ITRS) Technology-node cycles the period of time in which a new technology node is reached CARR(3yrs) =0.5 Λ0.1667-1 =-10.9% CARR(2yrs) =0.5 Λ 0.25-1 =-15.9%
SOC SOPC 1. 2. 3. EDA SOC 4. SOPC 5. IC 6. 7.
6 Technology shrinks by ~0.7 per generation But How to design chips with more and more functions? Design engineering population does not double every two years Adapted from Mani Srivastava s Slides. Copyright 2003
6 10,000,000 10,000 1,000,000 1,000 100,000 100 10,000 10 1,0001 100 0.1 0.01 10 Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity growth rate 100,000,000 10,000,000 1,000,000 100,000 10,000 1,0001 100 0.1 0.001 1 10 0.01 1981 1983 1985 1987 1989 1991 1993 Complexity Logic Transistor per Chip (M) Productivity (K) Trans./Staff - Mo. 1995 1997 1999 2001 2003 2005 2007 2009 Source: Sematech A growing gap between design complexity and design productivity f C ( d ) C
6
6 5000 100 2 4900, 20 3000.
6 960000 trans/month each designers Months until completion 4500 4000 3500 3000 2500 2000 1500 1000 5 10 15 20 25 30 35 40 42.6 24 18.3 16 15.4 16 18.3 24
6 Transistors per team per month 60000 50000 40000 30000 20000 43 10000 Team 16 15 16 19 18 24 23 Months until completion Individual 0 10 20 30 40 Number of designers [Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]
SOC SOPC 1. 2. 3. EDA SOC 4. SOPC 5. IC 6. 7.
7 EDA
2X growth in 1.96 year 7% growth per year 2X growth in 10 in year 4X growth every 3 year
A4 2 4