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1 First International omputer,inc Protable omputer Group HW epartment oard name : Mother oard Schematic. Schematic Page escription : Project : LEN/LN. PI & IRQ & M escription : Version : 0.. lock iagram : Initial ate : ecember/ 00. Nat name escription :. oard Stack up escription :. Schematic modify Item and History :. power on & off & S Sequence :. Layout Guideline : Manager Sign by : Eric_Yang rawing by : Spruce Wu Total confirm by :dam ho LN ircuit check by : Vivian hen udio ircuit check by : nnie Wang. switch setting FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ) Size ocument Number Rev 0. Thursday, June 0, 00 ate: Sheet of

2 POWER RILS P0: TITLE P: R POWER P0: TOP SHEET P: RT & TVOUT P0: LOK IGRM P: L & LI NN P0: NNOTTIONS P: EXTERNL LOK GENERTOR P0: SHEMTI MOIFY P: M PI/IS I/F P0: TIMMING P: M US, IE, F... P0: LYOUT GUIE- P: RESET IRUIT P0: LYOUT GUIE- P: ROM NN P0: SWITH SETTING P: IOS & RT P0: P NORTHWOO(/) P0: PRLLEL/SERIL PORT P: P NORTHWOO(/) P: K VER:. P: P POWER P: INT K/ /GP/LE NN P: THERML SENSE P: IP SW/PS/EUG NN P: RS00M-GTL P: Intel Lan i0ep P: RS00M-R I/F P: US.0 up000 P: RS00M-PI&GP I/F P: US NN P: RS00M-VIEO I/F & LK P: R(ardus) P: SYSTEM ONFINGURTION P: ardus Power/NN P: R SO-IMMS P: MINI PI TYPE P0: R TERMINTIONS P0: M NN P: SI P: LP PMU0 VM V VM V P: PTOR IN & IN VM.V P: PMUV & PMUV PMUV V S0-S PMUV.V S0-S P:.VM V V S0-S P: V/V V.V S0-S VS V S0-S P: VS/VS/VM/VM VS.V S0-S P: HRGE IRUIT VORE_PU VI[0..] P: HRGE OUTPUT SELET VI.V P0: OVER VOLTGE PROTET.VM.V P: OKING.VS.V S0-S P: UIO OR NN.VS.V P: VERS Y NN (IE).VM_N V.V P: MULTI Y NN (F) V.V SYSTEM P RS00M N L S00M S POWER PLV LV VOLTGE OFF IN S-S OFF IN S-S.V OFF IN S-S TRE 0 MIL.V.V TIVE SOPE OFF IN S-S OFF IN S-S OFF IN S-S OFF IN S-S OFF IN S-S OFF IN S-S OFF IN S-S OFF IN S-S OFF IN S-S ROUTING PLNE PLNE PLNE TRE 0 MIL TRE 0 MIL PLNE PLNE PLNE PLNE PLNEOPER TRE MIL PLNEOPER PLEOPER PLNEOPER TRE 0 MIL TRE 0 MIL TRE 0 MIL PGE RT_V.0V S0-S TRE 0 MIL V_K.V OFF IN S-S TRE 0 MIL S_V.V OFF IN S-S TRE MIL.VS.V S0-S TRE 0 MIL VS.V S0-S TRE 0 MIL.VM.V OFF IN S-S TRE 0 MIL VM_SIO.V OFF IN S-S TRE 0 MIL US_V.V S0-S TRE 0 MIL VORE_PU VI[0..] OFF IN S-S TRE 0 MIL TRE 0 MIL ISEL PIINT IRQ IRQ IRQ IRQ HIP HIP USMSTER REQ REQ0 / GNT0 REQ / GNT REQ / GNT REQ / GNT ardus & (RIHO R) Wireless LN US.0(NE up00) LN (INTEL 0EP) MiniPI/ardus/US.0 MiniPI/ardus/US.0 VG/ardus/US.0 LN/ardus HIP LN ardus Wireless LN US.0 M hannel M0 evice FIR M EP M FLOPPY ISK M UIO M (ascade) M Unused M Unused M Unused (disable by default) (MOEM / LN) IRQ hannel IRQ0 IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ0 IRQ IRQ IRQ IRQ IRQ esciption System timer Keyboard (asacde) LN / MOEM Serial Port UIO / VG / US FLOPPY ISK LPT RT PI (isable by default) FIR (MOEM/LN) ardbus PS/ mouse FPU H ROM Voltage Rails IN PMUV PMUV V VS VS VM VM VM Vcore_PU P Layers Layer Layer Layer Layer Layer Layer Layer Layer Primary system power supply.0v always on power rail by LTH or IN.V always on power rail by ON V always on power rail by PWR_TL or PSUS0.V power rail.0v power rail V switched power rail.v switched power rail.0v switched power rail.v switched power rail for PU TOP IN (HIGH SPEE) IN (HIGH SPEE) IN (OTHERS) V OTTOM FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ) Size ocument Number Rev TOP SHEET 0. Thursday, June 0, 00 ate: Sheet of

3 LOK IGRM THERML SENSE MX PENTIUM MOILE NORTHWOO -Pin ufpg 0- PU ORE 00MT/s 00 MHZ GTL/ LEVEL R POWER PTOR IN/IN PMUV/PMUV LVS ONN TVOUT ON MHZ LVS SVIEO/OMP TI N MOILE RS00M GTL/ P PU XFE INTEGRTE GPHIS LVS/TVOUT/TMS MHZ R 00/ UNUFFERE R SOIMM.VM V/V RT ON RT INTERNL LOK R /-LINK MHZ - Y.Mhz Y Mhz 00-PIN R SOIM Y.Mhz Y0.Mhz VS/VS VM/VM GRGE IRUIT GRGE OUT SELET OVER VOLTGE PROTET SI LP PMU0 0 US US RUS R PMI SLOTS PORT S/MS R US US0 Y.Mhz US.0 US.0 up000 Y 0Mhz MHZ MHZ Y.Khz -LINK MHZ LI S MOILE. T /00 PI. PI/PI GE IS US SUPER I/O - LINK MHZ PI MHZ T /00/ UIO OR ON M ON INTEL 0EP H ON 0 Y Mhz ROM ON ETHERNET RJ ON RESET IRUIT FLSH IOS FIR F SERIL LPT PORTS 0 0 MHZ IS US K V. Y Mhz Y.Khz XUS RT K INT MOUSE K/ GP ON FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ) Size ocument Number Rev LOK IGRM 0. Thursday, June 0, 00 ate: Sheet of

4 . Nat name escription : nother idea for Stack P Layers Trace Width mil mil mil mil Voltage Rails Trace Impedence: ohm_% IN Primary system power supply opper Trace Layer ielectric Layer Layer Width No Type Signals PMUV.0V always on power rail by LTH or IN /oz (MicroStrip) PMUV.V always on power rail by LTH or IN mil Layer TOP mil V V always on power rail by ON from PMU0 oz Layer V V always on power rail by ON from PMU0 mil.v.v always on power rail from V oz mil Layer IN (High Speed) mil VS V switched power rail by PSUS0, and exist at STR oz mil Layer IN(StripLine) (High Speed) VS V switched power rail by PSUS0, and exist at STR mil.vs.v power rail controlled by PSUS0, and exist at STR oz Layer mil.vs.v power rail controlled by PSUS0, and exist at STR oz mil Layer IN(StripLine) (Others) PI, IE VM V power rail controlled by SUSTT_0 mil VM.V switched power rail by SUSTT_0 oz Layer V mil VM.0V switched power rail by SUSTT_0 /oz mil Layer OTTOM (MicroStrip).VM.V switched power rail by SUSTT_0.VM.VM.V switched power rail by SUSTT_0.V power rail controlled by SUSTT_0 POWER RIL ESTINTION VOLTGE S0 URRENT VORE_PU VP 0.V-.0V power rail for PU controlled by VORE_PU anias 0.-.0V SYS_PWROK VP anias 0.-.0V. Vcore_PU 0.V~.0V power rail for PU controlled by MontaraGM 0. VR_ON.VM anias (PLL).V 0..VM.V power rail controlled by SYS_PWROK IHM (PLL) 0.0.VM MontaraGM.V. (ORE, HU, RL) (., 0.0, 0.).VM MontaraGM.V 0. Part Naming onventions (LVS,, VO) (0.0, 0.0, 0.0) IHM (ORE) 0. = apacitor.vs MontaraGM.V. N = onnector (R, LVSIO) (.0, 0.0) = iode (Run R RM.0(Idle). Mark) F = Fuse 0EM L = Inductor R 0. Q = Transistor.VM R RM.V 0.0 R = Resistor.VS IHM (LN).V 0.0 RP = Resistor Pack 0EM 0. U = rbitrary Logic evice.v IHM (SUS).V 0.0 Y = rystal and Osc VM IHM (IO).V 0. R 0. Net Name Suffix MiniPI FWH IOS 0 = ctive Low signal LP K 0.00 (Idle) OE 0.0 (Idle) LK GEN 0. LVS 0. Signal onditioning VS IHM (LN).V 0.00 = amped (by a resistor) R _Q_ = Isolated (by a Q-switch) MiniPI 0EM 0. _L_ = Filtered (by an inductor or bead) PMI V Layer No Layer Layer Layer Layer Layer Layer Trace Impedence: ohm_% Layer Type TOP(MicroStrip) IN(StripLine) (High Speed) (High Speed, IN(StripLine) others) V OTTOM (MicroStrip)(Others) V VM VS V PMUV PMUV.oard Stack up escription : P Layers IHM MP00 ROM H INT K/ INT MS INVERTER PMI V IHM US PMU0 SI_0 (SUS).V (Idle) 0. (Run) 0.0 (Idle) 0.~0.(Run) 0.0 (Idle) 0. (Run) 0.0 (Idle) 0. (Run) 0U GTL, LK, SRM, HU_LINK, LVS, US.0, FWH, highest frequency mode lowest frequency mode deeper sleep FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ).V 0.V 0.V Size ocument Number Rev nnotations 0. Thursday, June 0, 00 ate: Sheet of

5 / PGE EL,,,0,,,,0,0,,,,,,00,0. Schematic Modify Item and History Modify Item escription (b.) Q pin OPEN, and iode ISS & 0 pin, short.---.) ********************** >(for PowerON to boot steadily). (c.) N pin 內層斷線, need to be jumped-wire to. pin 內層與 line short : 修改方式是 to need to 將 pin via hole 鑽開後, 直接 jumping-wire to (). *********************** > (for PS Mouse no func.). (d.) U pin L to connect R(.k) to, and R cut off trace from LN_V. (e.) U pin J 直接 to connect LN_.VS (c.) U pin H, G 直接 to connect.vs, and R, R change into (NU). (d.) U pin 直接 to connect LN_.VS, and R change into (NU). (e.) U pin P to pull-up 0k to VM. ************************* > (for LN LOK cannot vibration). (f.) U pin,, 0, and U pin,, 0, 與 N pin,,,,,,, 0 cut-off traces 修改方法 :: 照此法跳線 ---->> U pin0 (TX0)< jumping wire >n pin (TX0) U pin (TX0-)< >N pin (TX0-) U pin (TX)< >N pin (TX) U pin (TX-)< >N pin (TX-) U pin0 (TX)< >N pin (TX) U pin (TX-)< >N pin (TX-) U pin (TX)< >N pin (TX) U pin (TX-)< >N pin 0 (TX-) ********************** > (for LN Jack pin define reverse)... (g.) R & R delete (h.) N pin to connect to signal( PI_ ). ************************************* > (for Insert Mini-PI LN module cannot boot ). (i) U(SI I) pin to jumping-wire to connect to signal(sustt_0). ************************************ >( for solve S function issue). (j) Q pin( ) to pull-up k to VM. ************************************* >(for solve Versa-ay(ROM/ VROM) no power issue). (k.)remove R, R0, Q, Q and short Q & Q (, ). ************************************ >(for solve ay reset function NG. 因 ROM_RST signal cannot be reversed to PI_RST0 ). (l.)l to 後焊 ( change into IP ) ************************************** >( P pad mismatch). (m.) Y, Y to 後焊 ( IP stage) **************************************** >(Y : P/N KHZ & Y : P/N -00-.KHZ). (n.) R delete to (NU), and R0& R cut-off trace from VS and then R0& R change into to connect to V( Q pin----->s 端 ). R cut-off trace from VM and then R change into to connect to PMUV( 0 ---> 端 ). (o.) R change into 0k (p/n : -0-00), and add iode (ISS SO------> p/n : ) 之 ( 端 / P 端 ) to connect U pin, and iode 之 (- 端 / N 端 ) to connect signal SUSTT_0( U pin ). (p.) R0 delete to (NU). (q.) R, R, R, R(0K ) cut-off traces from VS, and change to connect to VM(Q pin----> S 端 ). (r.) R0 delete to (NU). (s.) R delete to (NU). (t.) RP pin,,, cut-off traces from VS, and RP pin & change to connect to VM(Q pin-----> S 端 )., and RP pin & change to connect to PMUV( L 端 ) / PGE 0 M,M0,M,M HNGE TO VI HOL. / PGE NET NME FROM SEL HNGE TO SEL. / PGE R0 PULL HIGH O NET NME. / PGE N PIN 0 NET NME FROM PMUTE0 HNGE TO MP_MUTE0. / PGE N PIN,0 RESERVE PMU SM_US. / PGE PEEP SIGNL INVERTER / PGE 0 NET NME WIRELESS _RIO R PULL OWN. / PGE R PULL HIGH HNGE TO PULL OWN. / PGE N MS R PIN EFINE HNGE / PGE HNGE TO 0Ω / PGE,,,, some fuse or Poly switch for R,RT,S/MS,Port ar,versa ay,multi ay / PGE dd some NU part for intel Lan / PGE R for MIni PI WLN modify voltage from v changed to v / PGE US_ to US NN / PGE RESERVE IRQ R & R(RESERVE S/MS R ISSUE) / PGE L PIN EFINE FOR LYOUT HNGE. / PGE FOR EMI RESERVE & / PGE 0 FOR EMI M,M,M / PGE 0 MOIFY R_.VMMS POWER / PGE 0 FOR EMI M,M,M / PGE FOR EMI,,,& MOIFY, SIZE / PGE FOR EMI,0 / PGE FOR POWERMOIFY R & NET FROM PMU0REF HNGE TO PMUV / PGE FOR NE SPEIFITION S STTE SHORT HOT KEY WKE UP R &R. / PGE FOR NE SPEIFITION S STTE SHORT HOT KEY WKE UP RESERVE Q &Q. / PGE FOR US reserve pull high R & R. / PGE FOR S fail change power plan. / PGE FORps key some times can't work. change Q,Q,Q,Q PIN E &PIN pad. / PGE FOR L acklight better than pull up R0 / HOT KEY some times can't Latch pull down R0 / PGE EL R00 R / PGE EL ~,,,,00,0,0,,,,,~, R0,R0,R0~R0,R,R0,R,R,R,R,R,R,R,R0,R0,R0~R0,R0,R0,R,R, L,L,Q,Q0,U / PGE L,L,R,R,R0 / PGE EL 0,,,,,,00,0,,,,0,,,,0 L~L / PGE 0, / PGE EL 0,,,,,Q,R,R,R / PGE EL 0,,N,N,F,F ug List Root caues Solution Phase in plan LEN (PMTI U Li ) FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- Size ocument Number Rev Schematic Modify 0. Thursday, June 0, 00 ate: Sheet of

6 Power On Sequencing Timing iagram Ti 00M Power up Sequence VI VR_ON Vcc-core PU_UP Tsft_star_vcc Vboot Vid Tboot Tboot-vid-tr Tcpu_up Vccp Vccp_UP Tvccp_up Vccgmch GMHPWRG LK_ENLE# Tgmch_pwrgd V us min IMVP_PWRG Tcpu_pwrgd V us min VVI V_ORE ms min ms max us min TTERY ONLY POWER ON TIMING POWSW0 PMUV/PMUV M0 S SUSPEN N RESUME TIMING POWSW0 ON V MINSW0_IH To IH PMUV/PMUV ON V PM_RSMRST0 H H H H To IH_M PM_RSTRST0 PM_SLP_S0/S0/S0 PSUS0 To IH From IH From SI_0 From SI_0 PM_SLP_S0 PM_SLP_S0/S0 PSUS0 SUSTT_0 H H From IH_M From IH_M From SI_0 From SI_0 SUSTT_0 VS H VM,VS VM PM_PWROK SYS_PWROK PM_PWROK SYS_PWROK VRON_VP.VS N R_PWRG VRON_VP VP,.VM VP/.VM VORE_ON VORE_ON VR_ON VR_ON VORE_PU VORE_PU K0_PWRG0 PM_VGTE PU_PWRG PI_RST0 GTL_PURST0 To clock generator To GMH and IH From IH to PU To GMH/other PI device From GMH to PU K0_PWRG0 PM_VGTE PU_PWRGOO PI_RST0 GTL_PURST0 To clock Generator ToIH and GMH From IH to PU ToGMH/other PI device From GMH to PU FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ) Size ocument Number Rev Montara GM power on/off s timing 0. Thursday, June 0, 00 ate: Sheet of

7 Processor System us ata Signal Routing Guidelines Signal Names PU GTL_H0[..0] GTL_INV0[..0] GTL_STP0[..0] GTL_STN0[..0] RS00M Topology GTL_H0[..0] Stripline GTL_INV0[..0] Stripline GTL_STP0[..0] Stripline GTL_STN0[..0] Stripline Routing Length (ball-to-ball) Min Max (inches) (inches) Width & spacing (mils) & 0 & 0 & & No Use GP RS00M PU NOTE: The ata signals within each group must be routed to within /-0.00 inches of its associated"reference" strobe. The complement strobe must be routed to within /- 0.0" of the associate "reference" strobe. ll traces within each signal group must be routed on the same layer(required). It is recommnded that length of the strobes be centered to the average length of associated data or address traces to maximize setup/hold time margins. Processor System us ddress Signal Routing Guidelines Signal Names PU GTL_H0[..] GTL_HREQ0[..0] GTL_ST0[..0] RS00M GTL_H0[..] GTL_HREQ0[..0] GTL_ST0[..0] Topology Stripline Stripline Stripline Routing Length (ball-to-ball) Min (inches) (inches) Width & spacing (mils) NOTE: The ddress signals within each group must be routed to within /-0.00 inches of its associated strobe. ll traces within each signal group must be routed on the same layer(required). It is recommnded that length of the strobes be centered to the average length of associated data or address traces to maximize setup/hold time margins. Processor System us ontrol Signal Routing Guidelines GTL_PURST0 GTL_R00 GTL_NR0 GTL_PRI0 GTL_EFER0 GTL_LOK0 GTL_TRY0 GTL_RY0 GTL_S0 GTL_SY0 GTL_HIT0 GTL_HITM0 Signal Names PU GTL_RS0[..0] RS00M GTL_PURST0 GTL_R00 GTL_NR0 GTL_PRI0 GTL_EFER0 GTL_LOK0 GTL_TRY0 GTL_RY0 GTL_S0 GTL_SY0 GTL_HIT0 GTL_HITM0 GTL_RS0[..0] Topology Stripline Stripline Stripline Stripline Stripline Stripline Stripline Stripline Stripline Stripline Stripline Stripline Stripline Min Max Routing Length (ball-to-ball) (inches) (inches) Max & 0 & 0 & Width & spacing (mils) & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 Trace length === match within 00 mil lock Matching scheme for internal lock: Group E PM_VGTE N_PWRG S_PWRG Signal PULK_INT PULK0_INT HLKIN HLKIN0 GP_FLKIN_R LK_SIOPI LK_PI LK_MINIPI LK_PI LK_FWHPI LK_PMU0PI S_PILK_INT USLK_INT Source RS00M RS00M IXP00 RS00M RS00M Sink PU RS00M RS00M RS00M SUPER I/O IEEE EUG ON RUS LP IOS LP PNU0 IXP00 IXP00 VNI POWER SEQUENE Requirement Spacing Match clock pair //// within 0 mils. Match length of group. Match clock pair //// within 0 mils. Match length of group. // // Length Note (inches) to to to, // //.'' longer than the average trace in E Minimum length NOTE: The ddress signals within each group must be routed to within /-0.00 inches of its associated strobe. ll traces within each signal group must be routed on the same layer(required). It is recommnded that length of the strobes be centered to the average length of associated data or address traces to maximize setup/hold time margins. Miscellaneous Signal Routing Guidelines Signal Names PU IXP00 Topology Routing Length (ball-to-ball) Min Max (inches) (inches) Width & spacing (mils) PU_PWRG PI_RST0 GTL_PURST0 T T>= 0 ms T T ms < T < 0ms ms < T < ms PU_0M0 PU_0M0 Stripline PU_IGNNE0 PU_IGNNE0 Stripline PU_INTR PU_INTR Stripline PU_NMI PU_NMI Stripline PU_SMI0 PU_SMI0 Stripline PU_SLP0 PU_SLP0 Stripline PU_STPLK0 PU_STPLK0 Stripline PU_PWRGOO PU_PWRGOO Stripline PU_FERR_S0 S_FERR0 Stripline GTL_PROHOT_S0 Stripline GTL_THERMTRIP_S0 Stripline GTL_THERM GTL_THERM & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 0 & 0 0 & 0 FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ) Size ocument Number Rev LYOUT GUIE- 0. Thursday, June 0, 00 ate: Sheet of

8 Signals M_[..0] M_[..] M_QM0 M_QM Mismatch /- 0 mils /- 0 mils Relative to M_QS0 M_QS LVS Layout Guide M_[..] M_[..] M_[..] M_[..0] M_[..] M_QM M_QM M_QM M_QM M_QM /- 0 mils /- 0 mils /- 0 mils /- 0 mils /- 0 mils M_QS M_QS M_QS M_QS M_QS Match within 0 mils mil mil mil MUST HVE VI HOLE FOR EVERY 0. INH TXOUT0- mil TXOUT0 mil _POWER _POWER M_[..] M_QM /- 0 mils M_QS Match within 00 mils MUST HVE VI HOLE 0 mil area must clean no any trace and via hole MUST HVE VI HOLE ata Signal Topology & Group Routing Guidelines mil mil mil TXOUT- mil _POWER TXOUT mil _POWER RS00M M_[..0] M_QM[..0] M_QS[..0] Min=.0" Max=." Spacing = : M R[..0] M_QM_R[..0] M_QS_R[..0].VS ohm % ohm % 0.UF 0.UF Max=0." Max=.00" Max=0.0" SO-IMM0 P SO-IMM P // mil.vs Match within 0 mils MUST HVE VI HOLE FOR EVERY 0. INH ll LVS signals should be routed on the same layer. Please use the following rules when routing the LVS interface:. The differential impedance of all the LVS signals has to tightly controlled to 00 ohms for every pair. Please refer to the figure Zdiff alculation for differential trace routing for different stack ups.. It is recommended that all LVS signal traces be routed with a ratio of least : from other non-lvs signals. If this is not physically possible, a ground shield trace should be used. Place one via for every 0.'' of the guard trace.. ll traces within the same LVS pair should be mached within 0.00''. Matching between pairs should be within 0.00''. ommand Signal Topology & Group Routing Guidelines RS00M M[..0] M SR[..0] M_RS_FR0 M_RS_SR0 M_S_FR0 M_S_SR0 M_WE_FR0 M_WE_SR0 KE M_KE_R0 M_S00 M_S0_R0 M_S0 M_S_R0 M_S0 M_S_R0 M_S0 0 ohm % M_S_R0 Min=.0" Max=." Max=0." PF Max=0.0" ohm %.VS 0.UF 0.UF.VS Routing Guidelines for T/00 The S00 supports T/00. The guidelines for routing T/00 are as follows: ll the IE data lines IE[:0], IE_IOR#, and IE_HRY signals should be routed as follows: Route to maximum length between S00 and IE connectors. Match the length of all IE traces to /- 0. inches. SO-IMM 0, P dditional routing guidelines for T/00 include: The control and strobe signals (IE_IOW#, IE_IOR#, IE_HRY, IERQ) are critical and should be routed with a 0-mil spacing to other signals, and be referenced to the plane. The series termination resistors for the above control/strobe signals should be placed as close as possible to the S00 South ridge. To support both device side and host side detection for T/00 cables, place the device side detection capacitors (nf) close to the IE connectors. Place local bulk decoupling capacitors close to the IE connectors. lock Signal Topology & Group Routing Guidelines M_LK_R0 M_LK_R00 M_LK_R M_LK_R0 M_LK_R M_LK_R0 M_LK_R M_LK_R0 M_LK_R M_LK_R0 M_LK_R M_LK_R0 RS00M Min=." Max=" SO-IMM 0, P Trace width = mil ifferential Spacing = mil 0 mil space to other signals LK pair mismatch : mil SQS mismatch : /- 00mil IE Signals Signals MX Length Width (inch) (mils) IE_P[:0] IE_S[:0] IE_P0- IE_S0- IE_PS 0-0# IE_PREQ IE_SREQ IE_PIOW# IE_PTET IE_STET IE_PK# IE_SK# Space (mils) Ethernat Layout Guide Standard high-speed design practices should be adhered to while routing the MII interface between the S00 and the Phy (Ethernet Physical Inteface hip). These practices include: void crossing splits in the power or planes. Route MII clocks with a : spacing (e.g. -mil trace and -mil space). void stubs on MII signals if the design supports stuffing options for both on-board Phy and a NR or R slot. This can be performed using optional resistor packs. Use one high-frequency capacitor per Phy power pin. Place the Mhz crystal as close to the Phy as possible. Keep the crystal signals as far as possible from any other signals. Special care is needed when routing the high-speed Ethernet lines between the Phy and RJ connector. One should follow the routing guidelines for the specific Phy in order to obtain the best performance. The following general guidelines are recommended: void crossing splits in the power or planes. Transmit and receive pairs should be routed as 00-ohm differential impedance. Route differential pairs between transformer and RJ connector, max length =.0 inch. Route differential pairs between Phy and transformer, max length =.0 inch. Match signals within each differential pair to within /- 0-mils. Keep differential pairs at least 0-mils from other pairs and signals. Keep spacing between signals in a differential pair to a maximum of -mils. Void (remove) the power plane from the transformer to the RJ connector. Isolate the plane from the transformer to the RJ connector and connect this isolated to hassis. -Link and PI S00 will generate its own PI clocks for all PI slots connected to the MHz PI us. In order to properly route both _LINK and PI bus signals, follow these guidelines: Route the -Link signals point-to-point between S00 and RS00. Route to minimum length. Route the PI bus signals into the middle of PI slots, then branch out to both sides (T-topology). Route all PI clock signals generated from S00 (PILK[:0]) with a :0 ratio and place -ohm series termination resistors close to the S00 Southbridge. Route the feedback clock from PILK to PILK_F as short as possible. Match the length of all PI clocks except the PILK_F within /- inches (~ns). S00 input _LINK PI LK and output SE PI LKs should be treated separately. S00 input _LINK PI LK (S_PILK): Make sure S_PILK trace length is equal to the following: S_PILK 0. (S substrate trace length) == GP_FLKOUT_R GP_FLKIN_R Or S_PILK 0. (S substrate trace length) == GP_LK_INT GP_LK_INT_R (to take care of GP ard trace length). FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ) Size ocument Number Rev LYOUT GUIE- 0. Thursday, June 0, 00 ate: Sheet of

9 . Switch Setting Switch :Keyboard Select SW IT IT K/ SELET OFF OFF JPN(LVIE) ON OFF US OFF ON UK ON ON JPN(VersaPRO) Switch :bit MOS data clear used SW IT OFF ON Switch :bit Panic data clear used IT OFF ON MOS SELET NORML LER MOS T PNI NORML SEURITY YPSS MOE Switch :bit M/ I select :(Mother board version change detect) SW IT M_I0 OFF efaul ON E/S Switch :bit V select IT OFF ON VSEL see -ROM/V model see -ROM/V model Switch :Multibay Ejection Multibay evice ejection detect Switch :Multibay Ejection Multibay evice ejection detect -ROM -E-N ON -ROM RN-N ON R-RW UJ0NE-Z ON V-ROM S-NEN-MJ ON FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ) Size ocument Number Rev Switch Setting 0. Thursday, June 0, 00 ate: Sheet of

10 E PLE WITHIN." FROM PU U- HEK LYOUT GUILINE FOR ROUTING THOSE GROUPS GTL_H0[..] GTL_H0 K GTL GROUPS:,,,,,, VORE_PU GTL_H0 # GTL_H0[..0] K GTL_H00 GTL_H0 # 0# L GTL_H0 - R. GROUP 0: H_ REQ#[..0], H_#[..], H_ST#0 GTL_H0 # # K GTL_H0 R 00 % /W 00 GTL_H0 # # GTL_H0 - R. GROUP : H_#[..], H_ST# PU_INIT0 L GTL_H0 # # M GTL_H0 R0 00 % /W 00 GTL_H0 # # GTL_H0 - T GROUP 0: H_#[..0], H_I#0, H_STP#0, H_STN#0 PU_0M0 L GTL_H00 # # M GTL_H0 R0 00 % /W 00 GTL_H0 0# # GTL_H0 - T GROUP : H_#[..], H_I#, H_STP#, H_STN# PU_SLP0 M GTL_H0 # # N GTL_H0 R 00 % /W 00 GTL_H0 # # GTL_H0 - T GROUP : H_#[..], H_I#, H_STP#, H_STN# PU_INTR M GTL_H0 # # N GTL_H00 R 00 % /W 00 GTL_H0 # 0# G GTL_H0 - T GROUP : H_#[..], H_I#, H_STP#, H_STN# PU_NMI N GTL_H0 # # H N GTL_H0 R 00 % /W 00 GTL_H0 # # GTL_H0 PU_SMI0 T GTL_H0 # # R J GTL_H0 PU_STPLK0 R 00 % /W 00 GTL_H0 # # GTL_H0 PU_STPLK0 P GTL_H00 # # P GTL_H0 R 00 % /W 00 GTL_H0 0# # H GTL_H0 PU_IGNNE0 R GTL_H0 # # E T GTL_H0 PU_GHI0 R 00 % /W 00 GTL_H0 # # G GTL_H0 PU_GHI0 U GTL_H0 # # F P GTL_H00 GTL_H0 # 0# F U GTL_H0 GTL_H0 # # E T GTL_H0 GTL_H0 # # F V GTL_H0 GTL_H0 # # R GTL_H0 GTL_H0 # # L W GTL_H0,,,,,,,,,,,0,,,,, VM GTL_H00 # # G T GTL_H0 RP GTL_H0 0# # H U GTL_H0 RP K % 00* /W PR 0.mm N_NW_V # # M V GTL_H0 N_NW_W # # L W GTL_H0 PU_VI N_NW_Y # # J Y GTL_H00 PU_VI N_NW_ # 0# K GTL_H0 PU_VI # # H GTL_H0 PU_VI0 # M GTL_H0 R0 PU_VI # N GTL_H0 GTL_S0 G K % /W 00 N_NW_ S# # P GTL_H0 N_NW_V P0# # M V GTL_H0 P# # N GTL_H0 GTL_NR0 G NR# # M GTL_H0 GTL_PRI0 N_NW_ PRI# # N GTL_H0 INIT# # N GTL_H00,,,,,, VORE_PU 0# R GTL_H0 N_NW_L # P L GTL_H0 N_NW_K P# # R K GTL_H0 N_NW_K P# # R K GTL_H0 N_NW_J P# # T J GTL_H0 P0# # T GTL_H0 GTL_EFER0 E,,,,,, VORE_PU EFER# # T GTL_H0 GTL_RY0 H T R0,,,,,,,,,,,,,,,,,,,,0,,,,, VM RY# # GTL_H0 GTL_SY0 H U K % /W 00 SY# # GTL_H0 GTL_HREQ0[..0] GTL_HREQ0 # U H GTL_H00 GTL_HREQ0 REQ# 0# U J GTL_H0 GTL_HREQ0 REQ# # V GTL_H0 PU_PSLP0 Place resistor < 0." J S STPPU0,, R GTL_HREQ0 REQ# # U K GTL_H0 R R from PU interface GTL_HREQ00 REQ# # V GTL_H0 % /W 00 J 00 % /W 00 REQ0# # V GTL_H0,,,,,, VORE_PU 0 % /W 00 GTL_ST00 L ST0# # W Q GTL_H0 GTL_ST0 R ST# # Y GTL_H0 # W GTL_H0 M-FET-N SN0 0V 00M SOT- GTL_PURST0 S_FERR0 GTL_RS0 RESET# # Y F GTL_H0 GTL_RS0 RS# # Y G GTL_H00 R GTL_RS00 RS# 0# Y F GTL_H0 % /W 00 Q N_NW_ RS0# # GTL_H0 TRNS NPN N0 0V 00m SMT SOT- NS GTL_RS0[..0] RSP# # GTL_H0 GTL_TRY0 J R TRY# # % /W 00(NU) E PU_FERR_S0 R0 GTL_INV00 Q0 R.K % /W 00 GTL_R0 INV0#,,,,,, VORE_PU U G 0 % /W 00 TRNS NPN N0 0V 00m SMT SOT- NS GTL_INV0 R.K % /W 00 GTL_R0 R# INV# W GTL_INV0 R.K % /W 00 GTL_R0 R# INV# P Y R# INV# V GTL_INV0 VORE_PU,,,,,, GTL_R00 H GTL_STN00 R R0# STN0# E,,,,,, VORE_PU GTL_STP00 0pF 0V ± 0.pF 00 NPO(NU) % /W 00 STP0# F GTL_LOK0 G GTL_STN0 N_NW_V LOK# STN# K V GTL_STP0 R.K % /W 00 GTL_IERR_PU0 MERR# STP# J GTL_STN0 PU_INIT0 IERR# STN# R PU_INIT0 W INIT# STP# P GTL_STP0 STN# W GTL_STN0 GTL_HIT0 F W R HIT# STP# GTL_STP0 GTL_HITM0 E HITM# N_NW_. % /W 00 R0 % /W 00 FSSEL0 N_NW_ FSSEL PU_GHI0 GTL_GHI0 R 0 % /W 00 PULK GHI# R. % /W 00 PULK_INT F L R 0 % /W 00 PULK0 LK0 OMP0 PULK0_INT F P R. % /W 00 PLE TERMINTION N_NW_ LK OMP R0 % /W 00 N_NW_ ITP_LK0 GTL_PM_PREQ0 RESISTOR R,R ITP_LK PM# GTL_PM_PRY0 LOSE TO PU PU_0M0 PM# GTL_PM_ITP0 PU_0M0 Use.R % on R0, R for PU_FERR_S0 0M# PM# Y GTL_PM0_ITP0, version of RS00M PU_IGNNE0 FERR# PM# PU_IGNNE0 PU_INTR IGNNE# PM#,,,,,, VORE_PU PU_INTR PU_NMI LINT0 PM0# PU_NMI E R VM,,,,,,,,,,,,,,,,,,,,0,,,,, Trace width = mils PU_SMI0 LINT GTL_YPSSEN0 PU_SMI0 0 % /W 00 PU_STPLK0 SMI# YPSSEN# 0mil PLLV SETTING PU_STPLK0 Y STPLK# RESET E MSTER_RST0 PU_PSLP0 PU_VI0 PSLP# - MOILE NORTHWOO (EFULT) PU_VI0 E PU_VI VI0 GTL_REF_ PU_VI E R PU_VI VI GTLREF N_NW_F - ESKTOP NORTHWOO PU_VI E 0 % /W 00(NU) PU_VI VI GTLREF F N_NW_ PU_VI E. PLE THOSE IRUITRIES PU_VI VI GTLREF N_NW_F0 mils PU_VI E VI GTLREF0 F0,,,,,, VORE_PU LESS THN." FROM THE R.K % /W 00 L VORE_PU,,,,,, N_NW_F F GTL_OT R.K % /W 00 LL GTL_V RSV OT 0 GTL_MLK0 RP.μH 0% 00 MLF0RKT TK N_NW_ V MLK0 0 GTL_MLK RP.K % 00X /W PR 0.mm. THE 0PF PS HS TO VSENSE MLK E GTL_MLK R E LOSE TO THE LL S GTL_ VIOPLL MLK GTL_MLK R TuF V 0% 0 N_NW_ MLK GTL_MLKIO0 RP RP.K % 00* /W PR 0.mm 00 % /W 00 0 R POSSILE. 0 % /W 00 SENSE MLKIO0 GTL_MLKIO VI MLKIO R. % /W 00, VI F N_NW_ VI PM_VGTE, N_NW_F RSV PWRGOO F mil GTL_PROHOT_S0 RSV PROHOT# GTL_THERM TuF V 0% 0 THRM PU_SLP0 % /W 00(NU) GTL_THERM L THRM SLP# PU_SLP0 GTL_THERMTRIP_S0, VI THRMTRIP#.μH 0% 00 MLF0RKT TK N_NW_ GTL_TI N_NW_F RSV TI F GTL_TO N_NW_E RSV TO Q E F GTL_TMS uf 0V 0-0% 00 YV ESR<0. OHM N_NW_ RSV_PI TMS GTL_TK TR M-FET-N N00E 0V 0m SOT- SILIONIX Tolerance /- 0% N_NW_ RSV0 TK E GTL_TRST0. PLE THOSE IRUITRIES RSV_SMI# TRST# LESS THN." FROM THE G S_PWROK0 - USE / WITH / SPE FOR LL H_V N H /H_HIOPLL P PU P PZ0-- R 0 % /W 00. THE 0PF PS HS TO - PUT 0, 0 WITHIN 0." OF E LOSE TO THE LL S POSSILE. PU GTL_TI GTL_TO GTL_TMS GTL_TK R % /W 00 G R % /W 00 R % /W 00 R % /W 00 S R0 R 0 % /W 00 R % /W 00 R. % /W 00 R. % /W 00 R 00 % /W 00 uf 0V 0/-0% 00 YV R 00 % /W pF 0V 0% 00 XR uf 0V 0/-0% 00 YV 0pF 0V 0% 00 XR E FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, VORE_PU,,,,,, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ) Size ocument Number Rev P NORTHWOO (/) 0. E Thursday, June 0, 00 ate: Sheet of 0 E

11 E VORE_PU ulk ecoupling U- 0,,,,,, VORE_PU H MOILE NORTHWOO ESKTOP WILLMETTE/ H / Trace width > 00 mils Place close to the processor socket power and ground pins as possible (<.0 inch). NORTHWOO / PU H PU ORE VI TLE H ORE VRM.0/. VI[..0] Voltage VI[..0] Voltage V V 0 U V V V / V F V V 0 V V F V V 0 V V F 0 V V F V V 0 V V F 0 0 V V F V V 0 E V V0 F V V 0 E 0 V V E V V V 0 0.V E V0 V V V E V V E V V V V E V V 0 E V V V V E V V V 0 0.V E V V 0 E V V V V 0 F0 V V V 0 0.V F V V F V0 V V V F 0 V V F V V 0.000V 0.V F V V V V F V V F V V V V F V V V V 0 F V V0 0 G V V V 0 0.V G V V E V V G V0 V E G V V E V 0 0.V J V V E J V V E V V J E0 V V E0 E E V 0.V J V V K E V V F V V 0 0 K E V V0 F E F V 0 0.V 0 K V V K E0 V V F V V L E V0 V F L E V V F V 0.V F F L V V F V 0 0.0V L V M 0 0.0V 0.V M E 0 0.V 0.00V M E P PU P PZ0-- 0 M 0.00V NoPU E 0 N E N Mid Frequency ecoupling E N E N Place around Processor. E P mobil P eleron E P E P Frequency Voltage urrent Frequency Voltage urrent E P F R.G.V..G.V.0 F0 0 R.G.V..G.V. F R PU EOUPLING PITORS: 0.0G.V..G.V. F R.G.V..G.V. F T T-P: 0 PS POPULTE; 0uF,ESR=.m Ohm.G.V.0.G.V. F T F0 T Mo-P: For Frequency greater than or aqual to GHz F T F U Make sure mo-cap are XR/XR F U 0 U U One Ground 0 0 V V V PU EOUPLING PITORS LYOUT: One Via 0 V W W W. Use ~ vias per pad W Y 0 Y 0 Y Y Placed directly under PU when possible, P PU P PZ uF V 0-0% 00 YV 0 0.uF V 0-0% 00 YV 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR 0UF.V 0% 00 XR T0uF V mω KEMET 0UF.V 0% 00 XR T0uF V mω KEMET 0UF.V 0% 00 XR use two vias/pad 0UF.V 0% 00 XR T0uF V mω KEMET T0uF V mω KEMET 0 T0uF V mω KEMET 0.uF.V 0% 00 XR MURT 0.uF.V 0% 00 XR MURT 0.uF.V 0% 00 XR MURT 0.uF.V 0% 00 XR MURT 0.uF.V 0% 00 XR MURT 0.uF.V 0% 00 XR MURT 0.uF.V 0% 00 XR MURT 0.uF.V 0% 00 XR MURT 0.uF.V 0% 00 XR MURT 0.uF.V 0% 00 XR MURT 0, VI R0 % /W 00 0 GTL_THERMTRIP_S0 0/ modify FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ) Size ocument Number Rev P NORTHWOO (/) 0. Thursday, June 0, 00 ate: Sheet of E

12 S S Q0,, IN IN_PU FUSE V R00 SMT.*.mm F.uF V 0% 0 XR.uF V 0% 0 XR.uF V 0% 0 XR.uF V 0% 0 XR 0.uF V 0% 0 XR,,,,,,,,,0,,,,,0,,,,, VM.uF V 0% 0 XR 0.μF 0% V 00 XR M-FET-N FS 0V SO- FIRHIL 0.μF 0% V 00 XR Q M-FET-N FS 0V SO- FIRHIL 0mil Q S M-FET-N FS 0V SO- FIRHIL Q S M-FET-N FS 0V SO- FIRHIL / EMI add 000pF 0V 0% 00 XR E0QS0 SMT P P N 000pF 0V 0% 00 XR P N L 0.uH 0 HK-E00R TOHO E0QS0 SMT P uf 0-0% V 00 YV LOSE TO PU 00 mil I_MX=0 T0uF V mω KEMET ZENER RLZ. 0 0.uF V 0-0% 00 YV VORE_PU 0,,,,,, 000pF 0V 0% 00 XR IN_PU 0 PU_VI0 0 % /W 00 S_ORE U R VI 0 V 0.uF V 0% 00 XR R K % /W 00 R 0K % /W S_ORE PU_VI PU_VI PU_VI PU_VI R 0K % /W 00 0 % /W 00 0 NU_K % /W 00 R NU_0.uF V 0-0% 00 YV R R 0.K % /W 00 R0.K % /W 00 00pF 0V 0% 00 XR R.0K % /W 00 0 NU_0.uF V 0-0% 00 YV S_ORE 0K 0.% /W 00 0 % /W 00 0 % /W 00 0 % /W 00 R.K % /0W MF 00 R0 R R R 0 VI VI VI VI RMPSET FSET VMON F OMP OSET LTV OFFSET LTEN SOFT PGOO EN ISEN PWM PWM ISEN ISEN PWM NOV VSEN VRTN PM_PRSLPVR U.K % /W 00 UGTE PHSE VM,,,,,,,,,0,,,,,0,,,,, R 0 OOT EN PM_VGTE 0, PWM V LGTE VR_ON LNR-I ISL0-T Ld SOI PIN INTERSIL 0K % /W 00 R S_ORE R.K % /W uF V 00 YV R.K % /W 00 0.uF V 0% 00 XR 0K % /W 00 R N_P 0 % /W 00 R0 U VM,,,,,,,,,0,,,,,0,,,,, UGTE PHSE STPPU0 0,, OOT EN PWM V LGTE 0 LNR-I ISL0-T Ld SOI PIN INTERSIL uf V 0-0% 00 YV R 0 % /W 00 P N.uF V 0% 0 XR R 0 % /W 00 P N.uF V 0% 0 XR IOE ISS SO- HENMKO VM,,,,,,,,,0,,,,,0,,,,, IOE ISS SO- HENMKO VM,,,,,,,,,0,,,,,0,,,,, SI ISL SSOP PIN INTERSIL R.K % /0W MF 00 S_ORE.uF V 0% 0 XR.uF V 0% 0 XR.uF V 0% 0 XR.uF V 0% 0 XR.uF V 0% 0 XR 0.μF 0% V 00 XR IN_PU FOR PU VVI,,,,,,,,,,,0,,,,, VM.uF V 0-0% 00 YV U 0.uF 0V 0% 00 XR 0 mil U delay ms Pin Pin Pin Pin 00 Pin Pin Via to P_ORE S_ORE S_ORE R 0, U LNR-I SIH--T MSOP VISHY R VIN VOUT 0 % /W 00 J ELY ERROR# noise S# 0.uF V 0-0% 00 YV(NU) R 0 % /W 00 R0 0K % /W 00 R 0 % /W 00(NU) R 0 % /W 00 VI.uF V 0-0% 00 YV mil VR_ON Via to P_ORE M-FET-N FS 0V SO- FIRHIL M-FET-N FS 0V SO- FIRHIL S_ORE S S Q Q Q M-FET-N FS 0V SO- FIRHIL R 0 % /W 00 S S Q M-FET-N FS 0V SO- FIRHIL / EMI add P N E0QS0 SMT P 000pF 0V 0% 00 XR 000pF 0V 0% 00 XR P N E0QS0 SMT P L 0.uH 0 HK-E00R TOHO T0uF V mω KEMET(NU) 00 mil I_MX= pF 0V 0% 00 XR 0 0.uF V 0-0% 00 YV VORE_PU 0,,,,,, FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ) Size ocument Number Rev PU ORE (ISL) 0. Thursday, June 0, 00 ate: Sheet of

13 THERML SENSOR,,,,,,,,, V,,,,0,,,,,0,,,,, VS R 0K % /W 00, QSMLK_PMU, QSMT_PMU 0 mil R 0K % /W 00 R0 0K % /W 00 Thermal Power onsumption: ddress:00 0X U SLK ST Icc: Max 0u Icc stdby: Max 0u 0 0 R0 K % /W 00 0 mil VS,,,,0,,,,,0,,,,, GTL_THERM 0 0,,,,,,,,,,,,,,,,,,,,0,,,,, VM LERT# 00pF 0V 0% 00 XR 0,,,,,, VORE_PU R % /W 00 R 0 % /W 00(NU) R K % /W 00(NU),,,,0,,,,,0,,,,, VS 0 % /W 00(NU) R S_THRM0 R 0 % /W 00 R K % /W 00 R0 R 00 % /0W 00 0 mil N N 0.uF V 0% 00 YV STY# TEST TEST V - N N N N N N LNR-I MX QSOP PIN MXIM T=00PF SHOUL E PLE S LOSE S POSSILE TO THE MX GTL_THERM 0 R 0 % /W 00(NU) OVER_TEMP0, 0 GTL_PROHOT_S0 R 0 % /W 00(NU) Q TRNS NPN N0 0V 00m SMT SOT- NS(NU) E E Q TRNS NPN N0 0V 00m SMT SOT- NS(NU) _POWER (0mil) Layout Guide: Spacing: 0mil GTL_THERM (0mil) GTL_THERM (0mil) Spacing: 0mil _POWER (0mil) ifferential Pair: Signals Parallel,Trace Length Equal,as short as possible PTTERNS OF / - SHOUL E MINIMIZE VI. nd Thermal Sensor,,,,,,,, VS NER PU Place a little Plane on Top Side ( Without Mask ) U 0 % /W 00 (NU) HYST OS# R R_N VTEMP Vtemp V R 0K % /W 00 N_OVER_TEMP0 Place on Topps Side LM egree 0.uF V 0-0% 00 YV,,,,,,,,,0,,,,,0,,,,, VM Fan control,,,,,,,,, PMUV R 0K % /W 00 0mil mil 0mil *TRNS M-FET-P SI0S SMT SOT- VISHY-SILIONIX N L 00MHz 00Ω 00 H0K-0T0 L 00MHz 00Ω 00 H0K-0T0 R 0 % /W 00 FN_F R Q mil 0K % /W 00 N PIN -00 MOLEX 000pF V 0-0% 00 YV 0 00pF 0V % 00 NPO 000pF 0V 0% 00 XR 00pF 0V % 00 NPO R K % /W 00 FN_PWM mil mil E Q TRNS NPN TEU(UMT) 0V 00m ROHM FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ) Size ocument Number Rev THERML SENSE / FN NN 0. Thursday, June 0, 00 ate: Sheet of

14 room temp 0 ase temp. 0. junction temp 0. 0,,,,,, VORE_PU 0 GTL_H0[..0] GTL_H0[..0] TuF 0V 0% 0 0.uF V 0% 00 YV 0 0.uF V 0% 00 YV 0 0.uF V 0% 00 YV 0,,,,,, N_GTLREF 0 0.uF V 0% 00 YV 0 0.uF V 0% 00 YV PLE LOSE TO RS00M, USE 0/0 WITH/SPE VORE_PU R 00 % /W uF V 0% 00 YV 0 0.uF V 0% 00 YV R. % /W 00 uf 0V 0/-0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0pF 0V 0% 00 XR PM_SUSTT0 0,,,,,, VORE_PU 0,,,,,,,,,,,,,,,,,,,,0,,,,, VM 0mil 0 0 GTL_HREQ0[..0] 0 0 GTL_ST00 N_GTLREF GTL_H0[..] GTL_RS0[..0] MTHING LENGTH WITHIN 00-MIL ,,,,,,, 0,,,,,, GTL_ST0 GTL_S0 GTL_NR0 GTL_PRI0 GTL_EFER0 GTL_RY0 GTL_SY0 GTL_R00 GTL_LOK0 GTL_PURST0 GTL_RS0[..0] GTL_TRY0 GTL_HIT0 GTL_HITM0 VORE_PU Maximum.m 0mil GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H00 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_HREQ00 GTL_HREQ0 GTL_HREQ0 GTL_HREQ0 GTL_HREQ0 GTL_H0 GTL_H0 GTL_H0 GTL_H00 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H00 GTL_H0 GTL_RS0 GTL_RS0 GTL_RS00 PI_RST0 N_PWRG R % /W 00 R. % /W 00 R % /W 00 R 0 % /W 00 0.m M P M N N M P P P R P R N N M N R M L P T T R R R T U T U U U T V U V U K K L L L J J L E K K M J K L V V V G G G H0 J0 M0 N0 W P0 U # # # # # # # 0# # # # # # # REQ0# REQ# REQ# REQ# REQ# ST0# S# NR# PRI# EFER# RY# SY# R0# LOK# R. GROUP R. GROUP 0 # # # 0# # # # # # # # # # 0# # ST# PURST# RS# RS# RS0# TRY# HIT# HITM# ONTROL SUSSTT# SYSRST# POWERGOO OMPV OMP OMPLKV OMPLK P_VREF VPU VPU VPU VPU VPU VPU VPU VPU VPU VPU MIS. PRT OF GTL I/F PENTIUM IV T GROUP 0 T GROUP T GROUP T GROUP 0# # # # # # # # # # 0# # # # # # I0# STN0# STP0# # # # # 0# # # # # # # # # # 0# # I# STN# STP# # # # # # # # # 0# # # # # # # # I# STN# STP# # # 0# # # # # # # # # # 0# # # # I# STN# STP# J H H H J J G H F G G F F H F F H G G F E E E E E E0 F F0 0 F E F E 0 0 E F E F F E GTL_H00 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H00 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_INV00 GTL_STN00 GTL_STP00 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H00 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H00 GTL_H0 GTL_INV0 GTL_STN0 GTL_STP0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H00 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_INV0 GTL_STN0 GTL_STP0 GTL_H0 GTL_H0 GTL_H00 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H0 GTL_H00 GTL_H0 GTL_H0 GTL_H0 GTL_INV0 GTL_STN0 GTL_STP0 GTL_INV00 0 GTL_STN00 0 GTL_STP00 0 GTL_INV0 0 GTL_STN0 0 GTL_STP0 0 GTL_INV0 0 GTL_STN0 0 GTL_STP0 0 GTL_INV0 0 GTL_STN0 0 GTL_STP0 0 MTHING LENGTH WITHIN 00-MIL SI RS00M G TI R0 0 % /W 00 (NU),,,,,,,,, V R 0K % /W 00(NU),,,,.VS,,,,0,,,,,0,,,,,,,,,,,,, VS R VS 0 % /W 00 R 0 % /W 00 (NU) V R 0K % /W 00(NU) R0 K % /W 00(NU) E Q TRNS NPN N0 0V 00m SMT SOT- NS(NU) 0.uF V 0% 00 YV(NU) VRM_PWRG R R 00 % /W 00(NU) % /W 00(NU) T U L-I NSPX S-0 PIN FIRHIL 0.uF V 0% 00 YV 0.uF V 0% 00 YV T R.K % /W 00 U L-I NSPX S-0 PIN FIRHIL N_PWRG N_PWRG,,.VM R K % /W 00(NU) E Q TRNS NPN N0 0V 00m SMT SOT- NS(NU) G S Q M-FET-N N00 0V M TO-(NU) R0.K % /W 00 R K % /W 00(NU).uF V 0-0% 00 YV(NU) R 0 % /W 00 0, PM_VGTE R 0K % /W 00 E 0 uf 0V 0-0% 00 YV Q TRNS NPN N0 0V 00m SMT SOT- NS(NU) RS00M POWER GOO IRUIT FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ) Size ocument Number Rev RS00M-GTL 0. Thursday, June 0, 00 ate: Sheet of

15 These packs and resistor,please close to IMM,,,,.VS,0,0,0,0 M_S_R0 M_S0_R0 M_S_R0 M_S_R0 0 TuF 0V 0% uF V 0% 00 YV 0 0.uF V 0% 00 YV Layout note:place capacitors between and near RS00M HIPS if possible. 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV PLE SERIL TERMINTION RESISTOR LOSE TO MEMROY MOULE M_S0 M_S00 M_S0 M_S0 RP RP 0 % 00* /W PR 0.mm 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV M SR[..0],0 M SR[..0],0 M_RS_SR0 RP 0 % 00X /W PR RP 0 % 00X /W PR RP 0 % 00X /W PR RP 0 % 00X /W PR,0 M_QM_R[..0],0 M_RS_FR0 M SR M M SR0 M0 M SR M M SR M M SR M M SR M M SR M M SR M M SR M M SR0 M0 M SR M M SR M M SR M M SR M M SR M M_QM_R0 R % /W 00 M_QM_R R % /W 00 M_QM_R R % /W 00 M_QM_R R % /W 00 M_QM_R R0 % /W 00 M_QM_R R % /W 00 M_QM_R R % /W 00 M_QM_R R % /W 00 R 0 % /W 00 M_S_SR0 R 0 % /W 00,0 M_WE_SR0 R 0 % /W 00,0 M_KE_R0,0 M_QS_R[..0] M_QS_R0 R % /W 00 M_QS_R R % /W 00 M_QS_R R % /W 00 M_QS_R R % /W 00 M_QS_R R % /W 00 M_QS_R R % /W 00 M_QS_R R % /W 00 M_QS_R R % /W 00 M_LK_R00 M_LK_R0 M_LK_R0 M_LK_R M_LK_R0 M_LK_R M_LK_R0 M_LK_R M_LK_R0 M_LK_R M_LK_R0 M_LK_R 0pF 0V ± 0.pF 00 NPO 0pF 0V ± 0.pF 00 NPO 0 0pF 0V ± 0.pF 00 NPO 0pF 0V ± 0.pF 00 NPO 0pF 0V ± 0.pF 00 NPO 0pF 0V ± 0.pF 00 NPO 0pF 0V ± 0.pF 00 NPO,,,,.VS 0pF 0V ± 0.pF 00 NPO 0pF 0V ± 0.pF 00 NPO 0pF 0V ± 0.pF 00 NPO 0mil 0pF 0V ± 0.pF 00 NPO 0pF 0V ± 0.pF 00 NPO R 0 % /W 00 M0 M M M M M M M M M M0 M M M M M_QM0 M_QM M_QM M_QM M_QM M_QM M_QM M_QM M_RS_FR0 M_S_FR0 M_WE_FR0 KE M_QS0 M_QS M_QS M_QS M_QS M_QS M_QS M_QS M_S00 M_S0 M_S0 M_S0 0 0 E 0 E0 0 E E F0 E F E E Y E F E F E Y F F W F F F Y Y Y M&MQM,must same lengh U R_0 PRT OF R_Q0 R_ R_Q R_ R_Q R_ R_Q R_ R_Q R_ R_Q R_ R_Q R_ R_Q R_ R_Q R_ R_Q R_0 R_Q0 R_ R_Q R_ R_Q R_ R_Q R_ R_Q R_Q R_M0 R_Q R_M R_Q R_M R_Q R_M R_Q R_M R_Q0 R_M R_Q R_M R_Q R_M R_Q R_Q R_RS# R_Q R_S# R_Q R_Q R_WE# R_Q R_KE R_Q R_Q0 R_QS0 R_Q R_QS R_Q R_QS R_Q R_QS R_Q R_QS R_Q R_QS R_Q R_QS R_Q R_QS R_Q R_Q R_K0# R_Q0 R_K0 R_Q R_Q R_K# R_Q R_K R_Q R_Q R_K# R_Q R_K R_Q R_Q R_K# R_Q R_K R_Q0 R_Q R_K# R_Q R_K R_Q R_Q R_K# R_Q R_K R_Q R_Q R_S0# R_Q R_S# R_Q R_S# R_Q0 R_S# R_Q R_Q TESTMOE R_Q VRM VRM VRM VRM VRM VRM VRM VRM VRM VRM R I/F SI RS00M G TI VRM VRM VRM VRM VRM VRM VRM R_VREF E 0 F0 E F E E F E F F F E F F F E E E E E Y Y Y W W Y Y Y Y Y V0 W0 These packs and resistor,please close to IMM M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0mil 0mil M R[..0],0 RP RP % 00* /W PR 0.mm RP RP % 00* /W PR 0.mm RP RP % 00* /W PR 0.mm RP RP % 00* /W PR 0.mm RP RP % 00* /W PR 0.mm RP RP % 00* /W PR 0.mm RP RP % 00* /W PR 0.mm RP RP % 00* /W PR 0.mm RP0 RP % 00* /W PR 0.mm RP RP % 00* /W PR 0.mm RP RP % 00* /W PR 0.mm RP RP % 00* /W PR 0.mm RP RP % 00* /W PR 0.mm RP RP % 00* /W PR 0.mm RP RP % 00* /W PR 0.mm RP RP % 00* /W PR 0.mm.VS,,,, R_VREF, PLE LOSE TO RS00M, USE 0/0 WITH/SPE MXIMUM LVSRTTV MOE Pattern/test I V_ore (m) I V (m) I PLV (m).v I LPV (m) I LVR (m) Total I.V (m).v.v.v I V I VPU Total I.V (m) (m) (m) Total power (W) 0X,bpp,0HZ MRK FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ) Size ocument Number Rev RS00M-R I/F 0. Thursday, June 0, 00 ate: Sheet of

16 ,,.VM PI_[..0],,,,, PI_[..0],,,,, PI_/E0[..0],,,,, PI_PR,,,,, PI_FRME0,,,,, PI_IRY0,,,,, PI_TRY0,,,, PI_IRQ0,,,,, PI_EVSEL0,,,,, PI_STOP0,,,,, PI_SERR0, PI_REQ0, PI_SREQ0, PI_SGNT0, PI_REQ00, PI_REQ0, PI_REQ0, PI_REQ0, PI_GNT00, PI_GNT0,,,,,,,,,0,,,,,0,,,,, VM, PI_GNT0, PI_GNT0 0mil 0,,,,,,,,,,,,,,,,,,,,0,,,,, 0.uF V 0% 00 YV VM 0mil 0.uF V 0% 00 YV PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_/E00 PI_/E0 PI_/E0 PI_/E0 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV F F F E E E E E Y Y Y Y W W W W W V V W V Y T R T R V U U T V V U T T F Y T U V W U PI_0 PRT OF GP_0 PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_0 GP_0 PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_0 GP_0 PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_ GP_ PI_0 GP_0 PI_ GP_ GP_SST PI_E0# GP_SST# PI_E# GP_ST0 PI_E# GP_ST0# PI_E# GP_ST GP_ST# PI_PR PI_FRME# GP_E#0 PI_IRY# GP_E# PI_TRY# GP_E# INT# GP_E# PI_EVSEL# PI_STOP# GP_EVSEL# PI_SERR# GP_FRME# PI_TIVE_REQ# GP_IRY# GP_PR PI_SREQ# GP_PIPE# PI_SGNT# GP_RF# GP_SERR# PI_REQ0# GP_STOP# PI_REQ# GP_TRY# PI_REQ# GP_WF# PI_REQ#/PI_LK GP_REQ# PI_GNT0# GP_GNT# PI_GNT# PI_GNT# GP_S0 PI_GNT#/PI_LK GP_S GP_S GP_S GP_S V_V GP_S GP_S GP_S VPI VPI GP_ST0 VPI GP_ST VPI GP_ST VPI VPI GP_VOLTGE_ETETE GP_VREFX PI/GP I/F SI RS00M G TI R R P P P N N N L L L K K J J H M L L L K K K J H J G G G G F F F E M M H H M H M J N M N R E P P P F E E F F G G E R GP_TYPEET0: OPEN:VQ=.V TO :VQ=.V N_N_R N_N_R N_N_P N_N_P N_N_P N_N_N N_N_N N_N_N N_N_L N_N_L N_N_L N_N_K N_N_K N_N_J N_N_J N_N_H N_N_M N_N_L N_N_L N_N_L N_N_K N_N_K N_N_K N_N_J N_N_H N_N_J N_N_G N_N_G N_N_G N_N_G N_N_F N_N_F N_N_M N_N_M N_N_H N_N_H N_N_M N_N_H N_N_M N_N_J N_N_N N_N_N N_N_R N_N_E L_IGON_R N_N_P N_N_P N_N_P N_N_F GP_REQ_R0 GP_GNT_R0 N_N_ N_N_E L_LON_R0 N_N_E PI_LKRUN_R0 N_N_F N_N_G N_N_G N_N_ LVS_SSOUT_R R_LVS_SSIN GP_TYPEET0 GP_VREFX R R0 R0 GP_STP0 GP_USY0 0mil LVS_ENL LVS_ENKL PI_LKRUN0,,,, LVS_SSOUT LVS_SSIN ONFIGURE S LVS INTERFE PLE LOSE TO RS00M RUN 0-MIL TRE 0 0pF 0V 0% 00 XR TuF 0V 0% 0 Max: m.k % /W 00 0,,,,,,,,,,,,,,,,,,,,0,,,,, VM 0,,,,,,,,,,,,,,,,,,,,0,,,,,.K % /W 00.K % /W 00 R 0 % /W 00 RP 0 % 00* /W PR R0 0 % /W 00 R0 0 % /W 00 VM 0,,,,,,,,,,,,,,,,,,,,0,,,,, R % /W 00 R0 0 % /W 00 R K % /W uF V 0-0% 00 YV TuF 0V 0% 0 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0 0pF 0V 0% 00 XR R % /W 00 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0 0.uF V 0% 00 YV 0 0.uF V 0% 00 YV 0,,,,,,,,,,,,,,,,,,,,0,,,,, VM 0,,,,,,,,,,,,,,,,,,,,0,,,,, R % /W 00 0.uF V 0% 00 YV VQ/ 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV VM VM 0mil mil 0mil T U U U0 Y0 Y Y Y Y Y0 VM 0,,,,,,,,,,,,,,,,,,,,0,,,,, T0 R K % /W 00 R K % /W 00 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV 0.uF V 0% 00 YV PUT ON THE SOLER SIE OF RS00M 0.uF V 0% 00 YV K0 K K K K K L0 L L L L L M0 M M M M M R0 R R R R R T0 T T T T T U0 U U U U U G0 G K H P L K H 0.uF V 0% 00 YV UE 0.uF V 0% 00 YV V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_ORE V_.V V_.V V_GP V_GP V_GP V_GP V_GP V_GP PRT OF GP ORE PWR PWR/ SI RS00M G TI 0.uF V 0% 00 YV 0.uF V 0% 00 YV E N J Y F F N V K F 0 G F E G G G G G G0 J G K K K0 L L L0 M M M G N N0 N N N N N N N P0 P P P P P P P R R R R0 T T T GP PULL UPS 0,,,,,,,,,,,,,,,,,,,,0,,,,, VM R R R LVS_SSOUT.K % /W 00(NU).K % /W 00(NU).K % /W 00(NU) U ILK S S0 S LK V R LVS_SSIN % /W 00 0pF 0V ± 0.pF 00 NPO L VM 0,,,,,,,,,,,,,,,,,,,,0,,,,, R.K % /W 00 R.K % /W 00 R0.K % /W 00 LEE MK0S SOI PIN IS 00MHz 00Ω 00 H0K-0T0 0 R 0 % /W 00(NU) 0.uF V 0% 00 YV SPRE SPETRUM OFF LOW EMI ENLE (INTERNL PULL UP) ON ISLE SPRE SPETRUM FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ) Size ocument Number Rev RS00M-PI & GP I/F 0. Thursday, June 0, 00 ate: Sheet of

17 0,,,,,,,,,,,,,,,,,,,,0,,,,, VM VM VM L0 FM0V-0T0 OVERLP OMMON PS FOR UL-OP FERRITE ES Output : Max 0m 0mil U0 Vin Vout 0mil L 0 % /W 00 L 0 % /W 00 PLV V.V mil,,,,, VM SUSTT_0 V (RT) V.V V V (.V) VQ NGP REF (.V) PLLV PLL V (.V) L FM0V-0T0 0 uf 0V 0/-0% 00 YV O NOT SHRE VI ON JOINT 0 0.uF V 0% 00 YV N 0mil R 0K % /W 00 0 IOE ISS SO- HENMKO P 0.uF V 0% 00 YV JP JP_00_SHORT JP JP_00_SHORT JP JP_00_SHORT JP JP_00_SHORT JP JP_00_SHORT 0mil N_MHz_ / Output : Max 0m N Q N Q LR U Vin S0 P I SIT--T PLE LOSE TO RS00M S_PILK_INT USLK_INT FREQ OS MHZ pf TITIEN 0 PPM PUT V, V, VQ, PLV EOUPLING PS ON THE OTTOM, LOSE TO LLS ROUTE N_THRM N HW_ TRES S IFF PIRS TO SIO M_INT Maximum.m.V mil TERMINTION PLE LOSE TO U00 PILK0_INT VM 0,,,,,,,,,,,,,,,,,,,,0,,,,, Y V OUT Vout N S_OS_INT 0pF 0V ± 0.pF 00 NPO R 0.K % /W 00 R 0K % /W 00 V uf 0V 0/-0% 00 YV Use.R % for R, R in version of RS00M 0pF 0V ± 0.pF 00 NPO R % /W 00 PLV 0mil 0UF.V 0% 00 XR R % /W 00 R0 % /W 00 R 0 % /W 00 R % /W 00 0pF 0V ± 0.pF 00 NPO 0pF 0V ± 0.pF 00 NPO M_INT R % /W 00 V V V uf 0V 0/-0% 00 YV 0.uF V 0% 00 YV N Q SYS_FLKOUT0 SYS_FLKOUT 0.uF V 0% 00 YV 0.uF V 0% 00 YV Q N 0mil 0.uF V 0% 00 YV 0mil R % /W 00 R0 % /W 00 0.uF V 0% 00 YV mil mil mil Use R for R0, R0 in version of RS00M R 0 % /W 00 0.uF V 0% 00 YV R % /W 00 R % /W 00 RE GREEN LUE VSYN HSYN GP_FLKIN_R R GP_FLKOUT_R % /W 00 OVERLP OMMON PS FOR UL-OP RESISTORS T T PLV HLKIN HLKIN0 R % /W 00 RS00M_X RS00M_X SYS_FLKOUT0_R SYS_FLKOUT_R S_PILK_INT_R GPLK_INT_R USLK_INT_R M_PILK S_OS_INT_R G 0 W W E0 0 0 E F 0 E U E U F uf 0V 0/-0% 00 YV mil U.V V N Q V N VQ Q PRT OF THERMLIOE_N THERMLIOE_P PLLV0 PLLV PLL0 PLL RE GREEN LUE VSYN HSYN RSET XTLIN XTLOUT HLKIN HLKIN# RT SYS_FLKOUT# SYS_FLKOUT PI_LKF PILK_N GPLK GPLKIN/GP_FLKIN EXT_MEM_LK/GP_FLKOUT 0.uF V 0% 00 YV LVS SVI R 0 % /W 00 TXOUT_U0N TXOUT_U0P TXOUT_UN TXOUT_UP TXOUT_UN TXOUT_UP TXLK_UN TXLK_UP TXOUT_L0N TXOUT_L0P TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_LP TXLK_LN TXLK_LP LPV LP LVR LVR LR LR _R Y_G OMP_ RSET SL S PILK_STOP# PUSTOP#,,,,,,, 0,, F E E F E F0 F U F PI_RST0 STPPU0 R % /W 00 LVS_TXOUT_U0N LVS_TXOUT_U0P LVS_TXOUT_UN LVS_TXOUT_UP LVS_TXOUT_UN LVS_TXOUT_UP LVS_TXLK_UN LVS_TXLK_UP LVS_TXOUT_L0N LVS_TXOUT_L0P LVS_TXOUT_LN LVS_TXOUT_LP LVS_TXOUT_LN LVS_TXOUT_LP LVS_TXLK_LN LVS_TXLK_LP TV_ TV_Y TV_OMP VELK VET R 0 % /W 00 R 0 % /W 00 U R 0.uF V 0% 00 YV R.K % /W 00 L VM 0,,,,,,,,,,,,,,,,,,,,0,,,,, FM0K-T0 Maximum.m uf 0V 0/-0% 00 YV uf 0V 0/-0% 00 YV uf 0V 0/-0% 00 YV PLE EOUPLING PS T OTTON N LOSE TO LLS PLE LOSE TO THE LL.,, Maximum 0.0m 0.uF V 0% 00 YV 0.uF V 0% 00 YV STPPI0 USLK PULK_INT_R R % /W 00 REF/PILK SYSLK PULK0_INT_R R0 % /W 00 SYSLK# OS LK. GEN. 0,,,,,,,,,,,,,,,,,,,,0,,,,, VM SI RS00M G TI EFULT : INTERNL 0,,,,,,,,,,,,,,,,,,,,0,,,,, LOK VM S0 P I SIT--T R.K % /W 00 0 % /W 00(NU) L FM0K-T0 mil L FM0K-T0 mil L-I NSZPX S-0 PIN FIRHIL R 0K % /W 00 T0uF 0V ± 0%.VM 0 0UF.V 0% 00 XR LR 00mil 0UF.V 0% 00 XR uf 0V 0/-0% 00 YV PLE NER RS00M. TRE = 0 MIL 0pF % 0V 00 NPO(NU) PULK_INT 0 PULK0_INT 0 0pF % 0V 00 NPO(NU) T0uF 0V ± 0% VM 0,,,,,,,,,,,,,,,,,,,,0,,,,, RS00M_X RS00M_X 0mil The trace length of RS00M_X should be equal to RS00M_X R 0 % /W 00 R M % /W 00 R 0 % /W 00 0pF 0V % 00 NPO Y FREQ XTL.MHZ PF X000 TX 0pF 0V % 00 NPO NOTE: THERE RE THREE OPTIONS ) USE Y00 YSTL FOR.MHz ) USE Y00.MHz RYSTL N Y0 MHz OSILLTOR ) USE Y0.MHz OSILLTOR 0.uF V 0% 00 YV PILK0_INT 0mil R 0 % /W 00 VM 0.uF V 0% 00 YV U V V S/V S/ REF Y0Z-H LK LK LK LK LK LK LK LK FK 0 R % /W 00 PILK_MINI R % /W 00 PILK_US0 R % /W 00 PILK_LN R % /W 00 PILK_ N_0_ 0pF 0V ± 0.pF 00 NPO N_0_ 0pF 0V ± 0.pF 00 NPO N_0_0 N_0_ 0pF 0V ± 0.pF 00 NPO 0pF 0V ± 0.pF 00 NPO FI International omputer, Inc. FL.,NO,SE.,WENHW nd R. LINKOU HSING, TIPEI, TIWN,RO (-)00- LEN (PMTI U Li ) Size ocument Number Rev RS00M-VIEO I/F&LK 0. Thursday, June 0, 00 ate: Sheet of