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婉鞍满
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3 Abstract SoC (digital signal processor; DSP) (MMX (stackcontrol flow context switch ) memory hierarchy DSP (standalone) DSP (dual processor) DSP Analog Devices Inc.ADSP-2181 (ALUmultiplier unit barrel shifter) DCTFFTbiquad filter lattice filteriir filter ping-pong mode AMBA AHB 314 MHz ( CIC UMC 0.18um CMOS cell-based ) core size mm 2 52mW physical synthesizable Verilog RTLcycle-accurate SystemC modelseamless CVE model CIC EASY (Example AMBA System) EASY JPEG encoder 1

4 1. Introduction Control-oriented Computation-intensive function computation, signal processing Microcontroller Subsystem MIPS ARM MCU-related Coprocesors foreground memory (Cache) MMX-like Datapath DSP Processors Motorola Oak ADI TI program memory data memory communication & background memory Dedicated Hardware Configurable DSP Datapath ASIC 4 ASIC 3 ASIC 2 ASIC 1 interface unit foreground memory (SIU) Parallel Functional Units (control-oriented) (data-intensive) (baseband processing) (transformation) (DSP processor) RISC DSP RISC SIMD (single instruction multiple data) DSP DSP context switch 2

5 RISC DSP (standalone) RISC DCTFFTlinear filters DSP 8KB ping-pong mode AMBA Slave interface DSP (SFP; static floating point arithmetic) mantissa DSP (SDFG; synchronous data flow graph) (scheduler) DSP 3

7 2. Hardware Architecture DSP Core Instruction Memory (8K Byte) AMBA Slave Interface System Controller Computing Engine Data Memory (4K byte x 2) (Computing engine) (Data memory) (System controller) (Instruction memory) AMBA (AMBA Slave interface) 2.1. (Computing engine) dataflow rate (functional unit) branchloop 5

8 output-queue system input-queue systemoutput-queue system queue Input-queue system queue input/output-queue system two-port memory dataflow-rate N (L+1) Queue length: L Queue length: L N (L+1) A-Bus N (L+1) N functional units N functional units N (L+1) M-Bus (a) (b) (a) Output-queue; (b) input-queue-based data generator (linear) (sign extension) (register file) 4x4 crossbar router (a) (aligner) 6

9 (normalizer) (b) (register file) crossbar router Computing Engine Adder Register File A 4x4 Crossbar Router Multiplier Register File Shifter Register File M S add_src0 add_src1 a_rsh0_en a_rsh1_en >>1 >>1 + sub_en a_rsh2_en m_lsh_en >>1 add_rslt mpy_src0 x <<1 mpy_rslt mpy_src1 Data Memory s_shamt shft_src Shifter shft_rslt (a) (a) ; (b) (b) 7

10 2.2. (Data Memory) Data Memory Bank 0 (4K byte) Bank 1 (4K byte) System bus Block #1 (result) Block #3 (operand) Block #2 (computing) Computing engine Ping-pong switch Data Memory Bank 1 (4K byte) Bank 0 (4K byte) System bus Block #2 (result) Block #4 (operand) Block #3 (computing) Computing engine Ping-pong mode 8K byte 4K byte ping-pong mode (system bus) bank bank 1 block #2 bus bank 0 block #1 block #3 bank 0/1 block #3 block #2 block #4 block processing stream processingping-pong mode 8

11 2.3. (System Controller) FSM (finite state machine) IDLE DSP PINGPONG_SWITCH Ping-pong mode bank RUNNING DSP WAIT DSP PINGPONG_SWITCH EXCEPTION DSP (reset) 2D (TMODE) D 9

12 Control Register Bit width Comment CL 9 Instruction length to execute CSA 9 Instruction starting address OBL 8 Number of operand per iteration IOBSA 11 Operand starting address in data memory IOBSAINC 5 Operand starting address increment per iteration RBL 8 Number of result per iteration IRBSA 11 Result starting address in data memory IRBSAINC 5 Result starting address increment per iteration ITRN 8 Number of iteration per block BN 8 Number of block per data memory bank DATA_VALID 1 Data valid signal ACCESS 1 Bus accessing signal TMODE 2 2D transpose mode signal BUSY 1 Computing engine busy signal EXCEPTION 1 DSP core exception signal 2.4. (Instruction Memory) 8K byte AMBA bus bank bank 32 bank 2.5. AMBA (AMBA Slave Interface) AMBA Slave interface 10

13 Pin name Pin width Direction Comment HCLK 1 Input AMBA system clock HRESETn 1 Input AMBA reset signal active low HADDR 14 Input AMBA address HTRANS 2 Input AMBA type of transfer HWRITE 1 Input AMBA transfer direction signal HWDARA 32 Input AMBA write data HRDATA 32 Output AMBA read data HREADYin 1 Input AMBA transfer ready signal HREADYout 1 Output AMBA transfer ready signal HRESP 2 Output AMBA transfer response HSEL_DSPlite 1 Input AMBA slave select signal im_memgroupsel 1 Input im_bistmode 1 Input im_bistfail 4 Output Instruction memory BIST signals im_errmap 4 output im_finish 1 output iob_memgroupsel 1 input iob_bistmode 1 input iob_bistfail 4 output Data memory BIST signals iob_errmap 4 output iob_finish 1 output SCI 1 input SCO 1 output SCTM 1 input Scan chain signals TM 1 input 8KB 4KB Ping-pong 8KB 11

14 14'h0000 Instruction memory section (8KByte).. 14'h2000 Data memory section (4KByte visible).. Control Registers CL[8:0] CSA[8:0] 14'h3000 OBL[7:0] IOBSAINC* IOBSA[10:0] 14'h3004 RBL[7:0] IRBSAINC* IRBSA[10:0] 14'h3008 ITRN[7:0] BN[7:0] 14'h300C DATA_VALID 14'h3010 ACCESS 14'h3014 TMODE[1:0] 14'h3018 BUSY (read only) 14'h301C EXCEPTION (read only) 14'h 'h3024 unused.. *IOBSAINC[4:0], IRBSAINC [4:0] 14'h3FFF 12

15 3. Static Floating Point Arithmetic 3.1. (1)sign (2)exponent (3)mantissasign exponent (normalize) (fractional number) mantissa IEEE s exponent mantissa 1 bit 8 bits 23 bits IEEE754 exponent mantissa mantissa mantissa exponent mantissa 13

16 Floating-point Addition 1. Shift the mantissa to align the exponent part of two numbers 2. Add the mantissas 3. Normalize the sum, checking for overflow or underflow 4. Round the sum (a) Floating-point Multiplication 1. Add the exponent without bias 2. Multiply the mantissa 3. Normalize the product, checking for overflow or underflow 4. Round the product 5. Obtain the result s sign (b) (scale down) tap FIR [ , , , ] FIR [-528, -333, 3425, 6459] 13 (fractional number) mantissa exponent 14

17 3.2. (N+1) (fractional) (two s compliment) (alignment) >>1 >>1 >>1 (N+1)- bit <<1 N-bit fractional >> N (N+1) N N (N+1) Right shift 1-bit Right shift 1-bit +) truncated +) N-bit adder (N+1)-bit adder (a) (b) Round to N-bit (a)n ; (b)n+1 15

18 1-1 sign bit fraction x) radix point result 3.3. (SDFG, synchronous data flow graph) (edge) (1) (2) (3) (4) 3.4. (PEV Analysis) (edge) (node) 16

19 [M, r] M (magnitude)r (radix) exponent M 0.5~1 r [M 1, r 1 ] [M 2, r 2 ] = [M 1 M 2, r 1 + r 2 ] M r : M divided (multiplied) by 2 when r minus (plus) 1 r M r M M 0.5~1 [1 0] [0.5-1] [1-1] [1.5-1] [0.75-2] [0.8 0] [0.6-1] [0.48-1] [0.96 0] 3.5. Affine Form (correlation) (over estimation) y 17

20 affine form affine form (weight) [ w w Λ ] 0 1 w n w 0 w n 0 n w M affine form M = i w i ( ) affine form affine form ( ) affine form affine form M affine form [w x w y w z ] [1 0] [1 0 0] [1-1 0] [1-1] [1 0] [0 1 0] [0 1 1] [1 0 1] [1-1] [1 0] [0 0 1] [1-1] PEV [M r] affine form affine form y affine form 18

21 3.6. A+B C 0.5~1 A [1 0] + C B [1-1] (a) A[1 0] A >> 1 A [0.5-1] + C[1.5-1] C >> 1 C [0.75-2] B[1-1] (b) 19

23 4. Software Generation SDFG Simulator FP (floating point) to SFP (static floating point) Converter with saturation arithmetic ILP-based Scheduler Instruction Generator Floating-point SDFG SDFG Simulator Functionality? SFP Configuration Floating-point to static floating-point (SFP) converter SFP SDFG Precision? Wordlength? DFG structure? PE Configuration Memory Configuration ILP-based Scheduler Scheduled SDFG Control Signal Generation Micro instruction Compiler Micro-instruction 21

24 4.1. (bit-true) 4.2. (exponent) 4.3. (ILP; integer linear programming) 22

25 (a)asap; (b)alap; (c)scheduling range ASAP ALAP ASAP (dependency) (a) ALAP (b) ASAP ALAP (scheduling range) (c) A 0 ASAP ALAP A 0 1~4 A x i,j i j j x i,j 0 1 x i,j 1 i j 0 i j x i,j (c) x x 1.0 1; x x 1.1 1; x x

26 I 0 0~2 x x x 0.2 = 1 x x x x x x x register file register file x x 1.0 1; x x 1.1 1; x x 1.2 1; ILP (Lindo) 4.4. Adder Multiplier Shifter I/O a_mu x_sel [1:0] a_waddr[3:0] a_raddr0[3:0] a_raddr1[3:0] a_sh0_en a_sh1_en a_sh2_en m_mu m_waddr[3:0] m_raddr[3:0] x_sel [1:0] a_pa ss0,1 _en s_mu x_sel [1:0] s_waddr[3:0] s_raddr[3:0] s_shamt[3:0] i_mux _sel [1:0] io_rseq[7:0] s_pass_en 48 io_wseq[7:0] s_wenb a_sat_en m_coeff[15:0] a_sub_en a_wenb reserved 13 i_renb i_wenb reserved m_sh_en reserved m_pass_en m_wenb

27 5. Simulation Result and Hardware Implementation 5.1. IJG (Independent JPEG Group) s JPEG source code 8 8 DCT affine form 16 Algorithm Kernel Cycle count PSNR (db) Single precision FP bit fixed-point integer bit fixed-point integer bit SFP bit SFP

28 5.2. ( )Analog Device Inc.ADSP-218x ADSP-218x Algorithm Kernel ADSP-218x (< 160MHz) Proposed DSP Core (314MHz) 3 rd order lattice filter nd order biquad filter point complex FFT point 1-D DCT D DCT 2,

5.3. DSP CIC UMC 0.18um CMOS Technology UMC 0.18um 1P6M CMOS Core size 1.5 x 1.5 mm 2 Transistor/Gate Count 197655 Power dissipation Max.

29 5.3. DSP CIC UMC 0.18um CMOS Technology UMC 0.18um 1P6M CMOS Core size 1.5 x 1.5 mm 2 Transistor/Gate Count Power dissipation Max. frequency On-chip memory size 52 mw 314 MHz 16KB (8KB data / 8KB instruction) AMBA Interface System Controller DATA Memory (8KB) Instruction Memory (8KB) Computing Engine with SFP 27

31 6. Conclusion RISC DCTFFTlinear filters ( )Analog Device Inc. ADS-218x DSP DCT 24 PSNR db CIC UMC 0.18um CMOS cell-based design flow 314 MHz core size mm 2 52mW physical synthesizable Verilog RTLcycle-accurate SystemC modelseamless CVE model CIC EASY (Example AMBA System) EASY JPEG encoder 29

32 7. Reference [1] J. L. Hennessy and D. A. Patterson, Computer Architecture A Quantitative Approach, 3rd Edition, Morgan Kaufmann, 2002 [2] Digital Signal Processing Using the ADSP-2100 Family, Analog Device Inc., 1990 [3] IEEE Standard for Binary Floating-Point Arithmetic, IEEE Standard 754, 1985 [4] K. K. Parhi, VLSI Digital Signal Processing Systems Design and Implementation, John Wiley & Sons, 1999 [5] F. Fang, R. Rutenbar, M. Puschel, and T. Chen, Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling, in Proc. DAC, 2003 [6] LINDO API User s Manual, LINDO System Inc., 2002 [7] Independent JPEG Group, [8] G. A. Constantinides, P. Y. K. Cheung, W. Luk, Synthesis of saturation arithmetic architectures, ACM Trans. Design Automation of Electronic Systems, July

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2/80 2 2/80 2 3/80 3 DSP2400 is a high performance Digital Signal Processor (DSP) designed and developed by author s laboratory. It is designed for multimedia and wireless application. To develop application