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1 应用资料 3 编程指南应用资料 1 详细介绍了模块的性能与单片机的接口电路及应用指南应用资料 2 详细描述了模块芯片 MCU 的工作程序及工作流程流程示意图,SPI 协议时序图及各种数据应用资料 3 详细介绍了模块与单片机应用编程指南供参考目前 2.4G 产品应用比较广泛, 有些芯片性能也很不错, 但价位都比较偏高, 很难进入量产的产品为降低成本模块采用裸片绑定, 虽然性能指标略低于目前具有代表性的 nrf2401 CC2500 A7105 但它的价格要比它们低很多, 完全可以满足一般需要双向数据传输及双向遥控的短距离产品应用单发单收的产品使用比较简单, 加电加信号就发射, 收到信号就有输出, 纯硬件产品单向传输, 不需要软件程序的支持就可以完成收发功能 2.4G 产品就比较复杂化了, 芯片内有 CPU 需要软件程序的支持, 必须要有单片机的指令才可以完成双向收发功能单发单收的产品成本低廉应用广泛, 但存在着严重的无法避免的同频干扰,2.4G 产品具有跳频功能一般都有几十至 100 多个通道可以避开干扰但 2.4G 产品复杂的软件程序也使一些不懂单片机的工程师望而怯步, 同时 2.4G 产品的功耗及成本还有对墙体的穿透性能下降也影响到在低端产品的普及应用 1

2 确定和单片机的硬件连接后, 开始对单片机编程编程顺序一定义单片机的引脚功能二定义单片机通用寄存器三写模块初始化寄存器的值四写主程序 : 1. 设置单片机端口 2. 写复位 3. 写初始化微处理器寄存器 reg48---reg57 4. 写初始化 RF 寄存器 reg0---reg28 5. 写进入空闲模式五循环主程序 1. 写进入接收模式, 接收数据后由第一个字节判断是否丢失数据, 丢失则返回主循环接收正确的数据后给发射机返回数据, 收发不正确返回主程序 2. 写检测是否按下发射键, 如果有数据要发送则进入发射模式, 发送错误返回主循环 3. 写检测到 10ms 后进入空闲模式, 4. 写检测到 100ms 后进入发射模式编程流程图 2

3 2.4G 测试板程序 (EM78P156) 更改 2.4G 模块测试板 ( 双向数据返回 ) 测试程序 : 接通电源后电源指示灯亮接收处于周期性的休眠与唤醒状态按下主机发送按键主机发送指示灯闪亮从机收到数据后接收指示灯闪亮, 同时从机自动返回主机确认数据, 从机发送指示灯闪亮主机接收指示灯闪亮发送接收成功程序如下 : ;GENERaL REGISTER DEFINE INDF EQU 0X00 TCC EQU 0X01 PCL EQU 0X02 STATUS EQU 0X03 C EQU 0 ;CARRY FLAG,1=CARRY DC EQU 1 ;AUXILIARY CARRY FLAG,1=AUXILIARY CARRY Z EQU 2 ;ZERO FLAG,1=LOGIC OPERATION IS ZERO P EQU 3 ;POWER DOWN BIT T EQU 4 ;TIME-OUT BIT PS0 EQU 5 ; PS1 EQU 6 ;PS1-PS0 PAGE SELECT BIT GP EQU 7 ;GENERAL READ/WRITE BIT FSR EQU 0X04 ISR EQU 0X3F ;INTERRUPT STaTUS REG TCIF == 0 ;TCC OVERFOLW INTERRUPT FLaG ;ICIF == ;PORT6 INPUT STaTUS CHaNGE INTERRUPT FLaG EXIF == 1 ;EXTERNaL INTERRUPT FLaG, SET BY FaLLING EDGE /INT PIN ;****************************************************** ;MaCRO DIFINE ;****************************************************** 3

4 BaNK0 BaNK1 BaNK2 BaNK3 MACRO FSR,7 FSR,6 ENDM MACRO FSR,7 BS FSR,6 ENDM MACRO BS FSR,7 FSR,6 ENDM MACRO BS FSR,7 BS FSR,6 ENDM ;EM78P156 PORT6 assignment PORT6 EQU 0X06 PRESET_N == 6 PPKT_FLG == 5 PSPI_MOSI == 6 PSPI_MISO == 6 PSPI_CLK == 6 PSPI_SS == 6 ;PFIFO_FLG == 6 SPI_MISO == 4 RESET_N == 3 SPI_CLK == 5 SPI_MOSI == 6 SPI_SS == 7 ;FIFO_FLG == 6 PKT_FLG == 1 ;EM78P156 PORT5 assignment PORT5 EQU 0X05 4

5 PUP_LED == 5 PDOWN_LED == 5 PRIGHT_LED == 5 PLEFT_LED == 5 PMI_LED == 5 PHI_LED == 5 UP_LED == 2 RIGHT_LED == 3 MI_LED == 2 HI_LED == 3 ;PORT9 EQU 0X09 IOCA EQU 0X0A IOCB EQU 0X0B IOCC EQU 0X0C IOCD EQU 0X0D IOCE EQU 0X0E IOCF EQU 0X0F ;************************************************** ;BANK0 ;************************************************** A_BUFFER EQU 0X10 FSR_BUFFER EQU 0X11 STATUS_BUFFER EQU 0X12 FLAG EQU 0X13 ;;;0 IS 0 TX 发送 DaTa ;; IS 1 RX 发送 DaTa ;;1 IS 1 10MS 到了需要进入 IDE 模式 ;;2 IS 1 100MS 到了需要进入 RX 模式 SER_DIR == 0 SCAN_10_FINISH == 1 HAS_MAX_SIGNAL == 2 SPIRB EQU 0X14 ;SPI REaD FIFO REGISTER SPIWB EQU 0X15 ;SPI WRITE FIFO REGISTER SUM_UP EQU 0X16 SUM_DOWN EQU 0X17 SUM_LEFT EQU 0X18 SUM_RIGHT EQU 0X19 TIMEINC1 EQU 0X1a TIMEINC2 EQU 0X1B CODE_LEFT EQU 0X1C CODE_RIGHT EQU 0X1D 5

6 ADDR EQU 0X1E ;6210 REGISTER address VaLUE VALUE_H EQU 0X1F VALUE_L EQU 0X20 CH_NO_INDEX EQU 0X21 CH_NO EQU 0X22 ;COM CHaNNEL BUF TEMP0 EQU 0X23 TIMECNT1 EQU 0X26 TEMP1 EQU 0X2E TEMP2 EQU 0X2F CNT1 EQU 0X24 CNT2 EQU 0X25 TABLE_INDEX EQU 0X32 ;6210 REGISTER address INDEX TIMECNT EQU 0X33 COMTEMP EQU 0X34 TEMP3 EQU 0X35 BYTECNT EQU 0X36 RX_BUF0 EQU 0X2A RX_BUF1 EQU 0X2B RX_BUF2 EQU 0X2C RX_BUF3 EQU 0X2D ;************************************************** ;CONSTANT DEFINE ;************************************************** READ_MASK EQU 0X80 ;SPI REaD IS WRITTED "1" RX_MASK EQU 0X80 ;6210 RX CHANNEL MASK FIFO_REG EQU 0X50 ;6210 TX_FIFO REGISTER80 FIFO_PTR EQU 0X52 ;6210 FIFO_RD_PTR REGISTER82 CLR_W_PTR EQU 0X80 ;6210 FIFO_RD_PTR REGISTER82 BIT[15]=1 CLEaR TX_FIFO POINT TO 0 CLR_R_PTR EQU 0X80 ;6210 FIFO_RD_PTR REGISTER82 BIT[7]=1 CLEaR RX_FIFO POINT TO 0 ;************************************************** ;CODE START HERE ;************************************************** ORG 0X00 RESET: JMP MAIN_LOOP ORG 0X08 INT_INT: I 6

7 ;************************************************** ;LOOKUP TABLE ;FaMER REGISTER INITIaL VaLUE(REG48~57) ;************************************************** FRAME_TABLE: ;6210 寄存器 (REG48-57) 参数表 ADD PCL,A ;REGISTER 48 ;DaTa HIGH BYTE ;DaTa LOW BYTE ;VALUE_H ;VALUE_L ;0X96 ;0X28;18 ;0X80 ;0X56 DONGLE ;R52~R55 BE DEFINE BY THUNDER USERS ;IT IS SYNC WORD,THE VaLUE MUST BE SaME as ;PKT_FLG/FIFO_FLG HIGNT active ;0X04 ;0XC4 7

8 ;REG57[13]=1 ;0XC0 ;0XE0 ;0X80 ;0X00 L @0XFF ;LOOKUP TABLE ;RF TRaNSCEIVER REGISTER INITIaL VaLUE(REG0~28) RF_TABLE: ADD PCL,A ;REGISTER9 ;0X82 ;REGISTER 0 ;DaTa HIGH BYTE ;DaTa LOW BYTE

9 ;0X69 9

10 ;LOOKUP TABLE ;RF TRaNSCEIVER CHaNNEL 40 ;MaIN_LOOP MAIN_LOOP: A,@0B ;PRESCaLER 1:256 CONTW A,@0X02 ;@0XFC ;MISO=1, SEaRCH KEY IOW IOCD ;ENaBLE MISO,P90 INTERNaL PULL-HIGH FUNCTION A,@0X10;0;80 ;DISaBLE WDT FUNCTION IOW IOCE A,@0XFF IOW PORT5 a,@0xff PORT5,A 10

11 IOW PORT6 PORT6,A Bs PORT6,2 BS PORT6,1 DELAY_X1MS DELAY_X1MS CLR FLaG BS FLaG.1 CLR TIMEINC1 CLR TIMEINC2 ; INIT_GENERAL_REG RF_RST: PRESET_N,RESET_N DELAY_3US BS PRESET_N,RESET_N ;RESET RF MODULE REGISTER_INIT: A,@1 DELAY_X1MS FRAME_REG_INIT ; 初始化 RF 寄存器 R48-R57 ;88888;; FRAME_REG_TEST ;THE TEST PRO IS FOR PRODUCT DELAY_3US RF_REG_INIT ; 初始化 RF 寄存器 R0-R28 RF_REG_TEST ;THE TEST PRO IS FOR PRODUCT IDLE: ENTER_IDLE_STATE DELAY_3US CaLL IDLE0 ; 进入主循环 MaIN_WaIT_KEY_RECIVER: CaLL ENTER_RX_STaTE ; DELAY_3US ; DELAY_3US FLAG.1 CLR TIMEINC1 CLR TIMEINC2 RD_KEY_AND_RECIVER: BS PORT6,1 11

12 12 DELAY_3US DELAY_3US JBS PPKT_FLG,PKT_FLG JMP $+7 nop RECIVER_DATA ;nop BACK_SEND_DATA DELAY_X1MS BS PORT6,1 JBS PORT5,3 JMP ENTER_TX_STATE TIME_HAVE_10MS J FLAG,1 JMP INTO_IDLE JMP RD_KEY_AND_RECIVER INTO_IDLE: FLAG.2 CLR TIMEINC1 CLR TIMEINC2 ENTER_IDLE_STATE DELAY_3US IDLE0 INTO_IDLE_HAVE_KEY: TIME_HAVE_100MS J FLAG.2 JMP MAIN_WAIT_KEY_RECIVER NOP J PORT5,3 JMP INTO_IDLE_HAVE_KEY FLAG.2 CLR TIMEINC1 CLR TIMEINC2 FLAG.1 JMP MaIN_WaIT_KEY_RECIVER TIME_HAVE_10MS: INC TIMEINC1 A,TIMEINC1 SUB A,@0X8F J STATUS,Z

13 BS FLAG,1 TIME_HAVE_100MS: INC TIMEINC1 A,TIMEINC1 SUB J STATUS,Z INC TIMEINC2 A,TIMEINC2 SUB ;;A,#0X09 J STATUS,Z BS FLAG,2 RECIVER_DATA: PORT6,1 PSPI_SS,SPI_SS A,@80 OR A,@READ_MASK SPIWB,A SIM_SPI_WRITE_AN SIM_SPI_READ_AN A,SPIRB BYTECNT,A XOR A,@5 ;8 JBS STATUS,Z JMP ERR1 SIM_SPI_READ_AN A,SPIRB RX_BUF0,A SIM_SPI_READ_AN A,SPIRB RX_BUF1,A SIM_SPI_READ_AN A,SPIRB RX_BUF2,A SIM_SPI_READ_AN A,SPIRB 13

14 RX_BUF3,A BS PSPI_SS,SPI_SS ENTER_TX_STATE: Bc PORT6,2 JMP TX_STATE BACK_SEND_DATA: Bc PORT6,2 BS FLAG.0 TX_STATE: ENTER_IDLE_STATE DELAY_3US DELAY_3US FLAG.1 CLR TIMEINC1 CLR TIMEINC2 ;CLEAR FIFO WRITE POINT ADDR,A VALUE_H,A VALUE_L,A WRITE_SPI_REG ;TX ON AND SELECT CHANNEL ADDR,A VALUE_H,A ;0X04 VALUE_L,A WRITE_SPI_REG PSPI_SS,SPI_SS ; 所发送数据写入到 FIFO SPIWB,A SIM_SPI_WRITE_AN SPIWB,A 14

15 SIM_SPI_WRITE_AN SPIWB,A SIM_SPI_WRITE_AN SPIWB,A SIM_SPI_WRITE_AN SPIWB,A SIM_SPI_WRITE_AN SPIWB,A SIM_SPI_WRITE_AN BS PSPI_SS,SPI_SS MM: DELAY_3US JBS PPKT_FLG,PKT_FLG JMP MM NOP ; J FLAG.0 ; JMP URNMAIN RECEIVE_SPI JMP WAIT_PKT_HI URNMAIN: FLAG.0 Bs PORT6,2 WAIT_PKT_HI: A,@200 TEMP0,A RD: Bs PORT6,2 DELAY_3US DELAY_3US JBS PPKT_FLG,PKT_FLG JMP TIMOUT 15

16 RECIVER_DATA JMP MAIN_WAIT_KEY_RECIVER TIMOUT: DJZ TEMP0 JMP RD JMP MAIN_WAIT_KEY_RECIVER RECEIVE_SPI: ;CLEAR FIFO WRITE POINT ADDR,A VALUE_H,A VALUE_L,A WRITE_SPI_REG ;RX ON AND SELECT CHANNEL ADDR,A VALUE_H,A VALUE_L,A WRITE_SPI_REG ADDR,A READ_SPI_REG ERR1: A,TEMP1 XOR ;0B J STATUS,Z ;CHECK IF IS DISABLEPA3 STATUS JMP RF_RST BS PSPI_SS,SPI_SS JMP MAIN_WAIT_KEY_RECIVER ENTER_RX_STATE: 16

17 ;CLEAR FIFO WRITE POINT ADDR,A VALUE_H,A VALUE_L,A WRITE_SPI_REG ;RX ON AND SELECT CHANNEL ADDR,A VALUE_H,A VALUE_L,A WRITE_SPI_REG NOP ENTER_IDLE_STATE: ADDR,A VALUE_H,A VALUE_L,A ;ENTER IDLE STATUS WRITE_SPI_REG INTO_SLEEP: ENTER_IDLE_STATE DELAY_3US ; IDLE0 FLAG.1 CLR TIMEINC1 CLR TIMEINC2 LOOP_KEY: NOP JBS PORT5,2 JMP MAIN_WAIT_KEY_RECIVER JBS PORT5,3 JMP MAIN_WAIT_KEY_RECIVER JMP LOOP_KEY 17

18 *********** ;************************************ ; 读 REG64, 检查是否进入 IDLE 状态 ;********************************** IDLE0: A,@64 ADDR,A READ_SPI_REG RRC TEMP1 RRC TEMP1 RRC TEMP1 RRC TEMP1 A,@0X0F AND A,TEMP1 XOR A,@0X0C ;0X0C JBS STATUS,Z JMP ERR1 NOP ;SUBROUTINE PROGRAM /* INIT_GENERAL_REG: A,@0X10 FSR,A CLR_GENERAL_REG: ;WDTC ;CLEAR THE ALL USER'S RAM CLR INDF INC FSR A,FSR J STATUS,Z ; 等于零时结束 JMP INIT_GENERAL_REG_END ;AND A,@0X2F XOR A,@0X3F JBS STATUS,Z JMP CLR_GENERAL_REG ; A,@0X10 ;ADD FSR,A ;JMP CLR_GENERAL_REG INIT_GENERAL_REG_END: 18

19 */ FRAME_REG_INIT: CLR TABLE_INDEX CONFIG_FRAME: ;WDTC A,TABLE_INDEX FRAME_TABLE ADDR,A INC INC TABLE_INDEX A,TABLE_INDEX FRAME_TABLE VALUE_H,A TABLE_INDEX A,TABLE_INDEX FRAME_TABLE VALUE_L,A INC WRITE_SPI_REG TABLE_INDEX A,VALUE_L XOR JBS STATUS,Z ;CHECK IF WRITE FINISH JMP CONFIG_FRAME ;AFTER INITIAL FRAMER REGISTER RF STATUS WILL BE AUTOMATIY ;ENTER IDLE STATUS FROM SLEEP MODE WHEN WAITING CERTAIN TIMING RF_ON: ;WDTC ; 检查模组是否进入了 IDLE 状态 A,@5 DELAY_X1MS A,@64 ADDR,A READ_SPI_REG 19

20 A,TEMP1 XOR ;0B J STATUS,Z ;CHECK IF IS DISABLEPA3 STATUS ;JMP RF_ON A,@57 ADDR,A A,@0XC0 ;CRC,SCRAMBLE IS ON VALUE_H,A A,@0X00 VALUE_L,A WRITE_SPI_REG A,@5 DELAY_X1MS A,@64 ADDR,A READ_SPI_REG A,TEMP1 XOR A,@0XC0 J STATUS,Z ;CHECK IF IS IDLE STATUS SPI_ERROR: ;WDTC ; PORT5,1 ; PORT5,3 ; PORT5,0 ; BS PORT5,2 ;BS PRIGHT_LED,RIGHT_LED PORT6,1 ;IF FRAMER REGISTER HAS ERROR, THEN LED FLASH 32HZ A,@200;128 ; 如果模组寄存器初始化失败, 将给出错误信号指示灯 DELAY_X1MS A,@200;128 DELAY_X1MS ; PORT5,2 BS PORT6,1 A,@50;16 DELAY_X1MS 20

21 21 JMP SPI_ERROR FRAME_REG_TEST: CLR TABLE_INDEX FRAME_REG_TEST0: ;WDTC A,TABLE_INDEX FRAME_TABLE ADDR,A INC TABLE_INDEX A,TABLE_INDEX FRAME_TABLE VALUE_H,A INC TABLE_INDEX A,TABLE_INDEX FRAME_TABLE VALUE_L,A READ_SPI_REG INC TABLE_INDEX A,VALUE_L XOR J STATUS,Z A,VALUE_H SUB A,TEMP1 JBS STATUS,Z JMP ERROR_FRAME A,VALUE_L SUB A,TEMP2 J STATUS,Z JMP FRAME_REG_TEST0 ERROR_FRAME: ; BS PUP_LED,UP_LED ; PORT6,7

22 ; PORT5,1 ; PORT5,3 ; PORT5,0 ;WDTC ;BS PLO_LED,LO_LED ;IF FRAMER REGISTER HAS ERROR, THEN LED FLASH 32HZ A,@32 DELAY_X1MS ; PUP_LED,UP_LED A,@32 DELAY_X1MS JMP ERROR_FRAME ;RF MODULE REGISTER0~28 INITIAL RF_REG_INIT: CLR TABLE_INDEX CONFIG_RF: ;WDTC A,TABLE_INDEX RF_TABLE ADDR,A INC INC INC TABLE_INDEX A,TABLE_INDEX RF_TABLE VALUE_H,A TABLE_INDEX A,TABLE_INDEX RF_TABLE VALUE_L,A WRITE_SPI_REG TABLE_INDEX A,VALUE_L XOR A,@0XFF JBS STATUS,Z JMP CONFIG_RF 22

23 23 ;TEST PROGRAM RF_REG_TEST: CLR TABLE_INDEX RF_REG_TEST0: ;WDTC A,TABLE_INDEX RF_TABLE ADDR,A INC TABLE_INDEX A,TABLE_INDEX RF_TABLE VALUE_H,A INC TABLE_INDEX A,TABLE_INDEX RF_TABLE VALUE_L,A READ_SPI_REG INC TABLE_INDEX A,VALUE_L XOR J STATUS,Z A,VALUE_H SUB A,TEMP1 JBS STATUS,Z JMP ERROR_FRAME A,VALUE_L SUB A,TEMP2 JBS STATUS,Z JMP ERROR_FRAME JMP RF_REG_TEST0 ;R/W REGISTER SPI SUBROUTINE WRITE_SPI_REG:

24 24 PSPI_SS,SPI_SS A,ADDR SPIWB,A SIM_SPI_WRITE_AN A,ADDR SUB J STATUS,C DELAY_3US ;WDTC A,VALUE_H SPIWB,A SIM_SPI_WRITE_AN ;WDTC A,VALUE_L SPIWB,A SIM_SPI_WRITE_AN BS PSPI_SS,SPI_SS READ_SPI_REG: PSPI_SS,SPI_SS A,ADDR OR SPIWB,A SIM_SPI_WRITE_AN A,ADDR SUB J STATUS,C DELAY_3US ;WDTC SIM_SPI_READ_AN A,SPIRB TEMP1,A ;WDTC SIM_SPI_READ_AN A,SPIRB TEMP2,A BS PSPI_SS,SPI_SS

25 ;THE FOLLOWING IS SPI COMMUNICATION USE I/O,NON 451 SPI ;INTERFACE,SPI IS READY DATA ON FALLING EDGE AND READ DATA ;ON RISING EDGE, 250KBPS BAUD E SIM_SPI_WRITE_AN: PSPI_CLK,SPI_CLK ; PSPI_CLK,SPI_CLK JBS SPIWB,7 PSPI_MOSI,SPI_MOSI J SPIWB,7 BS PSPI_MOSI,SPI_MOSI BS PSPI_CLK,SPI_CLK PSPI_CLK,SPI_CLK JBS SPIWB,6 PSPI_MOSI,SPI_MOSI J SPIWB,6 BS PSPI_MOSI,SPI_MOSI BS PSPI_CLK,SPI_CLK PSPI_CLK,SPI_CLK JBS SPIWB,5 PSPI_MOSI,SPI_MOSI J SPIWB,5 BS PSPI_MOSI,SPI_MOSI BS PSPI_CLK,SPI_CLK PSPI_CLK,SPI_CLK JBS SPIWB,4 PSPI_MOSI,SPI_MOSI J SPIWB,4 BS PSPI_MOSI,SPI_MOSI BS PSPI_CLK,SPI_CLK PSPI_CLK,SPI_CLK JBS SPIWB,3 25

26 26 PSPI_MOSI,SPI_MOSI J SPIWB,3 BS PSPI_MOSI,SPI_MOSI BS PSPI_CLK,SPI_CLK PSPI_CLK,SPI_CLK JBS SPIWB,2 PSPI_MOSI,SPI_MOSI J SPIWB,2 BS PSPI_MOSI,SPI_MOSI BS PSPI_CLK,SPI_CLK PSPI_CLK,SPI_CLK JBS SPIWB,1 PSPI_MOSI,SPI_MOSI J SPIWB,1 BS PSPI_MOSI,SPI_MOSI BS PSPI_CLK,SPI_CLK PSPI_CLK,SPI_CLK JBS SPIWB,0 PSPI_MOSI,SPI_MOSI J SPIWB,0 BS PSPI_MOSI,SPI_MOSI BS PSPI_CLK,SPI_CLK PSPI_MOSI,SPI_MOSI PSPI_CLK,SPI_CLK SIM_SPI_READ_AN: A,@0XFF SPIRB,A PSPI_CLK,SPI_CLK BS PSPI_CLK,SPI_CLK JBS PSPI_MISO,SPI_MISO SPIRB,7 PSPI_CLK,SPI_CLK

27 BS PSPI_CLK,SPI_CLK JBS PSPI_MISO,SPI_MISO SPIRB,6 PSPI_CLK,SPI_CLK BS PSPI_CLK,SPI_CLK JBS PSPI_MISO,SPI_MISO SPIRB,5 PSPI_CLK,SPI_CLK BS PSPI_CLK,SPI_CLK JBS PSPI_MISO,SPI_MISO SPIRB,4 PSPI_CLK,SPI_CLK BS PSPI_CLK,SPI_CLK JBS PSPI_MISO,SPI_MISO SPIRB,3 PSPI_CLK,SPI_CLK BS PSPI_CLK,SPI_CLK JBS PSPI_MISO,SPI_MISO SPIRB,2 PSPI_CLK,SPI_CLK BS PSPI_CLK,SPI_CLK JBS PSPI_MISO,SPI_MISO SPIRB,1 PSPI_CLK,SPI_CLK BS PSPI_CLK,SPI_CLK JBS PSPI_MISO,SPI_MISO SPIRB,0 PSPI_CLK,SPI_CLK 27

28 ;TIMERBASE PROGRAM DELAY_3US: ;0.5US ;1US ;2US NOP DELAY_X1MS: CNT1,A DELAY_1MS: ;250*4US=1000US DELAY_X4US: CNT2,A DELAY_1MS0: NOP DJZ CNT2 JMP DELAY_1MS0 DJZ CNT1 JMP DELAY_1MS DELAY_X100MS: TEMP3,A DELAY_X1S0: ;100*1MS=100MS CNT1,A DELAY_X1S1: ;250*4US=1000US CNT2,A DELAY_X1S2: NOP 28

29 DJZ CNT2 JMP DELAY_X1S2 DJZ CNT1 JMP DELAY_X1S1 DJZ TEMP3 JMP DELAY_X1S0 ; RESET VECTOR ORG 0X3FF JMP RESET ; END OF PROGRAM EOP END 29

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