第1章 ISIS编辑器指南

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1 Proteus Design Suit 7 HTTP // 1

2 2

3 PROTEUS PROTEUS Design Suit 7 PROTEUS Windows 98 NT, Millennuium windows LABCENTER MICROSOFT PROTEUS VSM CPU 1G 256MB 150MB 3

4 Proteus LIBRARY PROTEUS 7 PROTEUS 4

5 ISIS 1 ISIS

6 VSM BUG C/C PROTEUS VSM C MPLAB IDE

7 ARES LAYOUT / / D PCB PCB PCB

9 I S I S 9

10 1 ISIS ISIS F6 F7 SHIFT Zoom in( ) Zoom Out( ) Zoom All( ) Zoom Area( ) F8 SHIFT ZOOM 1.2 F5 10

11 SHIFT Shift Pan Pan View Grid command 1thou ISIS / 2 ISIS 11

12 2.1 ISIS PAT 12

13 P P 2. Place Component From Libraries Keywords 741 Operational Amplifiers 13

14 1K,10K,12K,15K,56K,68K 100K Keyword 1k Resistors 1k

15 MINRES1K 90 R2. ISIS Selection 15

16 2D drag object 16

17 1. 2. Rotate Clockwise MINRES1K Drag Object 6. Clear Selection ISIS 2.4 ISIS wiring mode ( ), Selection Mode 17

18 Ctrl ISIS Terminal Icon Edit Properties Edit Properties 18

19 +12V OK V R2 DAC1 DAC2. 19

20 R2 ISIS HELP ---ISIS HELP ISIS ISIS ISIS Real Time Annotation Edit Componet 20

21 R1 R2 R2 ARES Global Annotator( ) 3.2 U th View Snap F2 50th U1 741 F3 100th ISIS 4 21

22 22

23 5 U2:A TL074 ceramic 220pF Block Copy U2:A MINRES12K R6 MINRES15K, MINRES12K R6 100K 10K 23

24 SW-SPDT SW TL074 6 ISIS Edit Properties PAT PAT PAT R5 PAT Tool PAT A, String REF=R#, Count 5 OK 24

25 ISIS PAT PAT ISIS 25

26 ARES ARES back-annotate ISIS ISIS 2D Tools Make Device 7.1 BOX 26

27 ISIS COMPONENT Device Pin ISIS Rotation (Mirror), VIN D0..D5,S1..3 DGND RFB IOUT AGND VDD VBB Drag Object Rotation (Mirror) 27

28 2D Edit Properties IOUT OUTPUT VDD VBB AGND DGND POWER Input VDD VBB AGND DGND PageDown NEXT 28

29 Make Device ISIS 7.2 Library Make Device Make Device 7110 U Next Add/Edit Add PACKAGE DIL16 29

30 A 8 D0 7 D1. 30

31 OK Make Device Make Device Next USERDVC 31

32 DA0 DA5 6 2D 2D ISIS Line TEXT FROM PIO-1A; Template GO TO Master Sheet 2D BOX TEMPLATE SYSTEM HEADER Design ROOT sheet 32

33 Design Edit Design Properties Edit Sheet Properties Edit Sheet Properties Sheet Name Sheet Title Sheet Name Sheet Title Sheet Title Edit Sheet Properties Master Sheet 9 File Save File Printer Setup Print 33

34 TL074 TL074 2D, P System OPAMP

35 Device Pin PIN Marker ISIS TL074 U Next / Add/Edit 11 PCB Add ARES PACKAGE DIL DIL14 4 V+ V- Gate are Interchangeable 35

36 +IP A 3 3. TAB 3 Assign Packages Make Device USERDVC Device Libraries 11.1 TL074, Make Device TL064 TL084 TL064 TL084 36

37 11.2 ISIS Library Make Symbol TEST Symbol TEST logo TEST Help Menu ISIS Help 13 ISIS Tool Design Explor ALT+X Physical Partist View ( ) missing ISIS ARES 37

38 Find C4 ISIS U3, U3 U3-VIN Goto Schematic Net 38

39 ISIS Physical Partslist View Physical Netlist View ( ) SW1 SW1-NO 39

40 GND Cross Probing Design Explorer 14 ISIS Tools PCB ISIS ARES 40

41 15 EPE.DSN EPROM / EPE EPE A3 PSU EMULATION RAM BANK PPSU File menu Open Design EPE.DSN Sample\Schematic&PCB design CPU emalator control ERAM, CTRL+C RAM CTRL+X 41

42 V S M 42

$1 1.1 PROTEUS VSM ISIS ISIS ISIS PIC16F84 PROTEUS Samples\Tutorials\$

43 1 1.1 PROTEUS VSM ISIS ISIS ISIS PIC16F84 PROTEUS Samples\Tutorials\ component P KEYWORD TRAFFIC PIC16F84 TRAFFIC LIGHTS PIC 43

44 VIEW F6 ZOOM IN F7 ZOOM OUT F8 ZOOM ALL ZOOM TO AREA SHIFT SHIFT ISIS Tool Manu PROTEUS PIC LIST p=16f84 ; PIC16F844 is the target processor #include "P16F84.INC" ; Include header file 44

45 CBLOCK 0x10 ; Temporary storage State l1,l2 ENDC org 0 ; Start up vector. goto setports ; Go to start up code. org 4 ; Interrupt vector. halt goto halt ; Sit in endless loop and do nothing. setports clrw ; Zero in to W. movwf PORTA ; Ensure PORTA is zero before we enable it. movwf PORTB ; Ensure PORTB is zero before we enable it. bsf STATUS,RP0 ; Select Bank 1 clrw ; Mask for all bits as outputs. movwf TRISB ; Set TRISB register. bcf STATUS,RP0 ; Reselect Bank 0. initialise clrw ; Initial state. movwf state ; Set it. loop call getmask ; Convert state to bitmask. movwf PORTB ; Write it to port. incf state,w ; Increment state in to W. andlw 0x04 ; Wrap it around. movwf state ; Put it back in to memory. call wait ; Wait :-) goto loop ; And loop :-) ; Function to return bitmask for output port for current state. ; The top nibble contains the bits for one set of lights and the ; lower nibble the bits for the other set. Bit 1 is red, 2 is amber ; and bit three is green. Bit four is not used. getmask movf state,w ; Get state in to W. addwf PCL,F ; Add offset in W to PCL to calc. goto. retlw 0x41 ; state==0 is Green and Red. retlw 0x23 ; state==1 is Amber and Red/Amber retlw 0x14 ; state==3 is Red and Green retlw 0x32 ; state==4 is Red/Amber and Amber. ; Function using two loops to achieve a delay. wait movlw 5 movwf l1 w1 call wait2 decfsz l1 goto w1 return 45

46 wait2 clrf l2 w2 decfsz l2 goto w2 return END SOURCE MENU ADD/REMUVE SOURCE FILE MPASM TL.ASM 2 SOURCE BUILD ALL MPASM HEX 3 PROGRAM HEX * BUG CTRL+F12 DEBUG WATCH WINDOW 46

47 000E F9 F12 Status Bar PC Debug F11 F11 clrw W w A A TRISB 0 Stepping Over F10 F11 getmask 0 W Watch Window 1 BUG W 4 0 W 4 ProteusVSM PROTEUS 47

48 Edit Properties Help PROTEUS

1.4 C/C++ 1.4.1 PROTEUS VSM C PROTEUS VSM 1. ISIS C 2. 3. 4.

49 1.4 C/C PROTEUS VSM C PROTEUS VSM 1. ISIS C PAUSE HEX COD VSM COFF Basic Stamp Program file 49

50 2 2.1 Debug Watch 2.2 Proteus VSM Proteus VSM LCD I2C Debug Configure Diagnostics 50

51 Trace Information Level Full Trace Arm Arm 51

52 2.3 ISIS Source / SPICE 52

53 2.3.2 NET NET ISIS Design Explorer Design Explorer Goto Schematic Net. 53

54 ISIS Edit Properties 3 Digital Analog 1 0 Arm 54

$MPLAB IDE, SAMPLE\VSM Viewer\Eval$ $Board\Explorer16 with$

55 4 OK PLAY CTRL+F12 3 MPLAB IDE Labcenter Microchip MPLAB Proteus VSM Viewer, MPLAB(V7.4 ) Proteus V7 1. MPLAB IDE, SAMPLE\VSM Viewer\Eval Board\Explorer16 with PIC24FJ128GA010\PIC24ExplDemo.mcw. 2. MPLAB IDE Debugger Select Tool Proteus VSM Proteus VSM MPLAB 3. Proteus VSM Viewer MPLAB Open 55

56 4. Project Build All 5. MPLAB IDE Proteus 6. 0 MPLAB IDE Play VSM Viewer 7. MPLAB IDE VSM Viewer MPLAB PIC24 4 PROTEUS VSM R3 R4 10 R1 R2 C1 56

57 ISISTUT.DSN 4.2 PROTEUS GENERATOR ISIS 10mV, 0.5S * ISIS Generators and Probes 57

58 4.3 PROTEUS 4.4 GRAPH ANALOGUE 1 / / / 2 GRAPH ADD TRACE 3 ADD TRACE / ISIS 10KHZ 100us START STOP STOP 1S 100us 4.5 GRAPH SIMULATE SPACE 58

59 0 ESC Graph ViewLog CTRL+V 4.6 CTRL+ 4.7 R4 R4 9.1*10e-8A 4.8 PROTEUS X Y 1 SIMULATION GRAPH FREQUENCY 2 Y PROTEUS REFERENCE GENERATROR 59

60 0dB 1 0 IN HZ 20KHZ 4.9 ISIS DC AC DC AC DC Sweep R1 R2 U1 DC Sweep DC Sweep U1(POS IP) 100k 5M R1 R2 470k X X AC Sweep 50Hz 4.10 ISIS PROSPICE 741 R1 R2 470 IN Edit Noise Graph db 0dB 1 pv Edit Noise Graph Log Spectral Contributions 60

61 A R E S 61

62 1 ARES,.ARES, 3D,,,,, 2 LAYOUT Proteus 7 Professional ARES Professional ARES ARES 62

63 PCB ARES ARES ARES View CTRL+F1 F2+F4 System Set Grids ARES Metric M Origin O Grid G X Cursor X ARES X 63

64 X 3 / 3.1 ARES ARES ARES ARES 64

65 3.2 Package Mode ARES ISIS Package P Library Pick Library Pick Library Browser P System Set Keyboard Mappings Library Browser Google Keywords 200 th pitch radial capacitor CAP20 65

66 CAP20 CAP20 CAP20 CAP20 DIL08 Integrated Circuits Through Hole Dual Inline DIL08 66

67 DIL08 RES40 Discrete Components RES40 Discrete Components RES DIL08 DIL08 ARES 67

68 8 IC DIL08 RES40 IC footprint Pad footprint footprint 68

69 (Drag Object) 3.5 Trace icon (Trace Styles) 20th T20 ARES 20th Trace 69

70 via System Set Layer Pairs PGUP GPDN CTRL-PGUP Top layer CTRL-PGDN Bottom layer CTRL CTRL CTRL 3.6 Selection Mode Edit Properties Part ID Value Auto Name Generator Part ID Values Display 70

71 System Set Template 3.7 ARES EDGE EDGE 1 Box icon 2 Layer Selector EDGE layout Path File New layout layout 3.8 Proteus samples PPSU.LYT 71

72 ratsnest ratsnest Package mode System Set Selection Filter 72

73 Trace bound selection Fully enclosed Partially enclosed PPSU 73

74 Edit Undo CTRL+Z ARES PCB ARES PPSU.LYT 74

75 3.9.2 Delete, Copy and Move the route. Change the layer and trace style. Change the via style. Control the Mitring for the route. (Trim the selection as required for further operations) Via ARES System Set Layer Pairs PGDN PGUP Via 75

76 / ARES Drag Routes(s) Trim 76

77 3.9.6 Delete Delete Routes Delete Chang Trace Style Edit New Trace Style 77

78 3.9.8 ARES System Set Default Rules Pad-Pad Pad-Trace Trace-Trace T10 10TH ARES Connectivity Highlight R 78

79 Delete D 3D ARES Output 3D Visualization Engine 3D PPSU 3D 79

3.10.1 ARES 3D Viewer View 3D Viewer F8 F12 3D View F6 F7

80 ARES 3D Viewer View 3D Viewer F8 F12 3D View F6 F View Navigation F View Auto Spin CTRL+S 80

81 3D File close ESC 3D viewer ARES 3D 3D Viewer 3.11 PCB Windows Windows Gerber Excellon NC Windows Output Printer Setup Windows Windows Output Print point and shoot OK ESC ARES / Set Devices CALTEST.LYT samples\schematic and PCB Design Print XCompensation/YCompensation ARES Printer Setup CADCAM Gerber Cadcam Output 3.12 ARES footprint ARES 81

82 Library Make Package Circular Pad C Box Library Make Package TESTPKG TESTS 3D 3D 3D 3D ARES Help 82

83 3D OK Make Package Package TESTPKG TESTS Output 3D 3D ORIGIN Library Facilities Decompose 2D 83

$DSN samples\tutorials PPSU ISIS PACKAGE PCB ISIS Tools Netlist to ARES ARES PCB PCB ISIS ISIS&ARES$

84 D logo 2D Make Symbol Decompose 3.13 PCB ARES ARES 7 ISIS 99 ARES PCB ARES PPSU PPSU.DSN samples\tutorials PPSU ISIS PACKAGE PCB ISIS Tools Netlist to ARES ARES PCB PCB ISIS ISIS&ARES 84

85 PPSU.LYT Delete Component ARES PPSU Rotation 85

86 PPSU U1 DIL08 ARES 86

87 ARES Force Vectors T25 Tools Auto Trace Selection C1 ARES 25th U1 4 R2 U4 Pin4 R2 Pin2 Layer Selector ARES ARES DRC U1-Pin4 R2-Pin2 R1 Pin2 ARES 87

88 DRC DRC undo CTRL Z DRC System Set Strategies Router Strategies DRC U1 Pin4 Q2 ARES Q2 U1 Pin4 U1 Pin2 R2 U1 SIGNAL DEFAULT R2 U1 Pin3 C1 Bottom Copper U1 Pin3 Edit Mitre PPSU.LYT Tools Auto-Router OK PPSU.LYT Ratsnest GND T 88

89 Edit Mitre ARES / 12VRAIL POWER POWER PCB System Set Strategies POWER Edit Strategy 45 4 H V 89

90 POWER ARES ISIS STRAT < > ARES Netlist Management Autorouting Tools net-group CRC PPSU 1. PPSU.LYT 2. 90

3. 4. GND POWER 5. T 6. 7. Tools Power Plane Generator 8. GND GND POWER 9. OK ARES ARES Power Plane 3.13.

91 3. 4. GND POWER 5. T Tools Power Plane Generator 8. GND GND POWER 9. OK ARES ARES Power Plane Proteus Design Explorer ISIS cross probing ARES ISIS PPSU.LYT, ISIS PPSU.DSN ARES PPSU.DSN / ISIS Design Explorer Physical Partlist View ISIS PCB Goto PCB Part 91

92 ARES / Windows Physical Netslist View ARES / PCB Gerber/CADCAM ARES Output CADCAM CADCAM Output 92

93 93

94 94

PIC16F F MPLAB 08 16F LED 15 LED

PIC16F F MPLAB 08 16F LED 15 LED PIC16F877 PIC16F877 03 16F877 05 06 MPLAB 08 16F877 13 LED 15 LED 17 20 24 2 PIC16F877 PIC16F877 DIP VDD VSS CLOCK CPU :,AND,OR,XOR ROM: CPU ROM RAM: CPU,CPU I/O:CPU, CPU,, 16F877 RAM 512 128 Bank Bank