1 of Microwave Bipolar/FET Bias circuits F/Microwave transistors/fet s require some form of circuit to set the correct bias conditions for a particular F performance. There are two main types used an active current mirror and a passive self-bias circuit. The main purpose of the bias circuit is to maintain the drain/collector current regardless of any drift in the current gain of the GAsFET/Bipolar. In the case of a GAsFET, over time the transconductance falls, with a resulting drop in the bias current. The S- parameters of a device are fixed and don t age so long as the correct bias current is maintained. A drop in bias current, over life, will cause the F device gain and output power to fall. A reduction in the gain of the device in the oscillator may cause oscillation to stop at the band edges where the open loop gain falls off. (1) Active current Mirror - FET The Bias circuit (Shown in Figure 1) works by adjusting the gate voltage to maintain a particular value of drain current. If the drain current falls (say due to a fall in gm) then the current flowing through the PNP transistor to the negative rail will increase. An increase in the current through the collector resistor will cause a larger potential difference across the resistor w.r.t to the negative rail the voltage at the other end of the resistor (connected to the FET gate) will also increase ie go more positive. A more positive voltage on the FET gate will cause a larger drain current to flow so eventually stabilising the circuit and maintaining a constant current to the FET. 1 2 3 -Vee d Figure 1 Showing the Active current mirror using a negative bias to supply a negative voltage to the F/Microwave MESFET. The circuit keeps the drain current constant regardless to the value of gm in the MESFET which falls over life and would under fixed bias cause the drain current to fall. The resistor network 1 & 2 set the Drain voltage applied to the FET ie ( Vds - 0.6) ( Vds - 0.6) ( Vds - 0.6). ( 3-0.6) ( 3-0.6) + Vds Assume 1 3K3Ω, Vbe 0.6V and V 1 1-1 1+ 2. 1 1- rearrange for 1.3300 Calculation of the drain resistor is given by:- F/Microwave 184 0.2 MESFet 3K0Ω 2-1+ 2 ds Ids + Isense.( + Vbe) 3300 -.( + 0.6) 3000 + 3300 129Ω 3 3 1E + 1E
2 of A bias current of about 1mA is allowed to flow through 3, which sets the gate voltage on the FET. Figure 2 shows an ADS simulation of the active bias circuit. The simulator allows all the node voltages and currents to be calculated. After simulation the Annotate Solution is selected which adds all the calculated currents and voltages to be added to the schematic as shown and agrees with the calculated resistors values previously. 1 2 3 c Ic Vc F/Microwave Bipolar V_ SC2 Vdc V 3000 7 129 1 ap_pnp_2n2907a_1993060 Q2 4 3300 8 4700 V_ SC3 Vdc- V ap_pnp_2n2907a_1993060 Q1 6 100 _Feed _Feed1 pf_nec_ne67383_1992121 A1 I_Probe Ic _Feed _Feed2 Figure 3 An active current mirror for biasing a F/Microwave bipolar transistor. The circuit is similar in operation to that of the MESFet accept that a negative bias is not required for the F/Microwave bipolar base. The voltage across 3 is constant ie Vbe ~0.6V The circuit provide a current source for the transistor base used to maintain a constant collector current Ic. (3) Passive Self-Bias Circuit MESFet Figure 2 ADS simulation of an active current mirror bias circuit using the resistor values calculated in the previous example. In practice the feeds need to be realised from inductors or inductive micro-strip line to isolate the F signals around the MESFET from leaking into the bias circuit causing certain signal loss and possible instability. (2) Active current Mirror Bipolar The active current mirror for biasing a F/Microwave bipolar transistor (as shown in figure 3) is very similar in operation to that of the MESFet current mirror except that the loop gain resistor 3 is connected to ground and not a negative bias. There will be a constant voltage across 3 due to the vbe of the F Bipolar but the collector current will be maintained by varying the current drawn by the F Bipolar base junction. (In the MESFet the drain current is maintained by varying the gate bias voltage). An alternative to the active current mirror for biasing is self-bias. This technique uses the F device itself to provide regulation. MESFets are N-type depletion devices and hence require a small negative bias applied to the gate-source junction to obtain a particular drain current. The circuit below sets the gate at ground but a small resistor (s) is placed between the source and ground. Therefore, as current flows through the source resistor (s) the voltage on the source will be greater than ground and hence greater than the gate. This means that a negative gate source bias is still applied. The drain resistor is selected to drop a particular voltage across the resistor (d) to set Vds for a particular drain current (Ids). This circuit works well and is simple however the there is a problem with F grounding the source correctly. Ideally the source needs to be grounded for all frequencies right up at the package, however this is not possible as the source leads will needs to be glued/soldered to a metallised pad this length of pad will add series inductance to the source. Addition of series inductance will modify the S-parameters
3 of of the device and may cause the device to be unstable at a particular frequency. As there is a series resistor in this bias configuration the source can only be grounded via a capacitor. Unfortunately capacitors are not ideal as they will add series inductance due to their electrical length and may be resonant at a particular frequency making the source effectively open-circuit giving rise to instability. Figure 4 Shows the circuit diagram of the FET self-bias circuit. Source decoupling capacitor d Vds F/Microwave Vgs s MESFet Figure 4 Passive self-bias circuit. The Source de-coupling capacitor is required to ensure that there is a F ground on the FET source, which can be a problem when an F ground is required over a wide range of frequencies to ensure F stability. Circuit Analysis Example The formula for calculating the drain current of the MESFet (Ids) is given: FET current formula Where gm transcondu ctance (ms) Using data sheet values for the NEC NE67384 & rearranging formula for vgs, we need to find the value of vgs to give a drain current of 10mA. Ids - Idss vgs gm Therefore value of s vgs/ids 0.6/10E - 3 Value of d (Assuming Vds 3V) - Vds Ids vgs gate to source potential (-ve V ) Idss Saturated drain current (vgs 0V) Ids drain current (ma) 10-40 0-3 200Ω 10E - 3 - Ids (vgs)gm + Idss - 0.6V 60 Ω Unfortunately, with this circuit we need to accurately know the gm and Idss of the device in order to predict the gate voltage required to give a specific drain current and hence what value resistor to fit to the source lead. Figure shows the ADS simulation of a self-bias circuit showing that the required source resistor for a drain current of 10mA was 22ohms (ie a gate voltage of 0.22V compared to the calculated 0.6V derived from the device data sheet). Unlike the active current mirror the initial setup and resistor values are dependant on the gm and Idss of the FET, while these are irrelevant to the active current mirror.
4 of V_ SC2 Vdc V I_Probe Ic _Feed _Feed2 1 c Vce 1 2 200 Ohm 2 Vbe F/Microwave Bipolar pf_nec_ne67383_19921216 A1 1 23 Ohm Emitter decoupling capacitor e Figure ADS circuit schematic of the FET self-bias circuit with a simulator box. The simulation was run and the circuit annotated with the nodal bias conditions. The realisation of the feed for F frequencies is talked about later. Such a feed would also be used on the FET gate to ground it. (4) Passive Self-Bias Circuit Bipolar The circuit for the Bipolar self-bias circuit is shown in figure 6. Here 1 and 2 form a potential divider, which will fix the base potential of the transistor. The current through this bias chain is usually set at 10 times greater than the base current required by the transistor. The base emitter voltage drop of the transistor is approximated as 0.6 volt. There will also be a voltage drop across the emitter resistor, e, this is generally set to about 10% of the supply voltage. The inclusion of this resistor also helps to stabilize the bias: If the temperature increases, then extra collector current will flow. If Ic increases, then so will Ie as Ie Ib + Ic. The extra current flow through e increases the voltage drop across this resistor reducing the effective base emitter voltage and therefore stabilizing the collector current. Figure 6 Passive self-bias circuit for a bipolar transistor. The resistor c may be omitted or substituted by an inductor (choke). The Emitter decoupling capacitor is required as most devices are characterised with the emitter F grounded and to ensure F stability The esistor will add inductance between the emitter and ground. The emitter decoupling capacitor is also known as a de-generating capacitor as without it the gain of the circuit would be the ratio of c and e. The capacitor bypasses the emitter by adding a small parallel AC impedance such the gain of the circuit will the ratio of c and this AC impedance. () Supplying bias to the device All the examples have assumed an ideal feed to the F device. What is required is a low resistance but a high F resistance to ensure that the F circuit is not loaded and F signals do not flow onto the supply lines (Where they could find their way back onto the input of the F device causing gain ripple and possibly instability). At lower frequencies (up to ~1.GHz) the F bias consists of a inductor followed by a shunt capacitor. The inductor chokes any F signal, in other words the F circuit see s an open circuit looking into the inductor. The capacitor shorts out any F leakage through the inductor. However, at very low frequencies where F devices have high gain the inductor will appear as a short circuit, ie will appear invisible to the F circuit. What the F circuit will see however is the short circuit of the capacitor. A short circuit applied to the F
of circuit may cause instability as devices are only guaranteed to be stable in a 0-ohm system. This can be improved by adding a 0- ohm resistor in series with the inductor so that at low frequencies the F circuit will see at least 0 ohms. Figure 7 shows the bias circuit configurations. Decoupling capacitor bias Inductor Choke 0-ohms F device Figure 7 F Bias circuit arrangement. The resistor provides a 0 ohm load to the F transistor at low frequencies (this resistor is omitted on the F bias circuit for the output of the F device.
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