MEMORY DEVICES, CIRCUITS, AND SUBSYSTEM DESIGN MEMORY DEVICES, CIRCUITS, AND SUBSYSTEM DESIGN 9.1 Program and Data Storage 9.2 Read-Only Memory 9.3 Random Access Read/Write Memories 9.4 Parity, the Parity Bit, and Parity- Checker/Generator Circuit 9.5 FLASH Memory 9.6 Wait-State Circuitry 9.7 8088/8086 Microcomputer System Memory Circuitry 611 37100 微處理機原理與應用 Lecture 09-2
9.1 Program and Data Storage The memory unit of a microcomputer is partitioned into a primary storage section and secondary storage section. Memory Unit Primary Storage Memory Program Data Storage Storage Memory Memory Secondary Storage Memory Input Unit MPU Output Unit 611 37100 微處理機原理與應用 Lecture 09-3 9.1 Program and Data Storage The basic input/output system (BIOS) are programs held in ROM. They are called firmware because of their permanent nature. The typical size of a BIOS ROM used in a PC today is 256 Kbytes. Programs are normally read in from the secondary memory storage device, stored in the program storage part of memory, and then run. 611 37100 微處理機原理與應用 Lecture 09-4
9.2 Read-Only Memory ROM, PROM, and EPROM Mask-programmable read-only memory (ROM) One-time-programmable read-only memory (PROM) Erasable read-only memory (EPROM) EPROM Programming unit 611 37100 微處理機原理與應用 Lecture 09-5 9.2 Read-Only Memory ROM, PROM, and EPROM 611 37100 微處理機原理與應用 Lecture 09-6 EPROM erasing unit
9.2 Read-Only Memory Block diagram of a read-only memory Address bus Data bus Control bus Chip enable (CE) Output enable (OE) A 0 -A 10 Address bus ROM O 0 -O 7 Data bus CE OE Control bus 611 37100 微處理機原理與應用 Lecture 09-7 Block diagram of a ROM 9.2 Read-Only Memory EXAMPLE Suppose the block diagram in the previous slide had 15 address lines and eight data lines. How many bytes of information can be stored in the ROM? What is its total storage capacity? Solution: With 8 data lines, the number of bytes is equal to the number of locations, which is 2 15 = 32,768 bytes This gives a total storage of 32,768 x 8 = 262,144 bits 611 37100 微處理機原理與應用 Lecture 09-8
9.2 Read-Only Memory Read operation Address bus A 0 -A 10 8088/8086 MPU Control bus CS Memory Interface circuits MEMR CE A 0 -A 10 OE D0 -D 7 Data bus D 0 -D 7 Read-only memory interface 611 37100 微處理機原理與應用 Lecture 09-9 9.2 Read-Only Memory Standard EPROM ICs EPROM 2716 2732 27C64 27C128 27C256 27C512 27C010 27C020 Density (bits) 27C040 4M Standard EPROM devices 611 37100 微處理機原理與應用 Lecture 09-10 16K 32K 64K 128K 256K 512K 1M 2M Capacity (bytes) 2Kx8 4Kx8 8Kx8 16Kx8 32Kx8 64Kx8 128Kx8 256Kx8 512Kx8
9.2 Read-Only Memory Standard EPROM ICs Pin layouts of standard EPROMs. 611 37100 微處理機原理與應用 Lecture 09-11 9.2 Read-Only Memory Standard EPROM ICs A short delay exists between address inputs and data outputs. Three important timing properties defined for the read cycle of an EPROM: Access time (t ACC ) Chip-enable time (t CE ) Chip-deselect time (t DF ) 611 37100 微處理機原理與應用 Lecture 09-12
9.2 Read-Only Memory Standard EPROM ICs EPROM device timing characteristics 611 37100 微處理機原理與應用 Lecture 09-13 9.2 Read-Only Memory Standard EPROM ICs 611 37100 微處理機原理與應用 Lecture 09-14 EPROM switching waveforms
9.2 Read-Only Memory Standard EPROM ICs A complex series of program and verify operations are performed to program each storage location in an EPROM. The two widely used programming sequences are the Quick-Pulse Programming Algorithm and the Intelligent Programming Algorithm. CMOS EPROMs are designed to provide TTLcompatible input and output logic level. 611 37100 微處理機原理與應用 Lecture 09-15 9.2 Read-Only Memory Standard EPROM ICs Quick-Pulse Programming Algorithm flowchart 611 37100 微處理機原理與應用 Lecture 09-16
9.2 Read-Only Memory Standard EPROM ICs Intelligent Programming Algorithm flowchart 611 37100 微處理機原理與應用 Lecture 09-17 9.2 Read-Only Memory Standard EPROM ICs DC electrical characteristics of the 27C256 611 37100 微處理機原理與應用 Lecture 09-18
9.2 Read-Only Memory Expanding EPROM word length and word capacity 611 37100 微處理機原理與應用 Lecture 09-19 Expanding word length 9.2 Read-Only Memory Expanding EPROM word length and word capacity 611 37100 微處理機原理與應用 Lecture 09-20 Expanding word capacity
9.3 Random Access Read/Write Memories The memory section of a microcomputer system is normally formed from both read-only memories and random access read/write memories (RAM) RAM is different from ROM in two ways: Data stored in RAM is not permanent in nature. RAM is volatile that is, if power is removed from RAM, the stored data are lost. RAM is normally used to store data and application programs for execution. 611 37100 微處理機原理與應用 Lecture 09-21 9.3 Random Access Read/Write Memories Static and dynamic RAMs For a static RAM (SRAM), data remain valid as long as the power supply is not turned off. For a dynamic RAM (DRAM), we must both keep the power supply turned on and periodically restore the data in each location. The recharging process is known as refreshing the DRAM. 611 37100 微處理機原理與應用 Lecture 09-22
9.3 Random Access Read/Write Memories Block diagram of a static RAM The most commonly used densities in RAM IC system designs are the 64KB and 256KB devices. The data lines are bidirectional and the read/write operations are controlled by the CE, OE, WE control signals. A 0 -A 12 Address bus CE, OE, WE Control bus SRAM I/O 0 -I/O 7 Data bus Block diagram of a static RAM 國立台灣大學生物機電系 611 37100 微處理機原理與應用 Lecture 09-23 林達德 9.3 Random Access Read/Write Memories A static RAM system 16K x 16-bit SRAM circuit 611 37100 微處理機原理與應用 Lecture 09-24
9.3 Random Access Read/Write Memories Standard static RAM ICs SRAM 4361 4363 4364 43254 43256A 431000A Density (bits) 64K 64K 64K 256K 256K 1M Organization 64Kx1 16Kx4 8Kx8 64Kx4 32Kx8 128Kx8 Part number 4364-10 4364-12 4364-15 4364-20 Read/write cycle time 100 ns 120 ns 150 ns 200 ns Speed selection for the 4364 SRAM Standard SRAM devices 611 37100 微處理機原理與應用 Lecture 09-25 9.3 Random Access Read/Write Memories Standard static RAM ICs (a) 4365 pin layout. (b) 43256A pin layout 國立台灣大學生物機電系 611 37100 微處理機原理與應用 Lecture 09-26 林達德
9.3 Random Access Read/Write Memories DC electrical characteristics of the 4364 611 37100 微處理機原理與應用 Lecture 09-27 9.3 Random Access Read/Write Memories SRAM read and write cycle operation Data valid Write-cycle timing diagram 611 37100 微處理機原理與應用 Lecture 09-28
9.3 Random Access Read/Write Memories SRAM read and write cycle operation Read-cycle timing diagram 611 37100 微處理機原理與應用 Lecture 09-29 9.3 Random Access Read/Write Memories Standard dynamic RAM ICs Dynamic RAMs are available in higher densities than static RAMs. The most widely used DRAMs are the 64K-bit, 256K-bit, 1M-bit, and 4M-bit devices. Benefits of using DRAMs over SRAMs are: Cost less Consume less power The 16- and 18-pin package take up less space To maintain the data in a DRAM, each of the rows of the storage array must typically be refreshed periodically, such as every 2 ms. 611 37100 微處理機原理與應用 Lecture 09-30
9.3 Random Access Read/Write Memories Standard dynamic RAM ICs SRAM 2164B 21256 21464 421000 424256 44100 44400 44160 416800 416400 416160 Density (bits) 64K 256K 256K 1M 1M 4M 4M 4M 16M 16M 16M 611 37100 微處理機原理與應用 Lecture 09-31 Organization 64Kx1 256Kx1 64Kx4 1Mx4 256Kx4 4Mx1 1Mx4 256Kx16 8Mx2 4Mx4 1Mx16 Standard DRAM devices 9.3 Random Access Read/Write Memories Standard dynamic RAM ICs (a) 2164B pin layout. (b) 21256 pin layout. (c) 421000 pin layout 國立台灣大學生物機電系 611 37100 微處理機原理與應用 Lecture 09-32 林達德
9.3 Random Access Read/Write Memories Standard dynamic RAM ICs Address bus A 0 -A 7 Data input DRAM Data output Q RAS Control inputs CAS W Block diagram of the 2164 DRAM 國立台灣大學生物機電系 611 37100 微處理機原理與應用 Lecture 09-33 林達德 9.3 Random Access Read/Write Memories 64K x 16-bit DRAM circuit 611 37100 微處理機原理與應用 Lecture 09-34
9.3 Random Access Read/Write Memories Evolution of RAM 1970 RAM / DRAM 4.77 MHz 1987 FPM 20 MHz 1995 EDO 20 MHz 1997 PC66 SDRAM 66 MHz 1998 PC100 SDRAM 100 MHz 1999 RDRAM 800 MHz 1999/2000 PC133 SDRAM 133 MHz 2000 DDR SDRAM 266 MHz 2001 EDRAM 450MHz 611 37100 微處理機原理與應用 Lecture 09-35 9.3 Random Access Read/Write Memories Evolution of RAM FPM-Fast Page Mode DRAM -traditional DRAM EDO-Extended Data Output -increases the Read cycle between Memory and the CPU SDRAM-Synchronous DRAM -synchronizes itself with the CPU bus and runs at higher clock speeds 611 37100 微處理機原理與應用 Lecture 09-36
9.3 Random Access Read/Write Memories Evolution of RAM RDRAM-Rambus DRAM -DRAM with a very high bandwidth (1.6 GBps) EDRAM-Enhanced DRAM -(dynamic or power-refreshed RAM) that includes a small amount of static RAM (SRAM) inside a larger amount of DRAM so that many memory accesses will be to the faster SRAM. EDRAM is sometimes used as L1 and L2 memory and, together with Enhanced Synchronous Dynamic DRAM, is known as cached DRAM. 611 37100 微處理機原理與應用 Lecture 09-37 9.4 Parity, the Parity Bit, and Parity- Checker/Generator Circuit To improve the reliability of information transfer between the MPU and memory, a parity bit can be added to each byte of data. The parity-checker/generator circuit can be set up to produce either even parity or odd parity. The parity-check/generator signals parity error to MPU by setting PE to zero. In a 16-bit microcomputer system, there are normally two 8-bit banks of DRAM ICs in the data-storage memory array. A parity bit DRAM is added to each bank. 611 37100 微處理機原理與應用 Lecture 09-38
9.4 Parity, the Parity Bit, and Parity- Checker/Generator Circuit Data-storage memory interface with parity-checker generator 611 37100 微處理機原理與應用 Lecture 09-39 9.4 Parity, the Parity Bit, and Parity- Checker/Generator Circuit (a) Block diagram of the 74AS280. (b) Function table. 國立台灣大學生物機電系 611 37100 微處理機原理與應用 Lecture 09-40 林達德
9.4 Parity, the Parity Bit, and Parity- Checker/Generator Circuit 611 37100 微處理機原理與應用 Lecture 09-41 Even-parity checker/generator connection 9.5 FLASH Memory Flash memory devices are similar to EPROMs in that they are nonvolatile, are read like an EPROM, and program with an EPROM-like algorithm. The key difference between a FLASH memory and an EPROM is that its memory cells are erased electrically, instead of by exposure to ultraviolet light. When an erase operation is performed on a FLASH memory, either the complete memory array or a large block of storage location, not just one byte, is erased. The erase process of FLASH memory is complex and can take as long as several seconds. The FLASH memories find their widest use in microcomputer systems for storage of firmware. 611 37100 微處理機原理與應用 Lecture 09-42
9.5 FLASH Memory Block diagram of a FLASH memory Address bus A 0 -A 17 Data bus CE Control inputs FLASH D 0 -D 7 OE WE Block diagram of a FLASH memory 611 37100 微處理機原理與應用 Lecture 09-43 9.5 FLASH Memory Bulk-erase, boot block, and FlashFile FLASH memory FLASH memory array architectures 國立台灣大學生物機電系 611 37100 微處理機原理與應用 Lecture 09-44 林達德
9.5 FLASH Memory Standard bulk-erase FLASH memories FLASH 28F256 28F512 28F010 28F020 Density (bits) 256K 512K 1M 2M Capacity (bytes) 32Kx8 64Kx8 128Kx8 256Kx8 Standard bulk-erase FLASH memory devices 611 37100 微處理機原理與應用 Lecture 09-45 9.5 FLASH Memory Standard bulk-erase FLASH memories The most popular package for housing FLASH memory ICs is the plastic leaded chip carrier, or PLCC. Part number 28F020-70 28F020-90 28F020-120 28F020-150 Access time 70 ns 90 ns 120 ns 150 ns Pin layout of the 28F020. 611 37100 微處理機原理與應用 Lecture 09-46 Standard speed selection for the 28F020
9.5 FLASH Memory Quick-erase algorithm of the 28F020. 611 37100 微處理機原理與應用 Lecture 09-47 9.5 FLASH Memory Standard bulk-erase FLASH memories 28F020 command definitions 611 37100 微處理機原理與應用 Lecture 09-48
9.5 FLASH Memory Quick-pulse programming algorithm of the 28F020. 611 37100 微處理機原理與應用 Lecture 09-49 9.5 FLASH Memory Standard boot block FLASH memories The boot block FLASH memories are designed for used in embedded microprocessor application. Pin-layout comparison of the TSOP 28F002, 28F004, and 28F008 IC 國立台灣大學生物機電系 611 37100 微處理機原理與應用 Lecture 09-50 林達德
9.5 FLASH Memory Standard boot block FLASH memories One of the important features of boot block FLASH memory is what is known as SmartVoltage. This capability enables the device to be programmed with either a 5-V or 12-V value of V pp. The boot block devices can be organized with either 8-bit or 16-bit bus. Address bus A 0 -A 18(17) RP (F400 only) Data bus CE FLASH D 0 -D 7(15) OE WE WP BYTE (F400 only) Block diagram of the 28F004/28F400 國立台灣大學生物機電系 611 37100 微處理機原理與應用 Lecture 09-51 林達德 9.5 FLASH Memory Standard boot block FLASH memories Another new feature introduced with the boot block architecture is that of a hardware-lockable block. In the 28F004/28F400, the 16Kbyte boot block can be locked by applying logic 0 to the write protected input (WP). Top and bottom boot block organization of the 28F004 國立台灣大學生物機電系 611 37100 微處理機原理與應用 Lecture 09-52 林達德
9.5 FLASH Memory Standard boot block FLASH memories If the 28F400 device is not in use, it can be put into the deep power-down mode to conserve power by switch RP (Reset/Deep power-down) input to logic 0. The 28F004/28F400 uses a command user interface (CUI), status register, and write-state machine to initiate an internally implemented and highly automated method of erasing and programming the blocks of the storage array. This is known as automatic erase and write. 611 37100 微處理機原理與應用 Lecture 09-53 9.5 FLASH Memory Standard boot block FLASH memories 28F004 command bus definition 611 37100 微處理機原理與應用 Lecture 09-54
9.5 FLASH Memory Standard boot block FLASH memories Status register bit definition 611 37100 微處理機原理與應用 Lecture 09-55 9.5 FLASH Memory Standard boot block FLASH memories Erase operation flowchart and bus activity 國立台灣大學生物機電系 611 37100 微處理機原理與應用 Lecture 09-56 林達德
9.5 FLASH Memory Standard FlashFile FLASH memories The highest-density FLASH memories available today are those designed with the FlashFile architecture. FlashFile memories are intended for use in largecode storage applications and to implement solidstate mass-storage devices such as the FLASH card and FLASH drive. The FlashFile memories support block locking. The blocks are independently programmable as locked or unlocked. 611 37100 微處理機原理與應用 Lecture 09-57 9.5 FLASH Memory Standard FlashFile FLASH memories RP 3/5 (SA only) Address bus A 0 -A 20 Data bus CE 0 D 28F016SA/SV 0 -D 15 CE 1 OE RY/BY WE WP BYTE Block diagram of the 28F016SA/SV 國立台灣大學生物機電系 611 37100 微處理機原理與應用 Lecture 09-58 林達德
9.5 FLASH Memory Standard FlashFile FLASH memories 611 37100 微處理機原理與應用 Lecture 09-59 Pin lay-out of the SSOP 28F016SA/SV 9.5 FLASH Memory Standard FlashFile FLASH memories Byte-wide mode memory map of the 28F016SA/SV 611 37100 微處理機原理與應用 Lecture 09-60
9.5 FLASH Memory FLASH packages Source: Micron Technology, Inc., 611 37100 微處理機原理與應用 Lecture 09-61 9.5 FLASH Memory FLASH memory applications Digital cellular phones PDAs Digital cameras LAN switches Digital set-top boxes Embedded controllers BIOS FLASH disk 611 37100 微處理機原理與應用 Lecture 09-62
9.6 Wait-State Circuitry Depending on the access time of the memory devices used and the clock rate of the MPU, a number of wait states may need to be inserted into external memory read and write operations. CS 0 CS 1 MRDC MWTC RESET CLK Wait-state generator READY Wait-state generator circuit block diagram 611 37100 微處理機原理與應用 Lecture 09-63 9.6 Wait-State Circuitry Typical wait-state generator circuit 國立台灣大學生物機電系 611 37100 微處理機原理與應用 Lecture 09-64 林達德
9.7 8088/8086 Microcomputer System Memory Circuitry Minimum-mode 8088 system memory interface 國立台灣大學生物機電系 611 37100 微處理機原理與應用 Lecture 09-65 林達德 9.7 8088/8086 Microcomputer System Memory Circuitry Minimum-mode 8086 system memory interface 國立台灣大學生物機電系 611 37100 微處理機原理與應用 Lecture 09-66 林達德
9.7 8088/8086 Microcomputer System Memory Circuitry Maximum-mode 8088 system memory interface 國立台灣大學生物機電系 611 37100 微處理機原理與應用 Lecture 09-67 林達德 9.7 8088/8086 Microcomputer System Memory Circuitry Program storage memory Attaching several EPROM devices to the system bus expands the capacity of program storage memory. High-order bits of the 8088 s address are decoded to produce chip-select signals. Each chip-select is applied to the CE (chip-enable) input of the EPROM. In the maximum-mode circuit, the 8288 bus controller, rather than the 8088, produces the control signals for the address latches and data bus transceiver. 611 37100 微處理機原理與應用 Lecture 09-68
9.7 8088/8086 Microcomputer System Memory Circuitry Data storage memory Information that frequently changes is normally implemented with random access read/write memory (RAM). If the amount of memory required in the microcomputer is small, the memory subsystem is usually designed with SRAMs. DRAMs require refresh support circuit which is not warranted if storage requirement are small. 611 37100 微處理機原理與應用 Lecture 09-69 9.7 8088/8086 Microcomputer System Memory Circuitry EXAMPLE Design a memory system consisting of 32Kbytes of R/W memory and 32Kbytes of ROM memory. Use SRAM devices to implement R/W memory and EPROM devices to implement ROM memory. The memory devices to be used are shown below. R/W memory is to reside over the address range 00000 16 through 07FFF 16 and the address range of ROM memory is to be F8000 16 through FFFFF 16. Assume that the 8088 microprocessor system bus signals that follow are available for use: A 0 through A 19, D 0 through D 7, MEMR, MEMW. 611 37100 微處理機原理與應用 Lecture 09-70
9.7 8088/8086 Microcomputer System Memory Circuitry SOLUTION: First let us determine the number of SRAM devices needed. No. of SRAM devices = 32Kbyte/(16K x 4) = 4 To provide an 8-bit data bus, two SRAMs must be connected in parallel. Two pairs connected in this way are then placed in series to implement the R/W address range, and each pair implements 16Kbytes. Next let us determine the number of EPROM devices needed. No. of EPROM devices = 32Kbyte/16Kbyte = 2 These two devices must be connected in series to implement the ROM address range and each implement 16Kbytes of storage. 611 37100 微處理機原理與應用 Lecture 09-71 9.7 8088/8086 Microcomputer System Memory Circuitry SOLUTION: Memory map of the system 611 37100 微處理機原理與應用 Lecture 09-72
9.7 8088/8086 Microcomputer System Memory Circuitry SOLUTION: RAM memory organization for the system design 611 37100 微處理機原理與應用 Lecture 09-73 9.7 8088/8086 Microcomputer System Memory Circuitry SOLUTION: ROM memory organization for the system design 611 37100 微處理機原理與應用 Lecture 09-74
9.7 8088/8086 Microcomputer System Memory Circuitry SOLUTION: Address range analysis for the design of chip select signals 611 37100 微處理機原理與應用 Lecture 09-75 9.7 8088/8086 Microcomputer System Memory Circuitry SOLUTION: 611 37100 微處理機原理與應用 Lecture 09-76 Chip-select logic