W77E58 77E58 8051 8051 8051 77E58 8051 1.5 3 COMS 32K EEPROM 1K SRAM 1 8 2 40M 4 3 8051 4 8051 5 4 8 I/O 6 4 I/O 44 PLCC QFP 7 16 / 8 12 9 10 11 1K 12 13 16 DPTR 14 15 DIP40 W77E58 25/40 PLCC44 W77E58P 25/40 QFP44 W77E58F 25/40
/EA I ROM ROM /PSEN O ROM ROM MOVC /PSEN ROM /PSEN ALE O
RST O CPU P0 P1 I/O P1 P1.0 2 P1.1 2 / / P1.2 1 P1.3 1 P1.4 2 /P1.5 3 P1.6 4 /P1.7 5 P4.0 P4.3 I/O 4 I/O P4.0 0 1 2 1 1 (CKCON): :8Eh WD1 WD0: :., 512 (, ). 2 17 2 17 2 20 2 20 2 23 2 23
26 2 26 T2M: 2 : 1 4, 2 12 T1M: 1 : 1 4, 2 12 T0M: 0 : 1 4, 2 12 MD2-0: MOVX. MOVX. MOVX, 77e58../RD /WR. 77E58 SRAM,MOVX. 1(3 )., 0. DPH1 DPL1: DPH1: ::85H DPL1: :86H DPTR1: 16., DPS, DPTR DPTR1, DPS 1,DPTR DPTR DPTR1. DPTR1,. DPS: :86h DPLDPH DPL1/DPH1. 1.DPL1/DPH1, DPL/DPH.. DPS 1-7, 0; :PCON :87H SMOD: 1, 1,2,3. SMOD0: : SMOD0 1,SCON.7(SCON1.7). FE(FE_1(t )). SMOD0 0,SCON.7(SCON1.7) 8052.
GF1-0: PD:POWER DOWN, 1,. IDL: 1,.,. TCON: 88H 8051. :TMOD 89H 8051. P1 :90H P1.7-1.0: I/O.,... : P1.0:T2 / 2 I/O. P1.1:T2EX / 2 /. P1.2:RXD1 1 P1.3:TXD1 1 P1.4:INT2: 2 P1.5: /INT3 3 P1.6: INT4 4 P1.7:/INT5 5 EXIF RG 91H IE5 5 INT5 1 IE4 4 INT5 1 IE3 3 INT5 1 IE2 2 INT5 1 XT/RG: /RC 1 RC 1 XTUP STATUS.4 1 XTOFF PMR.3 0 RGMD RC CPU 0 1 0 SCON
SM0/FE 0 0 PCON SMOD0 0 1 SM1 SM2 SM0 SM1 0 0 0 0 8 4/12 0 1 1 1 10 1 0 2 2 11 64/32 1 1 3 3 11 1 3 SM2 1 9 0 1 9 0 IP: B8H IP.7 PS1 1 1 PT2 1 2 PS 1 0 PT1 1 1 PX1 1 1 PT0 1 0 PX0 1 0 P4 A5H P4.3: 4 I O P4 SETB CLR IE A8H EA ES1 1 ET2 2 ES 0 ET1 1 ET0 1 ET0 0 EX0 0 Stave Address
SADDR A9H SADDR SADEN :B9H SADEN 0 SADEN 1 SADDR SADEN 0 SADEN 0 SADEN1 :BAH SADEN1 1 SADEN1 1 SADDR SADEN1 0 SADEN1 0 1 SCON1 C0H SM0_1/FE_1 1 0 PCON SFR SMOD0 0 1 SM1 SM2 SM0 SM1 0 0 0 0 8 4/12 0 1 1 1 10 1 0 2 2 11 64/32 1 1 3 3 11 1 3 SM2 1 9 0 1 9 0 0 SM2_1 1 0 12 8052 1 4 REN_1 1 1 TB8_1 9 2 3 RB8_1 2 3 9 SM2_1 0 RB8_1 0 TI_1 RI_1 SBUF1
C1H ROMMAP C2H WS 1 /WAIT P4.0 MOVX PMR C4H CD1 CD0 4 64 1024 / 4 64 1024 64 4 4 1024 CD1 CD0 / 0 0 Reserved 0 1 4 1 0 64 1 1 1024 SWB 1 CD1 CD0 4 XTOFF RC 1 0 XTUP STATUS.4 1 ALEOFF 1 ALE ALEOFF ALE DME0 1k MOVX SRAM 1 0 STATUS C5H HIP 1 1 RETI 0 LIP 1 1 RETI 0 XTUP 1 CPU XTOFF 1 0 XT/RG CPU
SPTA1 1. 1 1 TI_1 1 0 1 SWB 1 CD0 CD1 SPRA1 1. 1 8 1 RI_1 1 0 1 SWB 1 CD0 CD1 SPRA0 0. 0 1 RI 1 0 1 SWB 1 CD0 CD1 SPTA0 0. 0 1 TI 1 0 1 SWB 1 CD0 CD1 TA C7H TA TA AAH 55H 2 T2CON C8H TF2 2 2 1 RCLK TCLK 0 0 1 EXF2 CP/RL2 EXEN2 DCEN T2EX P1.1 2 1 0 T2EX RCLK 0 1 3 0 1 1 2 TCLK 0 1 3 0 1 1 2 EXEN2 2 2 T2EX / 0 T2EX T2EX 2 1 TR2 2 0 2 C/T2 / 2 2 0 T2M CKCON.5 1 T2 CP/RL2 / 2 RCLK TCLK 1 0 EXEN1 1 T2EX 1 EXEN2 1 T2EX 1 2 T2MOD
C9H HC5 INT5 CPU 5 5 0 HC4 INT4 CPU 4 4 0 HC3 INT3 CPU 3 3 0 HC2 INT2 CPU 2 2 0 T2CR 2 2 TH2 TL2 2 DCEN : T2EX 16 2 RCAP2L CAH RCAP2L TL2 2 16 RCAP2L 16 TL2 2 RCAP2H CBH RCAP2L TH2 2 16 RCAP2L 16 TH2 2 TL2 CCH 2 TH2 CDH
PSW D0H WDCON D8H SMOD_1: 1 1 2 3 1 POR 0 WDIF 0 WDRF CPU 0 EWT 0 EWT 1 RWT EWDI EIE.4 EWT 512 0 0x0x0xx0B WTRF CPU 1 0 EWT 0 POR EWT WDIF RWT ACC E0H EIE E8H EIE.7 5 1 EWDI EX5 5 EX4 4 EX3 3 EX2 2 B
F0H EIP F8H EIE.7 5 1 EWDI EX5 5 0 1 EX4 4 0 1 EX3 3 0 1 EX2 2 0 1 16 77E58 77E58 8032 8032/77E58
77E58 77E58 8051 P0 P2 P3
bush_yyl@sina.com bush_yyl@hotmail.com 1/25/2005