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CMOS 射频集成电路设计课程项目 唐长文 提交期限 : 2007 年 1 月 25 日,26 日课程项目报告 1. 项目简介射频电视调谐器芯片是将射频 50-860MHz 信道中的带宽 8MHz 的数字电视信号下变频到低中频 (7.2MHz) 上的一款射频前端电路 该项目的最终目标是在保证信道性能的前提下减小片外元件的需求, 达到 CMOS 工艺全集成 射频电视调谐器芯片系统结构框图如下所示 : 75Ω UpMixer RF Front-end DnMixer Analog Front-end Anti-Alias Pre-Filter VGA Filter Digital Baseband Complex Mixers I ADC I Band Limit Filter LNA First LO Second LO (Quadrature) Image Rejecter Error Detector PLL Q ADC Q Pre-Filter Anti-Alias Filter VGA RF CMOS TV Tuner for DVB-T/C System 芯片涉及到的主要核心模块有 : 宽带低噪声放大器 上 / 下变频混频器 第一级宽带频率综合器 第二级窄带频率综合器 固定增益低通滤波器, 抗叠混带通虑波器, 可控增益低通滤波器, 抑制镜像电路, 模数转换器等 1

2. 项目目标最终达到标准 CMOS 单芯片集成, 与基带信道解码器 (Demodulator) 芯片构成整个数字电视接收系统 整个射频 / 模拟前端芯片的电路结构如下图 : 芯片电路示意图该芯片的难点在于宽带低噪声放大器和低相位噪声频率综合器的设计和实现 2

系统芯片指标射频电视调谐器芯片的性能指标如下 : 频率范围 Frequency Range 信道带宽 Channel Bandwidth 最大增益 Maximum Gain 噪声系数 NF @ Max. Gain 灵敏度 Sensitivity 三阶交调量 IIP3 @ 20dB RF AGC Attenuation 二阶交调量 IIP2 @ 20dB RF AGC Attenuation 信道选择性 Channel selectivity (8MHz BW setting) @ 5.25MHz offset @ 5.75MHz offset I/Q 匹配性本振相位噪声 1kH-3.8MHz LO1@10kHz, @100kHz LO2@10kHz, @100kHz, Quadrature generator 功耗 Power consumption 芯片面积 Die size 50MHz-860MHz 8MHz 80dB <8dB -85dBm +8.5dBm +45dBm 29db 45dB -45dBc -37dBc -86dBc/Hz, -107dBc/Hz -92dBc/Hz, -112dBc/Hz <180mW@1.8V <9mm 2 @ 0.18µm CMOS 3. 课程项目 a) 宽带低噪声放大器设计 b) 宽带上变频混频器设计 c) 窄带正交下变频混频器设计 d) 宽带电感电容压控振荡器设计 e) 窄带正交输出电感电容压控振荡器设计 f) 宽带频率综合器设计 g) 窄带频率综合器设计 h) 固定增益低通滤波器设计 i) 抗叠混带通滤波器设计 j) 可变增益低通滤波器设计 k) 功率放大器 (RFID Reader) 设计上述 11 个设计项目任选一个, 独立完成电路级设计和仿真工作, 撰写完整设计报告 设计报告包括 : 电路图,Testbench 电路图, 元器件参数, 理论和原理分析, 手工计算, 性能仿真结果等 文档的整洁 排版格式 图中线条和文字的清晰度等占总分的 20% 3

1 宽带低噪声放大器设计 性能指标 : Input impedance Output impedance Bandwidth Minimum input level Maximum input level Gain IIP2 IIP3 Noise figure 75Ω over 50 860MHz bands Differential input No requirement Differential output Approx. 50 860MHz 13.8 dbµv rms (4.90µV, 94.95dBm) 105 dbµv (178mV, 3.75dBm) 12dB to 10dB, RF AGC range: 22dB 3bits, AGC Gain Step 3dB >145dBµV (36.25dBm) >120dBµV (11.25dBm) <4dB <1.8V*5mA=9mW [1] F.Bruccoleri, E. A. M. Klumperink, and B. Nauta, Wide-band CMOS low-noise amplifier exploiting thermal noise canceling, IEEE J. Solid-State Circuits, Vol.39, pp. 275-282, Feb. 2004. [2] S. B. T. Wang, A. M. Niknejad, and R. W. Rrodersen, A Sub-mW 960-MHz Ultra-Wideband CMOS LNA, Radio Frequency integrated Circuits (RFIC) Symposium, pp. 35-38, June 2005. [3] W Zhuo, S Embabi, J. Pineda de Gyvez, and E. Sanchez-Sinencio, Using capacitive cross-coupling technique in RF low noise amplifiers and down-conversion mixer design, in Proc. 26 th Eur. Solid State Circuits Conf., Sept. 2000, pp.116-119. [4] T. W. Kim, B. Kim, A 13-dB improved low-power CMOS RF programmable gain amplifier using differential circuit transconductance linearization for various terrestrial mobile D-TV applications, IEEE J. Solid-State Circuits, Vol.41, pp. 945-953, Apri. 2006. [5] T. W. Kim, B. Kim, and K. Lee Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors, IEEE J. Solid-State Circuits, Vol.39, pp. 223-229, Jan. 2004. [6] A. Amer, E. Hegazi, and H. Ragai, A low-power wideband CMOS LNA for WiMax, IEEE Transaction on Circuits and System II: Brief Paper, Dec. 2006. 4

2 宽带上变频混频器设计 性能指标 : IF frequency Input bandwidth Output bandwidth Minimum input level Maximum input level LO mixing signal Conversion gain IIP2 IIP3 Noise Figure Double Balance Architecture 1120MHz Approx. 50 860MHz 8MHz bandwidth @ 1120MHz 25.8dBµV rms (19.5µV, 83.0dBm) 95dBµV (56.2 mv, 13.8dBm) >0dBm(273.9mV) >5dB >145dBµV(36.25dBm) >122dBµV(13.25dBm) <8dB <1.8V*5mA=9mW Differential Input/Differential Output [1] E. A. M. Klumperink, S. M. Louwsma, G.J.M. Wienk, and B. Nauta, A CMOS switched transconductor Mixer, IEEE J. Solid-State Circuits, vol.39, pp.1231-1240, Aug. 2004. [2] M.T. Terrovitis and R. G. Meyer, Noise in current-commutating CMOS mixers, IEEE J. Solid-State Circuits, vol. 34, pp. 772-783, June 1999. [3] M. T. Terrovitis, and R. G. Meyer Intermodulation Distortion in Current-Commutating CMOS Mixer, IEEE Journal of Solid State Circuits, vol.35, pp.1461-1473, Oct. 2000. [4] H. Darabi and A. A. Abidi, Noise in RF-CMOS mixers: A simple physical model, IEEE J. Solid-State Circuits, vol. 35, pp. 15-25, Jan. 2000. [5] S. Chehrazi, R. Bagherl, and A. A. Abidi Noise in passive FET mixer, IEEE 2004 Custom Integrated Circuits Conference, pp.375-378. [6] D. Manstretta, M. Brandolini, F. Svelto, Second-order intermodulation mechanisms in CMOS downconverters, IEEE J. Solid-State Circuits, vol. 38, pp. 394-406, March. 2003. [7] H. Darabi and Janice Chiu, A Noise cancellation technique in active RF-CMOS mixers, IEEE J. Solid-State Circuits, vol. 40, pp. 2628-2632, Dec. 2005. [8] T. W. Kim, B. Kim, and K. Lee Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors, IEEE J. Solid-State Circuits, Vol.39, pp. 223-229, Jan. 2004. 5

3 窄带正交下变频混频器设计 性能指标 : Input bandwidth Output bandwidth Minimum input level Maximum input level LO mixing signal Conversion gain IIP2 OIP2 IIP3 Noise Figure Double Balance Architecture Image Reject 8MHz bandwidth @ 1120MHz 8MHz bandwidth @ 30 50MHz 30.8dBµV rms (34.7µV, 77.95dBm) 100dBµV peak amp (100 mv) Optimum (100 mv, 8.75dBm) >0dBm(273.9mV) >10dB 146dBµV(37.25dBm) 180dBµV(71.25dBm) 127dBµV(18.25dBm) <15dB <1.8V*5mA=9mW Differential Input/Differential Output [1] E. A. M. Klumperink, S. M. Louwsma, G.J.M. Wienk, and B. Nauta, A CMOS switched transconductor Mixer, IEEE J. Solid-State Circuits, vol.39, pp.1231-1240, Aug. 2004. [2] T. Terrovitis, and R. G. Meyer Intermodulation Distortion in Current-Commutating CMOS Mixer, IEEE Journal of Solid State Circuits, vol.35, pp.1461-1473, Oct. 2000. [3] H. Darabi and A. A. Abidi, Noise in RF-CMOS mixers: A simple physical model, IEEE J. Solid-State Circuits, vol. 35, pp. 15-25, Jan. 2000. [4] H. Darabi and Janice Chiu, A Noise cancellation technique in active RF-CMOS mixers, IEEE J. Solid-State Circuits, vol. 40, pp. 2628-2632, Dec. 2005. [5] S. Chehrazi, R. Bagherl, and A. A. Abidi Noise in passive FET mixer, IEEE 2004 Custom Integrated Circuits Conference, pp.375-378. [6] D. Manstretta, M. Brandolini, F. Svelto, Second-order intermodulation mechanisms in CMOS downconverters, IEEE J. Solid-State Circuits, vol. 38, pp. 394-406, March. 2003. [7] R. Montemayer, A 410-mW 1.22-GHz Downconverter in a Dual-Conversion Tuner IC for OpenCable Applications, IEEE J. Solid-State Circuits, vol. 39, pp. 714-718, April 2004. [8] T. W. Kim, B. Kim, and K. Lee Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors, IEEE J. Solid-State Circuits, Vol.39, pp. 223-229, Jan. 2004. 6

4 宽带电感电容压控振荡器设计 性能指标 : Tuning range Phase noise Output Voltage, Vpp 1150MHz 2000MHz (IF1=1120MHz) < 87dBc/Hz@10kHz < 110dBc/Hz@100kHz < 130dBc/Hz@1MHz >1.2V <1.8V*6mA=10.8mW [1] Hajimiri and T.H. Lee, Design issues in CMOS differential LC oscillators, IEEE J. Solid-State Circuits, vol. 34, pp.717-214, May 1999. [2] D. Ham, and A.Hajimiri, Concepts and method in optimization of integrated LC VCOs, IEEE J. Solid-State Circuits, vol. 36, pp.896-909, June. 2001. [3] A. Jerng, and C. G. sodini, The impact of device type and sizing on phase noise mechanisms, IEEE J. Solid-State Circuits, vol. 40, pp. 350-369, Feb. 2005. [4] A. Kral, F. Behbahani, and A. A. Abidi, RF-CMOS oscillators with switched tuning, IEEE Custom Integrated Circuits Conference, pp.555-558, 1998. [5] S. M. Oh, C.W. Kim, and S.-G. Lee, A 74%, 1.56-2.71 GHz, wide-tunable LC-tuned VCO in 0.35-mm CMOS technology, Microwave and Optical Technology Letters, vol. 37, pp.98-100, April, 2003. [6] A.D. Berney, A.M. Niknejad, R.G. Meyer, A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration, IEEE J. Solid-State Circuits, vol. 40, pp. 909-917, April 2005. [7] 唐长文, 何捷, 闵昊. 一种采用开关阶跃电容的压控振荡器 ( 上 ): 调谐特性的理论分析. 半导体学报. 2005 年第 10 期. [8] 唐长文, 何捷, 闵昊. 一种采用开关阶跃电容的压控振荡器 ( 下 ): 电路设计和实现. 半导体学报. 2005 年第 11 期. 7

5 窄带正交输出电感电容压控振荡器设计 性能指标 : Tuning range Phase noise Output Voltage, Vpp Quadrature Output Quadrature Phase Error Quadrature Amplitude Error 1050MHz 1190MHz (IF1=1120MHz) < 92dBc/Hz@10kHz < 112dBc/Hz@100kHz < 132dBc/Hz@1MHz >1.2V I+, I, Q+, Q <1 <0.5dB <1.8V*6mA=10.8mW [1] J. Tang, P. Ven, D. kasperkovitz, and A. Roermund, Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator, IEEE J. Solid-State Circuits, vol. 37, pp.657-661, May 2002. [2] P. Andreani, A. Bonfanti, L. Romano, and C. Samori, Analysis and design of a 1.8-GHz CMOS LC quadrature VCO, IEEE JSSC, vol. 37, pp.1737-1747, Dec. 2002. [3] S. L. J. Gierkink, S. Levantino, R. C. Frye, C. Samori and V. Baccuzzi, A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling, IEEE J. Solid-State Circuits, vol. 38, pp.1148-1154, July. 2003. [4] C. W. Yao, and A. N. Willson, A phase-noise reduction techniques for quadrature LC-VCO with phase-to-amplitude noise conversion, 2006 IEEE International Solid-State Circuits Conference, 11.3. [5] A. Mazzanti, P. Uggetti, F. Svelto, Analysis and design of injection-locked LC dividers for quadrature generation, IEEE JSSC, vol. 39, pp.1425-1433, Sept. 2004. [6] A. Mazzanti, F. Svelto, A 1.8-GHz injection-locked quadrature CMOS VCO with low phase noise and high phase accuracy, IEEE Transaction on CAS I: Regular papers, vol. 53, pp.554-560, Mar. 2006. [7] A. Mazzanti, F. Svelto, and P. Andreani On the amplitude and phase errors of quadrature LC-tank CMOS oscillators, IEEE JSSC, vol. 41, pp.1305-1313, June 2006. [8] L. Romano, S. Levantino, C. Samori, and A. L. Lacaita, Multiphase LC oscillators, IEEE Transaction on CAS I: Regular papers, vol. 53, pp.1579-1588, July 2006. [9] P. Andreani, A time-variant analysis of the 1/f 2 phase noise in CMOS parallel LC-tank quadrature oscillators, IEEE Transaction on CAS I: Regular papers, vol. 53, pp.1749-1760, Aug. 2006. 8

6 宽带频率综合器设计 性能指标 Tuning range Frequency Step Reference Frequency Locked Time Phase noise Reference Spurs Integer-N Architecture 1150MHz 2000MHz (IF1=1120MHz) 12.5MHz 25MHz <200µS < 87dBc/Hz@10kHz < 110dBc/Hz@100kHz < 130dBc/Hz@1MHz < 80dBc <1.8V*3mA=5.4mW, excluding VCO [1] 何捷, DVB-T 接收机中频率综合器的研究,2005 年 5 月, 复旦大学博士论文 [2] Li Lin, Design Techniques for High Performance Integrated Frequency Synthesizer for Multi-standard Wireless Communication Applications, Ph.D Dissertation, University of California, Berkeley, 2000. 注意 : 本题中的压控振荡器由选择题 4 的同学配合设计 9

7 窄带频率综合器设计 性能指标 Tuning range Frequency Step Reference Frequency Locked Time Phase noise Frequency Spur Σ Fractional-N Architecture 1050MHz 1190MHz (IF1=1120MHz) <62.5kHz 25MHz <100µS < 92dBc/Hz@10kHz < 112dBc/Hz@100kHz < 132dBc/Hz@1MHz < 80dBc <1.8V*3mA=5.4mW excluding VCO [1] 何捷, DVB-T 接收机中频率综合器的研究,2005 年 5 月, 复旦大学博士论文 [2] Li Lin, Design Techniques for High Performance Integrated Frequency Synthesizer for Multi-standard Wireless Communication Applications, Ph.D Dissertation, University of California, Berkeley, 2000.W. Rhee, B. S. Song, and A. Ali, A 1.1-GHz CMOS fractional-n frequency synthesizer with a 3-b third-order Σ modulator, IEEE J. Solid-State Circuits, vol. 35, pp.1453-1460, Oct. 2000. [4] C. H. Heng, and B. S. Song, A 1.8-GHz CMOS fractional-n frequency synthesizer with randomized multiphase VCO, IEEE J. Solid-State Circuits, vol. 38, pp.848-854, June. 2003. [5] H. Lee, J. K. Cho, K. S. Lee, I. C. Hwang, T. W. Ahn, K. S. Nah, B. H. Park, A Σ fractional-n frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications, IEEE J. Solid-State Circuits, vol. 39, pp.1164-1169, July 2004. [6] B. D. Muer, M. S. J. Steyaert, A CMOS monolithic Σ -controlled fractional-n frequency synthesizer for DCS-1800, IEEE J. Solid-State Circuits, vol. 37, pp.835-844, July 2002. [7] W. Rhee, B. S. Song, and A. Ali, A 1.1-GHz CMOS fractional-n frequency synthesizer with a 3-b third-order Σ Modulator, IEEE J. Solid-State Circuits, vol. 35, pp.1453-1460, Oct. 2000. [8] M. Gupta, and B. S. Song A 1.8-GHz spur-cancelled fractional-n frequency synthesizer with LMS-based DAC gain calibration, IEEE J. Solid-State Circuits, vol. 41, pp.2842-2851, Dec. 2006. 注意 : 本题中的压控振荡器由选择题 5 的同学配合设计 10

8 固定增益低通滤波器设计 性能指标 Input/output bandwidth Cut off frequency Attenuation @ 14.4MHz Minimum input level Maximum input level Gain IIP2 IIP3 Noise Figure 0-11.2MHz 11.3MHz >20dB 40.8dBµV rms (109.6µV, 68.0dBm) 99.5dBµV peak amp (94mV, -9.25dBm) 15dB 160dBµV (51.25dBm) 135dBµV (26.25dBm) <15dB <1.8V*5mA=9mW 11

9 抗叠混带通滤波器设计 性能指标 Input/output bandwidth Pass-band gain Cuff off frequency Attenuation @ 1.95MHz, 12.45MHz Stop-band frequency Stop-band attenuation I/Q cut-off mismatch Minimum input level Maximum input level IIP2 IIP3 Noise Figure 3.2-11.2MHz ( 8MHz Bandwith) 6dB, ripple<0.5db 3.1MHz, 11.3MHz >20dB >60dB <40kHz 55.8dBµV rms (616.7µV, 53.0dBm) 114.5dBµV (approx. 531mV, 5.75dBm) 170dBµV (61.25dBm) 139dBµV (30.25dBm) <35dB <1.8V*10mA=18mW 12

10 可变增益低通滤波器设计 性能指标 Input/output bandwidth Minimum input level Maximum input level Gain I & Q mismatch IIP2 IIP3 Noise Figure 0-11.2MHz 61.8dBµV rms (616.7µV, 47.0dBm) 108.8dBµV (275mV, 0dBm) -4.8 to +42.2dB, 47dB AGC range, with tuning step 6dB <2dB gain mismatch between I & Q paths 130dBµV (21.25dBm) 135dBµV (26.25dBm) <35dB <1.8V*5mA=9mW 13

11 功率放大器设计 性能指标 Frequency range load RF output power RF input power Power-added-efficiency PAE @ P1dB Gain Output spurs and harmonics Stability factor Architecture 860-960MHz 50Ω +20 to +25dBm <5dBm >30% 20 to 30 db -50dBc >1 Linear PA 14