SYSTEM PGE REF. PGE lock iagram System Setting PU()_MI,PEG,FI,LK,MIS PU()_R PU()_FG,RSV,GN PU()_PWR PU()_XP R SOIMM_0 R SOIMM_ R _Q VOLTGE VI ONTROLLER 0 PH_IEX()ST,IH,RT,LP PH_IEX()_PIE,LK,SM,PEG PH_IEX()_FI,MI,SYS PWR PH_IEX()_P,LVS,RT PH_IEX()_PI,NVRM,US PH_IEX()PU,GPIO,MIS PH_IEX()_POWER,GN PH_IEX()_POWER,GN PH_SPI ROM,OTH LK_ISLRS 0 E_IT0(/) E_IT0(/)K, TP,FP RST_Reset ircuit HNKSVILLE LNR UL UHEPHONE & SPEKER 0 _RU0 _Neward UG_ebug RT_L Panel RT_Sub isplay Port TV_HMI 0 FN_Fan & Sensor X_H & O US_US Port * MINIR(WLN) LE_Indicator SG_ischarge PW_PROTET 0 _ & T onn. T_luetooth TUN_TV Tuner ME_onn & Skew Hole ES_EST PH_XP, ONFI 0 VG_MXM 0 0 ontent PW_VORE(MX0) PW_SYSTEM(MX00) PW_I/O_VTT_PU&+.VM PW_I/O_R & VTT& +.VS PW_I/O_VM & ME_+VM_PWEG PW_+VGFX_ORE(MX0) PW_HRGER(MX0) PW_ETET PW_LO SWITH PW_SIGNL PW_FLOWHRT M0J SHEMTI Revision.00 R.,removed. R.,added. R., REMOVE. LOK IGRM P isplay Port HMI RT Page Page L Panel Page Touchpad Page Keyboard Page rray Mic udio mp Jack Page Page INT. MI Page Page Page Page 0 MXM (R.a) nvii N0PGS lock Generator ISLRS R.,changed Page 0 ebug onn. SPI E ROM ITE IT0E R.,removed. R. Page E ITE IT0E R.,changed rray Mic.SP Fortemedia FM00 zalia M zalia odec Realtek L Page Page 0 Page 0 Page Page Page ardreader+ Ricoh RU0 ardreader R., HNGE. Page 0 Page 0 HMI RT ep R.,removed. LVS R., HNGE. R., HNGE. PIE x SMus LP zalia PWM Fan Page Page 0 PIE x VI controller PU LRKFIEL MI x PH Ibex PeakM Page PM ST 0 Page ~ Page 0~ SPI IOS ROM R. Page O H() R NV_Q PIE x US Page H() Page Page est Page ischarge ircuit Page Reset ircuit Page 0 0 R SOIMM R 0/MHz Page ~ ONFI raidwood R.,removed. Miniard WLN Shirley Peak/ Echo Peak Page Miniard TV Tuner GigaLN R R.,changed Page Expressard US Port() US Port() US Port() & TT. onn. Page 0 Skew Holes Page Page Page Page Page Page Page US Port() Page N G Page SUSTeK OMPUTER IN. N R.,removed. RJ Page lock iagram James_Wu M0J Power VORE System.VS &.0VS R & VTT +.VS harger etect Load Switch Power Protect MOS amera Miniard TV Tuner luetooth. Finger Print. N Page 0 Page Page Page Page Page Page 0 Page Page EST controller PREES ST solution Remove when fixed. Page N OLE Page Page Page Page Page US Port() Page Thursday, July 0, 00 ate: Sheet of.00
PH_IEX GPIO PH_IEX GPIO Use s Signal Name GPIO 00 GPO N_TP GPIO 0 GPO N_TP GPIO [:] GPI PI_INT[E:H]# GPIO 0 GPO N_TP GPIO 0 GPO N_TP GPIO 0 GPI EXT_SMI# GPIO 0 Native N_PU GPIO 0 Native N_PU GPIO GPI EXT_SI# GPIO Native N_TP GPIO GPO N_TP GPIO GPO N_PU GPIO GPO T_LE GPIO GPI GPU_HOL_RST# GPIO GPI GPU_PWROK GPIO GPI LKREQ#_TV GPIO GPI STGP GPIO 0 Native LKREQ#_WLN GPIO GPI ST0GP GPIO GPO WLN_LE GPIO Native N_TP GPIO GPO N_TP GPIO GPI LKREQ#_NEWR GPIO GPI LK_REQ#_ GPIO GPO N_TP GPIO GPO WLN_ON# GPIO Native N_TP GPIO 0 GPO ME_SusPwrnck GPIO Native ME PRESENT GPIO GPIO PM_LKRUN# GPIO GPI H_OK_EN# GPIO Native N_TP GPIO GPO ST_LK_REQ# GPIO GPI GPU_PWR_EN# GPIO GPI GPU_PRSNT# GPIO GPI P_I0 GPIO GPI P_I GPIO 0 Native N_PU GPIO Native N_PU GPIO Native N_PU GPIO Native N_PU GPIO Native LK_REQ# GPIO Native N_TP GPIO Native N_TP GPIO GPI LKREQ_PEG# GPIO GPO N_TP GPIO GPIO PH_TEMP_LERT# GPIO 0 Native PI_REQ# GPIO Native PI_GNT# GPIO Native GPU_SELET#_R GPIO GPO N_TP GPIO Native PI_REQ# GPIO Native PI_GNT# GPIO GPI LKREQ_GLN# GPIO GPO T_ON GPIO GPIO SML_LK GPIO Native N_PU GPIO 0 Native SML0LERT# GPIO Native N_TP GPIO Native N_TP GPIO Native N_TP GPIO Native N_TP GPIO Native N_TP GPIO Native N_TP GPIO Native N_TP GPIO Native PM_TLOW# GPIO Native LK_REQ0# GPIO Native SMLLERT# GPIO GPIO SML_T Internal & External Pullup/down INT T EXT PU INT T INT T EXT PU & INT PU EXT PU EXT PU EXT PU EXT PU INT P EXT PU EXT P & INT T EXT P EXT PU EXT P EXT PU EXT P INT PU EXT P EXT PU EXT PU EXT PU EXT PU EXT PU EXT PU EXT PU EXT PU EXT PU INT PU INT PU INT PU EXT PU(IOE) EXT PU EXT PU EXT PU INT T INT T INT T INT T EXT PU EXT PU EXT PU Power +VS +VS +VS +VS +VS +VSUS +VSUS +VSUS +VSUS +VSUS +VSUS +VSUS +VSUS +VS +VS +VS +VS +VS +VS +VS +VS +VSUS +VSUS EXT P +VSUS INT WEK PU +VSUS EXT P +VSUS EXT PU(NI)/P(NI) +VSUS EXT PU +VSUS EXT PU +VSUS EXT PU +VS +VS +VS EXT P +VS EXT PU +VS EXT PU +VS EXT P +VS EXT P +VS EXT PU EXT PU EXT PU EXT P EXT PU +VSUS +VSUS +VSUS +VSUS +VSUS +VSUS +VSUS +VSUS +VS +VS +VS +VS +VS +VS +VS +VS +VSUS +VSUS +VSUS +VSUS +VSUS +VSUS +VSUS +VSUS +VS +VS +VS +VS +VSUS +VSUS +VSUS +VSUS E IT E GPIO Use s Signal Name E IT0 R. removed GP0 O PWR_LE# E GPIO Use s Signal Name GP O HG_LE# GPIO0 I ME_PM_SLP_M# GP GPIO I ME_SusPwrnck GP GPIO GP O L_L_PWM GPIO GP O FN0_PWM GPIO I ME_+VM_PWRG GP GPIO I ME_PM_SLP_LN# GP GPIO O ME PRESENT GP0 O TSEL_0 GPIO GP O TSEL_ GPIO GP O ME PRESENT_E GPIO GP IO SM0_LK GPIO0 GP IO SM0_T GPIO GP O 0GTE GPIO O ME_PWROK GP O RIN# GPIO GP O PM_RSMRST# GPIO O ME_SLP_M_E# GP0 GPIO GP IO SM_LK GPIO GP IO SM_T GPIO GP O PM_PWRTN# GPIO GP I _IN_O# GPIO GP O OP_S# GPIO0 GP I T_IN_O# GPIO GP I RFON_SW# GPIO GP0 I PWRLIMIT# GPIO GP I PM_SUS# GPIO GP I UF_PLT_RST# GPIO GP O EXT_SI# GPIO GP O EXT_SMI# GPIO GP O L_KOFF# GPIO GP I FN0_TH GPIO GP GPIO0 GPE0 O VSUS_ON GPIO GPE O EG (IT0 ddress/ata connect) GPIO GPE O EGS (IT0 ycle Start connect) GPIO GPE O EGLK (IT0 lock connect) GPIO GPE I PWR_SW# GPIO GPE GPIO GPE I LI_SW# GPIO GPE GPF0 O SM_US RESS : GPF PH Master GPF I EXP_GTE# SMus evice SMus ddress GPF lock Generator(ISLRS) 000x ( ) GPF I TP_LK SOIMM 0 00000x ( 0 ) GPF IO TP_T SOIMM 0000x ( ) GPF O THRO_PU VI ontroller(sm) 000x ( ) GPF O PH_SPI_OV WiFi/WiMax N/ GPG0 I ME_SusPwrnck_E E Master (SM) GPG I PM_SUS# SMus evice SMus ddress GPG PU Thermal Sensor GPG VG Thermal I(G) 000x ( ) GPH0 IO PM_LKRUN# GPH O GFX_VR_ON evice Identification GPH O HG_EN PU Thermal Sensor P/N: component name GPH O SUS_E# st GPH O SUS_E# S GPH O NUM_LE# S GPH O P_LE# S I SUS_PWRG lock Gen P/N: component name I LL_SYSTEM_PWRG st 0G0000 ISLRS I VRM_PWRG S I PH_TEMP_LERT# S I LS_ GPI0 GPI GPI GPI GPI GPI GPI I P_K_# GPI I P_K_# GPJ0 GPJ GPJ GPJ GPJ O O O O O PU_VRON PM_PWROK VSET_E ISET_E TP_LE GPJ st S S VG Thermal Sensor 0G0000 component name G PIE Minicard TV Tuner PIE Minicard WLN PIE Newcard PIE PIE ard reader PIE GLN PIE PIE ST 0 ST H () ST ST O ST ST H () ST EST US 0 US Port () US US Port () US US Port () US US Port () US Minicard TV Tuner US Neward US US US WLN US MOS amera US 0 US US luetooth US Finger Printer SUSTeK OMPUTER IN. N M0J System Setting James_Wu Thursday, July 0, 00 ate: Sheet of.00
MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP R.,item L FI_FSYN0 FI_FSYN FI_INT FI_LSYN0 FI_LSYN For Intel GFX display U00 MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] G MI_TX#[] F MI_TX#[] H MI_TX#[] MI_TX[0] F MI_TX[] E MI_TX[] G MI_TX[] E FI_TX#[0] FI_TX#[] FI_TX#[] FI_TX#[] G FI_TX#[] E FI_TX#[] F FI_TX#[] G FI_TX#[] FI_TX[0] FI_TX[] 0 FI_TX[] FI_TX[] G FI_TX[] E0 FI_TX[] F0 FI_TX[] G FI_TX[] F FI_FSYN[0] E FI_FSYN[] FI_INT F FI_LSYN[0] FI_LSYN[] MI Intel(R) FI PI EXPRESS GRPHIS PEG_IOMPI PEG_IOMPO PEG_ROMPO PEG_RIS PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] K J J G G F F E 0 J H H F G E F F 0 0 L M M M0 L K M J K H0 H F E L M M L0 M K M H K G0 G F E PEG_IROMP_R EXP_RIS PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXP0 PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP0 PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_TXN0 PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN0 PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXP0 PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP0 PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP R00 R00 X00 X00 X00 X00 X00 X00 X00 X00 X00 X00 X0 X0 X0 X0 X0 X0 X0 X0 X0 X00 X0 X0 X0 X0 X0 X0 X0 X0 X0 X00 X0 X0 % % PIEN_RXN[:0] 0 PIEN_RXP[:0] 0 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V.Ohm PIEG_RXN0 PIEG_RXN PIEG_RXN PIEG_RXN PIEG_RXN PIEG_RXN PIEG_RXN PIEG_RXN PIEG_RXN PIEG_RXN PIEG_RXN0 PIEG_RXN PIEG_RXN PIEG_RXN PIEG_RXN PIEG_RXN PIEG_RXP0 PIEG_RXP PIEG_RXP PIEG_RXP PIEG_RXP PIEG_RXP PIEG_RXP PIEG_RXP PIEG_RXP PIEG_RXP PIEG_RXP0 PIEG_RXP PIEG_RXP PIEG_RXP PIEG_RXP PIEG_RXP +VTT_PU For E request, to read PEI via E. onnection: R0.>Q00.>U00. THRO_PU PIEG_RXN[:0] 0 PIEG_RXP[:0] 0 +VTT_PU,,,0,,,0,,,,,,0 R00 don't remove H_PEI H_PUPWRG H_PROHOT_S# H_THRMTRIP# H_PURST# PM_SYN# H_RM_PWRG H_VTTPWRG H_PWRG_XP UF_PLT_RST# % R00 % R00.Ohm % R00.Ohm % R00 SL00 R0 T00 H_OMP H_OMP H_OMP H_OMP0 TP_SKTO#.Ohm % R00 H_TERR# R0 00 SL0 00 SL0 00 R.00,item L T00 SL0 00 H_PEI_ISO H_PROHOT_S#_R H_THRMTRIP#_R PM_SYN#_R SL0 VPWRGOO R 00 SL0 VPWRGOO_0_R 00 SL0 VPWRGOO_R 00 % R0.KOhm OHM PLT_RST#_R R0 % SKTO#:pulled to ground on processor. may use to determine if PU is present T T G T H K T N K P L N N K M M L U00 OMP OMP OMP OMP0 SKTO# TERR# PEI PROHOT# THERMTRIP# RESET_OS# PM_SYN VPWRGOO_ VPWRGOO_0 SM_RMPWROK VTTPWRGOO TPPWRGOO RSTIN# SOKET MIS THERML PWR MNGEMENT LOKS R MIS JTG & PM R.,item L LKREF LKREF# LK LK# LK_ITP LK_ITP# PEG_LK PEG_LK# PLL_REF_SSLK PLL_REF_SSLK# SM_RMRST# SM_ROMP[0] SM_ROMP[] SM_ROMP[] PM_EXT_TS#[0] PM_EXT_TS#[] PRY# PREQ# TK TMS TRST# TI TO TI_M TO_M R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] R0 KOhm R0 KOhm Place near R0,R0. LK_PU_LK LK_PU_LK# R0 LK_ITP_LK_R T0 LK_ITP_LK#_R E LK_EXP_P LK_EXP_N LKREF LKREF# F L SM_ROMP0 R0 % M SM_ROMP R0 % N SM_ROMP R0 % R.,item L M_RMRST#, 0.Ohm 0OHM Main oard LK selection SL0 LK_ITP_LK SL0 00 00 LK_ITP_LK# N PM_EXTTS#0, P PM_EXTTS# +VTT_PU RN00 0KOHM RN00 0KOHM T XP_PRY# P XP_PREQ# N XP_TLK P XP_TMS T XP_TRST# T XP_TI_R R XP_TO_R R XP_TI_M P XP_TO_M N H_R#_R R0 XP_RESET#,, XP_OS[:0] J XP_OS0_R RX0 XP_OS0 K XP_OS_R RX0 XP_OS K XP_OS_R RX0 XP_OS J XP_OS_R RX00 XP_OS J XP_OS_R RX0 XP_OS H XP_OS_R RX0 XP_OS K XP_OS_R RX0 XP_OS H XP_OS_R RX0 XP_OS SOKET G R. P.0: R.,item L SL00 LK_PU_P_PH SL00 LK_PU_N_PH SL00 LK_MI_PH SL00 LK_MI#_PH 00 00 00 00 LK_PU_LK LK_PU_LK# LK_EXP_P LK_EXP_N H_PURST# XP_TMS XP_TI_R XP_PREQ# XP_TLK R0 R0 R0 R0 R0 +VTT_PU OHM Ohm Ohm Ohm Ohm R.,item G R. P.0: *On larksfield rpg only designs, VPWRGOO_ on the larksfield processor can be left as No onnect. RMPWROK: (GU R.) VPWRGOO_R +.V R00.KOhm % FI disable: (For discrete graphic) R.,item R0.0KOHM %. N: FI_TX#[0:],FI_TX[0:],FI_RX#[0:],FI_RX[0:] V_XGSENSE,VSS_XGSENSE. Pulldown to GN via KΩ ± % resistor: FI_FSYN[0:],FI_LSYN[0:],FI_INT,GFX_IMON ~mw power saving.(g R0. P.0) JTG MPPING XP_TI_R XP_TO_M SL00 00 R00 XP_TI XP_TO XP_TRST#. onnected to GN: R0 VXG,. an be connected to GN directly: PLL_REF_LK,PLL_REF_LK#. onnect to +V.0S rail: XP_TI_M XP_TO_R R0 SL00 00 R0 Ohm VFIPLL FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN FI_INT G R. P.: 00 00 00 SL00 SL00 SL00 R.,item L *FI_FSYN[0],FI_FSYN[], FI_LSYN[0], FI_LSYN[] can be ganged together with one resistor. *On the other hand,fi_fsyn[0], FI_FSYN[], FI_LSYN[0], FI_LSYN[], and FI_INT signals on PH side can be left as no connect without any power or functional impact. KOhm KOhm R0 R0 H_PROHOT_S# 0, PWRLIMIT# 00 RV0 R.,item L0. Q00 N00ETG S G R.,item THRO_PU 0 SUSTeK OMPUTER IN. N M0J Friday, July 0, 00 ate: Sheet of PU()_MI,PEG,FI,LK,MIS James_Wu.00
Main oard U00 U00 M Q[:0] M S0 M S M S M S# M RS# M WE# M Q0 0 M Q 0 M Q M Q M Q 0 M Q 0 M Q E0 M Q M Q M Q F0 M Q0 E M Q F M Q E M Q M Q E M Q M Q H0 M Q G M Q K M Q J M Q0 G M Q G0 M Q J M Q J0 M Q L M Q M M Q M M Q L M Q L M Q K M Q0 N M Q P M Q H M Q F M Q K M Q K M Q F M Q G M Q J M Q J M Q0 J0 M Q J M Q L0 M Q K M Q K M Q L M Q K M Q L M Q N M Q M0 M Q0 R M Q L M Q M M Q N M Q T M Q P M Q M M Q N M Q M M Q T M Q0 T M Q L M Q R M Q P U E E S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] P Y Y P E E F H M G M N0 N F J N H K P T F H M H K0 N R Y W V V T Y U T U G T V M M0 M M M M M M M M M M M M M M M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS0 M QS M QS M QS M QS M QS M QS M QS M 0 M M M M M M M M M M 0 M M M M M M_LK_R0 M_LK_R#0 M_KE0 M_LK_R M_LK_R# M_KE M_S#0 M_S# M_OT0 M_OT M M[:0] M QS#[:0] M QS[:0] M [:0] M Q[:0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M S0 M S M S M S# M RS# M WE# E F F F F G H G J J G G J J J K L M K K M N F G J K G G J H K K M N K K M M P N T N N N T T N P P T T P R0 T0 W R Y S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] W W M V V M E H K H L R T F J L H L R R E H M G L P R U V T V R T R R R R P R F P N M M0 M M M M M M M M M M M M M M M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS0 M QS M QS M QS M QS M QS M QS M QS M 0 M M M M M M M M M M 0 M M M M M M_LK_R M_LK_R# M_KE M_LK_R M_LK_R# M_KE M_S# M_S# M_OT M_OT M M[:0] M QS#[:0] M QS[:0] M [:0] SOKET SOKET SUSTeK OMPUTER IN. N PU()_R James_Wu M0J Friday, July 0, 00 ate: Sheet of.00
Main oard IMM0_VREF_Q IMM_VREF_Q T0 T0 T0 T0 T0 T0 T0 T0 T0 T00 T0 T0 T0 T0 T0 T0 T00 T0 T0 FG0 FG FG FG FG FG FG FG FG FG FG0 FG FG FG FG FG FG FG FG R00 R00 T0 T00 T0 T0 T0 T0 0mil trace 0mil trace H_RSV_R H_RSV_R P L L L J G M L J H G G E E0 M0 M P L L0 M N M K K K J N0 N J J J0 K0 H 0 0 U T J J U00E RSV RSV RSV RSV RSV RSV RSV RSV S_IMM_VREFQ S_IMM_VREFQ RSV RSV RSV RSV FG[0] FG[] FG[] FG[] FG[] FG[] FG[] FG[] FG[] FG[] FG[0] FG[] FG[] FG[] FG[] FG[] FG[] FG[] RSV_TP_ RSV RSV RSV RSV RSV RSV0 RSV RSV RSV_NTF_ RSV_NTF_ RSV RSV RSV_NTF_ RSV_NTF_ RSV_NTF_0 RSV_NTF_ RESERVE RSV RSV RSV RSV RSV RSV_NTF_ RSV RSV RSV_NTF_0 RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV RSV_TP_ RSV_TP_0 KEY RSV RSV RSV RSV RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_0 RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_0 RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ VSS J J H K L R J J P T T R L L P0 P L T T P R T T P R R E F J H R R G E V V N W W N E P RSV_R RSV_R T00 T00 T00 T00 T00 T00 T00 T00 T00 R00 R00 U00H T0 VSS T VSS R VSS R VSS R VSS R VSS R VSS R0 VSS R VSS R VSS0 R VSS R VSS R VSS R VSS P0 VSS P VSS P VSS P0 VSS P VSS P VSS0 P VSS N VSS N VSS N VSS N0 VSS N VSS M VSS M VSS M VSS M0 VSS0 M VSS M VSS M VSS M VSS M VSS M VSS L VSS L VSS L VSS L0 VSS0 L VSS L VSS L VSS L VSS L VSS K VSS K VSS K VSS K0 VSS K VSS0 J VSS J VSS J0 VSS J VSS J VSS J VSS J VSS J VSS J VSS H VSS0 H VSS H VSS H VSS H VSS H0 VSS H VSS H VSS H VSS H VSS H0 VSS0 H VSS H VSS H VSS H VSS H VSS G0 VSS F VSS F VSS F VSS E VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS00 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 E E E E E0 E E E E E 0 0 0 Y Y Y W W W W W W0 W W W W W V0 U U U T T T T T T0 T T T T T R0 P P P N N N N N N0 N N N N N M0 L L L L L L K K K0 U00I K VSS K VSS K VSS K VSS J VSS J0 VSS J VSS J VSS H VSS H VSS0 H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS0 H VSS G VSS G VSS G0 VSS G VSS G VSS G VSS F0 VSS F VSS F VSS0 F VSS F VSS F VSS E VSS E VSS E VSS E VSS E VSS E VSS E VSS00 E VSS0 E VSS0 E VSS0 E VSS0 VSS0 0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF T TP_MP_VSS_NTF T TP_MP_VSS_NTF R TP_MP_VSS_NTF TP_MP_VSS_NTF T0 T0 T0 T0 SOKET SOKET SOKET FG strapping information: FG[:0]: PI Express Port ifurcation:(larksfield Only) = x PEG (efault) 0 = x PEG FG[]: PIE Static Numbering Lane Reversal.(uburndale Only) :Normal Operation (efault) 0:Lane Numbers Reversed > 0, >,... FG[]: Embedded isplayport etection.(uburndale Only) :isabled No Physical isplay Port attached to Embedded isplayport 0:Enabled n external isplay Port device is connected to the Embedded isplay Port FG[]: Fixed for PI Express.0 jitter specifications.(larksfield) larksfield (only for early samples prees) onnect to GN with.0k Ohm/% resistor For a common motherboard design (for U and F), the pulldown resistor should be used. oes not impact U functionality. Unmount if Intel has fixed this issue. Intel sighting #: 00() To drive a value of zero on FG[0] pin use a 0 Ohm pull down resistor to Vss. FG0 R0.0KOHM % FG R0.0KOHM % FG R0.0KOHM % ep=.k P FG R0.0KOHM % Note: (uburndale)hardware Straps are sampled on the asserting edge of VPWRGOO_0 and VPWRGOO_ and latched inside the processor. Note: (larksfield)hardware Straps are sampled after RSTIN# deassertion. R.,item SUSTeK OMPUTER IN. N PU()_FG,RSV,GN James_Wu M0J Friday, July 0, 00 ate: Sheet of.00
+VORE U00F G V G V G V G V G V G0 V G V G V G V G V0 F V F V F V F V F V F0 V F V F V F V F V0 V V V V V 0 V V V V V0 V V V V V 0 V V V V V0 V V V V V 0 V V V V V0 Y V Y V Y V Y V Y V Y0 V Y V Y V Y V Y V0 V V V V V V V V V V V0 V V V V V V V V V0 U V U V U V U V U V U0 V U V U V U V U V0 R V R V R V R V R V R0 V R V R V R V R V0 P V P V P V P V P V P0 V P V P V P V P V00 PU ORE SUPPLY POWER SENSE LINES PU VIS.V RIL POWER VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ PSI# VI[0] VI[] VI[] VI[] VI[] VI[] VI[] PRO_PRSLPVR VTT_SELET ISENSE V_SENSE VSS_SENSE VTT_SENSE VSS_SENSE_VTT H H H H0 J J H H G G G G F F F F E E F0 E0 0 0 Y0 W0 U0 T0 J J J J N K K K L L M M M G PU_VI0 PU_VI PU_VI PU_VI PU_VI PU_VI PU_VI PM_PRSLPVR_R VTT_SENSE TP_VSS_SENSE_VTT H_VTTVI VTT_TEST T N J J I_MON 0 +VTT_PU dd Jumper to measure power? R.00,item R0 0UF/.V 00 0UF/.V 0 UF/.V 0 R.00,item 0UF/.V 00 0UF/.V 0 0UF/.V 00 UF/.V 0 Intel use u R.,item L R00 0UF/.V 0 0UF/.V 00 0UF/.V 00 PU_VI[0:] T0 T0 +VORE 0UF/.V 0 0UF/.V 0 +VTT_PU PM_PSI# 0 R00 0 % R00 0 % 0 0UF/.V +VTT_PU 0 0UF/.V PM_PRSLPVR 0 VSENSE 0 VSSSENSE 0 R.00,item L T0 R00 +VTT_PU +VTT_PU +VGFX_ORE R.,item L UF/.V 0 UF/.V 0 UF/.V 0 Intel use u +VORE Intel use u UF/.V 0 UF/.V 0 UF/.V 0 Processor ecoupling ecoupling guide from Intel Schematic R0.: VORE uf * pcs 0 UF/.V 0uF * pcs 0uF* pcs( no stuff). 0 T T T T R R R R P P P P N N N N M M M M L L L L K K K K J J J J H H H H J J H K J J J H G G G F E E UF/.V U00G VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ SOKET 0 UF/.V FI PEG & MI 0 GRPHIS UF/.V POWER SENSE LINES GRPHIS VIs R.V RILS.V.V Schematic hecklist R0.: VORE uf * pcs 0 UF/.V 0uF * pcs 0uF* pcs( no stuff). VXG_SENSE VSSXG_SENSE GFX_VI[0] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VR_EN GFX_PRSLPVR GFX_IMON 0 UF/.V VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VTT0_ VTT0_0 VTT0_ VTT0_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VPLL VPLL VPLL 0 R T M P N P M P N R T M J F E E Y W W U T T P N N L H P0 N0 L0 K0 J J0 J H H0 H L L M UF/.V R.,item L GFX_VRON_EN GFXVR_PRSLPVR GVR_PWR_MON 0 UF/.V UF/0V 0 0 0UF/.V UF/.V 0 +VTT_PU +VTT_PU Intel use u UF/0V 0 R00 R00 UF/0V 0 UF/0V 0 GVR_PWR_MON UF/0V 0.UF/0V 0 0 0UF/.V UF/.V 0 UF/0V 0.UF/.V 0 UF/0V 0 +.VS UF/.V 0.KOhm.KOhm UF/.V 0 R0 UF/.V 0 +.V 0UF/V E00 PNSONI/EEFSX0XE ESR=mOhm/Ir= G R.,P xbuck Stuffing option Intel.V P. u: /.u: /.u: / 0u:/ + KOhm R.,item Main oard 00 0 0 0 0 0 0 UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V SOKET / delete 0 (UF,.V) for layout placement. (+.VS,VPLL) 0 00 0 0 0 0 0 0 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0 0 0 00 0 0 0 0 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V SUSTeK OMPUTER IN. N PU()_PWR James_Wu M0J Friday, July 0, 00 ate: Sheet of.00
Main oard PU XP connector +VTT_PU R.,item L J00 SIE 0 0 0 0 0 SIE 0 FP_ON_0P T00 T0 R00 PUPWRG_XP KOhm R00 HPM# T0 HPM# T0 HPM# T0 HPM0# T0 Ohm R0 XP_RST#_R KOhm R00 H_PWRG_XP XP_TRST# H_PUPWRG, XP_PREQ# XP_PRY# XP_TO XP_TI XP_TMS XP_TLK XP_RESET#,, H_PURST# SM_T_S,,,,,, SM_LK_S,,,,,, LK_ITP_LK# LK_ITP_LK () () () ( ) ( ) () () () () () () () (0) () +VTT_PU XP_RST#_R R0 UF_PLT_RST#,,0,,,0,,,,,,0 T0 T0 T0 T0 T0 T0 T0 T0 T00 XP_OS0 XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS PM_PWRTN#_R J00 FF path Put these test point near J00. Put it away from the FF path. SUSTeK OMPUTER IN. N PU()_XP James_Wu M0J Friday, July 0, 00 ate: Sheet of.00
SUSTeK OMPUTER IN. N N_**** James_Wu ustom M0J ate: Thursday, July 0, 00 Sheet of.00
Main oard SUSTeK OMPUTER IN. N N_**** James_Wu ustom M0J ate: Thursday, July 0, 00 Sheet of.00
Main oard SUSTeK OMPUTER IN. N N_**** James_Wu ustom M0J ate: Thursday, July 0, 00 Sheet 0 of.00
Main oard SUSTeK OMPUTER IN. N N_**** James_Wu ustom M0J ate: Thursday, July 0, 00 Sheet of.00
Main oard SUSTeK OMPUTER IN. N N_**** James_Wu ustom M0J ate: Thursday, July 0, 00 Sheet of.00
Main oard SUSTeK OMPUTER IN. N N_**** James_Wu ustom M0J ate: Thursday, July 0, 00 Sheet of.00
SUSTeK OMPUTER IN. N James_Wu M0J ate: Thursday, July 0, 00 Sheet of.00
SUSTeK OMPUTER IN. N James_Wu M0J ate: Thursday, July 0, 00 Sheet of.00
M M M M M M M M M M M M M M M M0 M QS M QS# M QS M QS M QS M QS# M QS M QS# M QS# M QS M QS# M QS#0 M QS M QS# M QS0 M QS# M M M M M M M 0 M M M M M 0 M M M M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q0 M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M [:0] M Q[:0] M_LK_R0 M_KE0 M_LK_R# M_LK_R M_KE M S# M_LK_R#0 M S M S0 M S M M[:0] M QS#[:0] M QS[:0] SM_T_S,,,,,, SM_LK_S,,,,,, M WE# PM_EXTTS#0, M_S# M RS# M_S#0 M_OT0 M_OT M_RMRST#, +VS +.V +0.VS M_VREF_IMM0 M_VREFQ_IMM0 +0.VS +.V +.V ate: Sheet of Friday, July 0, 00 SUSTeK OMPUTER IN. N R SOIMM_0.00 M0J James_Wu ate: Sheet of Friday, July 0, 00 SUSTeK OMPUTER IN. N R SOIMM_0.00 M0J James_Wu ate: Sheet of Friday, July 0, 00 SUSTeK OMPUTER IN. N R SOIMM_0.00 M0J James_Wu REV.mm SMus Slave ddress: 0H Layout Note: Place these caps near SO IMM 0 Layout Note: Place these caps near SO IMM 0 R. R. 0 R0 R0 0UF/.V 0UF/.V 0 0UF/.V 0 0UF/.V R0 0KOhm R0 0KOhm UF/0V UF/0V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0 0UF/.V 0 0UF/.V 0UF/.V 0UF/.V.UF/0V.UF/0V.UF/0V.UF/0V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V EVENT# GN 0 GN 0 N N NP_N 0 NP_N 0 OT0 OT 0 RS# 0 RESET# 0 S#0 S# S0 S 0 SL 0 S 00 TEST V V0 00 V 0 V 0 V V V V V V V V V V V V V V VSP VREF VREFQ VSS VSS 0 VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VTT 0 VTT 0 WE# J0 R_IMM_0P J0 R_IMM_0P.UF/0V.UF/0V UF/0V UF/0V UF/0V UF/0V + E0 0UF/V ESR=0mOhm/Ir=. + E0 0UF/V ESR=0mOhm/Ir=. R0 0KOhm R0 0KOhm 0UF/.V 0UF/.V 0 0UF/.V 0 0UF/.V UF/0V UF/0V 0 0/P 0 /# 0 0 0 0 0 S# K#0 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q QS#0 0 QS# QS# QS# QS# QS# QS# QS# QS0 QS QS QS QS QS QS QS J0 R_IMM_0P J0 R_IMM_0P
M M M M M M M M M M M M0 M QS# M QS M QS M QS M QS M QS# M QS# M QS#0 M QS M QS# M QS0 M QS# M M M M M M M 0 M M M M M 0 M M M M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M M M M M QS M QS M QS# M QS# M Q M Q0 M Q M Q M Q M Q M Q M Q M WE# M_S# M_LK_R M_KE M_LK_R# M_LK_R M_KE M S# M RS# M_LK_R# M_S# M_OT M_OT SM_T_S,,,,,, SM_LK_S,,,,,, M M[:0] M QS#[:0] M QS[:0] M S M S0 M S M_RMRST#, M [:0] M Q[:0] PM_EXTTS#0, +0.VS +0.VS +.V +.V M_VREF_IMM M_VREFQ_IMM +.V +VS +VS ate: Sheet of Friday, July 0, 00 SUSTeK OMPUTER IN. N R SOIMM_.00 M0J James_Wu ate: Sheet of Friday, July 0, 00 SUSTeK OMPUTER IN. N R SOIMM_.00 M0J James_Wu ate: Sheet of Friday, July 0, 00 SUSTeK OMPUTER IN. N R SOIMM_.00 M0J James_Wu SMus Slave ddress: H Layout Note: Place these caps near SO IMM Layout Note: Place these caps near SO IMM ST.mm R. R. SWP UF/0V UF/0V 0 0.UF/V 0 0.UF/V + E0 0UF/V ESR=0mOhm/Ir=. + E0 0UF/V ESR=0mOhm/Ir=. 0UF/.V 0UF/.V R0 0KOhm R0 0KOhm 0.UF/V 0.UF/V RX0 RX0 UF/0V UF/0V UF/0V UF/0V 0 0.UF/V 0 0.UF/V EVENT# GN 0 GN 0 N N NP_N 0 NP_N 0 OT0 OT 0 RS# 0 RESET# 0 S#0 S# S0 S 0 SL 0 S 00 TEST V V0 00 V 0 V 0 V V V V V V V V V V V V V V VSP VREF VREFQ VSS VSS 0 VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VTT 0 VTT 0 WE# J0 R_IMM_0P J0 R_IMM_0P 0.UF/V 0.UF/V UF/0V UF/0V 0.UF/V 0.UF/V 0UF/.V 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0.UF/V 0 0.UF/V 0UF/.V 0UF/.V.UF/0V.UF/0V.UF/0V.UF/0V 0UF/.V 0UF/.V.UF/0V.UF/0V 0 0/P 0 /# 0 0 0 0 0 S# K#0 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q QS#0 0 QS# QS# QS# QS# QS# QS# QS# QS0 QS QS QS QS QS QS QS J0 R_IMM_0P J0 R_IMM_0P 0 0.UF/V 0 0.UF/V R0 0KOhm R0 0KOhm
R Vref Intel ocument Number: 00 alpella larksfield R SOIMM VREFQ Platform esign Guide hange etails efault M M_VREF M_VREF_R M_VREF_IMM0 R0 R0 M_VREF_IMM M: Fixed SOIMM VREF_Q (efault Stuffing) *Option: Mount=R0,R0,R0,R0,R0 Unmount=R0,R0 R0 For R_VREF command & address. R0,R0 are always mount. WW MOW: For rrandale only designs: Only method M should be enabled. For larksfield only designs: oth M N M methods should be enabled. For ommon Motherboard designs.. oth M N M methods should be enabled M_VREFQ_IMM0 R.,item M_VREFQ_IMM R0 R0 IMM0_VREF_Q R0 R0 IMM_VREF_Q R.,item M M: Processor Generated SOIMM VREFQ New Requirement Option: Mount=R0,R0,R0,R0,R0, Unmount=R0,R0 R.,item L R.,item L SUSTeK OMPUTER IN. N R _Q VOLTGE James_Wu M0J Friday, July 0, 00 ate: Sheet of.00
PU_VI VR_VI PU_VI RNX0 VR_VI 0 PU_VI VR_VI PU_VI RNX0 VR_VI 0 PU_VI VR_VI PU_VI RNX0 VR_VI 0 PU_VI VR_VI PU_VI RNX0 VR_VI 0 PU_VI VR_VI PU_VI RNX0 VR_VI 0 PU_VI VR_VI PU_VI RNX0 VR_VI 0 PU_VI0 VR_VI0 PU_VI0 RNX0 VR_VI0 0 RNX0 R.,item L SUSTeK OMPUTER IN. N VI ustom M0J ate: Friday, July 0, 00 Sheet of.00
RT battery R.00,item L J00 SIE SIE T00 Wto_ON_P G0000 +RTT GN R00 R.,item L +V JP00 +RT_T KOhm T00 MM_OPEN_MIL +V_RT R.00,item L R.00,item L T0 00 T +V_RT GN R.00,item L T00 00 UF/0V R.,item L +V_RT RTRST# R delay should be ms~ms R00 0KOhm % 00 UF/0V JRST00 SGL_JUMP MOS Settings lear MOS Keep MOS Request by S for MOS clear function JRST00 Shunt Open (efault) GN 00 PF/0V X00.Khz R00 0MOhm U00 R00 0KOhm % R00 MOhm Z_LK_U Z_SYN_U, Z_RST#_U Z_SOUT_U 0 Z_LK_VG 0 Z_SYN_VG 0 Z_RST#_VG 0 Z_SOUT_VG H_OK_EN# GN GN TPM Settings 00 UF/0V lear ME RT Registers Keep ME RT Registers GN GN JRST00 Shunt JRST00 SGL_JUMP Open (efault) RX0 RX0 RX0 RX0 RX0 RX0 RX0 RX0 R.,item KOhm GN WW MOW: H_OK_EN# pulldown resistor changed to K Ohm. R0 Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm R.00,item L R.,item H_SYN: Select VVRM.V or.v Z_LK Z_SYN Z_RST# Z_SOUT 0 R.00,item L PH_SPI_OV R0 00KOhm PH_SPI_OV: L: SPI flash can't be override. H: SPI flash can be override. R.,item L GN GN R.,item H_OK_EN# R.,item L +VM_SPI R.00,item L R.00,item L Q00 N00ETG 00 PF/0V G +VS +VS R.,item L SPI_LK SPI_S#0 SPI_S# SPI_SI GN XRT R00: For Xtal measurement S T0 R00 0KOhm R0 00KOhm R.,item L R00 KOhm +V_RT PH_JTG_TMS PH_JTG_TI PH_JTG_TO PH_JTG_RST# KOhm R0 0 R.,item L0 PH_JTG_TK R0 Z_SIN0_U Z_SIN_VG T00 R00 H_OK_EN# H_OK_RST# X_RT X_RT RTRST# SRTRST# SM_INTRUER# Z_SOUT S_SPIS0# Z_LK Z_SYN S_SPKR Z_RST# Z_SIN_M R0 Ohm S_SPIS# R.00,item 0 R.00,item R00 T00 T00 Ohm SPI_SO 0KOhm 0 P 0 G0 F0 E F H J0 M K K J J V Y Y V RTX RTX RTRST# SRTRST# INTRUER# INTVRMEN H_LK H_SYN SPKR H_RST# H_SIN0 H_SIN H_SIN H_SIN H_SO H_OK_EN#/GPIO H_OK_RST#/GPIO JTG_TK JTG_TMS JTG_TI JTG_TO TRST# SPI_LK SPI_S0# SPI_S# SPI_MOSI SPI_MISO IEXPEKM RT IH SPI JTG LP ST FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/GPIO SERIRQ ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STIOMPO STIOMPI STLE# ST0GP/GPIO STGP/GPIO F K K K K H H H H F F F F H H F F F F T Y V PH_RQ#0 LP_RQ# ST,: ST0GP STGP ST_OMP +VTT_PH_VIO LP_0 0, LP_ 0, LP_ 0, LP_ 0, LP_FRME# 0, INT_SERIRQ 0 ST_RXN0 ST_RXP0 ST_TXN0 ST_TXP0 ST_RXN ST_RXP ST_TXN ST_TXP ES.0: ST port,port may not be available in all PH SKUs..Ohm % R00 R.,item L 0KOhm R0 T00 T00 ST_RXN ST_RXP ST_TXN ST_TXP ST_RXN ST_RXP ST_TXN ST_TXP +VS ST_LE# PH XP PH XP 0 esign Guide R. Update: page GPIO: This signal should be only asserted low through an external pulldown in manufacturing or debug environments ONLY. Without connecting GPIO, customers may not be able to override SPI flash contents. Strap information: H_SPKR: No reboot strap Low: isable. High:Enable H_OK_EN#:.Flash descriptor security: Sampled low: override Sampled high: in effect..gpio low on the rising edge of PWROK, Will also disable Intel ME. MoW0 IbexPeak JTG requirements: Stuff if required JTG support +VSUS_ORG +VSUS_ORG R0 0 % R0 0 % +VSUS_ORG R0 0 % R0 0 % R.,item L R0 0 % PH_JTG_TO PH_JTG_TMS PH_JTG_TI R0 0 % +VSUS_ORG R00 0KOhm % PH_JTG_RST# R0 0KOhm % PH_JTG_TK R0 Ohm +VTT_PH_VIO R0 R0 R0 R0 Ohm Ohm Ohm Ohm PH_JTG_TO PH_JTG_TMS PH_JTG_TI PH_JTG_RST# MoW IbexPeak JTG requirements: ES Enable:Mount R0,R0,R0,R0,R00,R0,R0. NI R0,R0. (TO) ES isable:mount R00,R0,R0. NI: others. INT_SERIRQ ST0GP STGP 0KOhm R0 0KOhm R0 0KOhm R0 +VS PH XP? SPI_MOSI: itpm strap. Mount R0: Enable Unmount R0: isable(default) GN GN GN GN ES Mount :R0,R0,R0,R0,R0,R0,R00,R0,R0. GN PH_IEX()ST,IH,RT,LP James_Wu SUSTeK OMPUTER IN. N M0J.00 Friday, July 0, 00 ate: Sheet of 0
U00 R.,item L PIE: TV turner PIE: WLN PIE: Newcard PIE: PIE> PIE: LN, PIE_RXN_TV PIE_RXP_TV PIE_TXN_ PIE_TXP_ PIE_RXN_WLN PIE_RXP_WLN PIE_TXN_ PIE_TXP_ PIE_RXN_NEWR PIE_RXP_NEWR PIE_TXN_ PIE_TXP_ PIE_RXN_GLN PIE_RXP_GLN PIE_TXN_ PIE_TXP_ LK_PIE_TV#_PH LK_PIE_TV_PH LKREQ_TV# LK_PIE_WLN#_PH LK_PIE_WLN_PH 0 PIE_RXN_R 0 PIE_RXP_R 0 PIE_TXN_ 0 PIE_TXP_ PIE,: LKREQ_WLN# LK_PIE_NEWR#_PH LK_PIE_NEWR_PH LKREQ_NEWR# R.,item L PIE_TXN_TV PIE_TXP_TV PIE_TXN_WLN PIE_TXP_WLN ES.0: port,port may not be available in all PH SKUs. R.,item 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V Ohm Ohm X0 X0 RX0 RX0 R0 R.,item L RX0 RX0 R R.,item L T0 X0 X0 X0 X0 X X X X RX0 RX0 R PIE_TXN_NEWR PIE_TXP_NEWR PIE_TXN_R PIE_TXP_R R.,item PIE_TXN_GLN PIE_TXP_GLN LK_REQ0# LK_PH_SR_N LK_PH_SR_P LK_PH_SR_N LK_PH_SR_P LK_PH_SR_N LK_PH_SR_P G0 J0 F H W0 0 0 0 U0 T0 U V E F H G J W T U U V G J G J K K P M M U M M N H H PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIE0N LKOUT_PIE0P PIE* PIELKRQ0#/GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/GPIO0 LKOUT_PIEN LKOUT_PIEP PIELKRQ#/GPIO From LK UFFER SMus ontroller PEG Link SMLERT#/GPIO SMLK SMT SML0LERT#/GPIO0 SML0LK SML0T SMLLERT#/GPIO SMLLK/GPIO SMLT/GPIO L_LK L_T L_RST# PEG LKRQ#/GPIO LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N/LKOUT_LK_N LKOUT_P_P/LKOUT_LK_P LKIN_MI_N LKIN_MI_P LKIN_LK_N LKIN_LK_P LKIN_OT_N LKIN_OT_P LKIN_ST_N/KSS_N LKIN_ST_P/KSS_P REFLKIN LKIN_PILOOPK H J G M E0 G T T T H N N T T W P P F E H H P J SML0LERT# SML0_LK SML0_T SMLLERT# SML_LK SML_T LK_PIE_PEG#_PH_L LK_PIE_PEG_PH_L T0 T0 R.,item L RX RX0 T0 T0 EXT_SI# 0 SL_ S_ SML_LK SML_T L_LK L_T L_RST# LKREQ_PEG# 0 LK_PIE_PEG#_PH 0 LK_PIE_PEG_PH 0 LK_MI#_PH LK_MI_PH LK_MI# LK_MI LK_PH_LK# LK_PH_LK LK_OT# LK_OT LK_ST# LK_ST LK_IH LK_PI_F R.,item L To E R.00,item L R.,item R EXT_SI# SML0LERT# SL_ S_ SML0_LK SML0_T SML_LK SML_T SMLLERT# G R.,page : +VSUS_ORG The pullup resistor value for SML0T and SML0LK has been updated from. K ±% to. K ±% to support 00kHz bus speed alpella G R. page: 0KOhm R0 0KOhm R.KOhm R.KOhm R.KOhm R.KOhm R.KOhm R.KOhm R 0KOhm R XTL_IN should be pulled to GN via a 0Ω resistor by default LK_PH_SR_N LK_PH_SR_P 0 LK_REQ#_ LK_REQ#_ M F XLK_OMP R 0.Ohm % PIELKRQ#/GPIO XLK_ROMP +VTT_PH_ORG LK_PIE_GLN_N_PH LK_PIE_GLN_P_PH 0 0 LK_PIE_R# LK_PIE_R LKREQ_GLN# R.,item R.,item L RX RX T0 Note: Place these resisters near to PIe Slots RX RX R LK_REQ# LK_PH_PEG_N LK_PH_PEG_P M M J0 J H K K P LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP PIELKRQ#/GPIO LKOUT_PEG N LKOUT_PEG P PEG LKRQ#/GPIO IEXPEKM lock Flex XTL_IN XTL_OUT LKOUTFLEX0/GPIO LKOUTFLEX/GPIO LKOUTFLEX/GPIO LKOUTFLEX/GPIO H H T P T N0 X_IN X_OUT LK_OUT0 LK_OUT LK_OUT LK_OUT T T T0 T0 X0 MOhm Mhz R R0 XOUT 0 PF/0V GN R0: For Xtal measurement PH LKREQ Setting: R.,item L Not connected to device. +VSUS_ORG LK_REQ0# R 0KOhm LK_REQ# R 0KOhm onnected to device. efault : lock free run. (P 0K). Reserver 0K PU for power saving purpose. +VS LKREQ_TV# LKREQ_WLN# R 0KOhm R 0KOhm +VSUS_ORG LKREQ_NEWR# LKREQ_GLN# LK_REQ#_ LKREQ_TV# LKREQ_WLN# LKREQ_NEWR# LKREQ_GLN# LK_REQ#_ LKREQ_PEG# R R R R.,item L R.,item L R 0KOhm R 0KOhm R 0KOhm R 0KOhm R 0KOhm R 0KOhm R.,item L 0KOhm 0KOhm 0KOhm GN SUSTeK OMPUTER IN. N PH_IEX()_PIE,LK,SM,PEG James_Wu M0J Friday, July 0, 00 ate: Sheet of.00
R.,item L prees not support Reversal Feature GN UXPWROK_R R 0KOhm G R.,page : R.,item For platforms that do not support Intel LN, LN_RST# should be pulled down to ground via a. kω to 0 kω pulldown resistor. PM_RI# PM_TLOW# PIE_WKE# R.,item L ME_SusPwrnck R.,item L PM_LKRUN# R 0KOhm R.KOhm R KOhm R0 0KOhm R.,item L +VSUS_ORG R.KOhm +VS,, ES.0: Intel LN XP_RESET# +VS Enabled : LN_RST# connected to the same source as MEPWROK isabled : LN_RST# must be grounded isabled : SLP_LN#>N. P. isabled : VLN connected to GN. KOhm R 0 +VTT_PH_ORG R0.Ohm % G.,page0: R.,item L 0,,,0 SS R.,item L R.,item L 0 R.,item L MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_OMP R.,item L +VS LL_SYSTEM_PWRG 0,,0 VRM_PWRG H_RM_PWRG ME_SusPwrnck PM_PWRTN#_R 0 PM_PWRTN# R PM_PWROK_PH R.,item L 0KOhm R PM_RSMRST#_PH ME PRESENT_PH +VSUS_ORG R.,item L RX0 RX0 RX0 RX0 RX0 RX0 RX RX0 RX0 RX0 RX RX RX RX RX RX R.,item L SYS_RESET# R R R.,item L R R R 0KOhm R MI_RXN0_R MI_RXN_R MI_RXN_R MI_RXN_R MI_RXP0_R MI_RXP_R MI_RXP_R MI_RXP_R MI_TXN0_R MI_TXN_R MI_TXN_R MI_TXN_R MI_TXP0_R MI_TXP_R MI_TXP_R MI_TXP_R R R MPWROK_R UXPWROK_R PM_RSMRST#_R U00 J W0 J0 G 0 G0 E F 0 E H 0 H F T M K 0 M P P MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI_ZOMP MI_IROMP SYS_RESET# SYS_PWROK PWROK MEPWROK LN_RST# RMPWROK RSMRST# SUS_PWR_N_K/GPIO0 PWRTN# PRESENT/GPIO MI System Power Management FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN WKE# LKRUN#/GPIO SUS_STT#/GPIO SUSLK/GPIO SLP_S#/GPIO SLP_S# SLP_S# SLP_M# TP H J E F G W J F H J G J Y P F E H P K N PM_SUS_STT# SUS_LK SLP_S# SLP_S#_R SLP_S#_R SLP_M#_R R.,item L PM_SLP_SW# R0 R T0 T0 T0 T0 PIE_WKE#,, PM_LKRUN# 0 PM_SUS# 0 PM_SUS# 0 R.,item L T0 T0 PM_TLOW# TLOW#/GPIO PMSYNH J0 PM_SYN# T0 PM_RI# F RI# SLP_LN#/GPIO F ME_PM_SLP_LN#_PH T0 R.,item L IEXPEKM R.,item L R.,item L 0'MoW0: Optional if ME FW is Ignition FW PM_PWROK_PH 0KOhm R +VSUS_ORG 0KOhm R 0KOhm R R.,item L Power failure solution (S0>G,S>G): PM_PWROK,PM_RSMRST#: previous platform solution. ME_PWROK,ME PRESENT: reserved for test. R 0 0KOhm SS PM_PWROK 0 PM_RSMRST#_PH R0 0 0KOhm SS PM_RSMRST#,0 ME PRESENT_PH R 0 0KOhm SS ME PRESENT 0 0 T 0 0: Prevent E drive hign, SUS_PWRG sink low in S>G. SUS_PWRG 0,, 0KOhm R T GN SUSTeK OMPUTER IN. N PH_IEX()_FI,MI,SYS PWR James_Wu M0J Friday, July 0, 00 ate: Sheet of.00
+VS L_TRL_LK R 0KOhm L_TRL_T R 0KOhm U00 R.,item L LVS isable: (For discrete graphic). N: LVS_T [:0], LVS_T# [:0], LVS_LK, LVS_LK#, LVS_T [:0], LVS_T# [:0], LVS_LK, LVS_LK# L_V_EN, L_KLTEN, L_KLTTL, LV_VREFH LV_VREFL, LV_IG, LV_VG. onnected to GN: VccLVS,VccTX_LVS T0 T0 R.,item L L_TRL_LK L_TRL_T T T Y Y V P P T T V V Y V 0 Y V P P Y T U T Y T U0 T L_KLTEN L_V_EN L_KLTTL L LK L T L_TRL_LK L_TRL_T LV_IG LV_VG LV_VREFH LV_VREFL LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T LVS igital isplay Interface SVO_TVLKINN SVO_TVLKINP SVO_STLLN SVO_STLLP SVO_INTN SVO_INTP SVO_TRLLK SVO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P J G J G F H T T G J U R.,item L J G 0 0 W Y E V0 E0 0 F H isplay Port isable: (For discrete graphic). N: LL isplay Port isplay Port SVO RT_LUE RT_GREEN RT_RE P_TRLLK P_TRLT U0 U RT isable: (For discrete graphic) R KOhm R.00,item GN _alpella_schematic_hecklist_rev. GN V RT LK V RT T Y RT_HSYN Y RT_VSYN _IREF RT_IRTN IEXPEKM RT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P T J0 G0 J G F H E isplay Port. N: _IREF used: K+/0.% RT_RE,RT_GREEN,RT_LUE _IREF not used: can be K+/% RT_HSYN,RT_VSYN. kω ±0.% pulldown to GN: _IREF. onnected to GN: RT_ITRN. onnect to +V.: V SUSTeK OMPUTER IN. N PH_IEX()_P,LVS,RT James_Wu M0J Monday, July 0, 00 ate: Sheet of.00
+V_NVRM_VQ NV_LE R KOhm change to PI_LK to sync IS 0 R.,item L PI_PME#: Internal PU to suspend plane. LK_GPI LK_PI_F LK_KPI_PH LK_EUG Ohm Ohm Ohm Ohm R.,item L RX0 RX0 RX0 RX0 0'WW0 MoW T0 T0 T0 T0 U00E H0 0 N J 0 E H E0 0 0 M M F M0 M J K F0 0 K M J K L F J0 G F M 0 H J0 /E0# G /E# H /E# G /E# PI_INT# G PI_INT# PIRQ# H PI_INT# PIRQ# PI_INT# PIRQ# PIRQ# PI_REQ0# F PI_REQ# REQ0# GPU_SELET#_R REQ#/GPIO0 PI_REQ# REQ#/GPIO M REQ#/GPIO PI_GNT0# F PI_GNT# GNT0# K PI_GNT# GNT#/GPIO F PI_GNT# GNT#/GPIO H GNT#/GPIO PI_INTE# PI_INTF# PIRQE#/GPIO K PI_INTG# PIRQF#/GPIO PI_INTH# PIRQG#/GPIO PIRQH#/GPIO PI_RST# K PIRST# PI_SERR# E PI_PERR# SERR# E0 PERR# PI_IRY# PI_PR IRY# H PI_EVSEL# PR F PI_FRME# EVSEL# FRME# PI_LOK# PLOK# PI_STOP# PI_TRY# STOP# TRY# PI_PME# M PME# PLT_RST# PLTRST# LK_GPI_R N LK_PI_F_R LKOUT_PI0 P LK_KPI_PH_R LKOUT_PI P LK_EUG_R LKOUT_PI P LKOUT_PI P LKOUT_PI IEXPEKM PI NVRM US NV_E#0 NV_E# NV_E# NV_E# NV_QS0 NV_QS NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_LE NV_LE NV_ROMP NV_R# NV_WR#0_RE# NV_WR#_RE# NV_WE#_K0 NV_WE#_K USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP0N USP0P USPN USPP USPN USPP USPN USPP USRIS# USRIS O0#/GPIO O#/GPIO0 O#/GPIO O#/GPIO O#/GPIO O#/GPIO O#/GPIO0 O#/GPIO Y NV_E#0 NV_E# P NV_E# NV_E# V G P NV_Q0 P NV_Q T NV_Q T NV_Q NV_Q V NV_Q NV_Q NV_Q E NV_Q NV_Q NV_Q0 NV_Q NV_Q J NV_Q J NV_Q G NV_Q Y U NV_ROMP V Y Y V F NV_QS[0] NV_QS[] NV_Q[0:] NV_E#0 NV_E[0]# NV_E[]# NV_E# NV_E[]# NV_E[]# NV_E# NV_E[]# NV_E[]# NV_E# NV_E[]# NV_E[]# NV_LE NV_LE INTEL recommend. ohm R Ohm % R.00,item NV_R_# NV_RE#_WR#0 GN NV_RE#_WR# NV_WE#_K0 R.,item L NV_WE#_K Place within 00 mils of PH MJ Recommand settings H US_PN0 J US_PP0 0 US port (IO/) US_PN US_PP US port(io/) N0 US_PN P0 US_PP US port J0 US_PN L0 US_PP US port F0 US_PN G0 US_PP TV turner R. 0 US_PN 0 US_PP Newcard M US_PN T0 N US_PP T0 annot use US_PN T0 US_PP T0 ard Reader(.0) H US_PN J US_PP WiFi/WiMax R. LM(.0) or UW(./.0) E US_PN F US_PP amera R.,item E 0 G G H US port (th) or ocking L US_PN M US_PP T (.) US_PN US_PP FP (.) USRIS_PN R +VSUS_ORG.Ohm % Place within 00 mils of IH N GN R.,item L 0KOHM RN0 J 0KOHM RN0 F 0KOHM RN0 L 0KOHM RN0 E 0KOHM RN0 G 0KOHM RN0 F 0KOHM RN0 T 0KOHM RN0 +V_NVRM_VQ NV_LE R KOhm +VS PI_INTG# RP0 0KOhm 0 PI_INT# RP0 0KOhm 0 PI_INT# RP0 0KOhm 0 PI_STOP# RP0 0KOhm 0 PI_PERR# RP0G 0KOhm 0 PI_LOK# RP0F 0KOhm 0 PI_EVSEL# RP0G 0KOhm 0 PI_SERR# RP0H 0KOhm 0 PI_INTE# RP0E 0KOhm 0 PI_IRY# RP0H 0KOhm 0 PI_INT# RP0 0KOhm 0 PI_REQ0# RP0 0KOhm 0 PI_INT# RP0 0KOhm 0 PI_INTF# RP0 0KOhm 0 PI_REQ# RP0 0KOhm 0 PI_REQ# RP0 0KOhm 0 PI_FRME# RP0 0KOhm 0 PI_TRY# RP0E 0KOhm 0 PI_INTH# RP0F 0KOhm 0 GPU_SELET#_R RP0 0KOhm 0 RP0F 0KOhm 0 RP0G 0KOhm 0 RP0H 0KOhm 0 RP0E 0KOhm 0 R.,item L R.,item L 0PF/0V 0 R.,item R.,item R.,item L R.,item L R.,item L GN GNT0#,GNT#: oot IOS Strap. oot IOS Strap PI_GNT# PI_GNT0# oot IOS Location 0 0 LP 0 PI 0 Reserved SPI (PH) GNT#: swap override Strap/ Toplock swap override jumper Low=Enabled swap override/ Toplock swap override High=efault +V Sampled on rising edge of PWROK. PI_GNT0# R0 KOhm PI_GNT# R KOhm GN PI_GNT# R KOhm GN PLT_RST# GN U0 V GN Y NSZ0PX_NL UF_PLT_RST#,,0,,,0,,,,,,0 R SUSTeK OMPUTER IN. N PH_IEX()_PI,NVRM,US James_Wu M0J Friday, July 0, 00 ate: Sheet of.00
+VS +VS R.,item L T T0 PH_GPIO0_R OKING_ET# Y U00F MUSY#/GPIO0 TH/GPIO LKOUT_PIEN LKOUT_PIEP H H R 0KOhm R 0KOhm P_I0 GPIO : efault internal P 0K. 0 R.,item L EXT_SMI# T T T T_LE R.,item L OKING_UNOK_UTTON# XIE_Y_IN# PM_LNPHY_EN GPU_HOL_RST# J F0 K T TH/GPIO TH/GPIO GPIO LN_PHY_PWR_TRL/GPIO GPIO STGP/GPIO MIS LKOUT_PIEN LKOUT_PIEP 0GTE LKOUT_LK0_N/LKOUT_PIEN F F U M 0GTE 0 LK_PU_N_PH +VTT_PU R R 0KOhm 0KOhm GN GN P_I R.,item GPIO :Enable VVRM,Low=disable. efault internal pull up. GPIO : efault internal PU 0K. WLN_ON# WLN_LE T T R.,item L T T R.,item L R.,item L GPU_PWROK VRM_EN O_LN_RST# R.,item L R0 GPU_PWR_EN# GPU_PRSNT# STP_PI# ST_LK_REQ# F Y H0 V M V TH0/GPIO SLOK/GPIO GPIO GPIO GPIO STP_PI#/GPIO GPIO STGP/GPIO STGP/GPIO GPIO PU LKOUT_LK0_P/LKOUT_PIEP PEI RIN# PROPWRG THRMTRIP# TP TP M G0 T E0 0 W R PM_THRMTRIP# T T LK_PU_P_PH H_PEI RIN# 0 H_PUPWRG, R OHM R0 R0 OHM R.,item 0'WW MoW R.00,item L R.00,item L H_THRMTRIP# P_I0 V SLO/GPIO TP T P_I P STOUT0/GPIO TP Y T T LK_REQ# H PIELKRQ#/GPIO TP Y T T LK_REQ# F PIELKRQ#/GPIO TP V T R.,item L R.00,item L T EMIL_LE R.,item L 0 PH_TEMP_LERT# R.,item L T_ON F STOUT/GPIO STGP/GPIO/TEMP_LERT# GPIO TP TP TP V F M TP_PH T T T TP0 N TP0_PH T R.,item L +VSUS_ORG EXT_SMI# 0KOhm R PH XP +VS R.,item R.,item L T T T T T T T T T T0 T T T T T T T T T0 T T T T T T T T T T0 T T TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF0 TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF0 TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF TP_VSS_NTF0 TP_VSS_NTF 0 E E F F H H H H J J J J J J0 J J E E VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ IEXPEKM NTF RSV TP TP TP TP TP TP TP TP TP N_ N_ N_ N_ N_ INIT_V# TP J K K M N M0 N0 H T P 0 TP_PH TP_PH TP_PH TP_PH TP_PH TP_PH TP_PH TP_PH_N TP_PH_N TP_PH_N TP_PH_N TP_PH_N INT_V# TP_PH_SST T T0 T T T T T T0 T T T T T T T T GPU_PWR_EN# GPU_HOL_RST# PH_TEMP_LERT# RN0 0KOHM RN0 0KOHM RN0 0KOHM GPU_PRSNT# RN0 0KOHM R.,item L GPU_PWROK R 0KOhm ST_LK_REQ# R 0KOhm R.,item 0'WW0 MoW GN SUSTeK OMPUTER IN. N PH_IEX()PU,GPIO,MIS James_Wu M0J Friday, July 0, 00 ate: Sheet of.00
+VTT_PH_VPLL_EXP +VTT_PH_VPLL_FI +VTT_PH_VPLL_EXP +VTT_PH_V +VTT_PH_VPLL_FI +VTT_PH_VIO GN +VTT_PH_VIO GN +VS_VGG GN +VTT_PH_VIO +VTT_PH_ORG +VTT_PH_ORG GN +VFI_VRM GN +.VS +VTT_PH_.VS_.VS +.VS +VTT_PH_ORG +V_NVRM_VPNN +VS_V_GIO +VS GN +VTT_PU +VM_VPEP GN +VM GN GN +VTT_PU_V_MI +VTT_PH_ORG +V_NVRM_VQ GN GN +.VS_VMI_VRM GN GN +V GN GN GN +VS GN GN +VTT_PH +VTT_PH_V +VTT_PH_ORG +VTT_PH_ORG +VTT_PH_VIO +VS +VFI_VRM +.VS_VMI_VRM +.VS_VT_LV +VS_V_LVS GN +.VS +VS +.VS +V_NVRM_VQ GN GN ate: Sheet of Friday, July 0, 00 SUSTeK OMPUTER IN. N.00 M0J James_Wu PH_IEX()_POWER,GN ate: Sheet of Friday, July 0, 00 SUSTeK OMPUTER IN. N.00 M0J James_Wu PH_IEX()_POWER,GN ate: Sheet of Friday, July 0, 00 SUSTeK OMPUTER IN. N.00 M0J James_Wu PH_IEX()_POWER,GN. S0 max m S0 idle 00m S0 max m S0 max m S0 max m S0 max m S0 max m S0 max m S0 max +VTT_PH_VPLL_EXP.. S0 max +VTT_PH_V_EXP.0 S0 max R.,item L R.,item L0 R.00,item L0 For EMI R.00,item L0 For EMI 0 0UF/.V 0 0UF/.V 0.UF/V 0.UF/V R R 0.UF/V 0.UF/V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL R R 00 SL0 00 SL0 R0 R0 R R R0 R0 R R R R 0 UF/.V 0 UF/.V 0.UF/V 0.UF/V R R 00 SL0 00 SL0 VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] F VSS[] F VSS[] P VSS[] F VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] J VSS[] J VSS[] J0 VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[0] J VSS[] T VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[0] K0 VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[0] K VSS[] L VSS[] L VSS[] M VSS[] M0 VSS[] M VSS[] M VSS[] M VSS[00] M VSS[0] M0 VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] U0 VSS[] M VSS[] V VSS[] M VSS[] M VSS[] 0 VSS[] N VSS[] N0 VSS[] N VSS[0] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] V VSS[] V VSS[] V0 VSS[] V VSS[0] V0 VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[0] W VSS[] F VSS[] W VSS[] W VSS[] W0 VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[0] Y VSS[] U VSS[] N VSS[] 0 VSS[0] VSS[] V VSS[] U VSS[] M VSS[] M VSS[] N VSS[] H VSS[] VSS[0] H VSS[0] VSS[] VSS[] U00H IEXPEKM U00H IEXPEKM R R JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL R R R R 0.UF/V 0.UF/V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL R R 0 0UF/.V 0 0UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0.UF/V 0.UF/V 0 UF/.V 0 UF/.V R R 0 UF/.V 0 UF/.V 00 SL0 00 SL0 UF/.V UF/.V 0.UF/V 0.UF/V R0 R0 L0 KOhm/00Mhz L0 KOhm/00Mhz R R 0 0.0UF/V 0 0.0UF/V 0 0UF/.V 0 0UF/.V R0 R0 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] F VORE[] F VORE[] F0 VORE[] F VORE[0] H VORE[] H VORE[] H0 VORE[] H VORE[] J0 VORE[] J VPNN[] K VPNN[] K0 VIO[] N VIO[] N VIO[] N VIO[0] N VIO[] N0 VIO[] N VIO[] T VIO[] T VIO[] U VIO[] U VIO[] V VIO[] V VIO[] W VIO[0] W VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] E VIO[0] E VIO[] G VIO[] G VIO[] H VIO[] J VIO[] J V[] E0 V[] E VTX_LVS[] P VTX_LVS[] P VLVS H VVRM[] T VVRM[] T VPLLEXP J VFIPLL J VPNN[] K VPNN[] K VPNN[] M VPNN[] M VIO[] K VTX_LVS[] T VTX_LVS[] T VSS_[] F VSS_LVS H VSS_[] F VIO[] M V_[] V_[] V_[] V_[] N VME_[] M VME_[] M VME_[] P VME_[] P VPNN[] K VPNN[] M VPNN[] M VMI[] T VMI[] U VIO[] N0 VIO[] N POWER V ORE MI PI E* RT LVS FI NN / SPI HVMOS U00G IEXPEKM POWER V ORE MI PI E* RT LVS FI NN / SPI HVMOS U00G IEXPEKM
+V.0_INT_VSUS TP_PH_VSW +VSST PRT +VTT_PH_V PL +VTT_PH_V PL +VTT_PH_V PL +V_VPSUS +.0VM_ORG +VTT_PH_V_LK +.0VM_VUX +VTT_PU_VPPU GN GN GN +V_RT +VTT_PH_VIO GN GN GN GN GN +VS_V_ GN GN GN GN +VTT_PU +VTT_PH_.VS_.VS +VSUS_ORG GN GN GN GN GN GN GN GN +VTT_PH_V PL +VTT_PH_V PL GN +VTT_PH_VPLL +VS_PH_VREF +VSUS_VPUS +VTT_PH_VIO GN +VTT_PH_VIO GN +VTT_PH_ORG +VS GN GN +VSUS_ORG GN GN GN GN +.0VM_ORG GN +VSUS_ORG +VS_V_ GN +VSUS_ORG +VTT_PH_VIO +VS_V_ +VS GN +VPLLVRM +VSUS_PH_VREFSUS +VTT_PH_ORG GN GN +VTT_PH_V PL +VTT_PH_V PL GN GN +VTT_PH_ORG GN GN +VTT_PH_.VS_.VS +VPLLVRM +.0VS +.0VM_ORG +VS +VS_V_ +VSUS_H +VSUS_ORG +VSUS +VSUS_ORG +VSUS +VSUS_ORG +.0VM_ORG +VM GN GN GN ate: Sheet of Friday, July 0, 00 SUSTeK OMPUTER IN. N.00 M0J James_Wu PH_IEX()_POWER,GN ate: Sheet of Friday, July 0, 00 SUSTeK OMPUTER IN. N.00 M0J James_Wu PH_IEX()_POWER,GN ate: Sheet of Friday, July 0, 00 SUSTeK OMPUTER IN. N.00 M0J James_Wu PH_IEX()_POWER,GN m S0 max m S0 max S0 max m S0 max m S0 max?? +.VM_VEPW >m S0 max m S0 max +VTT_PH_SSV.+m S0 max m S0 max +VTT_PH_VUSORE m S0 max +VTT_PH_V_ST +VS_VPPI +VS_VPORE 0mil trace at least R.,item L R.,item L R.,item L R.,item L R.,item L R.,item L G R. P.: R.,item L R.,item L 00m S0 max R.,item L R.,item L R.00,item L R.00,item L0 For EMI R.00,item L R.00,item L0 For EMI L0 KOhm/00Mhz L0 KOhm/00Mhz 0 0.UF/V 0 0.UF/V R R 0UF/.V 0UF/.V R R UF/.V UF/.V UF/.V UF/.V 0 T 0 T 0 UF/.V 0 UF/.V VSS[] Y VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] G VSS[] VSS[] VSS[] 0 VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[0] VSS[] H VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E0 VSS[] E VSS[] E0 VSS[00] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E0 VSS[0] E VSS[0] E VSS[0] F VSS[0] F VSS[0] F VSS[] G VSS[] G VSS[] G VSS[] G0 VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] VSS[] 0 VSS[] VSS[] E VSS[] E VSS[0] E0 VSS[] E VSS[] E0 VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] L0 VSS[] L VSS[] M VSS[] M VSS[] M0 VSS[] N VSS[] M VSS[] M VSS[0] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] P VSS[] P VSS[] P0 VSS[0] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[00] T VSS[0] T VSS[0] T VSS[0] U0 VSS[0] U VSS[0] U VSS[0] U VSS[0] P VSS[0] V VSS[0] P VSS[0] V VSS[] V0 VSS[] V VSS[] V0 VSS[] V VSS[] V VSS[] V VSS[] E VSS[] E VSS[0] F VSS[] F VSS[] G0 VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G0 VSS[0] G VSS[] G VSS[] V VSS[] V VSS[] V VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y0 VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] P VSS[] P VSS[] VSS[] F VSS[] H VSS[] H0 VSS[] H0 VSS[] H VSS[] H VSS[] H VSS[] T VSS[] VSS[] T VSS[] VSS[0] Y VSS[] T VSS[] M VSS[] T VSS[] M VSS[] K VSS[] K VSS[] V VSS[] K VSS[] K VSS[] H VSS[0] H VSS[] J U00I IEXPEKM U00I IEXPEKM JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0.UF/V 0.UF/V T0 T0 UF/.V UF/.V 0.UF/V 0.UF/V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0.UF/V 0.UF/V 0.UF/V 0.UF/V + E0 0UF/V ESR=0mOhm/Ir=. + E0 0UF/V ESR=0mOhm/Ir=. R 0 R 0 0.UF/V 0.UF/V UF/.V UF/.V 0.UF/V 0.UF/V UF/.V UF/.V 0.UF/V 0.UF/V 0UF/.V 0UF/.V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0.UF/V 0.UF/V 0 0.UF/V 0 0.UF/V 0UF/.V 0UF/.V UF/.V UF/.V 0.UF/V 0.UF/V T0 T0 L0 KOhm/00Mhz L0 KOhm/00Mhz + E0 0UF/V ESR=0mOhm/Ir=. + E0 0UF/V ESR=0mOhm/Ir=. L0 KOhm/00Mhz L0 KOhm/00Mhz L0 KOhm/00Mhz L0 KOhm/00Mhz T0 T0 0.UF/V 0.UF/V UF/.V UF/.V UF/.V UF/.V 0.UF/V 0.UF/V PSUSYP Y0 VME[] VME[] VME[] VME[] F VME[] F VSUSH L0 VSUS_[] U VIO[] V VIO[] VIO[] F0 VIO[] F VME[] V VME[] V VME[] V VME[0] Y VME[] Y VME[] Y VREF K V_[] J V_[] L V_[0] M V_[] N V_[] P V_[] U VRT VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] E VSUS_[] E VSUS_[0] F VSUS_[] F VSUS_[] G VSUS_[] G VSUS_[] H VSUS_[] H VSUS_[] J VSUS_[] J VSUS_[] L VSUS_[] L VSUS_[0] M VSUS_[] M VSUS_[] N VSUS_[] N VSUS_[] P VSUS_[] P VSUS_[] U VSUS_[] U VSUS_[] U VSUS_[] V VIO[] 0 VIO[0] VIO[0] H VPLL[] VPLL[] VIO[] J VREF_SUS F VIO[] H0 VIO[] VIO[] 0 VIO[] VIO[] F V_[] VIO[] H VVRM[] T0 PSUS Y VIO[] F VIO[] H VLN[] F VLN[] F VPLL[] VPLL[] VVRM[] U VLK[] P VLK[] P PRT V VIO[] F VME[] F VIO[] H VIO[] H PSST V VSTPLL[] K VSTPLL[] K VME[] VME[] Y VME[] Y VME[] V_[] V V_[] V V_[] Y VSUS_[] P VSUS_[0] U VSUS_[] U0 VSUS_[] U VIO[] V VIO[] V VIO[] Y VIO[] Y V_PU_IO[] T V_PU_IO[] U POWER ST US lock and Miscellaneous H PU PI/GPIO/LP RT PI/GPIO/LP U00J IEXPEKM POWER ST US lock and Miscellaneous H PU PI/GPIO/LP RT PI/GPIO/LP U00J IEXPEKM R R 0 UF/.V 0 UF/.V T0 T0.UF/.V.UF/.V 0.UF/V 0.UF/V R R R0 R0 0 T 0 T JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0.UF/V 0.UF/V UF/.V UF/.V 0.UF/V 0.UF/V T0 T0 UF/.V UF/.V R R 0.UF/V 0.UF/V UF/.V UF/.V R 0 R 0 0 UF/.V 0 UF/.V R R R R UF/.V UF/.V