FUION LOK IRM VI ON P P0 FM RIII ~00 RIII ~00 H H UNUFFERE RIII IMM UNUFFERE RIII IMM 0 PIE x PIE FX x ~ PIE INTERFE 0/00/iga bit ETHERNET 0EL/EL UMI

over heet LOK IRM M- Ver:.0 lock istribution VRM Intersil PHE M FM R IMM FH--PIE/PI/PU/LP/LK FH--PI/PIO/U/Z,,,, 0,, PU: M FM ystem hipset: M - Hudson FH--T/PI FH--POWER FH--TRP PI lot & PIE x lot PIE X LOT U.0 U.0 0 On oard hipset: U.0 RearX FrontX U.0 RearX FrontX TIII X LP uper I/O --F LN-Realtek E zalia OE - Realtek L o-lay VI & V ONNETOR LN - Realtek E udio odec - L/ IO - F/OM/LPT/FN YTEM POWER TX/Front Panel History,,,,0 Main Memory: R III * (Max ) Expansion lots: PI Express X lot * PI Express X lot * PI lot * VRM ontroller - Intersil IL Phase MIRO-TRT INT'L O.,LT. OVER HEET ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

FUION LOK IRM VI ON P P0 FM RIII ~00 RIII ~00 H H UNUFFERE RIII IMM UNUFFERE RIII IMM 0 PIE x PIE FX x ~ PIE INTERFE 0/00/iga bit ETHERNET 0EL/EL UMI PIE x LOT ZLI L/ V ONNETOR R HUON / U Rear X Front X U.0 PI PI lot U Rear X Front X 0 U.0 PI ONTROLLER PU ORE POWER N ORE POWER Intersil IL Intersil IL, PI ROM M PI us ~ ERIL T.0 i-tx PU P Power PU R Power PU Power FH ORE POWER UPER I/O F R RM POWER TX ON 0 K ERIL MOUE PORT PRINT PORT MIRO-TRT INT'L O.,LT. LOK iagram ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

H H INTERNL LOK MOE IMM(N) IMM IMM(N) IMM MEM_M_LK_H/L MEM_M_LK_H/L MEM_M_LK_H0/L0 MEM_M_LK_H/L MEM_M_LK_H/L MEM_M_LK_H/L MEM_M_LK_H0/L0 MEM_M_LK_H/L M HUON-/ M_M_M_O PILK0 MHZ MHZ IO F M PU_LKP/N 00MHZ FH_PU_LKP/N PILK0 MHZ PI LOT FM PU IP_LKP/N 00MHZ FH_IP_LKP/N (NO PRE) PP_LKP/N 00MHZ LN-Realtek E (FM, LNE) PIE LN RTLE LT_FX_LKP/N PP_LK0P/N PP_LKP/N PIE FX LOT (FM, LNE) PIE PP LOT (HUON-/, LNE) PIE PP LOT (FM, LNE) M Hz M_X M_X K_X K_X MHZ RT LOK.K Hz MIRO-TRT INT'L O.,LT. lock istribution ize ocument Number Rev M-.0 ate: Friday, July, 0 heet of

V VP _ V_ V R.R%00 VIN V VRM_PWR_R R 0K%00 R R KR%00 X_KR%00 Q R0.KR00 0.u0X00 NN-MKT0 V R.KR%00 VRM_PWR (,0) (0) VORE_EN ux00 VRM_PWROK ux00-rh U EN PWROK V R.R%00 ILR PV VOT.uY00 R X_.R%00 ux00-rh () PU_V () PU_V VRM_PWR_R PWR V V OOT UTE PHE R.R%00 UTE PHE 0.uX UTE () PHE () X_00p0X00 R X_0R%00 0p00 LTE 0 LTE LTE () () () OREF OREF- VP R 00R00 R R 0R00 0R00 X_0.u X_0.u R R.R%00.KR%00 0 0p0X00 R 0R%00 _VP R.KR%00 00pX00 0.0uX00 OMP F F_PI VEN R OOT UTE PHE UTE PHE LTE PWM UTE () PHE () LTE () PWM () RH (KOhm) UPI VOLTE ONOLE 0x0:RH=0K,RL=XX RE 0x 0X 0x 0x 0x 0x0 RL (KOhm) OPEN. 0.. 0... OPEN () NOREF R 00R00 VP_N R 00R00 R 0R00 X_0.uY00 0.KR00 V R 00R00 R0 R.KR%00 0R00 0p0X00 _VN R.KR%00 0 R X_0K%00 0 X_00pX00 p0n00 00pX00 R X_.KR%00 P 0 IEN R R%00 IEN- R IPHE R.0KR%00 IEN R R%00 IEN- R0 IPHE R.0KR%00 IEN R R%00 IEN- R IPHE R.0KR%00 R.R%00 UTE_N PHE_N LTE_N 0.uX V IEN X_0R00 IEN X_0R00 0.uX00 IEN X_0R00 0.uX00 UTE_N () PHE_N () LTE_N () IEN IEN IPHE IEN IEN IPHE IEN IEN IPHE V U_EL 0% V % 0% 0% % 00% V V V R R R0 X_00R00 X_00R00 X_00R00 IEN_N R 0R%00 IEN_N IEN_N- R X_0R00 IPHE_N R.KR%/ 0.uX00 R.KR%00 IEN_N IEN_N IPHE_N (0,) (0,) R0 LK0 T0 X_KR00 0.uX00 U V U_EL L OUT OUT OUT UPM_OT--HF U_EL=00%V _VP_R _VN_R R_F_ () _VP _VN R.KR%00 0.uX00 OTTOM P ONNET TO Through VIs R P0N00.KR%00 lose PHE Output hoke Vcore side RT 0KRT% I address:0x0 VIN HOKE H-.u.0m-RH VIN (,) PU_PWR PU_PWR VRM_PWROK E 0uV MIRO-TRT INT'L O.,LT. Intersil IL Phase LTE PWM PWM R.R%00 0.uX X_0.u R P0N00.KR%00 OMP_N F_N VEN_N P IEN IEN- IEN IEN- IEN IEN- IEN IEN- OOT_N 0 UTE_N PHE_N LTE_N 0.uX00 0.uX00 0.uX00 0.uX00 p0n00 IEN () IPHE () p0n00 IEN () IPHE () p0n00 IEN () IPHE () F OF RPTRL IEN_N IEN_N- TOMP 0.uX00 p0n00 IEN_N () IPHE_N () R 0KR00 R R 0R00 0R00 R 0KR%00 R 0KR%00 0 OP TOMP R.KR%00 R.KR%00 JPWR R X_hort V V E 0uV E 0uV E 0uV PWR-XM_natural-RH ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

VIN VORE 00 T:0 VP_N. T: () UTE UTE R R00 UTE_R Q N-P00 0uX VIN () PHE () LTE PHE LTE R R 0K%00 0R_00 LTE_R Q N-P00 Q N-P00 () () R IPHE IEN.R%00 0 000p0X00 P IPHE IEN HOKE H-0.u0.m-HF P VP 0u.X00 colse to choke () UTE_N () PHE_N () LTE_N UTE_N PHE_N LTE_N R R R00 0R_00 UTE_N_R R0 0K% 00 LTE_N_R Q N-P00 Q N-P00 0uX Q N-P00 R.R%00 000p0X00 P HOKE H-0.u0.m-HF P VP_N 0u.X00 () IPHE_N () IEN_N IPHE_N IEN_N colse to choke VIN () UTE UTE R R00 UTE_R Q 0uX () PHE () LTE PHE LTE R R 0K_% 00 0R00 LTE_R N-P00 Q N-P00 Q0 N-P00 R.R%00 000p0X00 P HOKE H-0.u0.m-HF P VP 0u.X00 colse to choke VP E 0u.O-RH- E 0u.O-RH- E 0u.O-RH- E 0u.O-RH- E 0u.O-RH- E0 0u.O-RH- VP_N E 0u.O-RH- E 0u.O-RH- () IPHE () IEN IPHE IEN E 0u.O-RH- E 0u.O-RH- E X_0u.pO-RH E X_0u.pO-RH E X_0u.pO-RH VIN R.R%00 ux00 VIN VP For EMI R._% 0.uX UTE R0 R00 UTE_R Q 0uX 0.uX00 0.uX00 () PWM PWM U UTE PHE OOT PV PWM V PHE N-P00 R 0K_% 00 HOKE H-0.u0.m-HF VP 0 0.uX00 0.uX00 0.uX00 LTE ILZT_OI-RH LTE R 0R_00 LTE_R Q Q R.R%00 P P 0u.X00 N-P00 N-P00 000p0X00 () IPHE () IEN IPHE IEN colse to choke MIRO-TRT INT'L O.,LT. PU Power ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

FM PIE I/F PUH mach@r PIE apacitors:nf to 00nF Layout: PLE P WITH PU < INH ROUTE LL PIE OHM /-0% PI EXPRE () FX_RX0P () FX_RX0N () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RX0P () FX_RX0N () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () PE_LN_RXP () PE_LN_RXN () PP_RXP () PP_RXN () PP_RXP () PP_RXN () UMI_RX0P () UMI_RX0N () UMI_RXP () UMI_RXN () UMI_RXP () UMI_RXN () UMI_RXP () UMI_RXN F P_FX_RXP0 F P_FX_RXN0 E P_FX_RXP E P_FX_RXN P_FX_RXP P_FX_RXN P_FX_RXP P_FX_RXN P_FX_RXP P_FX_RXN P_FX_RXP P_FX_RXN P_FX_RXP P_FX_RXN P_FX_RXP P_FX_RXN Y P_FX_RXP Y P_FX_RXN Y P_FX_RXP Y P_FX_RXN W P_FX_RXP0 W P_FX_RXN0 V P_FX_RXP V P_FX_RXN V P_FX_RXP V P_FX_RXN U P_FX_RXP U P_FX_RXN T P_FX_RXP T P_FX_RXN T P_FX_RXP T P_FX_RXN H P_PP_RXP0 H P_PP_RXN0 H P_PP_RXP H P_PP_RXN P_PP_RXP P_PP_RXN F P_PP_RXP F P_PP_RXN L P_UMI_RXP0 L P_UMI_RXN0 K P_UMI_RXP K P_UMI_RXN J P_UMI_RXP J P_UMI_RXN J P_UMI_RXP J P_UMI_RXN UMI_LINK PP RPHI P_FX_TXP0 E FX_TX0P P_FX_TXN0 E FX_TX0N P_FX_TXP E FX_TXP P_FX_TXN E FX_TXN P_FX_TXP FX_TXP P_FX_TXN FX_TXN P_FX_TXP FX_TXP P_FX_TXN FX_TXN P_FX_TXP FX_TXP P_FX_TXN FX_TXN P_FX_TXP FX_TXP P_FX_TXN FX_TXN P_FX_TXP FX_TXP P_FX_TXN FX_TXN P_FX_TXP FX_TXP P_FX_TXN FX_TXN P_FX_TXP Y FX_TXP P_FX_TXN Y FX_TXN P_FX_TXP W FX_TXP P_FX_TXN W FX_TXN P_FX_TXP0 W FX_TX0P P_FX_TXN0 W FX_TX0N P_FX_TXP V FX_TXP P_FX_TXN V FX_TXN P_FX_TXP U FX_TXP P_FX_TXN U FX_TXN P_FX_TXP U FX_TXP P_FX_TXN U FX_TXN P_FX_TXP T FX_TXP P_FX_TXN T FX_TXN P_FX_TXP R FX_TXP P_FX_TXN R FX_TXN P_PP_TXP0 H LN_TXP P_PP_TXN0 H LN_TXN P_PP_TXP PP_TXP P_PP_TXN PP_TXN P_PP_TXP PP_TXP P_PP_TXN PP_TXN P_PP_TXP F P_PP_TXN F P_UMI_TXP0 K UMI_TX0P_PU P_UMI_TXN0 K UMI_TX0N_PU P_UMI_TXP L UMI_TXP_PU P_UMI_TXN L UMI_TXN_PU P_UMI_TXP K UMI_TXP_PU P_UMI_TXN K UMI_TXN_PU P_UMI_TXP J UMI_TXP_PU P_UMI_TXN J UMI_TXN_PU 0 0 0 0 0.uX00 0.uX00 0.uX00 0.uX00 0.uX00 0.uX00 0.uX00 0.uX00 0.uX00 0.uX00 0.uX00 0.uX00 0.uX00 0.uX00 FX_TX0P () FX_TX0N () FX_TXP () FX_TXN () FX_TXP () FX_TXN () FX_TXP () FX_TXN () FX_TXP () FX_TXN () FX_TXP () FX_TXN () FX_TXP () FX_TXN () FX_TXP () FX_TXN () FX_TXP () FX_TXN () FX_TXP () FX_TXN () FX_TX0P () FX_TX0N () FX_TXP () FX_TXN () FX_TXP () FX_TXN () FX_TXP () FX_TXN () FX_TXP () FX_TXN () FX_TXP () FX_TXN () PE_LN_TXP () PE_LN_TXN () PE_PP_TXP () PE_PP_TXN () PE_PP_TXP () PE_PP_TXN () UMI_TX0P () UMI_TX0N () UMI_TXP () UMI_TXN () UMI_TXP () UMI_TXN () UMI_TXP () UMI_TXN () V_P_ R R% PU_P_ZP J P_ZP P_Z J PU_P_Z R R% <PU> MIRO-TRT INT'L O.,LT. FM PIE I/F ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_M0 MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_Q_H0 MEM_M_Q_L0 MEM_M_Q_L MEM_M_Q_H MEM_M_Q_H MEM_M_Q_L MEM_M_Q_H MEM_M_Q_L MEM_M_Q_L MEM_M_Q_H MEM_M_Q_H MEM_M_Q_L MEM_M_Q_L MEM_M_Q_H MEM_M_Q_H MEM_M_Q_L MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_NK0 MEM_M_NK MEM_M_NK MEM_M_M0 MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_Q_H0 MEM_M_Q_L0 MEM_M_Q_H MEM_M_Q_L MEM_M_Q_H MEM_M_Q_L MEM_M_Q_H MEM_M_Q_L MEM_M_Q_L MEM_M_Q_H MEM_M_Q_H MEM_M_Q_L MEM_M_Q_H MEM_M_Q_L MEM_M_Q_H MEM_M_Q_L MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T PU_M_ZVIO MEM_M_HOT# MEM_M_HOT# MEM_M_NK0 MEM_M_NK MEM_M_NK MEM_M L0 MEM_M L MEM_M_LK_L0 MEM_M_LK_H0 MEM_M L MEM_M_REET# MEM_M_OT0 MEM_M_OT MEM_M_R_L MEM_M_HOT# MEM_M L0 MEM_M L MEM_M_KE0 MEM_M_KE MEM_M_LK_H MEM_M_LK_L MEM_M_WE_L MEM_M_LK_L0 MEM_M_LK_H0 MEM_M_LK_H MEM_M_LK_L MEM_M_R_L MEM_M L MEM_M_WE_L MEM_M_REET# MEM_M_HOT# MEM_M_KE0 MEM_M_OT0 MEM_M_OT MEM_M_KE V_R PU_M_VREF V_R PU_M_VREF V_R MEM_M_Q_H[..0] (0) MEM_M_M[..0] (0) MEM_M_Q_L[..0] (0) MEM_M_Q_H[..0] () MEM_M_M[..0] () MEM_M_Q_L[..0] () MEM_M_[..0] (0) MEM_M_T[..0] (0) MEM_M_[..0] () MEM_M_NK0 () MEM_M_NK () MEM_M_NK () MEM_M_T[..0] () MEM_M_NK0 (0) MEM_M_NK (0) MEM_M_NK (0) MEM_M_HOT# (0) MEM_M_KE0 () MEM_M_KE () MEM_M_OT0 () MEM_M_OT () MEM_M L () MEM_M L0 () MEM_M_LK_H0 () MEM_M_LK_L0 () MEM_M_LK_L () MEM_M_LK_H () MEM_M_REET# (0) MEM_M_KE0 (0) MEM_M_KE (0) MEM_M_WE_L (0) MEM_M L (0) MEM_M_R_L (0) MEM_M_OT0 (0) MEM_M_OT (0) MEM_M L (0) MEM_M L0 (0) MEM_M_LK_L (0) MEM_M_LK_H (0) MEM_M_LK_H0 (0) MEM_M_LK_L0 (0) MEM_M L () MEM_M_WE_L () MEM_M_R_L () MEM_M_REET# () MEM_M_HOT# () ize ocument Number Rev ate: heet of MIRO-TRT INT'L O.,LT. M-.0 FM R I/F ustom Friday, July, 0 ize ocument Number Rev ate: heet of MIRO-TRT INT'L O.,LT. M-.0 FM R I/F ustom Friday, July, 0 ize ocument Number Rev ate: heet of MIRO-TRT INT'L O.,LT. M-.0 FM R I/F ustom Friday, July, 0 Layout: Place within.'' of PU mach@lok assignment can be changed FMR I/F Layout: Place within.'' of PU mach@00trace width 000p0X00 000p0X00 0 0.uX00 0 0.uX00 0.uX00 0.uX00 R KR00 R KR00 R KR00 R KR00 MEMORY HNNEL PU <PU> MEMORY HNNEL PU <PU> J M_ZIO K M_VREF U M_EVENT_L J M_REET_L Y M_WE_L Y M L W M_R_L M L W M L0 M0 L Y M0 L0 M_OT M_OT0 M0_OT M0_OT0 K M_KE L M_KE0 R M_LK_L R M_LK_H T M_LK_L T M_LK_H U M_LK_L T M_LK_H U M_LK_L0 U M_LK_H0 E0 M_Q_L F0 M_Q_H M_Q_L E M_Q_H F M_Q_L F0 M_Q_H M_Q_L M_Q_H E M_Q_L E M_Q_H M_Q_L M_Q_H E M_Q_L F M_Q_H M_Q_L H M_Q_H F M_Q_L0 M_Q_H0 M_M F M_M M_M E M_M F M_M F M_M H M_M E M_M H M_M0 L M_NK V M_NK W M_NK0 L M_ L M_ Y M_ M M_ N M_ V M_0 M M_ N M_ N M_ P M_ P M_ R M_ P M_ R M_ P M_ V M_0 H M_HEK F M_HEK M_HEK H M_HEK H0 M_HEK M_HEK E M_HEK F M_HEK0 M_T M_T F M_T M_T0 M_T F M_T E M_T M_T M_T E0 M_T E M_T M_T M_T E M_T0 M_T M_T M_T F M_T E M_T M_T E M_T F M_T M_T F M_T0 M_T M_T E M_T M_T F M_T M_T F0 M_T 0 M_T H M_T E M_T0 E M_T H M_T F M_T E M_T H M_T F M_T M_T F M_T E0 M_T M_T0 M_T E M_T H0 M_T 0 M_T F M_T E M_T H M_T F M_T F M_T H M_T0 M_T F M_T M_T E M_T H M_T M_T E M_T H M_T F M_T E M_T0 R KR%00 R KR%00 R.R%00 R.R%00 MEMORY HNNEL PU MEMORY HNNEL PU V M_EVENT_L J M_REET_L M_WE_L M L W M_R_L M L Y0 M L0 M0 L Y M0 L0 M_OT M_OT0 0 M0_OT 0 M0_OT0 J M_KE J0 M_KE0 R0 M_LK_L P0 M_LK_H T M_LK_L R M_LK_H T M_LK_L T M_LK_H U M_LK_L0 U0 M_LK_H0 M_Q_L M_Q_H L M_Q_L L M_Q_H J M_Q_L J0 M_Q_H L M_Q_L K M_Q_H H M_Q_L J M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H M_Q_L0 M_Q_H0 M_M J M_M K M_M H M_M L M_M M_M 0 M_M M_M M_M0 K M_NK V0 M_NK W M_NK0 J M_ K M_ M_ K M_ L M_ W M_0 L0 M_ M M_ M M_ M M_ M0 M_ N M_ N M_ P M_ N M_ V M_0 M_HEK 0 M_HEK M_HEK M_HEK M_HEK 0 M_HEK M_HEK M_HEK0 H M_T K M_T K M_T H M_T0 K M_T J M_T H M_T J M_T L0 M_T H0 M_T L M_T L M_T K M_T L M_T0 H M_T K M_T K M_T J M_T L M_T K M_T J M_T H M_T H M_T J M_T0 L M_T K M_T H M_T 0 M_T J M_T H M_T K0 M_T J0 M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T 0 M_T 0 M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 R KR%00 R KR%00

FM IPLY I/F () () () () () () () () P0_TX0P P0_TX0N P0_TXP P0_TXN P0_TXP P0_TXN P0_TXP P0_TXN () () P_TX0P P_TX0N PU NLO/IPLY/MI Layout: Place within.'' of PU 0.uX00 P0_TX0P_PU M P0_TXP0 P_UX_Z J P_UX_Z R 0R%00 0.uX00 P0_TX0N_PU M P0_TXN0 P_LON PU_LON TP 0.uX00 P0_TXP_PU L P0_TXP P_ION PU_ION TP 0.uX00 P0_TXN_PU L P0_TXN P_VRY_L H PU_LPWM TP 0.uX00 0.uX00 0.uX00 0.uX00 P0_TXP_PU P0_TXN_PU P0_TXP_PU P0_TXN_PU L L K K R R P0_TXP P0_TXN P0_TXP P0_TXN P_TXP0 P_TXN0 IPLY PORT 0 IPLY PORT MI. P0_UXP P0_UXN P_UXP P_UXN P_UXP P_UXN K K L L R R P0_UXP () P0_UXN () P_UXP () P_UXN () () () P_TXP P_TXN P P P_TXP P_TXN P_UXP P_UXN P P () () () () P_TXP P_TXN P_TXP P_TXN N N N N P_TXP P_TXN P_TXP P_TXN IPLY PORT P_UXP P_UXN P_UXP P_UXN N N M M V_R R0 0KR00 PU_THERMTRIP# E Q N-T0_OT V_R FH_THERMTRIP# () () () () () (,) (,) PU_LK PU_LK# IP_LK IP_LK# PU_I PU_I () PU_RT# (,) PU_PWR () PU_PROHOT# () () () NOREF () IOF () OREF () PU_V PU_V OREF TP OREF- OREF- TP TP PU_V PU_V PU_I PU_I PU_RT# PU_PWR PU_PROHOT# PU_THERMTRIP# PU_LERT# TP PU_TI PU_TO PU_TK PU_TM PU_TRT# PU_RY PU_REQ# P_ENE R_ENE L K H F0 0 J L K 0 E 0 E F0 F E H K K F LKIN_H LKIN_L IP_LKIN_H IP_LKIN_L V V I I REET_L PWROK PROHOT_L THERMTRIP_L LERT_L TI TO TK TM TRT_L RY REQ_L RV_ RV_ RV_ RV_ RV_ P_ENE N_ENE IO_ENE _ENE R_ENE _ENE ENE RV JT TRL ER. LK TET <PU> P0_HP P_HP P_HP P_HP P_HP P_HP THERM THERM TET TET TET TET TET0 TET TET TET TET TET TET TET TET0 TET TET TET TET TET_H TET_L TET_H TET_L TET0_H TET0_L TET TET_H TET_L TET FMR MTIVE_L K K P P M M H 0 0 F E F E F E E E E F P_HP P_HP P_HP P_HP PU_TET PU_TET PU_TET PU_TET PU_TET PU_TET PU_TET PU_TET PU_TET0 PU_TET PU_TET PU_TET PU_TET PU_TET_H PU_TET_L PU_TET_H PU_TET_L PU_TET0_H PU_TET0_L PU_TET PU_TET_H PU_TETL PU_TET PU_FMR FH_M_TIVE# R R00 R0 R0 R0 00KR00 00KR00 00KR00 00KR00 0R00 TP TP R0 KR00 TP TP TP TP R0 KR00 R0 KR00 R0 KR00 R0 KR00 R0 KR00 TP0 R KR00 R R%00 R R%00 TP TP R X_.R%00 R X_.R%00 R.R%00 TP TP R X_00R00 R0 00R00 PU_FMR (0) FH_M_TIVE# () P0_V_HP () P_VI_HP () PU_P V_R V_R PU_TET PU_TET PU_TET PU_TET PU_TET PU_TET PU_TET0 N onnector TP TP TP0 TP TP TP TP R 0KR00 PU_LERT# E Q N-T0_OT FH_TLERT# () PULL UP V_R R0 0KR00 PU_TI V_R R X_0KR00 PU_TO R R KR00 KR00 PU_I PU_I R R 0KR00 0KR00 PU_TK PU_TM R R 00R00 00R00 PU_RT# PU_PWR R R 0KR00 X_0KR00 PU_TRT# PU_RY R 0KR00 PU_REQ# R R R 00R00 KR00 KR00 PU_PROHOT# PU_LERT# PU_THERMTRIP# R KR00 FH_M_TIVE# V_R R0 R KR00 X_0R00 PU_V R R KR00 X_0R00 PU_V V_ R 0KR00 PU_FMR MIRO-TRT INT'L O.,LT. FM IPLY/MI ize ocument Number Rev ustom M-.0 Friday, July, 0 ate: heet of 0

VP VP VP VP VP VP_N V_R V_R PU_R PU_P VP VP PU_R PU_P V_P_ PU_R_ V_P_ PU_R_ VP_N _ V_R VP_N VP ize ocument Number Rev ate: heet of MIRO-TRT INT'L O.,LT. M-.0 FM POWER&EOUPLIN ustom 0 Friday, July, 0 ize ocument Number Rev ate: heet of MIRO-TRT INT'L O.,LT. M-.0 FM POWER&EOUPLIN ustom 0 Friday, July, 0 ize ocument Number Rev ate: heet of MIRO-TRT INT'L O.,LT. M-.0 FM POWER&EOUPLIN ustom 0 Friday, July, 0 OTTOM IE P and R support two separate power planes with single regulator OTTOM IE 0P0N00 0P0N00 000p0X00 000p0X00 u.x00 u.x00 0.0uX/ 0.0uX/ 000p0X00 000p0X00 0P0N00 0P0N00 0 X_u.X00 0 X_u.X00 0.UX 0.UX 0p0N00 0p0N00 u.x00 u.x00 u.x00 u.x00 u.x00 u.x00 X_0P0N00 X_0P0N00 0.UX 0.UX X_u.X00 X_u.X00 X_0p0N00 X_0p0N00 0p0N00 0p0N00 0.UX 0.UX u.x00 u.x00 0 X_0u.X00 0 X_0u.X00 POWER PUE <PU> POWER PUE <PU> M IO IO IO IO IO 0 IO IO IO IO IO IO IO Y IO Y IO Y IO Y IO W0 IO W IO W IO V IO V IO V IO V IO U IO U IO U IO T0 IO T IO T IO T IO R IO R IO R IO P IO P IO P IO P IO N0 IO N IO N IO M IO M IO M IO L IO L IO L IO K0 IO K IO K IO J IO J IO H R H R H R H R J P J P J P J P L R K R J R H R L0 P K0 P J0 P H0 P N N_P_ M N_P_ F N F N F N F N E N E N E N N N N N N N N N N N N N E X_.u.X X_.u.X 0 X_0.uX 0 X_0.uX X_u.X00 X_u.X00 0 0p0N00 0 0p0N00 X_u.X00 X_u.X00 PU <PU> PU <PU> T T T0 T T0 T R R R R P0 P0 P N N M M U M0 M M W M0 M L L L N L L W L K K0 K K K K K0 J J J J J J J U H H0 P M K K H H H F R R 0 Y Y Y0 Y Y Y Y Y0 Y W W W W V0 V V0 V U U 0 u.x00 0 u.x00 0 0.uX 0 0.uX 0 u.x00 0 u.x00 X_0.UX X_0.UX F 0L-0_00-RH F 0L-0_00-RH X_0.uX X_0.uX X_u.X00 X_u.X00 u.x00 u.x00.u.x.u.x u.x00 u.x00 u.x00 u.x00 u.x00 u.x00 0 u.x00 0 u.x00 0 X_0u.X00 0 X_0u.X00 0.UX 0.UX u.x00 u.x00 u.x00 u.x00 0.uX 0.uX 0 0.0uX/ 0 0.0uX/ 0 X_u.X00 0 X_u.X00 0 0.uX 0 0.uX 0.UX 0.UX 0.uX 0.uX 0 0p0N00 0 0p0N00 X_0u.X00 X_0u.X00 u.x00 u.x00 u.x00 u.x00 u.x00 u.x00 00p0X00 00p0X00 0.uX 0.uX u.x00 u.x00 0p0N00 0p0N00 u.x00 u.x00 X_.u.X X_.u.X PU <PU> PU <PU> E E E E E E0 0 0 0 0 Y Y Y Y Y Y W W W0 W W0 V V V V U U U U U0 U U0 T T T T P P M L L L L L L L L K K K K0 K K J J J J J J J J J J J H0 H H H H H H 0 F F F F F F F F F F E E E0 E u.x00 u.x00 0 X_0u.X00 0 X_0u.X00 0P0N00 0P0N00 X_u.X00 X_u.X00 X_0u.X00 X_0u.X00 0p0N00 0p0N00 PUF <PU> PUF <PU> _0 F _ F _ F _ F _ F0 _ F _ F _ F _ E _ E _0 E _ E _ E _ E _ E _ E _ E0 0 0 _ 0 _0 0 0 _ L _ 0 _ R _ R _ R0 _ R _ R0 _ P _ P _0 P _0 P _0 N _0 N _0 N _0 N _0 N0 _0 N _0 N0 _0 M _00 M _ M _ M _ M _ L _ L _ L0 _ L _ L _ L _0 L _ L0 _ K _ K _ V _ K _ K _ V _ K _ K _0 J _ J _ J _ J0 _ J _ J _ J _ J _ J0 _ H _0 H _ H _ H _ H _ H _ H _ H _ H _0 0 _ X_u.X00 X_u.X00 0p0N00 0p0N00 0 X_u.X00 0 X_u.X00 0 0.uX 0 0.uX u.x00 u.x00 X_0u.X00 X_0u.X00 0p0N00 0p0N00 X_u.X00 X_u.X00.u.X.u.X u.x00 u.x00 u.x00 u.x00 u.x00 u.x00 X_000p0X00 X_000p0X00 0.0uX/ 0.0uX/ X_u.X00 X_u.X00 0 0.uX 0 0.uX X_000p0X00 X_000p0X00 u.x00 u.x00 u.x00 u.x00 X_u.X00 X_u.X00 X_u.X00 X_u.X00 0.uX 0.uX u.x00 u.x00 0u.X00 0u.X00 u.x00 u.x00 0.u.X 0.u.X 0p0N00 0p0N00

V_R V VTT_R () MEM_M_Q_H[..0] MEM_M_HOT# MEM_M_HOT# () () MEM_M_Q_L[..0] () MEM_M_T[..0] MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T V_R MEM_VREF_ R 0.uX00 KR%00 R KR%00 V_R 0 MEM_VREF_Q R0 KR%00 0.uX00 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 IMM Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q 0 0 R P 0 0 VTT VTT N/PR_IN N/ERR_OUT N/TET RV FREE FREE FREE FREE 0 0 0/P 0 0 Q0 Q0# Q Q# Q Q# Q Q# Q Q# Q Q# Q Q# Q Q# Q Q# M0/Q N/Q# M/Q0 N/Q0# M/Q N/Q# M/Q N/Q# M/Q N/Q# M/Q N/Q# M/Q N/Q# M/Q N/Q# M/Q N/Q# OT0 OT KE0 KE 0# # 0 WE# R# # REET# K0 K0# K(NU) K#(NU) ME ME ME 0 0 0 0 0 0 0 0 VREFQ VREF L 0 MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_Q_H0 MEM_M_Q_L0 MEM_M_Q_H MEM_M_Q_L MEM_M_Q_H MEM_M_Q_L MEM_M_Q_H MEM_M_Q_L MEM_M_Q_H MEM_M_Q_L MEM_M_Q_H MEM_M_Q_L MEM_M_Q_H MEM_M_Q_L MEM_M_Q_H MEM_M_Q_L MEM_M_M0 MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_OT0 MEM_M_OT MEM_M_KE0 MEM_M_KE MEM_M L0 MEM_M L MEM_M_NK0 MEM_M_NK MEM_M_NK MEM_M_WE_L MEM_M_R_L MEM_M L MEM_M_REET# MEM_M_LK_H0 MEM_M_LK_L0 MEM_M_LK_H MEM_M_LK_L MEM_VREF_Q MEM_VREF_ MEM_LK MEM_T V MEM_M_[..0] () MEM_M_M[..0] () MEM_M_OT0 () MEM_M_OT () MEM_M_KE0 () MEM_M_KE () MEM_M L0 () MEM_M L () MEM_M_NK0 () MEM_M_NK () MEM_M_NK () MEM_M_WE_L () MEM_M_R_L () MEM_M L () MEM_M_REET# () MEM_M_LK_H0 () MEM_M_LK_L0 () MEM_M_LK_H () MEM_M_LK_L () MEM_VREF_Q MEM_VREF_ 0 0 0 0 0 0 0 0 ME ME ME RIII-0P_lue-RH R KR%00 MEM_VREF_Q MEM_VREF_ () MEM_LK () MEM_T MEM_LK MEM_T R R X_R/ X_R/ LK0 (,) T0 (,) IMM(HNNEL- ) M RE= 000p0X00 0 0.u0X00 000p0X00 0.u0X00 IMM(HNNEL- 0) M RE=0 MIRO-TRT INT'L O.,LT. R H- ize ocument Number Rev ustom M-.0 Friday, July, 0 ate: heet of 0

V_R V VTT_R () MEM_M_Q_H[..0] MEM_M_HOT# MEM_M_HOT# () () MEM_M_Q_L[..0] IMM 0 0 N/ERR_OUT N/TET RV FREE FREE FREE FREE MEM_M_T0 MEM_M_0 () MEM_M_T[..0] MEM_M_T Q0 0 MEM_M_[..0] () MEM_M_ MEM_M_T Q MEM_M_ MEM_M_T Q 0 MEM_M_ MEM_M_T Q 0 MEM_M_ MEM_M_T Q MEM_M_ MEM_M_T Q MEM_M_ MEM_M_T Q MEM_M_ MEM_M_T Q MEM_M_ MEM_M_T Q MEM_M_ MEM_M_T0 Q MEM_M_0 MEM_M_T Q0 0/P 0 MEM_M_ MEM_M_T Q MEM_M_ MEM_M_T Q MEM_M_ MEM_M_T Q MEM_M_ MEM_M_T Q MEM_M_ MEM_M_T Q MEM_M_T Q MEM_M_T Q 0 MEM_M_T Q 0 MEM_M_T0 Q 0 MEM_M_T Q0 MEM_M_T Q MEM_M_T Q MEM_M_T Q 0 MEM_M_T Q MEM_M_T Q MEM_M_Q_H0 MEM_M_T Q Q0 MEM_M_Q_L0 MEM_M_T Q Q0# MEM_M_Q_H MEM_M_T Q Q 0 MEM_M_Q_L MEM_M_T0 Q Q# MEM_M_Q_H MEM_M_T Q0 Q MEM_M_Q_L MEM_M_T Q Q# MEM_M_Q_H MEM_M_T Q Q MEM_M_Q_L MEM_M_T Q Q# MEM_M_Q_H MEM_M_T Q Q MEM_M_Q_L MEM_M_T Q Q# 00 MEM_M_Q_H MEM_M_T Q Q 0 MEM_M_Q_L MEM_M_T Q Q# 0 MEM_M_Q_H MEM_M_T Q Q 0 0 MEM_M_Q_L MEM_M_T0 Q Q# 0 0 MEM_M_Q_H MEM_M_T Q0 Q MEM_M_Q_L MEM_M_T Q Q# MEM_M_T Q Q MEM_M_T Q Q# 0 MEM_M_T Q 0 R MEM_M_M0 MEM_M_M[..0] () MEM_M_T Q M0/Q MEM_M_T Q N/Q# MEM_M_M MEM_M_T Q M/Q0 MEM_M_T Q N/Q0# 00 MEM_M_M MEM_M_T0 Q M/Q 0 MEM_M_T Q0 N/Q# 0 MEM_M_M MEM_M_T Q M/Q MEM_M_T Q N/Q# MEM_M_M MEM_M_T Q M/Q 0 MEM_M_T Q N/Q# 0 MEM_M_M MEM_M_T Q M/Q 0 MEM_M_T Q N/Q# 0 MEM_M_M MEM_M_T Q M/Q MEM_M_T Q N/Q# MEM_M_M MEM_M_T0 Q M/Q 0 MEM_M_T Q0 N/Q# MEM_M_T Q M/Q MEM_M_T Q N/Q# Q MEM_M_OT0 OT0 MEM_M_OT0 () MEM_M_OT OT MEM_M_OT () MEM_M_KE0 KE0 0 MEM_M_KE0 () MEM_M_KE KE MEM_M_KE () MEM_M L0 0# MEM_M L0 () MEM_M L # MEM_M L () MEM_M_NK0 0 MEM_M_NK0 () 0 MEM_M_NK 0 MEM_M_NK () MEM_M_NK MEM_M_NK () MEM_M_WE_L WE# MEM_M_WE_L () MEM_M_R_L R# MEM_M_R_L () MEM_M L # MEM_M L () MEM_M_REET# REET# MEM_M_REET# () MEM_M_LK_H0 K0 MEM_M_LK_H0 () MEM_M_LK_L0 K0# MEM_M_LK_L0 () 0 MEM_M_LK_H K(NU) MEM_M_LK_H () MEM_M_LK_L K#(NU) MEM_M_LK_L () MEM_VREF_Q VREFQ MEM_VREF_Q MEM_VREF_ VREF MEM_VREF_ MEM_LK L MEM_LK (0) MEM_T MEM_T (0) 0 0 0 V ME ME ME P 0 0 VTT VTT N/PR_IN 0 0 0 0 0 0 0 0 ME ME ME RIII-0P_lue-RH e-coupling aps For IMMs IMM(HNNEL- ) M RE= V_R ux ux 0.uX00 0.uX00 0.uX00 0.uX00 0.uX00 0.uX00 VTT_R 0.uX00 0.uX00 IMM(HNNEL- 0) M RE= MIRO-TRT INT'L O.,LT. R H- ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

UE 0 To PIEX,X,LN To IO PIE_RT# 0pN00 _RT# 0pN00 _RT# for LP device; PIE_RT# for PU PIE device; PIE_RT# FH PIE device (,) PIE_RT# () _RT# () UMI_RX0P () UMI_RX0N () UMI_RXP () UMI_RXN () UMI_RXP () UMI_RXN () UMI_RXP () UMI_RXN () UMI_TX0P () UMI_TX0N () UMI_TXP () UMI_TXN () UMI_TXP () UMI_TXN () UMI_TXP () UMI_TXN FH RUN FH RUN () () () () () PE_XF_LK0 () PE_XF_LK0# () PE_PP_LK () PE_PP_LK# () PE_PP_LK () PE_PP_LK# () PE_LN_LK () PE_LN_LK# R R00 PIE_RT#_R E R R00 _RT#_R 0.uX00 UMI_RX0P_FH E0 0.uX00 UMI_RX0N_FH E 0.uX00 UMI_RXP_FH 0.uX00 UMI_RXN_FH 0.uX00 UMI_RXP_FH 0.uX00 UMI_RXN_FH 0.uX00 UMI_RXP_FH 0 0.uX00 UMI_RXN_FH Y Y Y Y R 0R%00 PIE_LRP F R KR%00 PIE_LRN F R KR%00 IP_LK IP_LK# PU_LK PU_LK# V V W0 W W V V W W W LK_LRN F 0 R T H H T T J0 K H H J K F F E E M M M M N N HUON- Part of PIE_RT# _RT# UMI_TX0P UMI_TX0N UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_RX0P UMI_RX0N UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN PIE_LRP PIE_LRN PP_TX0P PP_TX0N PP_TXP PP_TXN PP_TXP PP_TXN PP_TXP PP_TXN PP_RX0P PP_RX0N PP_RXP PP_RXN PP_RXP PP_RXN PP_RXP PP_RXN LK_LRN PIE_RLKP PIE_RLKN IP_LKP IP_LKN IP_LKP IP_LKN PU_LKP PU_LKN LT_FX_LKP LT_FX_LKN PP_LK0P PP_LK0N PP_LKP PP_LKN PP_LKP PP_LKN PP_LKP PP_LKN PP_LKP PP_LKN PP_LKP PP_LKN PP_LKP PP_LKN PI EXPRE INTERFE LOK ENERTOR PI LK PI INTERFE LP PILK0 PILK/PO PILK/PO PILK/PO PILK/M_O/PO PIRT# 0/PIO0 /PIO /PIO /PIO /PIO /PIO /PIO /PIO /PIO /PIO 0/PIO0 /PIO /PIO /PIO /PIO /PIO /PIO /PIO /PIO /PIO 0/PIO0 /PIO /PIO /PIO /PIO /PIO /PIO /PIO /PIO /PIO 0/PIO0 /PIO E0# E# E# E# FRME# EVEL# IRY# TRY# PR TOP# PERR# ERR# REQ0# REQ#/PIO0 REQ#/LK_REQ#/PIO REQ#/LK_REQ#/PIO NT0# NT#/PO NT#/_LE/PO NT#/LK_REQ#/PIO LKRUN# LOK# INTE#/PIO INTF#/PIO INT#/PIO INTH#/PIO LPLK0 LPLK L0 L L L LFRME# LRQ0# LRQ#/LK_REQ#/PIO ERIRQ/PIO F PI_LK0_R F F PI_LK_R F PIRT# J 0 L L H J L N N J L 0 L M J K N M J0 L K 0 N E E F H H 0 E N _E#0 J _E# N0 _E# _E# 0 FRME# K EVEL# L0 IRY# F0 TRY# E0 PR H TOP# M PERR# H ERR# PREQ0# F M PNT#0 K H LOK# F PI_INTE# E PI_INTF# PI_INT# PI_INTH# LP_LK0 LP_LK_R LP_0 LP_ LP_ LP_ LP_FRME# LP_RQ#0 E H_ILE# E ERIRQ R R00 R R00 R R00 FRME# () EVEL# () IRY# () TRY# () PR () TOP# () PERR# () ERR# () PREQ0# () PNT0# () LOK# () PI_INTE# () PI_INTF# () PI_INT# () PI_INTH# () R R00 PILK0_IO PILK0_IO X_0p0N00 PILK0_IO () PI_LK () PILK_LOT PILK_LOT X_0p0N00 PILK_LOT () PI_LK () PI_LK () PIRT_LOT# PIRT_LOT# 0pN00 PIRT_LOT# () [..0] (,) _E#[..0] () V_ LP_RQ#0 R0 X_0KR00 LRQ#/PIO H_ILE# R0 0KR00 V ERIRQ R X_0KR00 V_ LP_LK0 () LPLK_TPM (,) FH_LT_TOP# R 0KR%00 LP_[..0] LP_[..0] () FOR HIPET UTOMTION LP_FRME# () LP_RQ#0 () ERIRQ () () IO_M_LK IO_M_LK R X_0p0N00 R00 FH_M R R N R J PP_LKP PP_LKN PP_LKP PP_LKN M_M_M_O PU M_TIVE# PROHOT# PU_P LT_TP# PU_RT# E E PU_P_R R FH_LT_TOP# F PU_RT# X_hort FH_M_TIVE# () PU_PROHOT# () PU_PWR (,) PU_RT# () VT V_ K_X FH_K_X X Layout:Place x'tal within. inch of FH FH_K_X Y.KHZ.P_- FH_K_X P0N00 P0N00 Y MHZP_- R MR00 FH_M_X FH_M_X Layout:Place x'tal within. inch of FH M_X M_X PLU K_X _ORE_EN RTLK INTRUER_LERT# T_RT_ H F F E FH_K_X _ORE_EN RT_LK VT_FH This signal is for enabling the standby power when plus logic is enabled TP RT_LK () ux00 R 0R00 VT_IN ux00 Z Y -T_OT R T KR%/ T-P-RH- N-0F0-H0 R P0N00 0MR P0N00 Note: LT_P, LT_TP# & LT_RT# are O and require a PU to the PU I/O rail. They are also in the domain to prevent glitching at power up. VT_FH JT HXM_LK-RH MIRO-TRT INT'L O.,LT. HUON PIE/PI/PU/LP/LK PLE THEE OMPONENT LOE TO U00, N UE ROUN UR FOR K_X N K_X ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

HUON PI/U/Z/PIO V_ V_ V () R R0 R R R LP_PME# R LP_# LP_# 0KR00 FH_THERMTRIP# X_0KR00 PI_PME# X_0KR00 LP_MI# X_0KR00 X_0KR00 00R00 R PE_WKE# PWRTN# 0R00 W_PWR PI_PME# () (,,0) LP_# (,,) LP_# () PWRTN# (0) FH_PWR Test Mode ignals () 0TE () KRT# () PI_PME# () LP_MI# (0) FP_RT# (,) PE_WKE# FH_THERMTRIP# TP TP TP TP PIE_RT# PIE_RT# FH PIE device LP_# LP_# PWRTN# FH_PWR FH_TET0 FH_TET FH_TET PI_PME# LP_MI# PE_WKE# W_PWR R W T W J N T T0 V E R T U K V R0 F PIE_RT#/EVENT# RI#/EVENT# PI_#/E_TT/EVENT# LP_# LP_# PWR_TN# HUON- PWR_OO Part of TET0 TET/TM TET 0IN/EVENT0# KRT#/EVENT# PME#/EVENT# LP_MI#/EVENT# LP_P#/EVENT# Y_REET#/EVENT# WKE#/EVENT# IR_RX/EVENT0# THRMTRIP#/MLERT#/EVENT# W_PWR U PI / WKE UP EVENT U. U MI ULK/M_M_M_O U_ROMP U_FP/PIO U_FN U_F0P/PIO U_F0N U_HP U_HN U_HP U_HN U_HP U_HN U_H0P U_H0N M INPUT FOR U/.M,M,M OUTPUT EXT H H H H H0 0 K0 J F K K U_ROMP R U (0) U- (0) U (0) U- (0) U (0) U- (0) U0 (0) U0- (0).KR%00 ULK TP U.0 for V_ V V_ R.KR00 R R R R0.KR00.KR00.KR00.KR00 IO_RMRT# LK0 T0 LK T 0 POWER OMIN ROUTE TO IMMs,LK en,io POWER OMIN ROUTE TO LN,PIE,PI () () IO_RMRT# (0) (,0) (,0) () () PKR LK0 T0 LK T PI_HOL#_R LK0 T0 LK T PI_HOL#_R U E E F H F T R J V W Y V0 F RMRT# LK_REQ#/T_I0#/PIO LK_REQ#/T_I#/PIO MRTVOLT/T_I#/PIO0 LK_REQ0#/T_I#/PIO0 T_I#/FNOUT/PIO T_I#/FNIN/PIO PKR/PIO L0/PIO 0/PIO L/PIO /PIO LK_REQ#/FNIN/PIO LK_REQ#/FNOUT/PIO IR_LE#/LL#/PIO MRTVOLT/HUTOWN#/PIO R_RT#/EVENT#/V_P E_LE0/PIO PI_HOL#/E_LE/EVENT# E_LE/EVENT0# E_TT0/EVENT# LK_REQ#/PIO/OIN/ILEEXIT# PIO U.0 U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN E0 F0 0 0 H F E U () U- () U () U- () U () U- () U () U- () U () U- () U () U- () V_ R 0KR00 O# O# O# O# O# O# O# O#0 O# O# O# O# O# O# O# O#0 M R T P F P J T LINK/U_O#/EVENT# U_O#/IR_TX/EVENT# U_O#/IR_TX0/EVENT# U_O#/IR_RX0/EVENT# U_O#/_PRE/TO/EVENT# U_O#/TK/EVENT# U_O#/TI/EVENT# U_O0#/PI_TPM_#/TRT#/EVENT# U O U_HP U_HN U_H0P E U_H0N E U_LRP U_LRN U TXP U TXN U () U- () U0 () U0- () U_LRP U_LRN Leave unconnected. R KR%00 R KR%00 FH U_ U_TX (0) U_TX- (0) Z_ITLK Z_OUT Z_YN 0 0 X_0p0N00 X_0p0N00 X_0p0N00 () Z_ITLK () Z_OUT () Z_IN0 () Z_YN () Z_RT# R R Z_IN0 R R R00 R00 R00 R00 Z_ITLK_R Z_OUT_R Z_YN_R Z_RT_R Y Y Y E K J J Z_ITLK Z_OUT Z_IN0/PIO Z_IN/PIO Z_IN/PIO Z_IN/PIO0 Z_YN Z_RT# P_T//PIO P_LK/E/L/PIO PI_#/E_TT/PIO H UIO U.0 U RXP U RXN U TXP U TXN U RXP E U RXN F U TXP F U TXN U RXP H U RXN U_RX (0) U_RX- (0) U_TX (0) U_TX- (0) U_RX (0) U_RX- (0) U_TX (0) U_TX- (0) U_RX (0) U_RX- (0) K Not Implemented: Use for alternate available function or leave not connected. 0 PK_T/PIO PK_LK/PIO0 PM_T/PIO PM_LK/PIO U TX0P J U TX0N H U RX0P J U RX0N K U_TX0 (0) U_TX0- (0) U_RX0 (0) U_RX0- (0) FOR PIO[:0] K Not Implemented: Use for alternate available function or leave not connected. F E0 F0 E 0 J H K KO_0/PIO0 KO_/PIO0 KO_/PIO KO_/PIO KO_/PIO KO_/PIO KO_/PIO KO_/PIO KO_/PIO KO_/PIO KO_0/PIO KO_/PIO0 KO_/PIO KO_/PIO KO_/X0/PIO KO_/X/PIO KO_/X/PIO KO_/X/PIO EMEE TRL L/PIO H LK R 0KR00 /PIO T R 0KR00 L_LV/PIO LK R X_0R00 PU_I (,) _LV/PIO T R X_0R00 PU_I (,) E_PWM0/E_TIMER0/PIO E E_PWM/E_TIMER/PIO H E_PWM/E_TIMER/WOL_EN/PIO J FH_PIO () E_PWM/E_TIMER/PIO00 H KI_0/PIO0 K KI_/PIO0 K KI_/PIO0 F FOR PIO[0:] KI_/PIO0 F K Not Implemented: KI_/PIO0 E Use for alternate available function or leave not connected. KI_/PIO0 KI_/PIO0 KI_/PIO0 F LK T R R 0KR00 0KR00 MIRO-TRT INT'L O.,LT. HUON PI/U/Z/PIO ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

U T RX TX RX- TX- RX TX RX- TX- TP_WHITE-P-RH T T_TX0_ T_TX0-_ T_RX0-_ T_RX0_ T_TX_ T_TX-_ T_RX-_ T_RX_ T_TX0_ 0 0.0uX00 T_TX0-_ 0 0.0uX00 T_RX0-_ 0.0uX00 T_RX0_ 0 0.0uX00 T_TX_ 0 0.0uX00 T_TX-_ 0.0uX00 T_RX-_ 0.0uX00 T_RX_ 0 0.0uX00 T_TX_ 0.0uX00 T_TX-_ 0.0uX00 T_RX-_ 0 0.0uX00 T_RX_ 0 0.0uX00 T_TX_ 0 0.0uX00 T_TX-_ 0.0uX00 T_RX-_ 0.0uX00 T_RX_ 0.0uX00 T_TX_ 0.0uX00 T_TX-_ 0 0.0uX00 T_RX-_ 0.0uX00 T_RX_ 0.0uX00 T_TX0 T_TX0- T_RX0- T_RX0 T_TX T_TX- T_RX- T_RX T_TX T_TX- T_RX- T_RX T_TX T_TX- T_RX- T_RX T_TX T_TX- T_RX- T_RX K M L0 N0 N L H0 J0 J H M K H J N L L N J H T_TX0P T_TX0N T_RX0N T_RX0P T_TXP T_TXN T_RXN T_RXP T_TXP T_TXN T_RXN T_RXP T_TXP T_TXN T_RXN T_RXP T_TXP T_TXN T_RXN T_RXP HUON- Part of R E LN _LK/LK_/PIO _M/LO_/PIO _#/PIO _WP/PIO _T0/TI_/PIO _T/TO_/PIO _T/PIO _T/PIO0 E_OL E_R E_MK E_MIO E_RXLK E_RX E_RX E_RX E_RX0 E_RXTL/RXV E_RXERR E_TXLK E_TX E_TX E_TX E_TX0 E_TXTL/TXEN E_PHY_P E_PHY_RT# E_PHY_INTR L N J H K M H J W0 H F E F E W E_OL E_R E_MIO E_RXERR E_PHY_INTR E NOT ENLE V_ R 0KR00 E_MIO E_PHY_INTR E_OL E_R E_RXERR RN PR-0KR00 TP_WHITE-P-RH T RX TX RX- TX- RX TX RX- TX- TP_WHITE-P-RH T TP_WHITE-P-RH T_TX_ T_TX-_ T_RX-_ T_RX_ T_TX_ T_TX-_ T_RX-_ T_RX_ T_TX_ T_TX-_ T_RX-_ T_RX_ FH RUN (0) R R T_LE# 0.0uX00 0.0uX00 0.0uX00 0.0uX00 KR%00 KR%00 TP TP0 T_RX- T_RX T_TX T_TX- T_LRP T_LRN T_LE# FH_T_X FH_T_X N L K M L N L L H H J J F F F T_TXP T_TXN T_RXN T_RXP N N N N N0 N N N T_LRP T_LRN T_T#/PIO T_X T_X ERIL T V MINLINK V PI ROM PI_I/PIO PI_O/PIO PI_LK/PIO PI_#/PIO ROM_RT#/PI_WP#/PIO V_RE V_REEN V_LUE V_HYN/PO V_VYN/PO V /PO0 V L/PO V RET UX_V_H_P UX_V_H_N UXL ML_V_L0P ML_V_L0N ML_V_LP ML_V_LN ML_V_LP ML_V_LN ML_V_LP ML_V_LN V V V T V L0 L M M N0 M N K V V U T T T T R R0 P P PI_TIN PI_TOUT PI_LK PI_# PI_WP#_R R 0R%00 R0 0R%00 _RET UX_V_H_P_ UX_V_H_N_ UXL R R 0R%00 X_0R00 R R%00 R 00R%00 PI_WP# V_R () V_ () V_ () V_HYN () V_VYN () V_T () V_LK () FH RUN P0_TX0P () P0_TX0N () P0_TXP () P0_TXN () P0_TXP () P0_TXN () P0_TXP () P0_TXN () R R 00KR00 0.uX00 0.uX00 00KR00 V R.KR00 P0_UXP () P0_UXN () R.KR00 ML_V_HP/PIO ML_V_HP T RX TX RX- TX- RX TX RX- TX- TP_WHITE-P-RH T TP_WHITE-P-RH T_TX_ T_TX-_ T_RX-_ T_RX_ T_TX_ T_TX-_ T_RX-_ T_RX_ V HP () () V_R V_ FH_TLERT# IO_OVT# R R R V 0R00 X_0R00 R 0KR00 X_0KR00 PIO PIO PIO H M J K N L FH_TLERT#_R K K K M FNOUT0/PIO FNOUT/PIO FNOUT/PIO FNIN0/PIO FNIN/PIO FNIN/PIO TEMPIN0/PIO TEMPIN/PIO TEMPIN/PIO TEMPIN/TLERT#/PIO HW MONITOR PI ROM & EU HEER V_ VIN0/PIO VIN/PIO VIN/TI_/PIO VIN/TO_/PIO VIN/LO_/PIO VIN/LK_/PIO0 VIN/E_TT/PIO VIN/E_LE/PIO N N N N N N M L N P P M M H0 L PIO PIO PIO PIO PIO PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO0 PIO PIO RN 0K/PR RN 0K/PR RN 0K/PR V_ JPI PI_TIN PI_TOUT PI_# PI_LK PI_HOL# HX[]M-mm_lack V_ R 0KR00 PI_HOL# V_ R 0KR00 PI_WP# V_ R 0KR00 PI_# () P0_V_HP E R R Q0 N-T0_OT KR00 0KR00 ML_V_HP PI_# PI_TIN PI_WP# U # V O HOL# WP# LK IO MXLEMI-0 PI_HOL# PI_LK PI_TOUT 0u.X00 0.uX00 R0 X_0R00 PI_HOL#_R () MIRO-TRT INT'L O.,LT. HUON T/V/PI/HWM ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

VP :m :m V L V L0 V 0L00m-00-RH 0L00m-00-RH.u00 X_0.uX00.u00 PL_.V FH_PL ML FH_N R V u.x00 u/0x/ X_u/0X/ PL_.V FH_PL ML FH_N R FH_PL U U PL_.V_PIE PL_.V_T PLNE u/0x/ mils mils 0 m E 0 u/0x/ m H 0 m V m U 0 m T m L m m H m PL Y PL PL ML N PL U_ PL PIE PL T U HUON- Part of IO PIP_ IO PIP_ IO PIP_ IO PIP_ IO PIP_ IO PIP_ IO PIP_ IO PIP_ IO PIP_ IO PIP_0 PL U_ PI/PIO I/O LKEN I/O ORE 0 R T R T R T0 R U R U R V R V R V0 R Y N LK_ H N LK_ J N LK_ K N LK_ L N LK_ M N LK_ N N LK_ N N LK_ P onnected directly to the power plane with width = 00 mils with area fill under the FH. : m :0 m 0 m.u.x FH RUN R R X_.u.X X_u.X00 u.x00 0 u/0x/ u/0x/ u/0x/ FH RUN V N LK VP 0R00 0R00 R.KR00 FH RUN Q N-O00_OT-RH 0 L X_0L00m-00-RH u/0x/.vul :m :0m V_ m V m L V_ L Hudson- Only Hudson- to 0L00m-00-RH X_0.uX00.u00 0L00m-00-RH.u00 X_0.uX00.u00 FH_PL U U FH RUN 0L00m-00-RH L.u00 be M is not enalbed R R R X_.u00 PL N ML 0R00 0R00 0R00 m LO_P m m m m M V Y V V V 0 0 LO_P PL N ML_ N ML_ N ML_ N ML_ IO E_ R E R E IO_E IO_E MIN LINK E LN ERIL T PI EXPRE N PIE_ N PIE_ Y N PIE_ E N PIE_ N PIE_ N PIE_ N PIE_ F N PIE_ N T_ N T_ Y0 N T_ N T_ N T_ N T_ N T_ 0 N T_ N T_ 0 N T_0 0 m m u/0x/ u/0x/ u/0x/ 0 u/0x/ u/0x/ u/0x/ u/0x/ FH RUN u/0x/ u/0x/ V L V L 0L00m-00-RH 0L00m-00-RH PL_.V_PIE PL_.V_T.VUL.VUL Hudson- Only Hudson- to V_ FH U U _U.u00 0L-0.u00 R0 L 0R00 0L-0 0u.X00 L u/0x/ u/0x/ 0u.X00 X_0.uX00 u.x00 0.uX00 0mils u/0x/ 0mils X_.u.X X_0.uX00 0 m 0 m :00 m : m 0 0.uX00 0.uX00 u/0x/ 0.uX00 N U H N U J N U K N U K N U M N U M0 N U N N U N0 N U M N U 0 N N U M N U U N U U N U T R U T R U P N U M N U N N U P N U P N U N R U N R U P R U M R U POWER U U.V_ I/O IO N IO L IO M IO V IO V IO Y IO Y IO W XL R N0 R M0 PL Y_ J N HWM_ M IO_Z_ FH_IO m 0mils R 0 u/0x/ XL_.V m mils R_.V m 0mils PL_.V 0 m N_.V_HWM m IO_Z m 0mils R X_u/0X/ u/0x/ u/0x/ 0.uX00 X_u/0X/ 0R00 V_ 0R00 V_ XL_.V R_.V PL_.V L.u00 R X_u/0X/ 0.u00 L L0.u00 0L00m-00-RH 0R00 X_0L00m-00-RH 0L00m-00-RH V_.VUL FH RUN.VUL N_.V_HWM V_ R 0R00.u00 HWM not Implement, ead not used MIRO-TRT INT'L O.,LT. HUON POWER&EOUPLIN ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

FH REQUIRE TRP RTLK PI_LK PI_LK PI_LK LP_LK0 LP_LK U V_ V V V V_ V_ HUON- E E E E F F F F F F F F F F H H H J J J0 J J J K K K K L L L L L L M M M M N N N N N P P P0 P P P R R R R T T T N N_HWM K XL H PL_Y Part of ROUN T T U U U U0 U U0 U V V V W W W W Y Y Y 0 E E E E F F F F 0 H H H H H H H H J J J K K L M M N N N N PL_ T N_ L NQ_ K IO_ N EFUE R PULL HIH PULL OWN (,) () () RT_LK () PI_LK () PI_LK () PI_LK () LP_LK0 LPLK_TPM FH_PIO PULL HIH PULL LOW RTLK Plus MOE ILE EFULT Plus MOE ENLE PI_LK EFULT FORE PIe at en FH EU TRP PI_ Use internal PLL clock EFULT ypass Internal PLL clock PI_ R 0KR00 PIe interface at en R R R R R R 0KR00 PI_LK Enable ebug traps EFULT PI_LK EFULT (,) (,) (,) (,) (,) LP_LK0 E ENLE isable PU_LK/IP_LK E ILE ebug traps Required setting X_.KR00 X_.KR00 X_.KR00 X_.KR00 X_.KR00 PI_ R X_0KR00 R 0KR00 Reserved R X_0KR00 R0 0KR00 *This strap i s not used in External clock mode PI_ isable I ROM EFULT Enable loading settings for UMI/PLL/misc from I ROM R X_0KR00 R 0KR00 EFULT R 0KR00 R.KR00 LP_LK Internal clock mode EFULT External clock mode PI_ Use ROMTYPE straps EFULT PIO oot from PI bus PIO (ROMTYPE) LP ROM PI ROM EFULT (ROMTYPE) Layout: PL_Y;N_HWM ONNET TO WITH EPRETE VI MIRO-TRT INT'L O.,LT. HUON TRP ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

[..0] (,) _E#[..0] () PI LOT (PI VER:. OMPLY) () () () () () () () () () PI_INTF# PI_INTH# PILK_LOT PREQ0# IRY# EVEL# LOK# PERR# ERR# V _E# _E# IRY# EVEL# LOK# PERR# ERR# _E# 0 PI_K# V -V V PI -V TRT# TK V TM TO TI V V V INT# INT# INT# INT# V PRNT# REERVE 0 0 REERVE#0 V(I/O) PRNT# REERVE# REERVE#.VUX RT# LK V(I/O)# NT# REQ# V(I/O)# PME# 0 0 0.V.V /E# IEL. 0 0 0.V /E#.V FRME# IRY#.V TRY# EVEL# TOP# LOK#.V 0 PERR# MLK 0.V MT ERR#.V PR /E#.V 0 X X X X 0.V V(I/O)# K# V V /E#0.V 0 V(I/O)# 0 REQ# V V LOT-0pin,IP,.mm,WHITE IEL = MTER = PI_REQ#0 PI_NT#0 V PI_PME# 0 I 0 FRME# TRY# TOP# PR _E#0 0 PI_REQ# V V_ PIRT_LOT# () PNT0# () R 00R00 PI_INTE# () PI_INT# () PI_PME# () FRME# () TRY# () TOP# () PR () V PI_K# R PI_REQ# R0.K/.K/ V V V_ V V V X_0.uX00 X_0.uX00 X_0.uX00 X_0.uX00 0 X_0.uX00 X_0.uX00 E 0u.O E 0u.O X_0.uX00 X_0.uX00 MIRO-TRT INT'L O.,LT. PI/PIE X LOTs ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

PI EXPRE x lot () PRNT V.Vaux.Vaux PRNT_R R X_0R00 (wake) (no wake) () () (,) LK T PE_WKE# V_ LK T V PE_WKE# () () () () () () () () () () () () () () () () () () () () () () () () () () () () () () FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TX0P FX_TX0N FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TX0P FX_TX0N PI Express X slot(x) -. - m - 0m.V -.0 0 0 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 FX_TXP_ FX_TXN_ FX_TXP_ FX_TXN_ FX_TXP_ FX_TXN_ FX_TXP_ FX_TXN_ FX_TX0P_ FX_TX0N_ FX_TXP_ FX_TXN_ FX_TXP_ FX_TXN_ FX_TXP_ FX_TXN_ FX_TXP_ FX_TXN_ FX_TXP_ FX_TXN_ FX_TXP_ FX_TXN_ FX_TXP_ FX_TXN_ FX_TXP_ FX_TXN_ FX_TXP_ FX_TXN_ FX_TX0P_ FX_TX0N_ V ME 0 0 0 0 0 0 0 0 ME PI_E ME V V RV MLK MT.V JT.VUX WKE# HOP HON HOP HON HOP HON RV PRNT# HOP HON HOP HON HOP HON HOP HON PRNT# HOP HON HOP HON HOP0 HON0 HOP HON HOP HON HOP HON HOP HON HOP HON PRNT# RV ME LOT-PIP_LUE-PITH-RH- V PRNT# V V JT JT JT JT.V.V 0 PWR E 0uV RV HIP HIN HIP HIN HIP HIN RV RV HIP HIN HIP HIN HIP HIN HIP HIN RV HIP HIN HIP HIN HIP0 HIN0 HIP HIN HIP HIN HIP HIN HIP HIN HIP HIN 0 0 0 0 0 0 0 V V FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_R0P FX_RX0N FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RX0P FX_RX0N X_0.uX00 R0 V FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RX0P () FX_RX0N () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RXP () FX_RXN () FX_RX0P () FX_RX0N () V PIE_RT# (,) X_0.uX00 V_ PE_WKE# LK T PE_WKE# LK T V_ V_ PE_WKE# (,) () () (,) () () () () () () LK T PE_PP_TXP PE_PP_TXN LK T PE_WKE# PE_PP_TXP PE_PP_TXN X_0.uX00 V V V PI_E V V PI_E V PI EXPRE X lot- 0 0 V V# RV MLK MT #.V JT.VUX WKE_# PRNT_# V# V# # JT JT JT JT.V#.V#0 PWR X LOT-PI_LK-PITH-RH- V V# RV MLK MT #.V JT.VUX WKE_# PRNT_# V# V# # JT JT JT JT.V#.V#0 PWR X RV# # HOP0 HOP0- # PRNT_# # # REFLK REFLK- # HIP0 HIP0- # X RV PE_XF_LK0 PE_XF_LK0 () 00 0.u0X00 FX_TXP_ REFLK PE_XF_LK0# () FX_TXP PE_XF_LK0# () 0 0.u0X00 FX_TXN_ HOP0 REFLK- () FX_TXN HON0 FX_RXP HIP0 FX_RXP () FX_RXN PRNT# HIN0 FX_RXN () RV# # HOP0 HOP0- # PRNT_# # # REFLK REFLK- # HIP0 HIP0- # X LOT-PI_LK-PITH-RH- 0 X X 0 X X V V V.Vaux.Vaux PIE_RT# (,) PE_PP_LK () PE_PP_LK# () PP_RXP () PP_RXN () PIE_RT# (,) PE_PP_LK () PE_PP_LK# () PP_RXP () PP_RXN () PI Express X slot (X).V -.0 PI EXPRE X (wake) (no wake) - - 0m - 0m MIRO-TRT INT'L O.,LT. ize ocument Number Rev ustom M-.0 Friday, July, 0 ate: heet of

POWER IRUIT FOR U PORT 0, V_RU V_RU () U- () U () U- () U U- U U- U L X_M-L-0-LF U- U- U U- U U U U- E-IP0 U- U U- U LN_U PWR U- U UP PWR U- U OWN 0 NER U RER ONNETOR RJ_UX_LEX_TX-I-RH- V_RU V_RU () U- () U () U- () U U- U U- U L X_M-L-0-LF U U U- E-IP0 U- V_RU U- U U- U V_RU U UP 0 OWN UXM_LK-RH- U- U V_RU X_0.u0X00 U- U E 0u.O EL E 0u.O EL Near Rear ==> JU_PW V TX_V U_RPW F V_RU F-MP0LR-RH N-00N-000-RH Near Front ==> JU_PW V TX_V U_FPW F V_FU F-MP0LR-RH N-00N-000-RH V_FU V_FU () U0 () U0- () U () U- U0 U0- U U- L U U0 U0- U U- U- U0- U0 U0 U0- E-IP0 JU V U0- U0 V U- U UO 0 U- U NER U Front ONNETOR X_M-L-0-LF HX[]M_LK-RH- V_FU V_FU V_FU V_FU E 0u.O EL E 0u.O EL () U- () U () U- () U U- U U- U L U U- U- E-IP0 U U- U U- U JU V U0- U0 V U- U UO 0 U- U U- U X_M-L-0-LF HX[]M_LK-RH- MIRO-TRT INT'L O.,LT. U.0 POWER/ONNETOR ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

() U_TX- () U_TX 0 0.u0X00 0.u0X00 TX- TX V_RU V_RU () U_RX- () U_RX U_RX- U_RX U U- U U- E-IP0 U- U U_RX U_RX- TX TX- U TX VU TX- - RX _ RX- 0 UXM_LUE-RH- () U_TX- () U_TX () U- () U () U- () U 0.u0X00 0.u0X00 L X_M-L-0-LF U- U U- U TX- TX U N 0 U_RX- N U_RX TX- N N TX U_RX- U_RX TX- TX U_RX- U_RX TX- TX U N 0 U_RX- N U_RX TX- N N TX E-PY0000-0-RH E-PY0000-0-RH V_RU TX TX- U- U U_RX U_RX- U TX 0 VU TX- - RX _ RX- NER U RER ONNETOR V_RU E0 0u.O EL () U_RX- () U_RX U_RX- U_RX UXM_LUE-RH- V_FU U JU () U () U- () U0 () U0- L U U- U0 U0- U U- 0 U0 U0- U- TX TX- U_RX - TX TX- RX X_M-L-0-LF E-IP0 V_FU U_RX- RX- VU NER U Front ONNETOR V_FU () U_TX- () U_TX 0.u0X00 0.u0X00 TX- TX U_RX- U_RX TX- TX U N 0 U_RX- N U_RX TX- N N TX E-PY0000-0-RH U0 U0- TX0 - TX E 0u.O EL () U_RX- U_RX- TX0- TX- () U_RX U_RX U_RX0 RX () U_TX0- () U_TX0 0.u0X00 0.u0X00 TX0- TX0 U_RX0- U_RX0 TX0- TX0 U0 N 0 U_RX0- N U_RX0 TX0- N N TX0 E-PY0000-0-RH V_FU U_RX0-0 RX- VU N ME ME X0_ONNETOR ME ME HX0[0]#-PITH_LK-RH () U_RX0- () U_RX0 U_RX0- U_RX0 MIRO-TRT INT'L O.,LT. U.0 POWER/ONNETOR ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of 0

VI ONNETOR 0.uX00 VI_TX-_R () P_TX0N 0.uX00 VI_TX_R () P_TX0P VI_L VI_ 0 0.uX00 VI_TX-_R () P_TXN 0.uX00 VI_TX_R () P_TXP VI_PWR_V VI_HOT_ET 0.uX00 VI_TX0-_R () P_TXN 0.uX00 VI_TX0_R () P_TXP 0.uX00 VI_TX_R () P_TXP 0.uX00 VI_TX-_R () P_TXN V_VI hell T T HIEL T T LK T N T 0 T HIEL T T V HPET T0 T0 HIEL0 0 T T HIELLK LK LK VI_TX- VI_TX VI_TX VI_TX- VI_TX0- VI_TX0 VI_TX R X_0R00 R X_0R00 R X_0R00 VI_TX- VI_TX VI_TX VI_TX- VI_TX0- VI_TX0 L VI_TX-_R VI_TX_R X_M-L-0000-RH L VI_TX_R VI_TX-_R X_M-L-0000-RH L VI_TX0-_R VI_TX0_R X_M-L-0000-RH L V ONNETOR () V_R () V_ () V_ R 0R%00 R 0R%00 R 0R%00 LOE TO V onnector L n00m.pn00 L n00m.pn00 L n00m.pn00 0.pN00.pN00.pN00 V hell V_VI-RH- VI_TX- R X_0R00 VI_TX VI_TX- VI_TX_R VI_TX-_R X_M-L-0000-RH VI_PWR_V VI_PWR_V () P_VI_HP Q N-T0_OT VI_HP R E R 0KR00 KR00 R 0R%00 VI_TX- R 0R%00 VI_TX VI_HOT_ET 0.uX00 R00 00KR00 VI_TX- VI_TX VI_TX0 VI_TX0- V V U R0.KR00 VI_V Q N-NN_OT N 0 VI_TX- N VI_TX VI_TX0 N N VI_TX0- F F-MIROM0 VI_PWR_V VI_PWR_V () V_LK () V_T R.KR00 R.KR00 () V_VYN () V_HYN R R R R 0.u0X00 R00 LK R00 VYN R00 HYN R00 T 0 p0n00 V_VI V_VI-RH- 0 LUE REEN RE R 0R%00 R 0R%00 VI_TX- VI_TX VI_PWR_V VI_PWR_V R 0R%00 R 0R%00 R 0R%00 R0 0R%00 Q N-N00_OT VI_TX0- VI_TX0 VI_TX VI_TX- VI_TX- VI_TX VI_TX- VI_TX VI_TX- VI_TX VI_TX- VI_TX U 0u.X00 0.uX00 p0n00 X_p0N X_p0N X_E-PY0000-0-RH V 0 0.uX00 N 0 N N N VI_L VI_ VI_HOT_ET X_E-IP0 LK VYN T HYN E-IP0 V_ V_ V_R E-IP0 X_E-PY0000-0-RH For EMI V_R LEVEL HIFT using MO(Fairchild ) V()=0.V~.V V VI_PWR_V V R X_.KR00 R X_.KR00 Fine-tune ate voltage at.0v R X_.KR%00 0.uX00 () () P_UXN P_UXP V P_UXN P_UXP R 0K/ V_R V 0.uX00 0.uX00 U P_UXN V V VI P_UXP VI_L_ EN P0P_TOP-RH 0.uX00 P_UXP VI_L_ Q X OT X_-RV-0_O-RH R.KR00 R0 X_0.uX00 VI_L_ VI X_KR%00 P_UXN VI Q X OT X_0.uY00 X_-RV-0_O-RH R.KR00 R 0R00 R 0R00 X_0.uY00 VI_L VI_ MIRO-TRT INT'L O.,LT. VI & V ONN. ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

RTLE/0E V R KR00 R K% LN_IO () PE_LN_TXP () PE_LN_TXN PE_LN_TXP PE_LN_TXN U HIP HIN PIE interface HOP HON LN_RXP LN_RXN 0.uX00 0.uX00 PE_LN_RXP () PE_LN_RXN () () PE_LN_LK () PE_LN_LK# PE_LN_LK PE_LN_LK# 0 REFLK_P REFLK_N PERT LKREQ LN_RT# R PIE_RT# (,) 0 width>0mil 0.uX00 0 ENWRE: : Enable switching regulator 0: isable switching requlator REOUT 0 0u.X00 H-.u0.0m-HF XR L0-0-T0 VL: L0-0-T0 near pin <00mil HOKE.u.X (,) width>0mil near pin <00mil PE_WKE# 0.uX00 u.x R 0 E0 LN_IO PE_WKE#.K% R 0R00 RET REOUT 0.uX00 IOLTE PM LNWKE RET ENWRE Regulator RE RE REOUT POWER (N) 0 0 0(N) 0 0 0(N) V0(N) E0 Pad Transceiver Interface EEPROM LOK MIP0 MIN0 MIP MIN MIP(N) MIN(N) MIP(N) MIN(N) KXTL KXTL RTLE-V-R 0 0 LE0 LE/EEK 0 EE/L EEI/ LE/EEO MLK(N) MT(N) PO TR_ TR_- TR_0 TR_0- TR_ TR_- TR_ TR_- LE0_LINK00# LN_EEK LN_EE LN_EEI LN_EEO R LN_M_ LK_LNI LK_LNO KR00 R 0K/ R 0K/ R0 0K/ Y MHZP_- PO: : Link up 0: Link down p0n p0n E: stuff 0E: unstuff Pin: via from top layer to layer and make the via at the center of I..v Power on rise time : ~00ms. Place near pin 0m V_ P X_OPPER P X_OPPER 0 0u.X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 00m Place near pin 0 0 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 0.u0X00 E: unstuff 0E: stuff TT 0.uX00 /RT R 0R00 LN_EEO LN_EEK E: 00R 0E: 0R R 00R/ E: unstuff 0E: 0R R X_0R/ R 00R/ E: 00R 0E: unstuff LN onnector For EMI 0.uX00 LN_U LE_T 0 TT 0 TR_0 PWR TR_0- T TR_ T- TR_- T TR_ T- TR_- T 0 TR_ T- TR_- T /RT T- LE_LINK000# LE0_LINK00# RJ_UX_LEX_TX-I-RH- pf 0-000- 0-000- 0 iga-lan N-F0 Link Yellow ctive linking 000 Orange 00 reen 0 None 0R Yellow pf 0-000-P0 0-000-N 0/00-Lan N-F0 Link Yellow ctive linking 00 reen 0 None 0 Yellow E: 0R 0E: 0.0uF only support LE0LE/LELE dual color LE combinations when using EEPROM 0R reen Orange reen 0E POWER onsumption E POWER onsumption.v mw.v mw 0 M Idle/TxRx / / 0 M Idle/TxRx / 0/ 00 M Idle/TxRx 0 LP /. / 00 M Idle/TxRx iga Idle/TxRx / / 0/ / LP LE_T LE0_LINK00# LE_LINK000# 000p0X00 000p0X00 000p0X00 MIRO-TRT INT'L O.,LT. LN-RTLE/0E. ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

L-V L () Z_OUT () Z_IN0 () Z_YN () Z_RT# () Z_ITLK 需用 XR X_0.uY.m 0 0u.X00 LO 0u.X00 R R/ X_0p losed odec PIFO REREF R0 0K% 0u.X00 IN0 ENE_ ENE_ MI_V_R MI_VREFO MI_V_L LINE_VREFO VREF_UIO JREF m losed odec 0 0 0 U 0 0.uX00 PIFI/EP PIFO T-OUT T-IN YN REET# LK V PIO0/MI_LK/PIFO REREF ense ense MI-VREFO-R MI-VREFO MI-VREFO-L PIN-VREFO LO-IN LINE-VREFO VREF ense JREF PEEP -IO PIO/MI-T LO-OUT LO-OUT losed odec 0.uX00 FRONT-R FRONT-L URR-R URR-L ENTER LFE IE-R IE-L LINE-R LINE-L LINE-R LINE-L MI-R MI-L MI-R MI-L -R 0 - -L L-R-RH 需用 XR 用 M P 手動量測會 FIL 在 THN 0u.X00 用 EL-P or OLI cap, 才會 pass u.x00 close to PIN E E E E 0 0 0 0 0 0 0u.X00 0u.X00 0u.X00 0u.X00 0u.X00 0u.X00.u.X.u.X.u.X.u.X.u.X.u.X 00uO 00uO 00uO 00uO LOUT_R LOUT_L ROUT_R ROUT_L EN_OUT URRK_R URRK_L LINE_IN_R LINE_IN_L LINE_R LINE_L MI_R MI_L MI_R MI_L 需用 XR LOUT_L LOUT_R E protect 0 0-000-I0 0-000-I0 ost own E-FI00 0-000-I0 LINE_IN_L LINE_IN_R MI_V_L MI_V_R MI_L MI_R R R for rear I/O port: V/:k for rear I/O port: V/:R R R/ R R/ R0 R.K/.K/ R R MI_L MI_R KR00 KR00 00p0N LOUT_L FRONT_J LOUT_R E-FI00 LINE_IN_L LINE_J LINE_IN_R MI_L MI_J MI_R 00p0N.k 變為.k, 麥克風錄音效果變好 KR00 KR00 00 00p0N 0 00p0N LIN_OUT UIOE MI UIOF reen JK-UIOX-P LIN_IN UIO L JK-UIOX-P lue Pink JK-UIOX-P ROUT_L ROUT_R EN_OUT URRK_L URRK_R LIN_IN R R/ R R/ 00p0N R R/ R R/ 0 00p0N R R/ R R/ 00p0N 00p0N LIN_IN ROUT_L URR_J ROUT_R EN_OUT EN_J 0 00p0N URRK_L URRK_J URRK_R 00p0N URR UIO R JK-UIOX-P EN/ UIO IEURR UIO lack Orang JK-UIOX-P ray JK-UIOX-P URR ME ME E LIN_OUT E LIN_OUT EN/ LOUT_L LOUT_R R K/ R K/ F MI F MI IEURR 當串接電容有極性時, 需上對地電阻 N-F0-K0 N-F0-K0 LINE_VREFO Z -T_OT Y X EMI X_0.uY P X_OPPER ENE_ losed odec ENE_ PIF OUT R R 0K% R R R.K% R 0K%.K% R 0K%.K% X_R/ FRONT_J LINE_J MI_J URR_J EN_J URRK_J FR-IO-EN TX_V PIFO X_TV L R 0R00 0L00m/ 0.u0X00 0u.X00 0.uX00 LO 需用 XR V JP MI_VREFO -T_OT LINE_L LINE_R MI_L MI_R F_MI_L F_MI_R F_LINE_R FR-IO-EN F_LINE_L E protect 0-000-I0 0-000-I0 ost own 0-000-I0 F_LINE_L F_LINE_R F_MI_L F_MI_R 00p0N HX_LK-RH PR-R/ Z RN Y X RN PR-.K/ E-FI00 E-FI00 E-FI00 F_LINE_L F_LINE_R R0 R/ E-FI00 R K/ R K/ 000pX X_000pX P X_OPPER N-0-H0 JU MI MIPWR PREENE# FLINE OUTR LINE NEXT R HPON 0 FLINE OUTL LINE NEXT L HX[]M_LK-RH MI_J LINE_J R R 0K%.K% lose to Front panel For H/ front cable. MIRO-TRT INT'L O.,LT. L ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of

() _RT# () LP_RQ#0 () ERIRQ () LP_FRME# () PILK0_IO () IO_M_LK (,) PU_I (,) PU_I (0) WTRT# () LP_MI# () IO_OVT# () LP_PME# () () () () PU_FN PU_FN_TL () Y_FN Y_FN_TL () Y_FN Y_FN_TL LP_MI# IO_OVT# () () YV_OFF () () R_OV R_OV _RT# LP_RQ#0 PILK0_IO IO_M_LK LP_[..0] R R R TP TP TP 0R00 0R00 0R00 IO_I IO_I WTRT# Y_TMP Y_TMP LP_0 LP_ LP_ LP_ VP_IO VIN_IO VIN_IO R_IO VORE_IO IO_WKE# YV_OFF R_OV R_OV HM_VREF TRP_TIMIN ULTE _TE# VTE 0 0 0 U LREET# ENEL#/PIO0 LRQ# MO#/PIO ERIRQ RV#/PIO 0 LFRM# WT#/PIO PILK IR#/PIO LKIN TEP#/PIO L0 HEL#/PIO L WTE#/PIO L RT#/PIO0 L TRK0#/PIO INEX#/PIO WPT#/PIO IR_LE#/L KH#/PIO PEI/ 00 WTRT#/PIO LT/PIO0 0 OVT# PE/PIO 0 PME# UY/PIO 0 K#/PIO 0 VIN LIN# 0 VIN INIT#/PIO 0 VIN(VIMM) ERR#/PIO 0 VIN() F#/PIO 0 VIN(VLT) T#/PIO 0 VIN(Vcore) P0/PIO0 0 P/PIO FNIN P/PIO FNTL P/PIO FNIN P/PIO FNTL P/PIO FNIN/PIO0 P/PIO FNTL/PIO P/PIO (PU) # VREF RI# 0 T# TR#/FN0_00 EVENT_IN0# RT#/TRP_PROTET ERP_TRL0# R# ERP_TRL# OUT/TRPE_E IN U_WRN#/TIMIN_ #/E/PIO0 U_K#/TIMIN_ RI#/EF/PIO PWROK/TIMIN_ T#/E/PIO LP_U#/TIMIN_ IN/EE/PIO IRW#/PIO0 OUT/E/PIO/TRP_PORT IRTX/#PIO0 R#/L#/PIO IRRX#/PIO0 RT#/E/PIO TRP_TIMIN TR#/E/PIO (P)_ate#/LOTO#/PIO0 IRTX/PIO ()_ate#/pio0/wtrt# IRRX/PIO (0P)_ate#/PIO/EEP LP Interface Hardware Monitor Power aving URT, IR and 0-Port F Parallel Port LT PE UY K# _LIN# INIT# ERR# F# T# _P0 _P _P _P _P _P _P _P # RI# T# TR# RT# R# OUT# IN# # RI# T# IN# OUT R# PRNT PIO PIO PIO PU_FN_TYPE R # () RI# () T# () TR# () RT# () R# () OUT () IN () 0K/% V PRNT () LT () PE () UY () K# () _LIN# () INIT# () ERR# () F# () T# () _P0 () _P () _P () _P () _P () _P () _P () _P () PU_FN_TYPE () V OPT OM R X_.KR00 PIO R.KR00 R X_.KR00 PIO R.KR00 R X_.KR00 PIO R.KR00 00p0N V VIN_IO R0 00K/% R K/% VP VORE_IO R 0KR%00 0u.X00 V_R R_IO R 0KR%00 00p0N VP VP_IO R 0KR%00 0 00p0N V # R X_.KR00 RI# T# IN# R# RN X_PR-.KR00 V # R.KR00 IN# R# T# RI# RN PR-.KR00 R0 V KRT# 0TE WTRT# IO_PWROK 00KR%00 R0 0KR%00 V R 0KR%00 R 0KR%00 R X_0KR%00 R0.KR00 VIN_IO 0 00p0N (0) (0) LE_V LE_V (,0) TX_PWROK (0) IO_PWROK (0) PIN# () PWRTN# (,,0) LP_# (,,) LP_# (0) TX_PON# () IO_RMRT# TPMRT# LE_V LE_V R TX_PWROK IO_PWROK IO_RMRT# HI R00 0 0 PIO/LE_V/LERT# PIO/LE_V PIO/PU_PW PIRT# PIRT# PIRT# PI_RT#/L/PIO0 PI_RT#//PIO RTON#/PIO TXP_IN/PIO PWOK PIN#/PIO POUT#/PIO # # P_ON#/PIO RMRT# OPEN# F PI Function K Function Power Pin F 0 KRT# 0 KT KLK 0 MT MLK V(V) I_VV VT V V V 0 (-) HM KRT# 0TE KT KLK MT MLK P 0.u0X00 X_OPPER KRT# () 0TE () KT () KLK () MT () MLK () 0.u0X00 0.u0X00 0.u0X00 MT MLK I_VV VT V_ V R R 0.u0X00 KR00 TX_V KR00 R 0R00 TX_V 0.uX00 X_-T_OT Y Z V_ X u/0x hasiss Intrusion VT R0 M/ JI N-000-0 HI HXM_LK-RH (,) LPLK_TPM TPM TPMRT# LP_0 LP_ LP_ LP_ LP_FRME# V_ V JTPM ERIRQ V HX[0]M-mm_lack TX_V F TRPPIN REITOR YV_OFF IO_WKE# RN.K/PR 0 TRP_TIMIN TR# M FN start duty is 0% Intel FN start duty is 00% V R R.KR00.KR00 PU_FN_TL Y_FN_TL OUT E E FNTL FNTL PWM mode mode mode mode R R R R R0 KR00 X_KR00 X_KR00 X_KR00 X_KR00 TRP_TIMIN TR# OUT OUT RT# HM_VREF TEMP ENOR FNTL OUT RT# mode 0Port decode output from OM isable UVP protection mode 0Port disable Enable UVP protection R 0K/% MMT0_OT Y_TMP Q NER IO NER MO RT 00p0X 0KRT% HM E Y_TMP 00p0X00 HM MIRO-TRT INT'L O.,LT. UPER I/O F ize ocument Number Rev ustom M-.0 ate: Friday, July, 0 heet of