Lab7:7 段顯示器控制電路 [ 實驗說明 ] : 這一個範例將分成兩階段 首先使用 ISE12.4 先進行叫用 Seven_Segmenet.vhd 模組建立 4bit HEX 轉換 7 段顯示器控制電路練習 接著再使用 Lab1 所設計的 2:4 解碼器與 Lab4 四位元加法器電路利用 Schematic 階層式設計快速建立加法器和輸出到 7 段顯示器的控制電路 你將開啟一個 Seven_Segmenet_Adder.sch 模組 ( 叫用 Seven_Segmenet.vhd decoder2to4.sch and Adder4bits.sch) 設計一個 HEX-to-seven-segment decoder 並將 Adder4bits 資料透過 decoder 顯示到七節燈管上 開啟此專案所需的 Test Bench(.tbw) 檔案, 並且利用 ISE12.4 的軟體完成整個設計流程, 同時利用 ISE12.4 的模擬功能來驗證結果的正確性! 此設計同時利用 Seven_Segment_Adder.ucf 來設定 I/O 腳的位置, 利用 Digilent Adept 軟體來燒錄到 FPGA 模擬板中, 驗證其設計結果是否正確 [ 實驗目地 ] : 當你完成整個專案之後, 你將學會以下的功能 (1). 利用 ISE12.4 的軟體開啟一個 Spartan3E FPGA 的專案. (2) 利用 Schematic 快速建立 7 段顯示器控制模組電路 (3). 使用電路元件來進行階層式模組化設計 (4). 產生測試型樣 Test Bench(.tbw) 來模擬你的設計. (5). 加入系統所需的 Constraints 檔案.(UCF file) (6). 完成整個設計流程. 並產生 Seven_Segmenet_Adder.bit 檔案 (7). 利用 FPGA Editor 來察看 FPGA 內部的結果, (8). 利用 Digilent Adept 來燒錄 Seven_Segmenet_Adder.bit 檔案到 FPGA [ 系統設計說明 ] --HEX-to-seven-segment decoder -- HEX: in, (HEX3 HEX2 HEX1 HEX0) -- Segment_out: out (CA CB CG); -- Enable: AN0 AN1 AN2 AN3(SWEEP) Binary(B3B2B1B0) 7Seg Display(Seg1) 共陽極 Seg1 need CA CB CC CD CE CF CG
B3B2B1B0 CA CB CC CD CE CF CG 0000 0 0 0 0 0 0 1 0001 1 0 0 1 1 1 1 0010 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 1 1 0 0100 1 0 0 1 1 0 0 0101 0 1 0 0 1 0 0 0 1 1 0 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 1 0 1 1000 0 0 0 0 0 0 0 1001 0 0 0 0 1 0 0 1010 0 0 0 1 0 0 0 1 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 1 1 0 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 1 1 1 0 0 0 CA=IN1+IN4+IN11+IN13 CB=IN5+IN6+IN11+IN12+IN14+IN15 CC=IN2+IN12+IN14+IN15 CD= IN1+IN4+IN7+IN10+IN15 CE= IN1+IN3+IN4+IN5+IN7+IN9 CF= IN1+IN2+IN3+IN7+IN13 CG= IN0+IN1+IN7+IN12 IN1=0001, IN2=0010 以上使用 Schematic 非常複雜 S1 S0 AN0 AN1 AN2 AN3 7Seg 0 0 0 1 1 1 1 0 1 1 0 1 1 2 1 0 1 1 0 1 3 1 1 1 1 1 0 4 AN0=S1+S0=(S1 S0 ), AN1=S1+S0, AN2=S1 +S0, AN3=S1 +S0 =>Lab1:decoder2to4 (enable: E=0)
使用階層式設計叫用 Seven_Ssegment.vhd 模組, 可減少設計複雜度 [Seven_Segmenet.vhd] library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. entity Seven_Ssegment is Port ( HEX : in std_logic_vector(3 downto 0); Segment_out : out STD_LOGIC_VECTOR (6 downto 0) ); end Seven_Ssegment; architecture Behavioral of Seven_Ssegment is begin with HEX SELect Segment_out<= "1111001" when "0001", --1 "0100100" when "0010", --2 "0110000" when "0011", --3 "0011001" when "0100", --4 "0010010" when "0101", --5 "0000010" when "0110", --6 "1111000" when "0111", --7 "0000000" when "1000", --8 "0010000" when "1001", --9 "0001000" when "1010", --A "0000011" when "1011", --b "1000110" when "1100", --C "0100001" when "1101", --d "0000110" when "1110", --E "0001110" when "1111", --F "1000000" when others; --0 end Behavioral;
[ 操作步驟 ]: (1) 開啟 ISE12.4 軟體, 開啟一個新專案 : [File] [New Project]->Lab7 (C:\Xilinx\projectB\Lab7) (1) -2. 設定硬體元件的參數 [ 元件系列 (Device Family)]:Spartan3E ( 請參考 Basys2_rm.pdf) [ 元件名稱 (Device)] : Spartan3E-100E ( 請參考 Basys2_rm.pdf) [ 元件包裝 (Package)]:CP 132( 請參考 Basys2_rm.pdf) [ 元件速度等級 (Speed)]: -5 ( FPGA 速度等級 ) [ 合成器工具 (Synthesis Tool)]:XST VHDL(VHDL 合成器的種類 ) [ 模擬器 (Simulator)] : ISE Simulator(ISE12.4 內建的模擬器 ) [ 產生模擬器的語言 (Generated Simulation Language)] : VHDL
(1)-3. 出現專案所有設定訊息, 若需重新設定, 則可 [back]( 上一步 ) 若無誤, 則按 [Finish]( 完成 ) (2)Design Entry: 加入新設計檔案 : [Project] [New Source]-> Schematic ->File name: Seven_Segment_Test [Save] Seven_Segment_Test.sch 加入 Seven_Ssegment VHDL Source: [Project] [Add Copy of Source]-> Seven_Segment.vhd (From 網路大學 copy to 桌面 Seven_Ssegment_vhd.txt Seven_Ssegment.vhd)
(3)Synthesis & Implement Design: [Process]->(double click) Implement Design<Two green Check>
(4)Simulation( 模擬 ) with Testbench Testbench :[Project] [New Source] [VHDL Test Bench] Filename= Seven_Segment_Test_tb [Select Source] Seven_Segment_Test
PROCESS BEGIN HEX(0)<='0'; WAIT for 50ns; HEX(0)<='1'; WAIT for 50ns; END PROCESS; PROCESS BEGIN HEX(1)<='0'; WAIT for 100ns; HEX(1)<='1'; WAIT for 100ns; END PROCESS; PROCESS BEGIN HEX(2)<='0'; WAIT for 200ns; HEX(2)<='1'; WAIT for 200ns; END PROCESS; PROCESS BEGIN HEX(3)<='0'; WAIT for 400ns; HEX(3)<='1'; WAIT for 400ns; END PROCESS; (4)-2. Simulation: [Design]->view: Simulation [ISim Simulator] (double click) [Behavioral Check Syntax]-> (double click) [Simulate Behavioral Model]->Zoom to Full View->Check is O.K.? 0 1 2 6 8
(5) 設定 I/O 腳位置, 利用 Seven_Segment.UCF 來設定 I/O 腳的位置, 以得到正確輸出檔案. [Project] [New Source]-> [Implementation Constraints File] ->File Name: Seven_Segment_Test (.ucf) -> Edit ->[Save] -> Generate Programming File NET "HEX<3>" LOC = "B4"; # Bank = 3, Signal name = SW3 NET "HEX<2>" LOC = "K3"; # Bank = 3, Signal name = SW2 NET "HEX<1>" LOC = "L3"; # Bank = 3, Signal name = SW1 NET "HEX<0>" LOC = "P11"; # Bank = 2, Signal name = SW0 NET "Segment_out<0>" LOC = "L14"; # Bank = 1, Signal name = CA NET "Segment_out<1>" LOC = "H12"; # Bank = 1, Signal name = CB NET "Segment_out<2>" LOC = "N14"; # Bank = 1, Signal name = CC NET "Segment_out<3>" LOC = "N11"; # Bank = 2, Signal name = CD NET "Segment_out<4>" LOC = "P12"; # Bank = 2, Signal name = CE NET "Segment_out<5>" LOC = "L13"; # Bank = 1, Signal name = CF NET "Segment_out<6>" LOC = "M12"; # Bank = 1, Signal name = CG NET "AN3" LOC = "K14"; # Bank = 1, Signal name = AN3 NET "AN2" LOC = "M13"; # Bank = 1, Signal name = AN2 NET "AN1" LOC = "J12"; # Bank = 1, Signal name = AN1 NET "AN0" LOC = "F12"; # Bank = 1, Signal name = AN0
(6) 下載與驗證 : 連接實驗板 (Digilent USB Cable)-> 連接到 USB -> 發展板 switch on-> [Start]->digilent->Adept->Program-> 實驗板操作驗證 (Seven_Segment_Test.bit)
Lab7_2:7 段顯示器控制電路 +2:4 解碼器與四位元加法器電路 (Add copy of source) Design Entry: 加入新設計檔案 : [Project] [New Source]-> Schematic ->File name: Seven_Segment_Adder [Save]
Add copy of source
Create Schematic Symbols: decoder2to4 Adder4bits Seven_Segment Seven_Segment_Adder->Set as Top Module->Symbols 引用元件
Seven_Segment_Adder.ucf NET "B3" LOC = "N3"; # Signal name = SW7 NET "B2" LOC = "E2"; # Signal name = SW6 NET "B1" LOC = "F3"; # Signal name = SW5 NET "B0" LOC = "G3"; # Signal name = SW4 NET "A3" LOC = "B4"; # Signal name = SW3 NET "A2" LOC = "K3"; # Signal name = SW2 NET "A1" LOC = "L3"; # Signal name = SW1 NET "A0" LOC = "P11"; # Signal name = SW0 NET "P0" LOC = "G12"; # Signal name = BTN0 NET "P1" LOC = "C11"; # Signal name = BTN1
NET "Segment_out<0>" LOC = "L14"; # Bank = 1, Signal name = CA NET "Segment_out<1>" LOC = "H12"; # Bank = 1, Signal name = CB NET "Segment_out<2>" LOC = "N14"; # Bank = 1, Signal name = CC NET "Segment_out<3>" LOC = "N11"; # Bank = 2, Signal name = CD NET "Segment_out<4>" LOC = "P12"; # Bank = 2, Signal name = CE NET "Segment_out<5>" LOC = "L13"; # Bank = 1, Signal name = CF NET "Segment_out<6>" LOC = "M12"; # Bank = 1, Signal name = CG NET "AN0" LOC = "F12"; # Bank = 1, Signal name = AN0 NET "AN1" LOC = "J12"; # Bank = 1, Signal name = AN1 NET "AN2" LOC = "M13"; # Bank = 1, Signal name = AN2 NET "AN3" LOC = "K14"; # Bank = 1, Signal name = AN3 NET "LD0" LOC = "M5" ; # Bank = 2, Signal name = LD0 (6) 下載與驗證 : 連接實驗板 (Digilent USB Cable)-> 連接到 USB -> 發展板 switch on-> [Start]->digilent->Adept->Program-> 實驗板操作驗證 (Adder4bit_Seven.bit)