10384 200030003 UDC 2003 8 2003 9 2003
Hardware Platform for 2D Barcode Reader Techniques Thesis for the degree of Master of Science By Liu Zhenyu (Electronic Engineering Dept., Xiamen University, P.R. China)
20 TMS320C6711 VVL VV6500 CMOS Xilinx Spartan XL XCS10XL-4TQ144C Microchip PIC16C54 CMOS FPGA DSP FPGA CMOS FPGA VHDL DSP i
Abstract Abstract Since the first barcode was invented over twenty years ago, the barcodes technique has been rapidly developed and widely used. By using 1D barcodes, both the data acquisition and processing speeds have been improved, which do a contribution to the development of scientized and modernized administration. Compared with 1D barcodes, the 2D barcodes technique provides a novel method of information storage and transmitting, specialized by hyper density and mass storage; it has the hyper-strong capability of deencrypting damaged barcodes. Based on the 2D barcode reader technique, we designed and realized a hyper-efficient hardware platform for real time image processing. This system contains a core computing and data processing chip with a TMS320C6711, a image data acquisition sensor with a VV6500 (VVL Company, UK), a image pre-processing and data buffer model with a XCS10XL-4TQ144C (Spartan-XL serials, Xilinx Company) and a central control unit with a single-chip of PIC16C54 (Microchip Company). Main parts in the system are connected by high-speed interface and software-controlled. The results obtained from the real test environment show that this system could work stable with satisfied output specifications. Herein, the whole thesis parted into seven chapters. The first chapter is the introduction chapter, which will give us a bird eye of development of 2D barcode reader technique. The second chapter contains the function requirements for the system, the system block diagram and models design. The model of CMOS image sensor, the model of FPGA data processing and programming and the model of DSP and interface design will be described respectively in Chapter 3, 4 and 5. The built-in image processing software and the results obtained from real test environment will be described in the last chapter-chapter 6, in this chapter, we also discussed the high-speed FPGA system design and the high-speed circuits routing technique. Last but not least, we give a brief conclusion of work for this thesis in Chapter 7. Key word: 2D Barcodes, Image, Sensor, CMOS, FPGA, VHDL, DSP ii
... i Abstract...ii... 1 1.1... 1 1.2... 1 1.3 IC... 3 1.4... 3 1.4... 4 1.5... 5... 6 2.1... 6 2.1.1... 6 2.1.2... 7 2.2... 8 2.2.1... 8 2.2.2... 9 2.2.3... 9 2.3... 11 2.3.1 MCU... 11 2.3.2 FPGA... 12 2.3.3 DSP... 13 CMOS... 15 3.1... 16 3.1.1 CCD... 16 3.1.2 CMOS... 16 3.2 VV6500 CMOS... 17 3.2.1 VV6500... 17 3.2.2 VV6500... 18 3.3 VV6500... 19 3.3.1... 19 3.3.2... 19 3.3.3... 20 3.3.4 VV6500... 21 3.3.5 VV6500... 21 3.3.6 VV6500... 23 3.3.7 VV6500... 24 iii
3.3.8 VV6500... 25 3.4 VV6500... 25 FPGA... 28 4.1... 29 4.1.1 EDA... 29 4.1.2 VHDL... 30 4.1.3 FPGA/CPLD... 31 4.1.4... 33 4.2 FPGA... 34 4.3 FPGA... 35 4.3.1... 35 4.3.2... 37 4.3.3... 39 4.3.4 FIFO... 42 4.3.5 FPGA... 43 DSP... 46 5.1 DSP... 46 5.2 DSP... 47 5.2.1 DSP... 47 5.2.2 TMS320C6711... 48 5.3 DSP... 50 5.3.1... 50 5.3.2 TMS320C6711... 51 5.3.3 TMS320C6711... 52 5.3.4 CSR... 52 5.3.5 IER... 53 5.3.6 IFR,ISR,ICR... 53 5.3.7... 54 5.3.8... 55 5.4 DSP... 56 5.4.1... 56 5.4.2 EMIF... 57 5.4.3 EMIF... 58 5.4.4 EMIF... 60... 63 6.1... 63 6.1.1 BAYER... 63 iv
6.1.2 C6711... 65 6.1.3... 65 6.1.4... 66 6.2 FPGA... 68 6.2.1 FIFO... 68 6.2.2 FPGA... 69 6.3... 70 6.3.1... 71 6.3.2... 71 6.3.3... 72 6.3.4... 72... 73... 76... 78 v
1.1 EAN UPC 70 80 70 80 ( ) 1.2 80 2-dimensional bar code 2000 1
80 250 1100 76mm 25mm PDF417 1848 2729 1000 10 26 Code l28 128 ASIC ( ) PDF 417 0-8 9 8 50 Stacked Bar Code Dot Matrix Bar Code Code 49 PDF 417 Code 16K Code one Data Matrix Maxicode 1 0 2
1.3 IC IC (1 ) IC IC 3 5 (2 3 ) IC IC PDF417 8 9 (PVC ) : IC 1.4 CCD (Linear Imager) PDF417, Image Reader PDF417 3
Symbol 1.4 :, Code49 Code16K PDF417 Code one, PDF417,,, ATAA(Air Transport Association of America) NASA AIAG(Automotive Industry Action Group) DOD (Department of Defense) Data Matrix Intel Pentium IV CPU Data Matrix PDF417 Code one, Symbol 1991 PDF417 PDF417 1994 1996 AIM (ANSI) Code one Code16K Code49 Data matrix Maxicode CEN 1997 (CEN) PDF417 (ISO) (IEC) JTC1/SC31 PDF417 Code16K Data matrix Maxicode ISO, GB/T17172-1997, 4
PDF417 1.5 PIC CMOS FPGA FPGA DSP Bayer 5
2.1 2-1 I/O Codeword / RS232 USB LCD 2-1 PDF 417 2.1.1 l. 2. 3. 4. 6
40KHz 16bit, 80K 80K 352 288 8bit 30 / CIF 6.1M 6.1M 2.1.2 12 SRAM DRAM PC100 SDRAM 134M/S ROM EPROM EEPROM FLASH ROM FLASH ROM LCD LCD LCD LCD 2bit 4 4bit 16 LCD Active Passly TFT LCD STN LCD / RS232 USB USB 1.1 12M/S 2.0 480Mb/s USB IrDA Bluetooth IrDA 7
PDA Bluetooth 2.2 2.2.1 MPU MCU I/O X86 80186 188 486 586 DVD WebPad SOC DSP Digital Signal Processor DSP I/O RISC Reduced Instruction Set Computer RISC RISC ARM ARM Hitachi SH MIPS LSI Logic IDT Aldeny Toshiba MIPS Motorola M-Core RISC ARM RISC TI DSP TMS320C54X TMS320C62X/TMS320C67X TMS320C54X 100M 25/20/15/12.5/10ns, 40/50/66/80/100MIPS. TMS320C54X TI TMS320C62X TMS320C67X DSP TMS320C62X 200MHz 1600MIPS TMS320C67X IEEE 167MHZ 1GFLOPS TMS320C6000 8
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