10384 9924012 UDC 2002 5 2002 2002 2002 5 1
Study on High Speed Switch System and Their ASIC Frontend Design Thesis for MS By Shuicheng Cai Supervisor: Prof. Donghui Guo Department of Physics Xiamen Unviersity People s Republic of China May 2002 2
ITUTBISDNATM ATM ASIC ATM ATM ATM 3 1 2 Crossbar MIN EMIN VOQ ilqf DPA ASIC 3 VerilogHDL Synopsys ATM DPA Crossbar ATM 3
Study on High Speed Switch System and Their ASIC Frontend Design Abstract In these years the quick development of fabric communication technology make the switch system becoming the barrier of modern high speed communication network. So study, design and manufacture high speed switch system are very important for modern high speed communication network. Asynchronous transfer mode (ATM) had been specified as the base of the broadband integrated services digital network by international telecommunication union telecommunication standardization sector (ITU-T). One important method of ATM to realize high speed data transfer is using cell whose size is fixed. Because of it, ASIC can deal with cell directly. So ATM switch can switch cell at high speed, and study on ATM switch is of great emphasis in these years. The result of the study has a great signification not only for ATM but also for other field using high speed switch. The goal of this article is to design a high speed ATM switch system, so there are three parts of this article. 1) Most switch systems used now are studied. The result of the research of most switch system including Time Divided Switch system and Space Divided Switch system, and its buffer strategy indicate that Time Divided Switch system can not meet with the data transfer speed in fabric when design large scale high speed switch system because of the process of semiconductor. So Space Divided Switch system is chosen in our design. 2) Choose the space divided switch fabrics and their scheduling algorithm for high speed switch system based on analysis and stimulation. The performances of two main space divided switch fabrics including Crossbar and Multistage Interconnect Network (MIN), including Extend Multistage Interconnect Network (EMIN) are study carefully. The result of analysis and stimulation of buffer strategy including input buffer and output buffer explain why using input buffer. Because of block in head of line (HOL), input buffer strategy make the whole switch system performances declining drastically at heavy offered load, and some improvements of input buffer strategy are put forward to overcoming the head of line block. Virtual output queues (VOQ) is chosen as input buffer strategy. DPA and ilqf cell scheduling algorithms for VOQ are simulated. The rueslt of simulation is the base of hardware design. 3) Design switch system using EDA based on the study. Because the function of switch system is very complicated, some modules are designed by schematics directly, most modules are designed by Verilog HDL using EDA technology, synthesized by the Synopsys software. At last a high speed ATM switch system is designed, including VOQ as input buffer strategy, DPA cell scheduling algorithm and Crossbar switch fabric. Key words : Switch System ATM EDA 4
1.1 1.2 2.1 2.2 2.3 2.4 3.1 3.1.1 3.1.2 3.2 3.2.1 3.2.2 3.3 3.3.1 ilqf 3.3.2 DPA 3.4 EMINCrossbar 4.1 4.1.1 4.1.2 4.1.3 Crossbar 4.2 ilqf 4.3 DPA 4.3.1 DPA 4.3.2 ATM 5.1 5.2 5.3 5
1. 1.1 ilqf 1.2 DPA 1.3 EMIN 2. HDL 2.1 2.1.1 2.1.2 HDL 2.1.3 FIFO HDL 2.2 FLIP 2.2.1 2.2.2 FLIP 2.2.3 HDL 2.2.4 1 2.2.5 2 2.3 ilqf HDL 2.4 DPA HDL 2.4.1 2.4.2 HDL 2.4.3 HDL 2.5 2.5.1 VOQDPA 2.5.2 2.5.2 6
1.1 20 70 ISDN ISDN 2Mbps11 1988 ITUT B ISDN BISDN 1 BISDN 11 ITUT BISDN 12 ATM11ATM 53 ASIC TCP/IP ASIC TCP/IP ATM 53 5 48 VPVCCLP ATM BISDN ATM QoS BISDN 2 7
12ITUT BISDN BISDN BISDN 20 BISDN 13 20 80 2 OH 14TMD WDM 10Gbps 14 1500nm 13 8
14 1500nm ATM ATM 15 ATM ATM ATM ATM ATM ATM 15 9
ATM ATM ATM Internet 1.2 Crossbar MIN EMIN VOQ ilqf DPA 16 VerilogHDL Synopsys HDL ATM 10
16 11
ITUTATM ATM ATM ATM BISDN 2.1 21 IM IM OM OM 21 ATM 3 VPI/VCI ATM ATM VPI/VCI VPI/VCI VPI/VCIATM ATM ATM ATM ATM multicast BISDN 12
2.2 NN 0.8 N0.8 2 ATM 3 2.3 22 Crossbar MINMIN Banyan BanyanBense 13
22 2.3.1 23 RAM N N RAM RAM 23 RAM 24 AF FIFO N 24 14
RAM N VLSI ATM SDH STM1 155MbpsSTM4622MbpsSTM162.5Gbps STM6410Gbps 2 2700ns625ns163ns40ns RAM N RAM N21 RAM 21ns STM1 STM4 STM16 STM64 155Mbps (622Mbps) (2.5Gbps) (10Gbps) 8 163.048 40.7619 10.1905 2.54762 16 81.5238 20.3809 5.09524 1.27381 32 40.7619 10.1905 2.54762 0.636904 64 20.3809 5.09524 1.27381 0.318452 128 10.1905 2.54762 0.636904 0.159226 N 256 5.09524 1.27381 0.318452 0.0796131 512 2.54762 0.636904 0.159226 0.0398065 1024 1.27381 0.318452 0.0796131 0.0199033 2113 RAM Moore RAM 222 R = 10 9 ρ = 0.9 RAM 22 RAM R = 10 9 ρ = 0. 9 15
2.3.2 Crossbar Banyan MIN 2 2 Crossbar 25 N Crossbar N N 2 26 16
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