DOI:10.13873/j.1000-97872014.07.024 98 Transducer and Microsystem Technologies 2014 33 7 * FPGA 550025 FPGA CMOS SDRAM VGA SOPC SOPC TP 391 A 1000 9787201407 0098 05 Design of a FPGA-based hardware platform of realtime video tracking system * LIU Zi-yanFENG LiangQI Jia College of Electronics and Information Guizhou University Guiyang 550025 China AbstractA FPGA-based hardware platform design of video tracking system is presented which includes DSP CMOS image acquisition multiport SDRAM controller image VGA display SOPC system and PTZ control drive circuit etc. By using the platform real-time image acquisition caching displaying and PTZ driving can be realizedby adding code to SOPC systemdetecting trackingand positioning of moving targets can be realized and rotation direction of PTZ can be changed autonomous tracking can be realized. Key wordsvideo trackingimage processingfpga 0 SOPC FPGA SOPC ARM 2~ DSP 4 FPGA 1 Nios II 2 PWM 1 1. 1 3 FPGA ARM DSP FPGA FPGA ASIC SOPC FPGA Nios II Nios II I /O 2014 01 06 * J 2011 2193
7 FPGA 99 VGA FPGA Nios II Nios II 1 1 5 1 6 2 1 Fig 1 Block diagram of video tracking system CMOS FPGA 1 FPGA SOPC Nios II CMOS RGB SDRAM Avalon Nios II SDRAM 7 1 VGA SDRAM VGA SOPC Nios II 1. 2 CMOS Fig 3 Architecture diagram of image capturing 2. 2 VGA 30 RGB FPGA SDRAM 2 SDRAM VGA SDRAM VGA SOPC DE2 70 VGA Nios II 16 D SUB Cyclone II FPGA VGA 2 ADV7123 3 10 2 DAC CMOS 1 600 1 200 SDROM VGA SOPC 4 VGA SDRAM 2. 1 VGA Fig 2 Work flow of video tracking system Terasic TRDB D5M TRDB D5M 500 GPIO FPGA TRDM D5M 3 FPGA FPGA I 2 C CMOS CMOS 3 SDRAM VGA VGA VGA
100 33 4_Port SDRAM 1 FIF02 4_Port SDRAM 2 FIF02 6 4_Port SDRAM Fig 4 4 VGA Image display architecture of VGA 2. 3 SDRAM SDRAM FPGA first in first out FIFO SDRAM SDRAM 5 4_Port SDRAM 1 SDRAM 6 4_Port SDRAM Fig 6 Design block diagram of double 4_Port SDRAM CMD control module 2. 4 SOPC CMD SOPC CMD SDRAM SDRAM CMD CMD SDRAM 7 SOPC 输入 输出 Fig 5 5 4_Port SDRAM Structure block diagram of 4_Port SDRAM controller VGA SOPC Nios II 7 SOPC Fig 7 SOPC system image processing flow 2 SDRAM 2 4_Port SDRAM SOPC Builder CMOS 2 4_Port SDRAM 1 SOPC Builder FIFO1 10 R 5 G Nios II SDRAM1 4_Port SDRAM 2 FIFO1 5 G 10 B SOPC 1 SDRAM2 VGA 4_Port SDRAM l FIFO1 4_Port SDRAM 2 FIFO1 Nios II 100 MHz SOPC SOPC CPU 1 FPGA 50 MHz
7 FPGA 101 2 FPGA SOPC Builder Nios II Process Nios II 3 SRAM 4 JTAG_UART PLL JTAG_UART PC Nios II PLL 5 PIO ID PIO Fig 10 FPGA hardware resource usage of system platform Nios II Nios 2 II 8. 1 IDE LCD 6 7 Nios II void task1void* pdata 2. 5 while 1 2 57 4 printf" Hello ucos - II /n" OSTimeDlyHMSM0 3 0 SOPC PWM 8 10 FPGA EP2C70 FPGA LCD 11 LCD Nios II FPGA 8 Fig 8 System block diagram of PTZ control circuit 11 LCD Fig 11 LCD display test of soft core THB7128 Nios II CMOS CMOS C CMOS 42 57 9 setup CMOS 9 Fig 9 Driver circuit architecture 3 Altera EP2C70 FPGA CMOS VGA IOWRCMOS_IF_0_BASE 4 0x00800860 maxaddr = 640* 512 128* 4 IOWRCMOS_IF_0_BASE 7 maxaddr IOWRCMOS_IF_0_BASE 1 0x00800880 IOWRCMOS_IF_0_BASE 2 &buffer1 length = 128* 4 IOWRCMOS_IF_0_BASE 3 length IOWRCMOS_IF_0_BASE 6 0x0001 FPGA 1 600 1200 12 100 MHz THB7128 10 FPGA SOPC Nios II
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