FPGA WP-01191-1.0 Coal 18.33 Fossil Fuels 26.10 Conversion Losses 24.61 Petroleum 0.40 Natural Gas 7.29 Other Gases 0.09 Nuclear Electric Power 8.35 Renewable Energy 4.28 Other 0.16 Energy Consumed to Generate Electricity 38.89 Gross Electricity Generation 14.28 Unaccounted for 0.16 Net Electricity Imports 0.12 Net Electricity Generation 13.49 Plant Use 0.79 T & D Losses 1.00 Residential 4.65 Commercial 4.51 Industrial 3.01 Transportation 0.03 Direct Use 0.57 101 Innovation Drive San Jose, CA 95134 www.altera.com 2013 1 Altera ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS STRATIX Altera www.altera.com/common/legal.html Altera Altera Altera Altera Altera Altera. ISO 9001:2008 Registered 2013 2 Altera
2 Power Generators T & D Utilities Substations Substations PMU Substations Control Center Substations PMU PMU Customers AMI AMI EV Electricity Communication f 2013 2 Altera FPGA
3 T&D AMI IEC 61850 FPGA 2013 2 Altera
4 2013 2 Altera FPGA
5 Operating Room Switchyard Fiber Optic Cable Copper Wire Sensors and Actuators Sensors and Actuators Conventional Substation Power Lines Fiber Optic Cable (Station Bus) IEC 61850 Implementation Fiber Optic Cable (Process Bus) S/A S/A S/A S/A S/A S/A FPGA 2013 2 Altera
6 Goose Sampled Values Client/Server Goose Sampled Values Mapping Layer Mapping Layer 7 Application 7 Application 6 Presentation 6 Presentation ISO Stack Layer 5 4 3 Session Transport (TCP) Network (IP) ISO Stack Layer 5 4 3 Session Transport (TCP) Network (IP) 2 Data Link 2 Data Link 1 PHY (Ethernet) 1 PHY (Ethernet) ( ) ( ) 800 ms 400 ms 12 ms 4 ms 12 ms 4 ms 8 ms 4 ms <1 ms <2 2013 2 Altera FPGA
7 IEC 62439 PRP Device LAN A LAN B PRP Device LAN A LAN B LAN A LAN B LAN A LAN B LAN A LAN B LAN A LAN B LAN A LAN B LAN A LAN B LAN LAN PRP Device PRP Device PRP Device PRP Device PRP Device LAN Device LAN Device FPGA 2013 2 Altera
8 Sending Node HSR Device Port A Port B HSR Device Port A Port B Port A Port B HSR Device Port A Port B Port A Port B Port A Port B HSR Device HSR Device HSR Device IEC 62351 f 2013 2 Altera FPGA
FPGA SoC 9 IEEE 1588-2008 Master Clock Slave Clock t 1 SYNC (t 1 ) t 2 t 4 Delay_Request Delay_Response (t 4 ) t 3 (t 2 - t 1 ) + (t 4 - t 3 ) Avg Path Delay t d = Offset From Master t 0 = (t 2 - t 1 ) - t d 2 UDP/IP Repeat Each Second FPGA SoC FPGA 2013 2 Altera
10 FPGA SoC DC/DC DC/AC Line Filter Switch EMI Filter To Meter/ Grid V/I Gate Drivers V/I Gate Drivers/Opto Isolators V/I V PV/I PV V DC/I DC VAC/I AC PWM PWMs FPGA V PV/I PV MPPT V DC V AC V REF V Control PLL I r I REF I AC I Control DSP/FPGA Analog Interface Memory Comms MCU Keypad LCD Memory 2013 2 Altera FPGA
FPGA SoC 11 T&D Secure Gateway Router Control Center GPS Receiver Internet Other Secure Substations Controller (PLC) IEC 61850-8-1 (Substation Bus) IEC 61850-9-2 (Process Bus) RedBox = Redundancy Box Controller (PLC) IEC 62439-3 Ethernet Switches Industrial Computer RedBox Remote Operator Legacy Bus (e.g., CAN, etc.) Intelligent IED IED IED Electronic Devices I/O Relays, Switches & Reclosers HV Wiring MU Merging Unit HV Wiring Switchyard FPGA 2013 2 Altera
12 FPGA SoC Port A Port B FPGA (Fault Detection Algorithms) Fieldbus 10/100/1000 (IEEE 1588) DSP (Fault Detection Algorithms) CPU (Housekeeping, MMI Communication) Keypad/ Display Memory Modbus Time Sync Analog Interface (V-I Sense) 16 bit Relays HV Wiring 2013 2 Altera FPGA
FPGA SoC 13 Programming Software RTOS Synchronization Processor PRP/HSR Fieldbus Digital I/O Modules Analog I/O Modules Backplane T&D Fieldbus (Optional) Port A PHY MII/GMII MAC Registers CAN UART Port B PHY MII/GMII MDIO I 2 C MAC MMD MII/GMII STA MAC CPU Aux PHY MII/GMII MAC IEEE 1588 FPGA 2013 2 Altera
14 FPGA SoC T&D GPS Receiver Modem Port A PHY Port B PHY Microprocessor DSP 16 bit 2013 2 Altera FPGA
15 Port A PHY Port B PHY Display Keyboard Graphics Controller Microprocessor Communications 16 bit DSP CAN UART Equipment Operator Terminals Service Life (Years) 6-10 Communications 10-20 Secondary Equipment, IEDs 15-25 Switchgear/Transformers 30-40 FPGA 2013 2 Altera
16 Altera FPGA SoC 2013 2 Altera FPGA
Altera FPGA SoC 17 Altera FPGA SoC Performance 4,000 DMIPS at < 1.8 W ARM Cortex-A9 (800 MHz) L1 Cache NAND Flash L1 Cache QSPI Flash Control ARM Cortex-A9 (800 MHz) L1 Cache 64 KB RAM Ethernet (x2) CAN, SPI, UART (x2) Communications Fieldbus, IEC 42439-3 Compatible PRP/HSR Reliability Highest Level of ECC Coverage USB (x2) DMA (x11) Timers (x11) JTAG FPGA Configuration HPS to FPGA FPGA to HPS GPIO Power and Footprint FPGA and MCU Have Up to 30% Lower Power Consumption and Up to 50% Footprint Reduction Performance Two Hard-Coded Memory Controllers Hard Multi-Port DDR SDRAM Controller (x2) FPGA Fabric PCIe Transceivers Flexibility, Reliability, and Upgrades RISC Cores, Variable Precision DSP, Soft-Coded Peripherals & Hardware Accelerators FPGA 2013 2 Altera
18 Altera FPGA SoC 2013 2 Altera FPGA
19 2013 2 1.0 FPGA 2013 2 Altera