UM/UM SYSTEM LOK IGRM THERML SMS R-SOIMM RVS Type PG R-SOIMM RVS Type PG PG LOK SLGSPVTR (QFN-) PG ual hannel R 00/0.V rrandale ( rpg ) PG,,, POWER REGULTOR +.V_SUS/+0.V_R_VTT +.0V_VTT POWER /TT ONNETOR PG PG +.0V_PH PG PG SYSTEM RESET IRUIT TT HRGER RUN POWER SW +.V_SUS/+V_SUS +V/+.V/+.V PU VR / +.V_LW/+V_LW/ +V_LW PG PG PG PG PG ST-O ST-H PG PG ST ST FI MI X LVS TMS LEVEL SHIFTER PIVPLSZE PG Panel onnector PG HMI ONN. PG US conn x PG luetooth T onn T PG 0 amera PG 0 US.0 US.0 US.0 IH PH (HM) VG PIE.0 PIE.0 US.0 PIE.0 US.0 RT ONN. LOM RTL0E MINI-R WLN MINI-R WWN PG PG PG PG - MI conn PG UIO/MP LQ-GR udio udio SPK conn Jacks x PG PG 0 USER INTERFE PG PG ONN PG SPI FLSH Mbytes PG LP K ITE0 PG X PS/ Touchpad PG PG,,,0,, SPI FLSH Mbytes PG Keyboard PG US.0 US.0 ONN PG US.0 US.0 VER : PW: PW: R REER RTS PG US conn x QUNT OMPUTER Schematic lock iagram Size ocument Number Rev UM/UM ate: Wednesday, September 0, 00 Sheet of
Table of ontents PGE ESRIPTION Schematic lock iagram Front Page - larksfield/uburndale - PH - RIII SO-IMM(0P) lock Generator - LNK PGE HMI ONN L ONN RT ONN ONN SIO (ITE0) FLSH / RT MINI-ard (WWN) 0 MINI-ard (WLN\WPN) US ST (H & _ROM) TP / KEYOR PWR SWITH / /LE FN / THERML OE L LN(RTL0M/RJ-) System Reset ircuit LNK PGE 0.V_RUN(RT0/RT0) harger (MX) V/V (TPS)._R/0.(TPS).0V_PH(TPS).0_VTT(TPS) GFX_VORE (MX0) PU ORE(MX0) Run Power Switch in & att 0 P & SREW EMI P SMUS LOK THERML MP Power lock iagram Power sequence lock XP 0 POWER PLNE +PWR_SR +RT_ELL +V_LW +V_LW +.V_LW +V_SUS +.V_SUS +.V_SUS +0.V_R_VTT +V_RUN +.V_RUN +.V_RUN +.V_RUN +V_H +.0V_PH +V_ORE +LV +V_MO VOLTGE 0V~+V +.0V~+.V +V +V +.V +.V +0.V +V +.V +.V +.V +V +0.V~+.V +.V +V PGE,0,,,,,,0, 0,,,0,,,,,,,0,,,,,,, Power States 0,0,0,0,,,,,,,,,,,,,,0, 0,0,,,,0,,,,,,,,,,,,0,,,,,,0,,,,,,,,,,,0,,,,,,,,0,,,,,,0 0,,,,,,, 0, GN PLNE PGE ESRIPTION GN LL +V +.0V_VTT +.V 0,0,0,,,0 ESRIPTION MIN POWER RT LRGE POWER SLP_S# TRL POWER SLP_S# TRL POWER SOIMM POWER SOIMM POWER SLP_S# TRL POWER SLP_S# TRL POWER SVO POWER Express ard/min ard H Power PU ORE POWER L Power MO Power ONTROL SIGNL,,, LRGE POWER MIN POWER +.V,0,,,,,,,,,,, LW_ON SUS_ON SUS_ON SUS_ON RUN_ON RUN_ON RUN_ON RUN_ON RUN_ON H_EN +.0V 0,0,,, PH POWER RUN_ON IMVP_VR_ON LV_TST_EN & ENV MO_EN TIVE IN S0~S S0~S S0~S S0~S 0 POWER.V_LW_ON S0~S PU POWER RUN_ON QUNT OMPUTER Index & Power Status Size ocument Number Rev UM/UM ate: Wednesday, September 0, 00 Sheet of
[] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_TXN[:0] FI_TXP[:0] FI_FSYN0 FI_FSYN FI_INT FI_LSYN0 FI_LSYN U MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] G MI_TX#[] F MI_TX#[] H MI_TX#[] MI_TX[0] F MI_TX[] E MI_TX[] G MI_TX[] FI_TXN0 E FI_TXN FI_TX#[0] FI_TXN FI_TX#[] FI_TXN FI_TX#[] FI_TXN FI_TX#[] G FI_TXN FI_TX#[] E FI_TXN FI_TX#[] F FI_TXN FI_TX#[] G FI_TX#[] FI_TXP0 FI_TXP FI_TX[0] FI_TXP FI_TX[] 0 FI_TXP FI_TX[] FI_TXP FI_TX[] G FI_TXP FI_TX[] E0 FI_TXP FI_TX[] F0 FI_TXP FI_TX[] G FI_TX[] F FI_FSYN[0] E FI_FSYN[] FI_INT F FI_LSYN[0] FI_LSYN[] MI Intel(R) FI PI EXPRESS -- GRPHIS PEG_IOMPI PEG_IOMPO PEG_ROMPO PEG_RIS PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_IOMPI K J J G G F F E 0 J H H F G E F F 0 0 L M M M0 L K M J K H0 H F E R./F R 0/F [] H_PUET# [0] H_PEI [0] H_THERM [] PM_SYN [0] H_PWRGOO [] PM_RM_PWRG [] H_VTTPWRG [,,,0,] PLTRST# R0 U H_OMP T OMP H_OMP T OMP H_OMP G OMP H_OMP0 T OMP0 H SKTO# H_TERR# K TERR# H_PEI T PEI H_PROHOT# N PROHOT# K THERMTRIP# H_PURST# P RESET_OS# L PM_SYN N VPWRGOO_ N VPWRGOO_0 PM_RM_PWRG K SM_RMPWROK M VTTPWRGOO M TPPWRGOO.K/F L RSTIN# MIS THERML PWR MNGEMENT LOKS R MIS JTG & PM LK LK# LK_ITP LK_ITP# PEG_LK PEG_LK# PLL_REF_SSLK PLL_REF_SSLK# SM_RMRST# SM_ROMP[0] SM_ROMP[] SM_ROMP[] PM_EXT_TS#[0] PM_EXT_TS#[] PRY# PREQ# TK TMS TRST# TI TO TI_M TO_M R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] R0 T0 E F L M N N P T P N P T T R R P N J K K J J H K H SM_ROMP_0 SM_ROMP_ SM_ROMP_ XP_TRST# XP_TI_M R XP_TO_M RESET# T T0 LK_PU_LK [0] LK_PU_LK# [0] LK_PIE_GPLL [] LK_PIE_GPLL# [] REFSSLK [] REFSSLK# [] R_RMRST# [,] R R R SJ_00 0K 0K +.0V_VTT R,R Remove / Ray PM_EXTTS#0 [] PM_EXTTS# [] R *.K/F_N PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] L M M L0 M K M H K G0 G F E +.V_SUS R.K/F PM_RM_PWRG R K/F R 0/F larksfield/uburndale RESET# R K +.V_RUN larksfield/uburndale R use a k pull-up to.v_s for R# TRST# use a ohm pull down. Processor Pullups +.0V_VTT Processor ompensation Signals R ompensation Signals H_OMP0 SM_ROMP_ H_OMP SM_ROMP_ R./F R./F R *_N H_OMP H_OMP SM_ROMP_0 R_RMRST# 0 H_PWRGOO 0 H_TERR# H_PROHOT# R./F R./F R0 0/F R 0/F R 0/F R./F R 00/F Layout Note: Place these resistors near Processor 0.0U 0.0U H_PURST# UURN / QUNT OMPUTER Size ocument Number Rev UM/UM Friday, October 0, 00 ate: Sheet of
UURNLE/LRKSFIEL PROESSOR (R) U U [] M Q[:0] [] [] [] [] [] [] M S0 M S M S M S# M RS# M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q 0 S_Q[0] 0 S_Q[] S_Q[] S_Q[] 0 S_Q[] 0 S_Q[] E0 S_Q[] S_Q[] S_Q[] F0 S_Q[] E S_Q[0] F S_Q[] E S_Q[] S_Q[] E S_Q[] S_Q[] H0 S_Q[] G S_Q[] K S_Q[] J S_Q[] G S_Q[0] G0 S_Q[] J S_Q[] J0 S_Q[] L S_Q[] M S_Q[] M S_Q[] L S_Q[] L S_Q[] K S_Q[] N S_Q[0] P S_Q[] H S_Q[] F S_Q[] K S_Q[] K S_Q[] F S_Q[] G S_Q[] J S_Q[] J S_Q[] J0 S_Q[0] J S_Q[] L0 S_Q[] K S_Q[] K S_Q[] L S_Q[] K S_Q[] L S_Q[] N S_Q[] M0 S_Q[] R S_Q[0] L S_Q[] M S_Q[] N S_Q[] T S_Q[] P S_Q[] M S_Q[] N S_Q[] M S_Q[] T S_Q[] T S_Q[0] L S_Q[] R S_Q[] P S_Q[] S_S[0] S_S[] U S_S[] E S_S# S_RS# E S_WE# R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] P Y Y P E E F H M G M N0 N F J N H K P T F H M H K0 N R Y W V V T Y U T U G T V M M0 M M M M M M M M M M M M M M M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS0 M QS M QS M QS M QS M QS M QS M QS M 0 M M M M M M M M M M 0 M M M M M M LK0 [] M LK0# [] M KE0 [] M LK [] M LK# [] M KE [] M S0# [] M S# [] M OT0 [] M OT [] M M[:0] [] M QS#[:0] [] M QS[:0] [] M [:0] [] [] M Q[:0] [] [] [] [] [] [] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M S0 M S M S M S# M RS# M WE# E F F F F G H G J J G G J J J K L M K K M N F G J K G G J H K K M N K K M M P N T N N N T T N P P T T P R0 T0 W R Y S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY - S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] W W M V V M E H K H L R T F J L H L R R E H M G L P R U V T V R T R R R R P R F P N M M0 M M M M M M M M M M M M M M M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS0 M QS M QS M QS M QS M QS M QS M QS M 0 M M M M M M M M M M 0 M M M M M M LK0 [] M LK0# [] M KE0 [] M LK [] M LK# [] M KE [] M S0# [] M S# [] M OT0 [] M OT [] M M[:0] [] M QS#[:0] [] M QS[:0] [] M [:0] [] larksfield/uburndale hannel Q[,,,], M[] Requires minimum mils spacing with all other signals, including data signals. larksfield/uburndale hannel Q[,,,,,,0,,] Requires minimum mils spacing with all other signals, including data signals. UURN / QUNT OMPUTER Size ocument Number Rev UM/UM ate: Friday, October 0, 00 Sheet of
PRSLPVR VI GFXVR_EN VI VI0 VI VI VI0 PRSLPVR VI VI VI H_PSI# VI VI VI TP_VSS_SENSE_VTT VI VI GFXVR_PRSLPVR [] GFXVR_EN [] GFXVR_IMON [] GFXVR_VI_0 [] GFXVR_VI_ [] GFXVR_VI_ [] GFXVR_VI_ [] GFXVR_VI_ [] GFXVR_VI_ [] GFXVR_VI_ [] VSS_XG_SENSE [] H_PSI# [] I_MON [] VSENSE [] VSSSENSE [] PRSLPVR [] VI0 [] VI [] VI [] VI [] VI [] VI [] VI [] V_XG_SENSE [] +.V_RUN +.0V_VTT +V_ORE +.0V_VTT +.0V_VTT +V_ORE +V_ORE +.0V_VTT +V_GFX_ORE +.0V_VTT +.0V_VTT +.V_SUS Size ocument Number Rev ate: Sheet of QUNT OMPUTER UM/UM UURN / Friday, October 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER UM/UM UURN / Friday, October 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER UM/UM UURN / Friday, October 0, 00 PU ore Power UURNLE/LRKSFIEL PROESSOR (POWER) UURNLE/LRKSFIEL PROESSOR (GRPHIS POWER) lose to PU POWER PU ORE SUPPLY.V RIL POWER SENSE LINES PU VIS UF larksfield/uburndale POWER PU ORE SUPPLY.V RIL POWER SENSE LINES PU VIS UF larksfield/uburndale ISENSE N VTT_SENSE PSI# N VI[0] K VI[] K VI[] K VI[] L VI[] L VI[] M VI[] M PRO_PRSLPVR M VTT_SELET G V_SENSE J VSS_SENSE_VTT V G V G V G V G V G V G0 V G V G V G V0 G V F V F V F V F V F V F0 V F V F V F V0 F V V V V V V 0 V V V V0 V V V V V V 0 V V V V0 V V V V V V 0 V V V V0 V Y V Y V Y V Y V Y V Y0 V Y V Y V Y V0 Y V V V V V V V V V V V V0 V V V V V V V0 V V U V U V U V U V U V U0 V U V U V U V0 U V R V R V R V R V R V R0 V R V R V R V0 R V P V P V P V P V P V P0 V P V P V P V00 P VTT0_ F0 VTT0_ E0 VTT0_ 0 VTT0_ 0 VTT0_ Y0 VTT0_ W0 VTT0_ U0 VTT0_0 T0 VTT0_ J VTT0_ J VTT0_ H VTT0_ H VTT0_ H VTT0_ H0 VTT0_ J VTT0_ J VTT0_ H VTT0_ H VTT0_ G VTT0_0 G VTT0_ G VTT0_ G VTT0_ F VTT0_ F VTT0_ F VTT0_ F VTT0_ E VTT0_ E VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VSS_SENSE J VTT0_ J VTT0_ J 0U 0U + 0U. + 0U. 0U 0U U U R K R K R0 *K_N R0 *K_N T0 T0 *0U_N *0U_N *U_N *U_N 0U 0U U U R K R K *U_N *U_N R *K_N R *K_N U U U U *0U_N *0U_N 0 *0U_N 0 *0U_N *0U_N *0U_N 0U 0U U U POWER GRPHIS VIs GRPHIS R -.V RILS FI PEG & MI SENSE LINES.V.V UG larksfield/uburndale POWER GRPHIS VIs GRPHIS R -.V RILS FI PEG & MI SENSE LINES.V.V UG larksfield/uburndale GFX_VI[0] M GFX_VI[] P GFX_VI[] N GFX_VI[] P GFX_VI[] M GFX_VI[] P GFX_VI[] N GFX_VR_EN R GFX_PRSLPVR T GFX_IMON M VXG_SENSE R VSSXG_SENSE T VXG T VXG T VXG T VXG T VXG R VXG R VXG R VXG R VXG P VXG0 P VXG P VXG P VXG N VXG N VXG N VXG N VXG M VXG M VXG M VXG0 M VXG L VXG L VXG L VXG L VXG K VXG K VXG K VXG K VXG J VXG0 J VXG J VXG J VXG H VXG H VXG H VXG H VTT_ J VTT_ J VTT_ H VTT_ K VTT_ J VTT_0 J VTT_ J VTT_ H VTT_ G VTT_ G VTT_ G VTT_ F VTT_ E VTT_ E VQ J VQ F VQ E VQ E VQ VQ VQ VQ Y VQ W VQ0 W VQ U VQ T VQ T VQ P VQ N VQ N VQ L VQ H VTT0_ P0 VTT0_0 N0 VTT0_ L0 VTT0_ K0 VPLL L VPLL L VPLL M VTT_ J VTT_ J0 VTT_ J VTT_ H VTT_ H0 VTT_ H R0 00/F R0 00/F R K R K.U/.V.U/.V 0U 0U U U + *0U_N. + *0U_N. R K R K 0U 0U 0U 0U U U R *K_N R *K_N U U *U_N *U_N *U_N *U_N R K R K *U_N *U_N 0U 0U *0U_N *0U_N U U U U 0 U 0 U R.K/F R.K/F R *K/F_N R *K/F_N + *0U_N + *0U_N R *K_N R *K_N 0 *0U_N 0 *0U_N U U *0U_N *0U_N 0U 0U U U U U R 00/F R 00/F R *K_N R *K_N U U 0U 0U U U T T 0U 0U *U_N *U_N *U_N *U_N 0U 0U *0U_N *0U_N U U 0U 0U 0 U 0 U U U U U R K R K + 0U + 0U T0 T0 U U 0U 0U 0 0U 0 0U U U U U U U + 0U. + 0U. R *K_N R *K_N 0U 0U 0U 0U 0 U 0 U R *K_N R *K_N U U R0 K R0 K U U *0U_N *0U_N.U.U R *K_N R *K_N U U 0U 0U R K R K 0 U 0 U 0U 0U 0 U 0 U R K R K R *K_N R *K_N *0U_N *0U_N
UURNLE/LRKSFIEL PROESSOR (GN) UH UI UURNLE/LRKSFIEL PROESSOR( RESERVE, FG) UE T0 T R R R R R R0 R R R R R R P0 P P P0 P P P N N N N0 N M M M M0 M M M M M M L L L L0 L L L L L K K K K0 K J J J0 J J J J J J H H H H H H0 H H H H H0 H H H H H G0 F F F E VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS00 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 E E E E E0 E E E E E 0 0 0 Y Y Y W W W W W W0 W W W W W V0 U U U T T T T T T0 T T T T T R0 P P P N N N N N N0 N N N N N M0 L L L L L L K K K0 K K K K J J0 J J H H H H H H H H H H H H H G G G0 G G G F0 F F F F F E E E E E E E E E E E 0 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS00 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF T T R +M_VREF_Q_IMM0 +M_VREF_Q_IMM T P T P T P T P R0 R FG0 FG FG FG *0_NTP_RSV_R *0_NTP_RSV_R P RSV L RSV L RSV L RSV J RSV G RSV M RSV L RSV J S_IMM_VREF H S_IMM_VREF G RSV G RSV E RSV E0 RSV M0 FG[0] M FG[] P FG[] L FG[] L0 FG[] M FG[] N FG[] M FG[] K FG[] K FG[] K FG[0] J FG[] N0 FG[] N FG[] J FG[] J FG[] J0 FG[] K0 FG[] H RSV_TP_ RSV RSV 0 RSV 0 RSV U RSV T RSV0 RSV RSV RSV_NTF_ RSV_NTF_ J RSV J RSV RSV_NTF_ RSV_NTF_ RSV_NTF_0 RSV_NTF_ larksfield/uburndale RESERVE RSV RSV RSV RSV RSV RSV_NTF_ RSV RSV RSV_NTF_0 RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV RSV_TP_ RSV_TP_0 KEY RSV RSV RSV RSV RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_0 RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_0 RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ VSS J J H K L R J J P T T R L L P0 P L T T P R T T P R R E F J H RSV_R RSV_R R R *0_N *0_N No need to pull down RSV,,, &, these resistors are for intel internal test only. R R G E V V N W W N E P an be left N is Intel RM R implementation; ES/G SJ_00 recommendation to GN larksfield/uburndale larksfield/uburndale The larkfield processor's PI Express interface may not meet PI Express.0 jitter specifications. Intel recommends placing a.0k +/- % pull down resistor to VSS on FG[] pin for both rpg and G components. This pull down resistor should be removed when this issue is fixed. UURN / QUNT OMPUTER Size ocument Number Rev UM/UM ate: Wednesday, September 0, 00 Sheet of
IEX PEK-M (MI,FI,GPIO) [] MI_RXN0 [] MI_RXN [] MI_RXN [] MI_RXN [] MI_RXP0 [] MI_RXP [] MI_RXP [] MI_RXP [] MI_TXN0 [] MI_TXN [] MI_TXN [] MI_TXN [] MI_TXP0 [] MI_TXP [] MI_TXP [] MI_TXP +.0V_PH [,] PH_PWRG [] PM_RM_PWRG [] IH_RSMRST# [] SUS_PWR_K [] SIO_PWRTN# [] _PRESENT R0./F MI_ZOMP XP_RESET# LN_RST# IH_RSMRST# PM_TLOW# PM_RI# +.V_RUN U MI0RXN J MIRXN W0 MIRXN J0 MIRXN MI0RXP G MIRXP 0 MIRXP G0 MIRXP E MI0TXN F MITXN 0 MITXN E MITXN MI0TXP H MITXP 0 MITXP MITXP H MI_ZOMP F MI_IROMP T SYS_RESET# M SYS_PWROK PWROK K MEPWROK 0 LN_RST# RMPWROK RSMRST# M P PWRTN# P PRESENT / GPIO TLOW# / GPIO F RI# IbexPeak-M_RP0 MI System Power Management SUS_PWR_N_K / GPIO0 FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN WKE# LKRUN# / GPIO SUS_STT# / GPIO SUSLK / GPIO SLP_S# / GPIO SLP_S# SLP_S# SLP_M# TP PMSYNH SLP_LN# / GPIO H J E F G W J F H J G J PIE_WKE# Y LKRUN# P RSV_LPP# F IH_SUSLK E SIO_SLP_S# H SLP_S#_R P SIO_SLP_S# K SLP_M#_R N J0 F PM_SLP_LN#_R FI_TXN0 [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXP0 [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_INT [] SIO_SLP_S# [] [] PNEL_KEN [] ENV [] [] L_LK [] L_T PIE_WKE# [] LKRUN# [] T T T T T [] [] [] L_0+ L_+ L_+ T P [] [] [] [] [] [] [] VGHSYN [] VGVSYN I_PWM [] L_LK- [] L_LK+ FI_FSYN0 [] [] L_LK- [] L_LK+ FI_FSYN [] [] L_0- FI_LSYN0 [] [] L_- [] L_- FI_LSYN [] T P L_0- L_- L_- T P L_0+ L_+ L_+ T P [] VG_LU [] VG_GRN [] VG_RE [] G_LK_ SIO_SLP_S# [] [] G_T_ PM_SYN [] T PNEL_KEN ENV L_LK L_T L_TRL_LK L_TRL_T R.K LVS_VG P LVS_T# LVS_T LVS_T# LVS_T VG_LU VG_GRN VG_RE R R R K For UM HMI Function IEX PEK-M (LVS,I) U T L_KLTEN T L_V_EN Y L_KLTTL L LK Y L T L_TRL_LK V L_TRL_T P LV_IG P LV_VG T LV_VREFH T LV_VREFL V LVS_LK# V LVS_LK LVS LVS_T#0 LVS_T# Y LVS_T# V LVS_T# LVS_T0 0 LVS_T Y LVS_T V LVS_T P LVS_LK# P LVS_LK Y LVS_T#0 T LVS_T# U LVS_T# T LVS_T# Y LVS_T0 T LVS_T U0 LVS_T T LVS_T RT_LUE RT_GREEN RT_RE V RT LK V RT T Y RT_HSYN Y RT_VSYN _IREF RT_IRTN RT IbexPeak-M_RP0 igital isplay Interface SVO_TVLKINN J SVO_TVLKINP G SVO_STLLN J SVO_STLLP G SVO_INTN F SVO_INTP H SVO_TRLLK T SVO_TRLT T P_UXN G P_UXP J P_HP U P_0N P_0P P_N J P_P G P_N 0 P_P 0 P_N W P_P P_TRLLK Y P_TRLT P_UXN E P_UXP P_HP V0 P_0N E0 P_0P 0 P_N F P_P H P_N P_P P_N P_P P_TRLLK U0 P_TRLT U P_UXN P_UXP P_HP T P_0N J0 P_0P G0 P_N J P_P G P_N F P_P H P_N E P_P M_HMI_SL M_HMI_S R R P_HP_Q P_LNE0_N P_LNE0_P P_LNE_N P_LNE_P P_LNE_N P_LNE_P P_LNE_N P_LNE_P +V_RUN *K_N *K_N Q N00K-T-E M_HMI_SL [] M_HMI_S [] +.0V_PH isplay port isplay port isplay port SVO LKRUN# L_T L_LK L_TRL_LK L_TRL_T XP_RESET# PM_RI# PM_TLOW# PIE_WKE# R 0K/F R.K R0.K R 0K/F R 0K/F R 0K/F +.V_SUS R 0K/F R.K/F R K PH_PWRG IH_RSMRST# LN_RST# R R00 R 0K/F 0K/F 0K/F lose to VG side VG_LU VG_GRN VG_RE R R R 0/F 0/F 0/F PNEL_KEN R 00K ENV R 00K +.V_RUN P_LNE0_N P_LNE0_P P_LNE_N P_LNE_P P_LNE_N P_LNE_P P_LNE_N P_LNE_P R.K R.K 0 0.U 0 0.U 0.U 0.U 0.U 0.U 0.U 0.U M_HMI_SL M_HMI_S HMI_T_N [] HMI_T_P [] HMI_T_N [] HMI_T_P [] HMI_T0_N [] HMI_T0_P [] HMI_LK_N [] HMI_LK_P [] P_HP_Q R 00K IEX PEK-M / QUNT OMPUTER M_HMI_HP [] Size ocument Number Rev UM/UM ate: Friday, October 0, 00 Sheet of
+RT_ELL [] [] [,] [] IH_Z_OE_ITLK IH_Z_OE_SYN IH_Z_OE_RST# IH_Z_OE_SOUT +.V_RUN SPKR R *K_N +.V_SUS Res. of TI near PH R0 PH_JTG_TMS PH_JTG_TI PH_JTG_TO PH_JTG_RST# N all Res. when PH is production stage. Z_IT_LK Z_SYN Z_RST# Z_SOUT Place all series terms close to PH except for SIN input lines,which should be close to source.placement of R, R, R & R should equal distance to the T split trace point. asically, keep the same distance from T for all series termination resistors. R 00 R 00 R 00 R 00 R 00 R 00 R 0K R 0K R *P_N 0 R R No Reboot strap. SPKR R M Low = efault. High = No Reboot. Res. of TO PH ES stage : N PH ES stage : pop R0 R 0K/F 0K/F Flash escriptor Security Override GPIO U Low = Enabled High = isabled PH_JTG_TK_UF +RT_ELL INTVRMEN(Internal Voltage Regulator Enable) : This signal enables the internal.0 V regulators. This signal must be always pulled-up to VccRT. Note : GPIO is a signal used for Flash escriptor Security Override/ME ebug Mode.This signal should be only asserted lowthrough an external pull-down in manufacturing or debug environments ONLY. R U Note : Only pop when PH is production stage & need "JTG boundary Scan". Remember to depop XP side Res. [] ap values depend on Xtal [] P/0V Y.KHZ P/0V R0 IH_Z_OE_SIN0 SPKR [] [] [] [] T T T0 T T T T SPI JTG IH RT ST LP 0K SPI_LK SPI_S0# SPI_SI SPI_SO Z_SYN SPKR RT_X RT_X Z_IT_LK Z_RST# Z_SOUT GPIO RT_RST# PH_JTG_TK_UF PH_JTG_TMS PH_JTG_TI SRT_RST# SM_INTRUER# PH_INVRMEN PH_JTG_TO PH_JTG_RST# SPI_LK SPI_S0# SPI_S# SPI_SI SPI_SO JTG Test Pads are need to put on the same side of mother board. T R0 0M IEX PEK-M (H,JTG,ST) 0 P 0 G0 F0 E F H J0 M K K J J V Y Y V U RTX RTX RTRST# SRTRST# INTRUER# INTVRMEN H_LK H_SYN SPKR H_RST# H_SIN0 H_SIN H_SIN H_SIN H_SO H_OK_EN# / GPIO H_OK_RST# / GPIO JTG_TK JTG_TMS JTG_TI JTG_TO TRST# SPI_LK SPI_S0# SPI_S# SPI_MOSI SPI_MISO IbexPeak-M_RP0 +.V_RUN FWH0 / L0 FWH / L FWH / L FWH / L FWH / LFRME# LRQ0# LRQ# / GPIO SERIRQ ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STIOMPO STIOMPI STLE# ST0GP / GPIO STGP / GPIO R0 F K K K K H H H H F F F F H H F F F F T Y V ST port / are not support in HM. They are only in PM SPI_SI ST_OMP itpm ENLE/ISLE *K_N R R TPM Function Enable isable R R 0K/F 0K/F./F 0K/F LP_L0 [,0] LP_L [,0] LP_L [,0] LP_L [,0] LP_LFRME# [,0] IRQ_SERIRQ [] ST_RX0- [] ST_RX0+ [] ST_TX0- [] ST_TX0+ [] ST_RX- [] ST_RX+ [] ST_TX- [] ST_TX+ [] +.0V_PH +.V_RUN S p i T n T # P G c Mount o N n P (efault) n G e c t ST_T# [] t o E +.V_RUN ST H ST O istance between the PH and cap on the "P" signal should be identical distace between the PH and cap on the "N" signal for the same pair. IEX PEK-M / QUNT OMPUTER Size ocument Number Rev UM/UM Friday, October 0, 00 ate: Sheet of
[0] [] [0] LK_LP_EUG R LK_PI_0 LK_PI_F R LKOUT_PI[0..]: ohm series resistor is recommend (single & double load) on PG v. LK_LP_EUG LK_PI_0 US_MR_ET# [0] T_ET# PIRST#: G(V.0) P an be left unconnected. PR: S(V.0) P an be left unconnected if not using PI. PME: G(V.0) P an be left unconnected. 0 Reserve capacitor pads for improving WWN. T T T0 T T T T T T T R PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_REQ0# HMI_PWR_TRL S_WWN_PIE_RST# US_MR_ET# GNT0# GNT# GNT# GNT# PH_IRQH_GPIO S_WLN_PIE_RST# T_ET# PH_IRQH_GPIO PI_RST# PI_SERR# PI_PERR# PI_IRY# PI_EVSEL# PI_FRME# PI_PLOK# PI_STOP# PI_TRY# PME# IEX PEK-M (PI,US,NVRM) PI_PLTRST# LK_LP_EUG_ LK_PI_0_ LK_PI_F_ H0 N J 0 E H E0 0 M M F M0 M J K F0 K M J K L F J0 G F M H J0 G H G G H F M F K F H K K E E0 H F M N P P P P UE 0 0 0 0 /E0# /E# /E# /E# PIRQ# PIRQ# PIRQ# PIRQ# REQ0# REQ# / GPIO0 REQ# / GPIO REQ# / GPIO GNT0# GNT# / GPIO GNT# / GPIO GNT# / GPIO PIRQE# / GPIO PIRQF# / GPIO PIRQG# / GPIO PIRQH# / GPIO PIRST# SERR# PERR# IRY# PR EVSEL# FRME# PLOK# STOP# TRY# PME# PLTRST# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI IbexPeak-M_RP0 +.V_SUS US_IS RSV_SMLERT# 0K/F R RSV_IH_L_RST# 0K/F R IH_SMLK.K/F R IH_SMT.K/F R0 +.V_RUN SM_LK_ME0.K/F R 0 SM_T_ME0.K/F R T_ET# R.K/F *P_N SM_LK_ME.K/F R0 PH_IRQH_GPIO R0.K/F 0 SM_T_ME.K/F R0 S_WWN_PIE_RST# R.K/F *P_N LP_SPI_INTR# 0K/F R S_WLN_PIE_RST# R0.K/F PI NVRM US NV_E#0 NV_E# NV_E# NV_E# NV_QS0 NV_QS NV_Q0 / NV_IO0 NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q0 / NV_IO0 NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_LE NV_LE NV_ROMP NV_R# NV_WR#0_RE# NV_WR#_RE# NV_WE#_K0 NV_WE#_K USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP0N USP0P USPN USPP USPN USPP USPN USPP USRIS# USRIS O0# / GPIO O# / GPIO0 O# / GPIO O# / GPIO O# / GPIO O# / GPIO O# / GPIO0 O# / GPIO Y P V G P P T T V E J J G Y U V Y Y V F H J N0 P0 J0 L0 F0 G0 0 0 M N H J E F G H L M N J F L E G F T O0# O# O# O# O# O# O# O# NV_LE [0] NV_LE [0] IH_USP0- [] IH_USP0+ [] IH_USP- [] IH_USP+ [] IH_USP- [] IH_USP+ [] IH_USP- [] IH_USP+ [] IH_USP- [0] IH_USP+ [0] IH_USP- [] IH_USP+ [] IH_USP- [0] IH_USP+ [0] IH_USP- [] IH_USP+ [] amera IH_USP- [] IH_USP+ [] ard reader O0# [] O# [] O0#~O#: G(V.0)P Pin efault Port Mapping O0# Port0,Port O# Port,Port Right Side pair to Right Side pair to Left Side pair Left Side pair for " Mini ard (WLN) Mini ard (WWN) Mini ard (WPN) Express ard Note : place these resistors near to PIe Slots Place TX blocking caps close PH. MiniWWN MiniWLN LOM US port / are not support in HM. They are only in PM R./F +.V_SUS +.V_RUN [] [] [] [] MiniWLN MiniWWN 0/00 LOM [] [] [] [] [0] [0] [0] [0] PIE_RX- PIE_RX+ PIE_TX- PIE_TX+ PIE_RX- PIE_RX+ PIE_TX- PIE_TX+ PIE_RX-/GLN_RX- PIE_RX+/GLN_RX+ PIE_TX-/GLN_TX- PIE_TX+/GLN_TX+ [0] [0] [] [] [] [] [] PIE lock Request R R R R R 0K 0K 0K 0K 0K LK_PIE_MINI# LK_PIE_MINI [0] MINILK_REQ# LK_PIE_MINI# LK_PIE_MINI MINILK_REQ# LK_PIE_LOM# LK_PIE_LOM [] LOM_LK_REQ# MINILK_REQ# R_LK_REQ# LK_PIE_REQ# LK_PEG0_REQ# LOM_LK_REQ# 0.U 0.U 0.U 0.U 0.U 0.U LK_PIE_REQ# PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ LK_PEG0_REQ# MINILK_REQ# LK_PIE_REQ# MINILK_REQ# R_LK_REQ# LOM_LK_REQ# IEX PEK-M (PI-E,SMUS,LK) G0 J0 F H W0 0 0 0 U0 T0 U V E F H G J W T U U V G J G J K K P M M U M M N H H M M M J0 J H K K P U PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIE0N LKOUT_PIE0P LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP PI-E* PIELKRQ0# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO0 PIELKRQ# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P PEG LKRQ# / GPIO From LK UFFER lock Flex SMus IbexPeak-M_RP0 LKOUT_PEG P/N,LKOUT_PEG P/N, LKOUT_MI_P/N,support GEN- and GEN- ontroller PEG Link SMLERT# / GPIO SMLK SMT SML0LERT# / GPIO0 SML0LK SML0T SMLLERT# / GPIO SMLLK / GPIO SMLT / GPIO L_LK L_T L_RST# PEG LKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N / LKOUT_LK_N LKOUT_P_P / LKOUT_LK_P LKIN_MI_N LKIN_MI_P LKIN_LK_N LKIN_LK_P LKIN_OT_N LKIN_OT_P LKIN_ST_N / KSS_N LKIN_ST_P / KSS_P REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT XLK_ROMP LKOUTFLEX0 / GPIO LKOUTFLEX / GPIO LKOUTFLEX / GPIO LKOUTFLEX / GPIO H J G M E0 G T T T H N N T T W P P F E H H P J H H F T P T N0 RSV_SMLERT# IH_SMLK IH_SMT RSV_IH_L_RST# SM_LK_ME0 SM_T_ME0 LP_SPI_INTR# SM_LK_ME SM_T_ME PEG_LKREQ# LK_PI_F XTL_IN XTL_OUT XLK_ROMP R LK_FLEX0 LK_FLEX LK_FLEX LK_FLEX R T T T T LKOUTFLEX: ES(V.0) :support MHz MHz and.mhz. T IH_SMLK [0] IH_SMT [0] SML0LK/SML0T: G(V.) P: The SMus signals (SM_T and SM_LK) cannot be connected to any other devices other than the PH. onnect the SM_T and SM_LK pins to the PH SML0T and SML0LK pins, respectively. LK_PIE_GPLL# [] LK_PIE_GPLL [] REFSSLK# [] REFSSLK [] LK_UF_PIE_GPLL# [] LK_UF_PIE_GPLL [] LK_UF_LK_N [] LK_UF_LK_P [] LK_UF_REFLK# [] LK_UF_REFLK [] LK_ST_REFSSLK# [] LK_ST_REFSSLK [] LK_IH_M [] XTL_OUT XTL_IN LKOUTFLEX[0..]: PG v.: ohm series resistor is recommend (PI & non PI routing, single & double load) T T LKIN_PILOOPK: PG (V.): ohm series resistor is recommend 0 0./F *0_N P 0 NPO +.0V_PH R M Y MHz P 0 NPO Non-iMT PEG_LKREQ# 0K/F dd uffers as needed for Loading and fanout concerns. R0 O# O# O# O# +.V_SUS RP 0 0PR-.K O# O# O# O0# +.V_SUS R R 0K 0K MINILK_REQ# LK_PIE_REQ# PIELKRQ{0,,,,,}# should have a 0K pull-up to +V..PIELKRQ{,} should have a 0K pull-up to +.S +.V_SUS PI_PLTRST# +.V_SUS *0.0U_N 0 R U *TSZFU(TL,F,T)_N SJ_00 PLTRST# [,,,0,] PH_IRQH_GPIO PI_REQ0# PI_PIRQ# US_MR_ET# +.V_RUN PI_STOP# PI_PIRQ# PI_PIRQ# PI_IRY# +.V_RUN RP 0 0PR-.K RP 0 0PR-.K +.V_RUN PI_TRY# PI_FRME# HMI_PWR_TRL PI_PIRQ# +.V_RUN PI_SERR# PI_PERR# PI_PLOK# PI_EVSEL# SM_LK_ME SM_T_ME +.V_SUS Q N00W--F Q N00W--F SMLK [] SMT [] QUNT OMPUTER IEX PEK-M / Size ocument Number Rev UM/UM ate: Friday, October 0, 00 Sheet of
UF IEX PEK-M (GPIO,VSS_NTF,RSV) +.V_SUS [0] PIE_MR_ET# [] SIO_EXT_WKE# S_GPIO SIO_EXT_SMI# SIO_EXT_SI# SIO_EXT_WKE# LN_PHY_PWR_TRL K PIE_MR_ET# [] PIE_MR_ET# GPIO register not cleared by Fh reset event. [0] T_RIO_IS# [] WWN_RIO_IS# [] RIT_TEMP_REP# [] SIO_EXT_SMI# [] SIO_EXT_SI# GPIO reserve for internal VR. R [] US_MR_ET# R R [0] WLN_RIO_IS# T0 0K/F *0K_N US_MR_ET# T_RIO_IS# GPIO GPIO WWN_RIO_IS# GPIO GPIO TP_PH_GPIO STGP STGP GPIO WLN_RIO_IS# RIT_TEMP_REP# Y J F0 T STGP SJ_00 PIE_MR_ET#_R F Y H0 V M V V P H F F MUSY# / GPIO0 TH / GPIO TH / GPIO TH / GPIO GPIO GPIO GPIO GPIO GPIO GPIO MIS LN_PHY_PWR_TRL / GPIO GPIO STGP / GPIO TH0 / GPIO SLOK / GPIO STP_PI# / GPIO STLKREQ# / GPIO STGP / GPIO STGP / GPIO SLO / GPIO STOUT0 / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO STOUT / GPIO STGP / GPIO PU LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP 0GTE LKOUT_LK0_N / LKOUT_PIEN LKOUT_LK0_P / LKOUT_PIEP PEI RIN# PROPWRG THRMTRIP# TP TP TP TP TP TP TP TP TP H H F F U M M G0 T E0 0 W Y Y V V F M PH_THRMTRIP#_R R /F SIO_0GTE [] LK_PU_LK# [] LK_PU_LK [] H_PEI [] SIO_RIN# [] H_PWRGOO [] (oth these should be close to PH) +.0V_VTT R /F H_THERM [] TP_PH_GPIO R GPIO R GPIO R GPIO R LN_PHY_PWR_TRL R SIO_EXT_SMI# R SIO_EXT_SI# R SIO_EXT_WKE# R PIE_MR_ET# R PIE_MR_ET#_R R0 WLN_RIO_IS# R T_RIO_IS# R SIO_RIN# R SIO_0GTE R STGP R RIT_TEMP_REP# R STGP R STGP R US_MR_ET# R 0K/F 0K/F 0K/F 0K/F 0K/F +.V_RUN 0K/F 0K/F 0K/F 0K/F 0K/F 0K/F 0K/F 0K/F 0K/F 0K/F 0K/F 0K/F 0K/F 0K/F TP0 N VSS_NTF_ VSS_NTF_ VSS_NTF_ 0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 E VSS_NTF_ E VSS_NTF_ F VSS_NTF_ F VSS_NTF_ H VSS_NTF_ H VSS_NTF_ H VSS_NTF_ H VSS_NTF_ J VSS_NTF_ J VSS_NTF_0 J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J0 VSS_NTF_ J VSS_NTF_ J VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ E VSS_NTF_0 E VSS_NTF_ IbexPeak-M_RP0 NTF RSV TP TP TP TP TP TP TP TP TP N_ N_ N_ N_ N_ INIT_V# TP J K K M N M0 N0 H T P 0 MI Termination Voltage Set to Vcc when LOW NV_LE Set to Vcc/ when HIGH R *K_N [] NV_LE R *K_N [] NV_LE anbury Technology Enabled High = Enable NV_LE Low = isable +NVRM_VQ +.V_RUN WWN_RIO_IS# S_GPIO WWN_RIO_IS# R R 0K/F 0K/F -X High = Strong (efault) MUSY#: If not used, require a weak pull-up (.- KΩ to 0 kω) to Vcc_. R(V.0)P: it has K PU and 00 ohm on this net for validation purpose. MUSY#:(Intel feedback) Follow R checklist, K is for intel IOS validation purpose. IEX PEK-M / QUNT OMPUTER Size ocument Number Rev UM/UM ate: Friday, October 0, 00 Sheet 0 of
IEX PEK-M (POWER) +.0V_PH VPLLEXP = 00m max +.0V_PH =.0 max +.0V_PH V_ = 0. max +.0V_PH VORE=. max +.0V_PH 0U 0 U F 0 F F0 F H H H0 H J0 J +.0V_PH VPLLEXP: This pin can be left as no connect in On-ie VR enabled mode (default). VFIPLL = 00m max L L 0U 0 0 U +.V_RUN *uh_n *uh_n 0.U 0 U +.0V_LN_VPLL_EXP VVRM = 0.0 max +.VS_.VS +.0V_VFIPLL +.0V_PH M *0U_N VIO =.0 max +.0V_PH 0 *0U_N U U K J N0 N N N N N J J T T U U V V W W E E G G H N0 N N T J +.0V_PH +.V_RUN +.V_RUN +.V_RUN UG VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[0] VORE[] VORE[] VORE[] VORE[] VORE[] VIO[] VPLLEXP VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] V_[] VVRM[] VFIPLL VIO[] IbexPeak-M_RP0 R R POWER V ORE PI E* FI *0_N *0_N +.V_VPLL +.V_VPLL RT LVS HVMOS MI NN / SPI +.VS_.VS SJ_00 +NVRM_VQ V[] V[] VSS_[] VSS_[] VLVS VSS_LVS VTX_LVS[] VTX_LVS[] VTX_LVS[] VTX_LVS[] V_[] V_[] V_[] VVRM[] VMI[] VMI[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VME_[] VME_[] VME_[] VME_[] PH ES(V.0) P +NVRM_VQ:. V supply for ual hannel NN interface. This power is supplied by core well. If unused, this pin should be connected to Vcc_. L L R R R0 0uH 0uH *0_N + 0U SJ_00 E0 E F F H H P P T T T T U M K K0 K K K M M M M M P P +V 0.U +.V_RUN +.V_RUN VVRM = 0.0 max +.VS_.VS VPNN = 0. max +NVRM_VQ VME_ = 0.0 max +.V_RUN +.0V_PH VLK = 00m max L *0uH_N +.V_LN_V_LK VME =. max +.0V_PH +.0V_PH +.V_RUN V_ = 0. max SJ_00 +.0V_VTT +.0V_PH VME_: ES(V.0)P:supply for the Intel Management Engine.This is a separate power plane that may or may not be powered in S S states. This plane must be on in S0 and other times the Intel Management Engine is used. U L VMI = 0.0 max R U 0.U 0.U 0.0U 0 0.0U 0.U 00 0.0U R 0U. U *0_N U 0 0.uH L LMPGSN U U +.VS_.VS +.V_RUN PSUSYP PRT VPLL = 0.0 max +.V_VPLL VPLL = 0.0 max +.0V_PH +.V_SUS +.V_RUN +.0V_VTT +RT_ELL +.V_VPLL VIO =.0 max PSST PSUS VSUS_ = 0. max V_ = 0. max V_PU>m.U U 0 U U 0.U 0.U 0 *0U_N 0.U 00 U 0.U U 0.U 0 U 0.U 0.U 0.U V = 00m max 0 0.U *U_N 0 0.U P P F F Y0 F F F V V V Y Y Y V U H J H F H F V Y P U U0 U V V Y T U UJ VLK[] VLK[] VLN[] VLN[] PSUSYP VME[] VME[] VME[] VME[] VME[] VME[] VME[] VME[] VME[] VME[0] VME[] VME[] PRT VVRM[] VPLL[] VPLL[] VPLL[] VPLL[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] PSST PSUS VSUS_[] VSUS_[0] VSUS_[] VSUS_[] V_[] V_[] V_[] V_PU_IO[] V_PU_IO[] VRT IbexPeak-M_RP0 POWER lock and Miscellaneous RT PU PI/GPIO/LP ST PI/GPIO/LP US H VIO[] VIO[] VIO[] VIO[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VIO[] VREF_SUS VREF V_[] V_[] V_[0] V_[] V_[] V_[] V_[] VSTPLL[] VSTPLL[] VIO[] VVRM[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VME[] VME[] VME[] VME[] VSUSH V V Y Y V U U U P P N N M M L L J J H H G G F F E E U V F K J L M N P U K K H T0 H 0 F F0 F H0 0 Y Y L0 +VREF_SUS +VREF 0 *U_N 0.U +.0V_PH U 0.U 0.U +.VS_.VS +.0V_PH +.0V_VSTPLL VVRM = 0.0 max U U U R 0.U *0U_N +.0V_PH +.V_SUS VIO =.0 max R0 00 +.V_RUN VIO =.0 max VME =. max R 00 SJ_00 U L0 SM0K--F SM0K--F +.V_SUS VIO =.0 max VSUS_ = 0. max +V_SUS +.V_SUS +V_RUN +.V_RUN V_ = 0. max *0uH_N VREF_SUS>m VREF>m +.0V_PH +.0V_PH VSUSH = m max + 0 0U U VRT = m max IEX PEK-M / QUNT OMPUTER Size ocument Number Rev UM/UM Wednesday, September 0, 00 ate: Sheet of
Size ocument Number Rev ate: Sheet of QUNT OMPUTER UM/UM IEX PEK-M / Wednesday, September 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER UM/UM IEX PEK-M / Wednesday, September 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER UM/UM IEX PEK-M / Wednesday, September 0, 00 IEX PEK-M (GN) UI IbexPeak-M_RP0 UI IbexPeak-M_RP0 VSS[] Y VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] G VSS[] VSS[] VSS[] 0 VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[0] VSS[] H VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E0 VSS[] E VSS[] E0 VSS[00] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E0 VSS[0] E VSS[0] E VSS[0] F VSS[0] F VSS[0] F VSS[] G VSS[] G VSS[] G VSS[] G0 VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] VSS[] 0 VSS[] VSS[] E VSS[] E VSS[0] E0 VSS[] E VSS[] E0 VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] L0 VSS[] L VSS[] M VSS[] M VSS[] M0 VSS[] N VSS[] M VSS[] M VSS[0] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] P VSS[] P VSS[] P0 VSS[0] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[00] T VSS[0] T VSS[0] T VSS[0] U0 VSS[0] U VSS[0] U VSS[0] U VSS[0] P VSS[0] V VSS[0] P VSS[0] V VSS[] V0 VSS[] V VSS[] V0 VSS[] V VSS[] V VSS[] V VSS[] E VSS[] E VSS[0] F VSS[] F VSS[] G0 VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G0 VSS[0] G VSS[] G VSS[] V VSS[] V VSS[] V VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y0 VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] P VSS[] P VSS[] VSS[] F VSS[] H VSS[] H0 VSS[] H0 VSS[] H VSS[] H VSS[] H VSS[] T VSS[] VSS[] T VSS[] VSS[0] Y VSS[] T VSS[] M VSS[] T VSS[] M VSS[] K VSS[] K VSS[] V VSS[] K VSS[] K VSS[] H VSS[0] H VSS[] J UH IbexPeak-M_RP0 UH IbexPeak-M_RP0 VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] F VSS[] F VSS[] P VSS[] F VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] J VSS[] J VSS[] J0 VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[0] J VSS[] T VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[0] K0 VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[0] K VSS[] L VSS[] L VSS[] M VSS[] M0 VSS[] M VSS[] M VSS[] M VSS[00] M VSS[0] M0 VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] U0 VSS[] M VSS[] V VSS[] M VSS[] M VSS[] 0 VSS[] N VSS[] N0 VSS[] N VSS[0] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] V VSS[] V VSS[] V0 VSS[] V VSS[0] V0 VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[0] W VSS[] F VSS[] W VSS[] W VSS[] W0 VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[0] Y VSS[] U VSS[] N VSS[] 0 VSS[0] VSS[] V VSS[] U VSS[] M VSS[] M VSS[] N VSS[] H VSS[] VSS[0] H VSS[0] VSS[] VSS[]
WLN_SMLK WLN_SMT M 0 M M M M M M 0 M M M M M M M M M M M0 M M M M M M M M M M M M M M M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q IMM0_S0 IMM0_S PM_EXTTS#0 WLN_SMLK [,,0] WLN_SMT [,,0] M [:0] [] M S0 [] M S [] M S [] M S0# [] M S# [] M LK0 [] M LK0# [] M LK [] M LK# [] M KE0 [] M KE [] M S# [] M RS# [] M WE# [] M QS[:0] [] M QS#[:0] [] M M[:0] [] M OT0 [] M OT [] M Q[:0] [] R_RMRST# [,] PM_EXTTS#0 [] +.V_SUS +R_VTTREF +SMR_VREF_Q0 +.V_SUS +.V_RUN +0.V_R_VTT +SMR_VREF_IMM0 +.V_RUN +.V_SUS +0.V_R_VTT +SMR_VREF_IMM0 +SMR_VREF_Q0 +SMR_VREF_IMM0 +.V_SUS +SMR_VREF_Q0 +M_VREF_Q_IMM0 +R_VTTREF Size ocument Number Rev ate: Sheet of QUNT OMPUTER UM/UM R IMM-0 Friday, October 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER UM/UM R IMM-0 Friday, October 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER UM/UM R IMM-0 Friday, October 0, 00 M VREF M VREF Place these aps near So-imm..U/.V/00.U/.V/00 0.U 0.U 0.U 0.U 0.U 0.U 0U 0 0 0U 0 0 R 0K/F_ R 0K/F_ R *0_N R *0_N U U 0.U 0.U 0U 0U 0U 0 0 0U 0 0 0 0U 0 0U R 0K/F_ R 0K/F_ R K/F R K/F U U R *0_N R *0_N 0 U 0 U 0 0U 0 0 0 0U 0 0.U/.V/00.U/.V/00 P00 R SRM SO-IMM (0P) JIM S0-JSG-H P00 R SRM SO-IMM (0P) JIM S0-JSG-H V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 G G G G R K/F R K/F 0U 0U 0.U 0.U R0 K/F R0 K/F 0.U 0.U 0.U 0.U R0 *0_N R0 *0_N 0 0.U 0 0.U 0 0U 0 0U U U R K/F R K/F 0U 0U 0.U/.V/00 0.U/.V/00 0U 0U + 0U. + 0U. P00 R SRM SO-IMM (0P) JIM S0-JSG-H P00 R SRM SO-IMM (0P) JIM S0-JSG-H 0 0 0/P 0 /# 0 0 0 0 S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q 0 0.U 0 0.U 0.U 0.U R SJ_00 R SJ_00
M M M M Q M QS# M Q M Q M Q M Q M M QS IMM_S WLN_SMLK WLN_SMT M M M M QS# M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M M QS M Q0 M 0 M M M QS# M Q M Q M Q M M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M QS M M M M M M QS# M Q M M QS M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M M M M M QS# M Q M QS M 0 M Q0 M Q M Q M Q M M M M QS# M Q M QS M M QS0 M M0 M M QS# M M Q M QS#0 IMM_S0 M PM_EXTTS# M QS WLN_SMLK [,,0] WLN_SMT [,,0] M [:0] [] M S0 [] M S [] M S [] M S0# [] M S# [] M LK0 [] M LK0# [] M LK [] M LK# [] M KE0 [] M KE [] M S# [] M RS# [] M WE# [] M QS[:0] [] M QS#[:0] [] M M[:0] [] M OT0 [] M OT [] M Q[:0] [] R_RMRST# [,] PM_EXTTS# [] +.V_SUS +R_VTTREF +M_VREF_Q_IMM +.V_SUS +.V_RUN +0.V_R_VTT +SMR_VREF_IMM +.V_RUN +.V_SUS +0.V_R_VTT +SMR_VREF_IMM +.V_RUN +SMR_VREF_Q +SMR_VREF_IMM +SMR_VREF_Q +SMR_VREF_Q +R_VTTREF +.V_SUS Size ocument Number Rev ate: Sheet of QUNT OMPUTER UM/UM R IMM- Friday, October 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER UM/UM R IMM- Friday, October 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER UM/UM R IMM- Friday, October 0, 00 Place these aps near So-imm. M VREF M VREF R *0_N R *0_N 0.U 0.U 0.U 0.U R0 *0_N R0 *0_N U U 0.U 0.U R K/F R K/F 0U 0 0 0U 0 0 U U 0.U 0.U 0U 0U.U/.V/00.U/.V/00.U/.V/00.U/.V/00 0U 0 0 0U 0 0 P00 R SRM SO-IMM (0P) JIM S0-NSN-H P00 R SRM SO-IMM (0P) JIM S0-NSN-H V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 G G G G 0U 0U.U/.V/00.U/.V/00 R K/F R K/F 0.U 0.U 00 0.U 00 0.U + *0U_N. + *0U_N. 0U 0U 0 0U 0 0 0 0U 0 0 0U 0U 0.U 0.U R *0_N R *0_N 0.U 0.U P00 R SRM SO-IMM (0P) JIM S0-NSN-H P00 R SRM SO-IMM (0P) JIM S0-NSN-H 0 0 0/P 0 /# 0 0 0 0 S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q 0 U 0 U 0U 0U R K/F R K/F 0 0.U 0 0.U R 0K/F_ R 0K/F_ R0 0K/F_ R0 0K/F_ 0 0U 0 0U 0 U 0 U R SJ_00 R SJ_00 R K/F R K/F 0.U 0.U
+.V_RUN L LMPG00SN 0 [] LK_IH_M +.V_RUN Realtek: 0.uFxpcs, ufxpcs IT: 0.uFxpcs, 0uFxpcs 0U 0 0.U 0.uF near the every power pin. LK_IH_M 0 0.U R 0.U 0K R 0mil 0.U 0 0.U +.V_LK_V +VIO_LK K_PWRG PU_SEL 0 U V_US V_L V_SR V_PU V_REF V_SR_IO V_PU_IO K0 QFN PU-0 PU-0# PU- 0 PU-# VSS_ST OTT_LPR VSS_US OT_LPR VSS_L VSS_SR SR- VSS_PU SR-# VSS_REF ST 0 ST# PU_STOP# MHz_nonSS K_PWRG/P#_. MHz_SS REF_0/PU_SEL LK_UF_LK_P LK_UF_LK_N LK_UF_REFLK LK_UF_REFLK# Place within 0." of LKGEN LK_UF_PIE_GPLL LK_UF_PIE_GPLL# LK_ST_REFSSLK LK_ST_REFSSLK# LK_UF_LK_P [] LK_UF_LK_N [] LK_UF_REFLK [] LK_UF_REFLK# [] LK_UF_PIE_GPLL [] LK_UF_PIE_GPLL# [] LK_ST_REFSSLK [] LK_ST_REFSSLK# [] Place the ohm resistors close to the K 0 [,] SMT [,] SMLK XTL_OUT XTL_IN SMT SMLK XOUT XIN ST SLK GN SLGSPVTR Realtek: 0.uFxpcs, ufxpcs IT: 0.uFxpcs, 0uFxpcs +.V_RUN +VIO_LK dd capacitor pads for improving WWN. 0 LK_IH_M XTL_IN Y XTL_OUT +.0V_PH R0 *0_N L LMPG00SN 0 0mil 0 *P_N 0 0 P 0.MHZ 0 P 0 R0 0 SLG,IT: +.0V Realtek: +.V 0U HP: 0u xpcs 0.U 0.U Place each 0.uF cap as close as possible to each V IO pin. Place the 0uF caps on the V_IO plane. +.V_RUN +VIO_LK: SLG date sheet (V0.) P: Min.0V,Max.V. Realtek date sheet(v.) P: Min.0V,Max.V. IT date sheet(v0.) P0: Min 0.V,Max.V. R *.K_N PU_SEL R.K 0 *0P/0V_N EMI apacitor PIN 0 PU_0 PU_ 0(default) MHz MHz (0.V-.V) 00MHz 00MHz PU_SEL: SLG date sheet (V0.) P: High Voltage: Min 0.V, Max.V. Low Voltage: Min Vss-0.V, Max 0.V. Realtek date sheet(v.) P: High Voltage: Min 0.V, Max.V. Low Voltage: Min Vss-0.V, Max 0.V. IT date sheet(v0.) P0: High Voltage: Min 0.V, Max.V. Low Voltage: Min Vss-0.V, Max 0.V. [] VR_PWRG_LKEN# +.V_RUN R 0K K_PWRG Q0 N00W--F lock Generator QUNT OMPUTER Size ocument Number Rev UM/UM ate: Friday, October 0, 00 Sheet of
LNK PGE FOR PGE NUMER SME S ISRETE QUNT OMPUTER VG-M-XT (PIe) Size ocument Number Rev UM/UM ate: Wednesday, September 0, 00 Sheet of
LNK PGE FOR PGE NUMER SME S ISRETE QUNT OMPUTER VG-M-XT (PIe) Size ocument Number Rev UM/UM Wednesday, September 0, 00 ate: Sheet of
LNK PGE FOR PGE NUMER SME S ISRETE QUNT OMPUTER VG-M-XT (PIe) Size ocument Number Rev UM/UM Wednesday, September 0, 00 ate: Sheet of
LNK PGE FOR PGE NUMER SME S ISRETE QUNT OMPUTER VG-M-XT (PIe) Size ocument Number Rev UM/UM Wednesday, September 0, 00 ate: Sheet of
LNK PGE FOR PGE NUMER SME S ISRETE QUNT OMPUTER VG-M-S (VRM) Size ocument Number Rev UM/UM Wednesday, September 0, 00 ate: Sheet of 0
LNK PGE FOR PGE NUMER SME S ISRETE QUNT OMPUTER VG-M-XT (PIe) Size ocument Number Rev UM/UM ate: Wednesday, September 0, 00 Sheet of
LNK PGE FOR PGE NUMER SME S ISRETE QUNT OMPUTER VG-M-XT (PIe) Size ocument Number Rev UM/UM ate: Wednesday, September 0, 00 Sheet of
HMI_TX+_L HMI_TX-_L L EXG00U HMI_TX+ HMI_TX- HMI_TX0-_L HMI_TX0+_L L EXG00U HMI_TX0- HMI_TX0+ +V_RUN HMI N FHMR0 Female HMI_TX+_L HMI_TX-_L L EXG00U HMI_TX+ HMI_TX- HMI_LK+_L HMI_LK-_L L0 EXG00U HMI_LK+ HMI_LK- R 0 0 R R.K.K HMI_TX+ HMI_TX- HMI_TX+ HMI_TX- HMI_TX0+ HMI_TX0- HMI_LK+ HMI_LK- HMI_SL HMI_S HMI_ET 0 TYPE + - GN 0+ 0- GN E SL GN HP GN + - GN K+ K- RSV S +V +V_RUN *0.U_N 0.U 0 GN FHMR0 +.V_RUN L LMPGSN U 0.U EQULIZTION SETTING P:P0=0:0 d P:P0=0: d Recommanded P:P0=:0 d P:P0=: 0d SLZ/SZ Low-level input/output Voltage FG0:FG00=0:0 VIL:<0.V VOL:0.V (efault) GF0:GF00=0: VIL:<0.V VOL:0.V GF0:GF00=:0 VIL:<0.V VOL:0.V GF0:GF00=: VIL:<0.V VOL:0.V HMI_PWR_TRL 0 is Enable is isable 0.U 0.U 0.U +.V_RUN +.V_RUN 0.U R 00K HMI_ET PQ N00W--F +V_HMI 0 0.U [] HMI_LK_P [] HMI_LK_N [] HMI_T0_P [] HMI_T0_N [] HMI_T_P [] HMI_T_N [] HMI_T_P [] HMI_T_N [] M_HMI_SL [] M_HMI_S [] M_HMI_HP 0.U R.K R *.K_N R.K R *.K_N R *.K_N R 0 0.U _EN P0 P FG00 FG0 SJ_00 R.K V V V V V V 0 V V SL S HP _EN P0 P UF_EN FG 0 RT_EN# OE# REXT ONTROL POWER GN IN_+ IN_- IN_+ IN_- IN_+ IN_- IN_+ IN_- OUT_+ OUT_- OUT_+ 0 OUT_- OUT_+ OUT_- OUT_+ OUT_- SL_SINK S_SINK HP_SINK 0 GN GN GN GN GN GN GN GN GN GN EP PIVPLSZE HMI_LK+_L HMI_LK-_L HMI_TX0+_L HMI_TX0-_L HMI_TX+_L HMI_TX-_L HMI_TX+_L HMI_TX-_L HMI_SL HMI_S HMI_ET_L R K HMI_ET R *0_N R *0_N R *0_N R 0 R0 *0_N _EN P0 P FG00 FG0 HMI QUNT OMPUTER Size ocument Number Rev UM/UM ate: Friday, October 0, 00 Sheet of
+V_LW +.V_RUN R 0K LV_ON Q FN R 0 +LV U 0.0U 0 0 +LV 0.U 0.0U +.V_RUN 0.U R *00K_N 0.0U +.V_SUS R K Q N00W--F Q N00W--F Support the new imbeded diagnostics. [] [] ENV LV_TST_EN T T/R EN_LV Q TEU--F +PWR_SR 0mil FL HI0TR-0(0,) 0mil +GFX_PWR_SR Shunt capacitors on LVS for improving WWN. J [] L_T +.V_RUN +LV L_LK L_T L_LK [] L_0- L_0+ L_0- [] [] L_0+ L_- L_+ 0 L_+ [] L_- L_+ L_- [] [] L_+ L_LK- L_LK+ L_0- L_0- [] L_0+ [] L_0+ L_- 0 L_+ [] L_- L_+ [] L_- L_- [] L_+ [] L_+ L_LK- L_LK+ LT_PWM 0 L_K# [] [] IH_USP+ IH_USP- [] L_TST [] R *0_N +V_RUN R 0 0 +.V_RUN ON0 000P 0 [] L_- +GFX_PWR_SR +GFX_PWR_SR 00P 0 0 00P +GFX_PWR_SR 00 00P 0 L_LK- L_LK+ L_LK- L_LK+ L_0- L_- L_- L_0- L_- L_- R *0_N R *0_N 0 *.P_N 0 0 *.P_N 0 0 *.P_N 0 *.P_N 0 *.P_N 0 *.P_N 0 0 0 0 *.P_N *.P_N L_0+ L_+ L_+ L_0+ L_+ L_+ L_LK- [] L_LK+ [] L_LK- [] L_LK+ [] [] I_PWM LT_PWM [] PWM_VJ T T/R R 0K QUNT OMPUTER L ONN & K-SS Size ocument Number Rev UM/UM Friday, October 0, 00 ate: Sheet of
E +.V_RUN +V_RUN Layout Note: Setting R,G, treac impedance to 0 ohm. *0U_N *0U_N *0U_N [] VG_RE L LM0SN [] [] VG_GRN VG_LU R 0/F L L 0P/0V_ 0P/0V_ 0P/0V_ P 0 0P/0V 0 RE GREEN LUE +V_RT_REF +.V_RUN +V_RT_REF +V_RT_REF RP.KX Q SS--F 0.0U +V_RUN [] G_T_ R K G_T [] VGHSYN HSYN [] G_LK_ G_LK [] 0.U VGVSYN VSYN Q SS--F JVG_HS JVG_VS +.V_RUN U HTGGW U *0P/0V_N 0 L LM0S 0 L LM0S 0 HTGGW 0 0P/0V 0P/0V 0P/0V 0 0 L 0 LM0SN R 0/F 0P/0V 0 LM0SN L 0 LM0SN L 0 LM0SN LM0SN 0P/0V 0 0 JVG SUY_00FR0SJZR G_T JVG_HS JVG_VS G_LK SM0K--F R 0/F P 0 P 0 RP.KX *0P/0V_N 0 0P/0V 0 0 Place near JVG connector < 00 mil RT&TV ONN QUNT OMPUTER Size ocument Number Rev UM/UM Friday, October 0, 00 ate: Sheet of E
E J 0 0 FP/FF-P +V_SUS O0# [] +.V_RUN US_RIGHT_EN# [] IH_USP+ [] IH_USP- [] IH_USP0+ [] IH_USP0- [] IH_USP+ [] IH_USP- [] MI_J# [] HP_J# [] U_MI_R [] U_MI_L [] U_HP_R [] U_HP_L [] US RIHGT US RIHGT ard reader +V_SUS +.V_RUN 0 0U. 0 0.U 0 000P 0.U 0 0U. 0 000P 0 0.U close to connector QUNT OMPUTER (US PORT/R REER/UIO JK) ONN Size ocument Number Rev UM/UM ate: Friday, October 0, 00 Sheet of E
+.V_LW 0 0U 0. 0 0.U Place these caps close to ITE0. SERIRQ S(V.0)P:.-k pull-up to +V.S R uses a 0-k pull-up to +V.S. [] 0.U [,,,0,] PLTRST# [] LK_PI_0 [,0] LP_LFRME# [,0] LP_L0 [,0] LP_L [,0] LP_L [,0] LP_L [] LKRUN# [] IRQ_SERIRQ [0] SIO_EXT_SMI# [0] SIO_EXT_SI# [0] SIO_0GTE [] L_TST [0] [] N_MUTE# 0.U SIO_RIN# L_K# 0.U [] [] KSO[0..] KSI[0..] R KSO KSO KSO KSO KSO KSO KSO KSO0 KSO KSO KSO KSO KSO KSO KSO KSO KSO KSO0 KSI KSI KSI KSI KSI KSI KSI KSI0 IRQ_SERIRQ SMK00L--F SMK00L--F SMK00L--F SMK00L--F WRST# L_K# IH_Z_OE_RST0# U KSO/GP KSO/GP KSO KSO KSO KSO/SLT KSO/ERR KSO0/PE KSO/USY KSO/K KSO/P KSO/P KSO/P 0 KSO/P KSO/P KSO/P KSO/P KSO0/P0 KSI KSI KSI KSI KSI/SLIN 0 KSI/INT KSI/F KSI0/ST SJ_00 LPRST/WUI/GP LPLK LFRME 0 L0 L L L LKRUN/GPH0/I0 SERIRQ ESMI/GP ESI/GP G0/GP LPP/WUI/GPE KRST/GP WRST PWUREQ/GP L0HLT/GPE0 0 L0LLT/WUI/GPE ITE0E LQFP-L KEYOR LP / PWM IR/URT VT V VSTY VSTY 0 VSTY VSTY VSTY VSTY 0/GPI0 /GPI /GPI /GPI /GPI 0 /GPI /GPI /GPI 0/GPJ0 /GPJ /GPJ /GPJ /GPJ 0 /GPJ PWM0/GP0 PWM/GP PWM/GP PWM/GP PWM/GP 0 PWM/GP PWM/GP PWM/GP TH0/GP TH/GP TMRI0/WUI/GP 0 TMRI/WUI/GP RX/GP0 0 TX/GP 0 GP0 TX0/GP RX/GPH/I TX/GPH/I HWPG SIO_SLP_S# US_LEFT_EN# ST_LE IMVP_VR_ON +.V_RUN +.V_LW SMK00L--F R 0.U HWPG [,] IMVP_PROHOT# [] SUS_PWR_K [] PT_PRES# [] IINP [] SIO_SLP_S# [] RIT_TEMP_REP# [0] SIO_EXT_WKE# [0] US_LEFT_EN# [] LN_PIE_PWR_TRL# [] IH_RSMRST# [] SIO_PWRTN# [] RETH_LE# [] T_LE [] FN_PWM [] PWM_VJ [] T_LE [] P T EEP [] FN_TH [] PNEL_KEN [] LI_SW# [] [,] IH_Z_OE_RST# SIO_SLP_S# [] ST_LE [] H_PUET# [] IMVP_PWRG [] RUN_ON_ [] P T IMVP_VR_ON [] +RT_ELL SJ_00 Ray / SMT0 SMLK0 SMT SMLK US_LEFT_EN# SUS_ON IMVP_VR_ON SMT SMLK IRQ_SERIRQ L_K# LI_SW# iscrete R R *0K_N Q *MMST0--F_N R R R0 SJ_00 +.V_RUN R *0.U_N 0 +.V_LW 0K 00K *00K_N 00K +.V_LW +.V_RUN R 0K/F R *0K_N R *00K_N RP.KX RP 0KX RP.KX +.V_SUS IH_Z_OE_RST0# Q *N00W--F_N oard I Straps LK, L and Thermal harge and T [,] THERM_STP# KHz lock. ITE0_XTL [,] SMLK0 [,] SMT0 [] [] SMLK SMT [,] SMLK [,] SMT [] PS_I T P [] LK_TP_SIO [] T_TP_SIO +.V_LW T P T P R 00K WRST# *SMK00L--F_N U 0 0 SMLK0 SMT0 SMLK SMT SMLK SMT +.V_LW L L 0 0 LM0S ITE0_XTL ITE0_XTL ITE0IX_JX LM0S 0.U 0 0 SMLK0/GP SMT0/GP SMLK/GP SMT/GP SMLK/GPF SMT/GPF PSLK0/GPF0 PST0/GPF PSLK/GPF PST/GPF PSLK/GPF PST/GPF KK KKE VORE VSS VSS VSS VSS VSS VSS V VSS SMUS PS/ SUS_ON FLFRME/GPG/LF 00 FLRST/GPG0/TM 0 FL/GPG 0 LP/FWH FLSH FL/SO 0 FL/SI 0 FL0/SE 0 FLLK 0 PH_PWRG EG/GPE EGP EGS/GPE EGLK/GPE I GPH/I US_RIGHT_EN# GPH/I GPIO I GPH/I L_SIZE_I GPH/I L_SIZE_I GPG/I 0 R *00K_N RI/WUI0/GP0 RI/WUI/GP SMK00L--F WUI/GPE RING/PWRFIL/LPRST/GP PWRSW/GPE GINT/GP ITE0E lqfp-x- SUS_ON [,,] E_FLSH_SPI_O [] E_FLSH_SPI_IN [] E_FLSH_SPI_S# [] E_FLSH_SPI_LK [] PH_PWRG [,] LW_ON [] P T US_RIGHT_EN# [] +.V_LW ST_T# [] V_IN [,] _PRESENT [] SYS_PWR_SW# [] LV_TST_EN [] R *0K_N R 0K UM " VG_IENTIFY L_SIZE_I () " 0." " 0 I R *0K_N R0 0K I0 US_RIGHT_EN# 0 0 0 0 0 0 R00 R *0K_N 0K R 0K L_SIZE_I (0) 0 0 UM(UM) SSI (X00) PT (X0) ST (X0) QT (00) (0) R0 *0K_N R0 R0 *0K_N 0K US_RIGHT_EN# I L_SIZE_I I L_SIZE_I UM (is) SSI (X00) PT (X0) ST (X0) QT (00) (0) W LK_PI_0 ITE0IX_JX ITE0_XTL.KHZ P/0V 0 P/0V 0 R 0.P 0 0.U QUNT OMPUTER I/O ontroller IT0 Size ocument Number Rev UM/UM ate: Friday, October 0, 00 Sheet of