SH69P481 4K 12 ADC 4 SH6610D 12 ADC 4 OTPROM: 4K X 16 RAM: 287 X : - fosc = 30kHz - 4MHz, VDD = 2.4V - 5.5V - fosc = 4MHz - 10MHz, VDD = 4.

Transcription

1 4K 12 ADC 4 SH6610D 12 ADC 4 OTPROM: 4K X 16 RAM: 287 X : - fosc = 30kHz - 4MHz, VDD = 2.4V - 5.5V - fosc = 4MHz - 10MHz, VDD = 4.5V - 5.5V 14 I/O 8 ( 8 / : - / - ( 0, 1 - PORTB/D ( ( / ( - : kHz, 400kHz - 10MHz - : 400kHz - 10MHz - RC : 16MHz ±2% - : 30kHz - 10MHz (4/Fosc : HALT STOP - (WDT ( - (POR - (LVR, ( ADC Vref 2.4V 0.5% / (ADC (OP (RDT 2 (8 + 2 (PWM PORTC (CMP OTP 16 SOP 8 SOP CMOS 4 SH6610D CPU, RAM, ROM,, I/O, Vref, 12 /, 2 (8+2,,, 1 V2.0

2 2 /SOP16L PWM1/PORTD.3 PWM0/PORTC.2 T0/PORTC.3 RESET/PORTE.1 GND AN1/PORTA.1 VDD PORTB.3/AN7 PORTB.2/AN6/OPIN0 PORTE.0/AN11/OSCI PORTC.1/AN10/VREF PORTC.0/OSCO PORTD.0/AN8 PORTD.1/AN9/OPIN1 VCMP/AN0/PORTA.0 AN2/PORTA.2 /SOP8L VDD OSCI/AN11/PORTE.0 PWM0/PORTC.2 RESET/PORTE.1 PORTA.1/AN1 PORTA.2/AN2 PORTA.0/AN0/VCMP GND

3 RESET/ POTRTE.1 Reset Circuit WDT RC Watchdog Timer Oscillator AN11 PORTE.0/AN11/OSCI/SCK PORTC.0/OSCO RAM 95 X 4 bits System Register RAM 192X 4 bits Data Memory 10ch X 12bits ADC PORTA [3 bits] AN0 - AN2 PORTA.0/AN0/VCMP PORTA.1/AN1 PORTA.2/AN2 OTP ROM 4096 X 16 bits OP PORTB [2 bits] AN6 - AN7 PORTB.2/AN6/OPIN0 PORTB.3/AN7 CMP CPU 2ch X (8 + 2 bits PWM PORTC [4 bits] AN10 PORTC.1/AN10/VREF PORTC.2/PWM0 PORTC.3/T0 VDD GND Power Circuit Timer 0 (8 bits PORTD [3 bits] AN8 - AN9 PORTD.0/AN8 PORTD.1/AN9/OPIN1 PORTD.3/PWM1 Timer 1 (8 bits 3

4 SOP16L SOP8L PORTD.3 - /PWM1 PORTC.2 - /PWM0 PORTC.3 - /T0 RESET /PORTE.1 I/O I O I/O I O I/O I I I O I/O ( I/O ( I/O ( / ( (, I/O ( 5 8 GND P 6 7 PORTA.0 /AN0 /V CMP I/O I I I/O ADC AN0 7 6 PORTA.1 I/O I/O /AN1 I ADC AN1 8 5 PORTA.2 I/O I/O /AN2 I ADC AN2 PORTB.2 I/O I/O /AN6 I I ( ADC AN6 /OPIN0 I OP 10 - PORTB.3 - /AN7 I/O I I I/O ( ADC AN VDD P 12 2 OSCI /PORTE.0 /AN11 I I/O I,, I/O ADC AN OSCO - /PORTC.0 O I I/O,, RC, ( I/O PORTC.1 I/O I/O /AN10 I I ( ADC AN10 /VREF I ADC 15 - I/O PORTD.0 I/O I - ( I /AN8 I ADC AN PORTD.1 - /AN9 /OPIN1 I/O I I I I, I: ; O: ; P: ; Z: I/O ( ADC AN9 OP 4

5 OTP (OTP SOP16L SOP8L 11 1 V DD P V DD (+5V 4 4 V PP P RESET (+8.5V 5 8 GND P GND 12 2 SCK I OSCI/PORTE.0/AN SDA I/O PORTA.0/AN0/V CMP, I: ; O: ; P: ; Z: 5

6 说 1.CPU CPU : (PC, 1.4. (TBR (ALU, (CY,,, (INX,, (TJMP DPH, DPM, DPL, (RTNW ROM, ROM 12 : TBR AC TJMP (PC11, (PC10, PC9, PC8, PC7, ((PC11 - PC8 X (2 8 + (TBR, AC RTNW, PC6, PC5, PC4, PC3, PC2, PC1, PC0 (TBR, AC ROM PC TBR, 3-0 AC K ROM, (JMP DPH(3, DPM(3 DPL(4 3FFH 4K ROM ( ROM (INX, DPH, DPM DPL 1.2. ALU CY 1.6. ALU ALU : / (ADC, ADCM, ADD, ADDM, SBC, SBCM,, SUB, SUBM, ADI, ADIM, SBI, SBIM CY PC(11-0 CY, / (DAA, DAS 13 X 8 (RTNI/RTNW, (AND, ANDM, EOR, EORM, OR, ORM, ANDIM, PC EORIM, ORIM (BA0, BA1, BA2, BA3, BAZ, BNZ, BC, BNC : (SHR (CY ALU,, RTNI 8 8, RTNW, 1.3. (AC, ALU, 2. RAM RAM RAM, CPU STOP HALT 2.1. RAM : : $000 - $02F, $380 - $3AE : $030 - $0EF 2.2. : / $00 IEAD IET0 IET1 IEP / $01 IRQAD IRQT0 IRQT1 IRQP / 2-0 : $02 T0S T0M.2 T0M.1 T0M.0 / 0 3 : T0 2-0 : $03 REV0 T1M.2 T1M.1 T1M.0 / 1 3 : 0 $04 T0L.3 T0L.2 T0L.1 T0L.0 / 0 / $05 T0H.3 T0H.2 T0H.1 T0H.0 / 0 / $06 T1L.3 T1L.2 T1L.1 T1L.0 / 1 / 6

7 : ( / $07 T1H.3 T1H.2 T1H.2 T1H.0 / 1 / PORTA $08 REV0 PA.2 PA.1 PA.0 /3, 0. I/O PORTB $09 PB.3 PB.2 REV0 REV0 0 1, 0. / 8, 2 3, 0. I/O PORTC $0A PC.3 PC.2 PC.1 PC.0 /8, 0 1 3, 0. I/O PORTD $0B PD.3 REV0 PD.1 PD.0 2, 0. / 8, 0 1 3, 0. I/O $0C - - PE.1 PE.0 / PORTE $0D $0E TBR.3 TBR.2 TBR.1 TBR.0 / $0F INX.3 INX.2 INX.1 INX.0 / $10 DPL.3 DPL.2 DPL.1 DPL.0 / (4 $11 - DPM.2 DPM.1 DPM.0 / (3 $12 - DPH.2 DPH.1 DPH.0 / (3 3 : Timer1 $13 T1GO REV0 - REV0 / : ADC $14 VREFS - - ADCON / 3 : / $15 GO/ DONE 0 : 10bit ADC TADC1 TADC0 ADCS /2-1 : ADC 3 : ADC / $16 ACR3 ACR2 ACR1 ACR0 / ADC $17 CH3 CH2 CH1 CH0 / ADC PORTA / $18 REV1 PACR.2 PACR.1 PACR.0 /3, 1. I/O PORTB / $19 PBCR.3 PBCR.2 REV1 REV1 0 1, 1. / 8, 2 3, 1. I/O $1A PCCR.3 PCCR.2 PCCR.1 PCCR.0 PORTC / /8, 0 1 3, 1. I/O $1B PDCR.3 REV1 PDCR.1 PDCR.0 PORTD / 2, 1. / 8, 0 1 3, 1. I/O $1C - - PECR.1 PECR.0 / PORTE / 7

8 : ( / $1D WDT.2 WDT.1 WDT.0 /2-0 : $1E WDT : ( $1F : PWM0 $20 PWM0S T0CK1 T0CK0 PWM0_EN /2-1 : PWM0 3 : PWM0 0 : PWM1 $21 PWM1S T1CK1 T1CK0 PWM1_EN /2-1 : PWM1 3 : PWM1 $22 PP0.3 PP0.2 PP0.1 PP0.0 / PWM0 $23 PP0.7 PP0.6 PP0.5 PP0.4 / PWM0 $ PDF0.1 PDF0.0 / PWM0 (2 $25 PD0.3 PD0.2 PD0.1 PD0.0 / PWM0 $26 PD0.7 PD0.6 PD0.5 PD0.4 / PWM0 $27 PP1.3 PP1.2 PP1.1 PP1.0 / PWM1 $28 PP1.7 PP1.6 PP1.5 PP1.4 / PWM1 $ PDF1.1 PDF1.0 / PWM1 (2 $2A PD1.3 PD1.2 PD1.1 PD1.0 / PWM1 $2B PD1.7 PD1.6 PD1.5 PD1.4 / PWM1 $2C $2D A3 A2 A1 A0 ADC ( 4 ( $2E A7 A6 A5 A4 ADC ( 4 ( $2F A11 A10 A9 A8 ADC ( 4 ( $380 RDT.3 RDT.2 RDT.1 RDT.0 / ROM / $381 RDT.7 RDT.6 RDT.5 RDT.4 / ROM / $382 RDT.11 RDT.10 RDT.9 RDT.8 / ROM / $383 RDT.15 RDT.14 RDT.13 RDT.12 / ROM / PORTD $384 PDIEN.3 REV0 PDIEN.1 PDIEN.0 / 2 0 $385 PDIF.3 - PDIF.1 PDIF.0 / PORTD PORTB $386 PBIEN.3 PBIEN.2 REV0 REV0 / $387 PBIF.3 PBIF / PORTB $388 - PPACR.2 PPACR.1 PPACR.0 / PORTA $389 PPBCR.3 PPBCR / PORTB $38A PPCCR.3 PPCCR.2 PPCCR.1 PPCCR.0 / PORTC $38B PPDCR.3 - PPDCR.1 PPDCR.0 / PORTD $38C PPECR.0 / PORTE 2 : STOP 0 : $38D - FSTP OXS OXON /1 : $38E - - T0SP T0S1 / 0 : T0 1 : STOP Timer0 8

9 : ( / $38F~ $ : ADC $393 ADCH1 ADCH0 - ADCHC / 2-3 : ADC $ ADCH2 / ADC $395 ADCH9 ADCH8 ADCH7 ADCH6 / ADC $ ADCH11 ADCH10 / ADC 0 : OP $397 - OPOS OPCH OPEN /1 : OP 2 : $ : PWM $ TPWM REV0 / 0 : 0 $39A~ $3A : ADC $3A4 - ADCM VREFS2 VREFS1 / 2 : ADC $3A5 ADCTS3 ADCTS2 ADCTS1 ADCTS0 / 12bit ADC $3A6 PCIEN.3 PCIEN.2 PCIEN.1 PCIEN.0 / PORTC $3A7 PCIF.3 PCIF.2 PCIF.1 PCIF.0 / PORTC $3A $3A : $3AA - - CLVEN COVEN / 1 : 0 : $3AB - - CLVIF COVIF / 1 : 0 : $3AC - CMPD1 CMPD0 CMPEN / 1-2 : debounce $3AD $3AE 0-1 : CMPLV1 CMPLV0 CMPOV1 CMPOV0 / 2-3 : DPCCR.3 DPCCR.2 DPCCR.1 DPCCR.0 / PORTC 9

10 3. ROM ROM 4096 X 16, $0000 $0FFF 3.1. ($000 $004 $000 $004, $000 JMP* RESET $001 JMP* ADC $002 JMP* Timer0 $003 JMP* Timer1 $004 JMP* *JMP 3.2. ROM $380 - $383: / $380 RDT.3 RDT.2 RDT.1 RDT.0 / ROM / $381 RDT.7 RDT.6 RDT.5 RDT.4 / ROM / $382 RDT.11 RDT.10 RDT.9 RDT.8 / ROM / $383 RDT.15 RDT.14 RDT.13 RDT.12 / ROM / RDT 1 ROM (RDT (RDT.11 - RDT.0 16 ROM (RDT.15 - RDT.0 ROM, ROM RDT.15 0 RDT.15 1 Information 12 (,, RDT ( 12 Information 10

11 : /Reset / WDT $00 IEAD IET0 IET1 IEP $01 IRQAD IRQT0 IRQT1 IRQP $02 T0S T0M.2 T0M.1 T0M uuuu $03 REV0 T1M.2 T1M.1 T1M uuuu $04 T0L.3 T0L.2 T0L.1 T0L.0 xxxx xxxx $05 T0H.3 T0H.2 T0H.1 T0H.0 xxxx xxxx $06 T1L.3 T1L.2 T1L.1 T1L.0 xxxx xxxx $07 T1H.3 T1H.2 T1H.2 T1H.0 xxxx xxxx $08 REV0 PA.2 PA.1 PA $09 PB.3 PB.2 REV0 REV $0A PC.3 PC.2 PC.1 PC $0B PD.3 REV0 PD.1 PD $0C - - PE.1 PE $0D $0E TBR.3 TBR.2 TBR.1 TBR.0 xxxx uuuu $0F INX.3 INX.2 INX.1 INX.0 xxxx uuuu $10 DPL.3 DPL.2 DPL.1 DPL.0 xxxx uuuu $11 - DPM.2 DPM.1 DPM.0 -xxx -uuu $12 - DPH.2 DPH.1 DPH.0 -xxx -uuu $13 T1GO REV0 - REV u-u $14 VREFS - - ADCON 0--0 u--0 $15 GO/ DONE TADC1 TADC0 ADCS uuu $16 ACR3 ACR2 ACR1 ACR uuuu $17 CH3 CH2 CH1 CH uuuu $18 REV1 PACR.2 PACR.1 PACR $19 PBCR.3 PBCR.2 REV1 REV $1A PCCR.3 PCCR.2 PCCR.1 PCCR $1B PDCR.3 REV1 PDCR.1 PDCR $1C - - PECR.1 PECR $1D $1E WDT WDT.2 WDT.1 WDT $1F $20 PWM0S T0CK1 T0CK0 PWM0_EN 0000 uuu0 $21 PWM1S T1CK1 T1CK0 PWM1_EN 0000 uuu0 $22 PP0.3 PP0.2 PP0.1 PP uuuu $23 PP0.7 PP0.6 PP0.5 PP uuuu $ PDF0.1 PDF uu $25 PD0.3 PD0.2 PD0.1 PD uuuu : x =, u =, - =, '0' 11

12 : ( /Reset / WDT $26 PD0.7 PD0.6 PD0.5 PD uuuu $27 PP1.3 PP1.2 PP1.1 PP uuuu $28 PP1.7 PP1.6 PP1.5 PP uuuu $ PDF1.1 PDF uu $2A PD1.3 PD1.2 PD1.1 PD uuuu $2B PD1.7 PD1.6 PD1.5 PD uuuu $2C $2D A3 A2 A1 A0 xxxx uuuu $2E A7 A6 A5 A4 xxxx uuuu $2F A11 A10 A9 A8 xxxx uuuu $380 RDT.3 RDT.2 RDT.1 RDT $381 RDT.7 RDT.6 RDT.5 RDT $382 RDT.11 RDT.10 RDT.9 RDT $383 RDT.15 RDT.14 RDT.13 RDT $384 PDIEN.3 REV0 PDIEN.1 PDIEN $385 PDIF.3 - PDIF.1 PDIF $386 PBIEN.3 PBIEN.2 REV0 REV $387 PBIF.3 PBIF $388 - PPACR.2 PPACR.1 PPACR $389 PPBCR.3 PPBCR $38A PPCCR.3 PPCCR.2 PPCCR.1 PPCCR $38B PPDCR.3 - PPDCR.1 PPDCR $38C PPECR $38D - FSTP OXS OXON u00 $38E - - T0SP T0S $38F~ $ $393 ADCH1 ADCH0 - ADCHC 00-0 uu-0 $ ADCH u $395 ADCH9 ADCH8 ADCH7 ADCH uuuu $ ADCH11 ADCH uu $397 - OPOS OPCH OPEN $ $ TPWM REV $39A~ $3A : x =, u =, - =, '0' 12

13 : ( /Reset / WDT $3A4 - ADCM VREFS2 VREFS $3A5 ADCTS3 ADCTS2 ADCTS1 ADCTS $3A6 PCIEN.3 PCIEN.2 PCIEN.1 PCIEN $3A7 PCIF.3 PCIF.2 PCIF.1 PCIF $3A $3A $3AA - - CLVEN COVEN $3AB - - CLVIF COVIF $3AC - CMPD1 CMPD0 CMPEN $3AD CMPLV1 CMPLV0 CMPOV1 CMPOV $3AE DPCCR.3 DPCCR.2 DPCCR.1 DPCCR : x =, u =, - =, '0' 4.2. : (PC $000 CY (AC 13

14 5. CPU RC fosc = frc/2 frc/4 = fosc/ : ( kHz, 4/32.768kHz ( 122.1µs (2 10MHz, 4/10MHz (= 0.4µs (3 16MHz/2, 4/8MHz (= 0.5µs (4 16MHz/4, 4/4MHz (= 1µs 5.2. (1 : 400kHz - 10MHz OSCI C1 Crystal OSCO (2 : 400kHz - 10MHz OSCI C1 C2 Ceramic OSCO C2 (3 RC : 16MHz OSCI/PORTE.0 OSCO/PORTC.0 ( kHz + RC OSCI C kHz OSCO C2 (5 : 30kHz - 10MHz OSCI External clock source OSCO/PORTC.0 : - RC, OSCO I/O (PORTC.0 OSCI PORTE.0 14

15 $38D / 2 : STOP 0 : $38D - FSTP OXS OXON /1 : - X X 0 / - X X 1 / - X 0 X / - X 1 X / - 0 X X /STOP - 1 X X /STOP : OP_OSC kHz + RC kHz RC kHz + RC : a. :, $38D OXON 1, NOP OXS = 1, b., $38D OXS 0, NOP, OXON = 0, C1 C2 455kHz pF pF ZT 455E 3.58MHz - - ZT 3.58M* 4MHz - - ZT 4M* *- C1 C kHz pF pF DT 38 ( 3 X 8 KDS 4MHz 8-15pF 8-15pF 49S-4.000M-F16E 8MHz 8-15pF 8-15pF 49S-8.000M-F16E : 1.! 2., 3., /, 15

16 6. I/O 14 I/O $08 - $0C ($18 - $1C I/O 开 I/O PORTE.1, PORTC, ($388 - $38C PORTC ($3AE, 1 ($388 - $38C, 0 PORTC, 1 PORTC ($3AE 0 PORTC ($38A, 0 (PORTC $38A $3AE ($388 - $38C, $3AE,, / PORTB/C/D, PORTB/D, PORTC ( ( ( $08 - $0C: / $08 REV0 PA.2 PA.1 PA.0 / PORTA $09 PB.3 PB.2 REV0 REV0 / PORTB $0A PC.3 PC.2 PC.1 PC.0 / PORTC $0B PD.3 REV0 PD.1 PD.0 / PORTD $0C - - PE.1 PE.0 / PORTE PE.1 N I/O : 1. REV , $09 2/3 $0A 0/1/3 $0B 0/1/3, 0 $18 - $1C: / / $18 REV1 PACR.2 PACR.1 PACR.0 / PORTA / $19 PBCR.3 PBCR.2 REV1 REV1 / PORTB / $1A PCCR.3 PCCR.2 PCCR.1 PCCR.0 / PORTC / $1B PDCR.3 REV1 PDCR.1 PDCR.0 / PORTD / $1C - - PECR.1 PECR.0 / PORTE / : 1. REV , $19 2/3 $1A 0/1/3 $1B 0/1/3, 1 PA (/B/C/D/E CR.n, (n = 0, 1, 2, 3 0:. ( 1: $388 - $38C: / $388 - PPACR.2 PPACR.1 PPACR.0 / PORTA $389 PPBCR.3 PPBCR / PORTB $38A PPCCR.3 PPCCR.2 PPCCR.1 PPCCR.0 / PORTC $38B PPDCR.3 - PPDCR.1 PPDCR.0 / PORTD $38C PPECR.0 / PORTE PPA (/B/C/D/E CR.n, (n = 0, 1, 2, 3 0:. ( 1: 16

17 $3AE: PORTC / $3AE DPCCR.3 DPCCR.2 DPCCR.1 DPCCR.0 / PORTC DPCCR.n, (n = 0, 1, 2, 3 0:. ( 1: PORTC $38A $3AE, ($3AE I/O VDD Pull high Register I/O Control Register VDD Pull high DATA Register I/O Pin GND DATA READ DATA IN READ M2T1 0 1 s,, (PDR,,, PORTA.0-2 ADC (AN0-2 PORTB.2-3 ADC (AN6-7 PORTC.1 ADC (AN10 PORTD.0-1 ADC AN8-9 (AN8-9 PORTE.0 ADC (AN11 RC, OSCO, PORTC.0 RC, OSCI, PORTE.0 RESET PORTE,1 I/O PORTE.1 17

18 PORTB PORTC PORTD PORTB PORTC PORTD I/O, VDD GND $384 - $387, $3A6 - $3A7 0 ( CPU HALT STOP $384, $386, $3A6: / $384 PDIEN.3 REV0 PDIEN.1 PDIEN.0 / PORTD $386 PBIEN.3 PBIEN.2 REV0 REV0 / PORTB $3A6 PCIEN.3 PCIEN.2 PCIEN.1 PCIEN.0 / PORTC : REV0 0 PDIEN.n, PBIEN.n, PCIEN.n (n = 0, 1, 2, 3 0: ( 1: $385, $387, $3A7: / $385 PDIF.3 - PDIF.1 PDIF.0 / PORTD $387 PBIF.3 PBIF / PORTB $3A7 PCIF.3 PCIF.2 PCIF.1 PCIF.0 / PORTC PDIF.n, PBIF.n, PCIF.n (n = 0, 1, 2, 3 0: ( 1: 0 PBIEN.n PCIEN.n PDIEN.n IEP PORTB.n PORTC.n PORTD.n PBCR.n PCCR.n PDCR.n Note: n = 0, 1, 2, 3 Falling/Rising Edge Detector PBIF.n PCIF.n PDIF.n IRQP Port Interrupt : 1., 1 2. PIF.n = 1 PIEN.n = 1, (IRQP = 1 PORTC 1. PORTC, 0, 1 2. PIF.n = 1 PIEN.n = 1, (IRQP = 1 HALT STOP CPU 18

19 ADC $14: / $14 VREFS - - ADCON / X / ADC X / ADC 0 : ADC 3 : / ADC, PORTA.0-2, PORTB.2-3, PORTC.1, PORTD.0-1 PORTE.0 I/O ADC, ADC ($16 PORTA.0-3, PORTB.0-3, PORTC.1, PORTD.0-1 PORTE.0 I/O ADC ADC PORTA.0 V CMP CMP $3AC / $3AC - CMPD1 CMPD0 CMPEN / 0 : 1-2 : debounce - X X 0 / I/O ADC ( - X X 1 / PORTB.2 OP OP $ / $397 - OPOS OPCH OPEN / 0 : OP 1 : OP - X 1 X / PORTB.2 I/O ADC ( - X 0 1 / PORTB.2 OP OPIN0 PORTC.1 VREF ADC VREF $14: / $14 VREFS - - ADCON / 0 : ADC 3 : / X / PORTC.1 I/O ADC ( X / PORTC.1 PORTC.2 PWM0 (PWM0. PWM0 $20: / 0 PWM0 $20 PWM0S T0CK1 T0CK0 PWM0_EN / 2-1 PWM0 3 PWM0 X X X 0 / PORTC.2 I/O ( X X X 1 / PORTC.2 PWM0 PWM0 19

20 PORTC.3 Timer0 (T0. Timer0 $02: / $02 T0S T0M.2 T0M.1 T0M.0 / 2-0 : 0 3 : T0 0 X X X / PORTC.3 I/O ( 1 X X X / PORTC.3 T0 ( PORTD.1 OP OP $ / $397 - OPOS OPCH OPEN / 0 : OP 1 : OP - X 0 X / PORTD.1 I/O ADC ( - X 1 1 / PORTD.1 OP OPIN1 PORTD.3 PWM1 (PWM1. PWM1 $21: / $21 PWM1S T1CK1 T1CK0 PWM1_EN / 0 : PWM1 2-1 : PWM1 3 : PWM1 X X X 0 / PORTD.3 I/O ( X X X 1 / PORTD.3 PWM1 PWM1 20

21 7. Timer 8 Timer0 Timer Timer0 : Timer0 : System clock T kHz MUX tosc SYNC PRESCALER T0S1 T0S T0M.2 T0M.1 T0M.0 8-BIT COUNTER 4 Timer, :, -, Timer0 : Timer0 Load Reg. L Load Reg. H 8 (TL0L, TL0H 8 8-bit timer counter (TC0, TC0H (TL0L, TL0H Timer 4 Timer $FF $00 Latch Reg. L, Timer Timer0 Timer0 T0M Timer0, Timer0 T0M.2-0, T0S T0S1 Timer0 : $02 T0M.2 T0M.1 T0M /2 11 /T0/32.768kHz /2 9 /T0/32.768kHz /2 7 /T0/32.768kHz /2 5 /T0/32.768kHz /2 3 /T0/32.768kHz /2 2 /T0/32.768kHz /2 1 /T0/32.768kHz /2 0 /T0/32.768kHz 21

22 / T0 Timer0 / T0 0, CPU Timer0 ( 2 tosc ( 2 tosc : T0H (T0 2 * tosc + T T0L (T0 2 * tosc + T; T = 20ns, TM0, : N * T0 T0 high time = T0 low time = 2 : T0 = Timer0 N =, : N * T0 4 * tosc + 2 * T 2 * tosc + T T0 2 N T0 Timer0, T0 : : 4 * tosc + 2 * T T0 = Timer0 period N / $02 T0S T0M.2 T0M.1 T0M.0 / 2-0 : 0 3 : T0 0 X X X / T0S1 = 0 Timer0 1 X X X / T0S1 = 0 Timer0 T / $38E - - T0SP T0S1 / 0 : T0 1 : STOP Timer0 - - X 0 / Timer0 T0S - - X 1 / Timer kHz X / STOP Timer X / STOP Timer0 STOP Timer0 STOP Timer0 T kHz kHz 22

23 7.2. Timer1 Timer1 : Timer1 : System clock MUX TM1S0 T1M.2 tosc PRESCALER T1M.1 T1M.0 SYNC 8-BIT COUNTER 4 Timer, : Timer1 : Timer1 结 8- (TL1L, TL1H 8- Load Reg. L Load Reg. H (TC1L, TC1H 8-bit timer counter (TL1L, TL1H Timer 4 Timer $FF $00, Timer Latch Reg. L Latch Reg. H Timer1 Timer1 T1M Timer1, Timer1 T1M.2-0 Timer1 : $ / $03 REV0 T1M.2 T1M.1 T1M.0 / 2-0 : 1 3 : 0 X / : /2 11 X / : /2 9 X / : /2 7 X / : /2 5 X / : /2 3 X / : /2 2 X / : /2 1 X / : /2 0 23

24 Timer1 Timer1 Timer1 : $ / $13 T1GO REV0 - REV0 / 3 : Timer X - X / / ( : ; 1 X - X / / ( : ; Timer1 Timer1 $07 Timer1 $06 - $07 内 载 Timer1 $13 T1GO 3 1 ($00 1 IET1 1 $FF $00, Timer1 Timer1 ($13 T1GO ( 3 1, Timer1 ($06 - $07 Timer1 ($13 T1GO ( 3 0 ($07, Timer1 ($06 - $07 Timer1 : $06 - $ / $06 T1L.3 T1L.2 T1L.1 T1L.0 / Timer1 / $07 T1H.3 T1H.2 T1H.2 T1H.0 / Timer1 / 24

25 8. : - ADC - Timer0 - Timer1 - ( PORTB/D ( PORTC ( / $00 $01, 0 : / $00 IEAD IET0 IET1 IEP / $01 IRQAD IRQT0 IRQT1 IRQP / IEx 1 (IRQx 1,, PC CY,, (IEx 0, IRQx = 1 IEx 1, Inst.cycle Instruction Execution N Instruction Execution I1 Instruction Execution I2 Interrupt Generated Interrupt Accepted Vector Generated Stacking Fetch Vector address Reset IE.X Start at vector address CPU, IE N,, I1 I2, ADC $00 (IEX 3 ADC A/D (IRQAD = 1, ADC (IEAD = 1, ADC A/D HALT CPU (Timer0, Timer1 Timer0 Timer1 (Timer0 / T0 $FF $00, (IRQT0 IRQT1 = 1, (IET0 IET1 = 1 HALT CPU 25

26 PORTB/D ( PORTC ( / IRQP IEP / PORTB/C/D PORTC (IRQP = 1 VDD GND $384, $386, $3A6: / $384 PDIEN.3 REV0 PDIEN.1 PDIEN.0 / PORTD $386 PBIEN.3 PBIEN.2 REV0 REV0 / PORTB $3A6 PCIEN.3 PCIEN.2 PCIEN.1 PCIEN.0 / PORTC : REV0 0 $385, $387, $3A7: / $385 PDIF.3 - PDIF.1 PDIF.0 / PORTD $387 PBIF.3 PBIF / PORTB $3A7 PCIF.3 PCIF.2 PCIF.1 PCIF.0 / PORTC V CMP COVIF=1 CLVIF=1 IRQP=1 $3AA: / $3AA - - CLVEN COVEN / $3AB: / $3AB - - CLVIF COVIF / 0 : 1 : 0 : 1 : 26

27 9. / (ADC / (ADC ADC VREF VDD VREF VREF ADC : /,,, /, / / : - (, VREF - /, - / - GO/ DONE = 1, / $14: ( / / $14 VREFS - - ADCON / $393 X / ADC X / ADC 0 : ADC 3 : ADC X / VREFS1 VREFS X / / $393 ADCH1 ADCH0 - ADCHC / $394 0 : ADC 2-3 : ADC X X - 0 / ACR0~ACR3 ADC X X - 1 / ADCH0~ADCH11 ADC X 0 - X / PORTA.0 I/O X 1 - X / PORTA.0 ADC AN0 0 X - X / PORTA.1 I/O 1 X - X / PORTA.1 ADC AN / $ ADCH2 / ADC / PORTA.2 I/O / PORTA.2 ADC AN2 27

28 $ / $395 ADCH9 ADCH8 ADCH7 ADCH6 / ADC $396 X X X 0 / PORTB.2 I/O X X X 1 / PORTB.2 ADC AN6 X X 0 X / PORTB.3 I/O X X 1 X / PORTB.3 ADC AN7 X 0 X X / PORTD.0 I/O X 1 X X / PORTD.0 ADC AN8 0 X X X / PORTD.1 I/O 1 X X X / PORTD.1 ADC AN / $ ADCH11 ADCH10 / ADC $ X 0 / PORTC.1 I/O - - X 1 / PORTC.1 ADC AN X / PORTE.0 I/O X / PORT E.0 ADC AN / $16 ACR3 ACR2 ACR1 ACR0 / ADC / ACR3 ACR2 ACR1 ACR PE.0 PC.1 PD.1 PD.0 PB3 PB PA.2 PA.1 PA PE.0 PC.1 PD.1 PD.0 PB.3 PB PA.2 PA.1 AN PE.0 PC.1 PD.1 PD.0 PB.3 PB PA.2 AN1 AN PE.0 PC.1 PD.1 PD.0 PB.3 PB AN2 AN1 AN PE.0 PC.1 PD.1 PD.0 PB.3 PB AN2 AN1 AN PE.0 PC.1 PD.1 PD.0 PB.3 PB AN2 AN1 AN PE.0 PC.1 PD.1 PD.0 PB.3 PB AN2 AN1 AN PE.0 PC.1 PD.1 PD.0 PB.3 AN AN2 AN1 AN PE.0 PC.1 PD.1 PD.0 AN7 AN AN2 AN1 AN PE.0 PC.1 PD.1 AN8 AN7 AN AN2 AN1 AN PE.0 PC.1 AN9 AN8 AN7 AN AN2 AN1 AN PE.0 AN10 AN9 AN8 AN7 AN AN2 AN1 AN0 1 1 X X AN11 AN10 AN9 AN8 AN7 AN AN2 AN1 AN0 28

29 $17 ( / / $17 CH3 CH2 CH1 CH0 / ADC / ADC AN / ADC AN / ADC AN / / ADC AN / ADC AN / ADC AN / ADC AN / ADC AN / ADC AN / OPOUT ADC * *OPOUT OP $2D - $2F( / / / $2D A3 A2 A1 A0 ADC ( 4 ( $2E A7 A6 A5 A4 ADC ( 4 ( $2F A11 A10 A9 A8 ADC ( 4 ( 12BIT $2D - $2F( / / $2D - - A1 A0 ADC ( 2 ( $2E A5 A4 A3 A2 ADC ( 4 ( $2F A9 A8 A7 A6 ADC ( 4 ( 10BIT $3A4: ( / / $3A4 - ADCM VREFS2 VREFS1 / 0-1 : ADC 2 : ADC - X 0 0 / VREFS=0 VDD - X 0 1 / VREFS=0 1 (VREF = 3.3V - X 1 0 / VREFS=0 2 (VREF = 2.4V - X 1 1 / VREFS=0 3 (VREF = 2.0V - 0 X X / 10 BIT - 1 X X / 12 BIT ADC ADC 500uS ADC 1 2 3, 20uS 29

30 $15 ( / / 0 : 10bit ADC $15 GO/ DONE TADC1 TADC0 ADCS /2-1 : ADC 3 : ADC / $3A5 X X X 0 // = 204 tad X X X 1 // = 780 tad X 0 0 X // tad = tosc X 0 1 X // tad = 4tOSC X 1 0 X // tad = 8tOSC X 1 1 X // tad = 16tOSC 10bit kHz X // = 12 tad / tad = tosc 0 X X X // 1 X X X /ADCON = 1, / / $3A5 ADCTS3 ADCTS2 ADCTS1 ADCTS0 / 12bit ADC 12bit ADC 2 tad = (TS [3:0]+1 * tad 15 tad 12bit = 14 tad + 10bit $15 ADCS 16 tosc 11 8 tosc 10 MUX 4 tosc 01 tosc 00 tosc 0 1 MUX tad TADC1 TADC0 EN32k 14 tad+(ts [3:0]+1 t 204 tad 780 tad 1X MUX 12 tad 0 1 MUX tad_conversion ADCM ADCS EN32k / kHz EN32K 1 EN32K 0 30

31 CH3:CH PORTA.0/AN0 A/D Coverter VREF Select VREF VDD Internal VREF PORTC.1 /VREF PORTA.1/AN1 PORTA.2/AN2 PORTB.2/AN6/OCP/OPIN1 PORTB.3/AN7/OVP PORTD.0/AN8 Input voltage 1001 PORTD.1/AN9/OPIN PORTC.1/VREF/AN10 OSCI/PORTE.0/AN OPOUT / : - / t AD, 1µs t AD 33.4 µs - /, / ( / - PXCR (X = A, B, D - I/O, I/O - / GO/ DONE - GO/ DONE - GO/ DONE / / - / 4tOSC - ADC HALT, "STOP" - ADC CPU HALT ( ADC 31

32 10. (OP 1 OP OPIN0 OPIN1 8 ADC Battery Bat+ OPOS 20m OPCH OPIN0/1 OP OPOUT TO ADC off-chip R 7R $397: OP / 0 : OP $397 - OPOS OPCH OPEN / 1 : OP 2 : - X X 0 / OP - X X 1 / OP X 0 X / OPIN0 OP X 1 X / OPIN1 OP - 0 X X / - 1 X X / 32

33 11. (PWM 8+2 PWM PWM PWMC PWM PWMP PWM PWMD PWM $20, $21 : PWM (PWMC / 3 : PWMn 0 : PWMn $20, $21 PWMnS TnCK1 TnCK0 PWMn_EN /2-1 : PWMn X X X 0 / I/O ( X X X 1 / PWMn X 0 0 X / PWMn = t PWMB ( X 0 1 X / PWMn = 2 t PWMB X 1 0 X / PWMn = 4 t PWMB X 1 1 X / PWMn = 8 t PWMB 0 X X X / PWMn ( 1 X X X / PWMn ( n = 0 1 PWM0 PORTC.2 PWM1 PORTD.3 t PWMB PWM TPWM tosc trc PWM $399: PWM (PWMCS / 1 : PWM $ TPWM REV0 / 0 : X / t PWMB = tosc X / t PWMB = trc 16M RC PWM RC RC 10µs PWM RC $22 - $23, $27 - $28: PWM (PWMP / $22,$27 PPn.3 PPn.2 PPn.1 PPn.0 / PWMn $23,$28 PPn.7 PPn.6 PPn.5 PPn.4 / PWMn n = 0 1 PWM = [PPn.7, PPn.0] X PWMn. [PPn.7, PPn.0] = 00H, PWMnS 0, PWMn [PPn.7, PPn.0] = 00H, PWMnS 1, PWMn 33

34 $24 - $26, $29 - $2B: PWM (PWMD / $24,$ PDFn.1 PDFn.0 / PWMn (2 $25,$2A PDn.3 PDn.2 PDn.1 PDn.0 / PWMn $26,$2B PDn.7 PDn.6 PDn.5 PDn.4 / PWMn n = 0 1 PWMn = ([PDn.7, PDn.0] + [PDFn.1, PDFn.0] / 4 X PWMn [PPn.7, PPn.0] [PDn.7, PDn.0], PWMnS 0, PWMn [PPn.7, PPn.0] [PDn.7, PDn.0], PWMnS 1, PWMn D 7E 7F 80 EF F PWMn clock tpwm PWMn output (PWMnS = 0 PWMn output (PWMnS = 1 [PPn.7, PPn.0] = F0H [PDn.7, PDn.0] = 7FH [PDFn.1, PDFn.0] =00H (n = 0 or 1 PWM output duty cycle = 7FH X tpwm PWM output period cycle = F0H X tpwm PWM A 0B 0C 0D 0E 0F A 0B 0C 0D PWMn clock tpwm Write [PPn.7, PPn.0] = 0DH Write [PDn.7, PDn.0] = 07H PWMn output (PWMnS = 0 n = 0 or 1 Duty cycle = 06H X tpwm Duty cycle = 06H X tpwm Duty cycle = 07H X tpwm Period cycle = 0FH X tpwm Period cycle = 0DH X tpwm PWM 34

35 tpwm [PDn.7, PDn.0] = 4; [PPn.7, PPn.0] = 10 [PDFn.1, PDFn.0] = 0 PWM 4/10 4/10 4/10 4/10 4/10 [PDFn.1, PDFn.0] = 1 PWM 5/10 4/10 4/10 4/10 5/10 [PDFn.1, PDFn.0] = 2 PWM 5/10 5/10 4/10 4/10 5/10 [PDFn.1, PDFn.0] = 3 PWM 5/10 5/10 5/10 4/10 5/10 PWM modulation period:10 tpwm modulation cycle 0 modulation cycle 1 modulation cycle 2 modulation cycle 3 modulation cycle 0 PWM cycle: 40 tpwm (8+2 bits PWM (8+2 bits PWM, PWM ( 0-3, : [PDFn.1, PDFn.0] (0-3 PWM I (I = 0-3 : I < [PDFn.1, PDFn.0] I [PDFn.1, PDFn.0] ([PDn.7, PDn.0] + 1/[PPn.7, PPn.0] [PDn.7, PDn.0]/[PPn.7, PPn.0] PWM PWM PWM [PPn.7, PPn.0] X tpwm 4*[PPn.7, PPn.0] X tpwm (4 X [PDn.7, PDn.0] + [PDFn.1, PDFn.0]/(4 X [PPn.7, PPn.0] (1 PWM (2 PWM (PWMP PWM : 4, 4 (3 PWM (PWMD PWM : 2, 4, 4 (4 PWM (PWMC PWMS PWM (5 PWM, PWM (PWMC PWM_EN 1 PWM (6 PWM, 2 3 (7 PWMn, 4, 4 (8 PWM HALT (9 PWM t PWMB = trc PWM STOP PWM t PWMB = tosc PWM "STOP" 35

36 12. (CMP V CMP V REFOV V REFLV 400K VIN VREFOV CMPOV debounce to over voltage comparator interrupt VCMP 100K VREFLV CMPLV debounce to lack voltage comparator interrupt to ADC(AN0 off-chip V IN V CPM =1/5V IN ADC AN0 V CMP $3AC: CMP $3AC / $3AC - CMPD1 CMPD0 CMPEN / 0 : 1-2 : debounce / I/O ADC ( / X / debounce =2µs X / debounce =4µs X / debounce =8µs X / debounce =16µs $3AD: / 0-1 : $3AD CMPLV1 CMPLV0 CMPOV1 CMPOV0 / V REFOV 2-3 : V REFLV X X 0 0 / 1.02V ( X X 0 1 / 1.04V X X 1 0 / 1.06V X X 1 1 / 1.08V 0 0 X X / 0.98V ( 0 1 X X / 0.96V 1 0 X X / 0.94V 1 1 X X / 0.92V 36

37 13. (LVR LVR, LVR LVR 4.0V 2.5V LVR : - VDD V LVR - VDD > V LVR 14. (WDT, RC, WDT MCU WDT ($1E 2-0, WDT ($1E 3 1 $1E, WDT STOP $1E: (WDT / - WDT.2 WDT.1 WDT.0 /2-0 : $1E WDT : ( X / WDT 4096ms X / WDT 1024ms X / WDT 256ms X / WDT 128ms X / WDT 64ms X / WDT 16ms X / WDT 4ms X / WDT 1ms 0 X X X WDT 1 X X X WDT, WDT : VDD = 5V 15. HALT STOP HALT, CPU HALT HALT, CPU (, ADC, STOP, CPU STOP STOP, ( ( Timer0 ( HALT, CPU STOP, ( Timer0 ( CPU, CPU HALT/STOP, HALT/STOP 37

38 16., :, Reset LVR : (1 fosc = 30kHz - 2MHz, 1/2 15 (32768 (2 fosc = 2MHz -10MHz, 1/2 14 ( STOP, WDT : kHz STOP RC - 1/2 7-1/ kHz : 1/2 2 1/2 15 (1 STOP, STOP (2 STOP, STOP (3 STOP, STOP STOP, warmup warmup,, warmup,,,, 38

39 : OP_OSCMSEL&OSC [3:0]: = = RC (16MHz/4=4MHz = RC (16MHz/2=8MHz = 8M 10M 8M 12M = 455K( =90pF~200pF 2M = 400K 455K( =65pF~90pF 1M = 4M ( =12pF~23pF = 4M ( =23pF~40pF = 8M 10M 8M 12M = kHz + RC (16MHz/4=4MHz = kHz + RC (16MHz/4=8MHz : OP_OSC 4: 0 = 2MHz - 10MHz ( 1 = 30kHz - 2MHz : OP_WDT: 0 = ( 1 = STOP OP_WDT_STOP: 0 = ( 1 = ( OP_WDT = 0,, CPU : OP_LVR: 0 = ( 1 = : OP_LVR0: 0 = LVR 4.0V ( 1 = LVR 2.5V OP_RST 0 = ( 1 = ( PORTE.1 I/O 39

40 OTP OTP OTP COB (Chip on Board, OTP In System Programming (, PCB OTP OTP OTP PCB, OTP, OTP OTP PCB OTP, OTP, PCB 4 OTP (VDD, VPP, SDA, SCK, Application PCB OTP Chip VPP VDD SCK SDA GND OTP Writer To Application Circuit Jumper : (1 PCB OTP 4 (2 OTP OTP (3 OTP, 4 OTP, OTP 40

41 ADC X (, B bbb xxx xxxx AC <- Mx + AC + CY CY ADCM X (, B bbb xxx xxxx AC, Mx <- Mx + AC + CY CY ADD X (, B bbb xxx xxxx AC <- Mx + AC CY ADDM X (, B bbb xxx xxxx AC, Mx <- Mx + AC CY SBC X (, B bbb xxx xxxx AC <- Mx + -AC + CY CY SBCM X (, B bbb xxx xxxx AC, Mx <- Mx + -AC + CY CY SUB X (, B bbb xxx xxxx AC <- Mx + -AC +1 CY SUBM X (, B bbb xxx xxxx AC, Mx <- Mx + -AC +1 CY EOR X (, B bbb xxx xxxx AC <- Mx AC EORM X (, B bbb xxx xxxx AC, Mx <- Mx AC OR X (, B bbb xxx xxxx AC <- Mx AC ORM X (, B bbb xxx xxxx AC, Mx <- Mx AC AND X (, B bbb xxx xxxx AC <- Mx & AC ANDM X (, B bbb xxx xxxx AC, Mx <- Mx & AC SHR > AC [3], AC [0] -> CY; AC 1 ADI X, I iiii xxx xxxx AC <- Mx + I CY ADIM X, I iiii xxx xxxx AC, Mx <- Mx + I CY SBI X, I iiii xxx xxxx AC <- Mx + -I +1 CY SBIM X, I iiii xxx xxxx AC, Mx <- Mx + -I +1 CY EORIM X, I iiii xxx xxxx AC, Mx <- Mx I ORIM X, I iiii xxx xxxx AC, Mx <- Mx I ANDIM X, I iiii xxx xxxx AC, Mx <- Mx & I 1.3. DAA X xxx xxxx AC, Mx <- CY DAS X xxx xxxx AC, Mx <- CY CY 41

42 2. LDA X (, B bbb xxx xxxx AC <- Mx STA X (, B bbb xxx xxxx Mx <- AC LDI X, I iiii xxx xxxx AC, Mx <- I 3., BAZ X xxxx xxx xxxx PC <- X, AC = 0 BNZ X xxxx xxx xxxx PC <- X, AC 0 BC X xxxx xxx xxxx PC <- X, CY = 1 BNC X xxxx xxx xxxx PC <- X, CY 1 BA0 X xxxx xxx xxxx PC <- X, AC (0 = 1 BA1 X xxxx xxx xxxx PC <- X, AC (1 = 1 BA2 X xxxx xxx xxxx PC <- X, AC (2 = 1 BA3 X xxxx xxx xxxx PC <- X, AC (3 = 1 CALL X RTNW H, L xxxx xxx xxxx h hhh llll ST <- CY, PC +1 PC <- X ( p PC <- ST; TBR <- hhhh, AC <- llli RTNI CY, PC <- ST CY HALT STOP JMP X 1110p xxxx xxx xxxx PC <- X ( p TJMP PC <- (PC11-PC8 (TBR (AC NOP PC I AC -AC CY & Mx bbb RAM p ROM B RAM ST TBR 42

43 * V to +7.0V GND-0.3V to VDD + 0.3V C to +85 C C to +125 C *, (VDD = V, GND = 0V, TA = 25 C, VDD V 30kHz fosc 10MHz VDD V 30kHz fosc 4MHz (HALT IOP ISB ma ma ma ma (STOP ISB µa WDT IWDT µa VIL1 GND X VDD V I/O, VDD = 5.0V fosc = 10MHz, NOP, WDT, ADC, LVR VDD = 5.0V fosc = 4MHz, NOP, WDT, ADC, LVR VDD = 5.0V fosc = 10MHz ( HALT, WDT, ADC, LVR VDD = 5.0V fosc = 4MHz ( HALT, WDT, ADC, LVR VDD = 5.0V ( STOP, WDT, ADC, LVR, VDD = 5.0V ( STOP, WDT, ADC, LVR, VDD = 5.0V VIL2 GND X VDD V RESET, T0, T1, OSCI, VDD = 5.0V VIH1 0.7 X VDD - VDD V I/O, VDD = 5.0V VIH2 0.8 X VDD - VDD V RESET, T0, T1, OSCI, VDD = 5.0V IIL -1-1 µa I/O, GND < VIN< VDD, VDD = 5.0V RPH kω VDD = 5.0V RPH kω VDD = 5.0V VOH VDD V I/O, PWM0, IOH = -10mA, VDD = 5.0V VOL - - GND V I/O, PWM0, IOL = 20mA, VDD = 5.0V : 5.0V, 25 C, VDD 150mA GND 150mA 43

44 (VDD = 2.4V - 5.5V, GND = 0V, TA = 25 C, f OSC = 30kHz - 10MHz, treset µs VDD = 5.0V WDT twdt ms VDD = 5.0V RC frc MHz VDD =5.0V, TA =2 5 C RC frc MHz VDD =3.0V~5.5V, TA = -40 C ~ 85 C tcy µs fosc = 30kHz - 10MHz T0 tiw (tcy + 40/N - - ns N = tipw tiw/2 - - ns T1 T2 T3 T4 T5 T6 T7 T8 T1 T2 T3 T4 fosc System Clock tcy tipw(l tipw(h T0 input signal tiw 44

45 / (A/D (VDD = 2.4V - 5.5V, GND = 0V, TA = 25 C, f OSC = 30kHz - 10MHz, NR bit GND VAIN VREF 1 VREF V 2 VREF V VDD =2.7~ 5.5V 3 VREF V VDD =3.6~5.5V VREF VDD V ADC VAIN GND - VREF V ADC RAIN kω VIN = 5.0V ZAIN kω ADC IAD ma ADC, VDD = 5.0V EDNL - - ±1 LSB EINL - - ±3.5 LSB EF - - ±4 LSB EZ - - ±6.5 LSB V DD =2.7~ 5.5V V REF = 5.0V/2.4V, ADC CLK 1.0MHz V DD =2.7~ 5.5V V REF = 5.0V/2.4V, ADC CLK 1.0MHz V DD =2.7~ 5.5V V REF = 5.0V/2.4V, ADC CLK 1.0MHz V DD =2.7~ 5.5V V REF = 5.0V/24V, ADC CLK 1.0MHz EAD - - ±8 LSB V DD =2.7~ 5.5V V REF = 5.0V/2.4V, ADC CLK 1.0MHz ADC tad µs fosc = 30kHz - 10MHz ADC tcnv tad ADCM = 1 ADC tcnv tad ADCM = 0 ADCS = 0 ADC tcnv tad ADCM = 0 ADCS = 1 VREF ppm/ OP (VDD = 2.4V - 5.5V, GND = 0V, TA = 25 C, f OSC = 30kHz - 10MHz, IOP ma OP VCMPOS mv OP VOPIN mv VOPOUT GND V VDD =3.0~ 5.5V (CMP (VDD = 2.4V - 5.5V, GND = 0V, TA = 25 C, f OSC = 30kHz - 10MHz, ISSDC µa CMP VDD =5V VCMP V CMP ECMP mv CMP PSRR db CMP VDD =3.6V CMRR db CMP VDD =3.6V (GND = 0V, TA = 25 C, f OSC = kHz - 10MHz, 1 VLVR V LVR 2 VLVR V LVR 45

46 46 ( C3 104 C12 22uF /10V D1 R1 8.2K PC USB-IN R PA1 J2 J1 USB-OUT VDC=+5V V+ D+ D- V- GND GND V+ D+ D- V- GND GND C10 22uF/10V C11 22uF /10V C2 104 R3 100K R2 400K C1 104 OUTE C6 104 PWM1 PORTC.2 PORTC.3 RESET GND PORTA.0 PORTA.1 PORTA.2 PORTD.1 PORTD.0 PORTC.1 PORTC.0 PORTE.0 VDD PORTB.3 PORTB OUTE OPIN0 VDD PC2 U1 AN8 PB3 PC1 PC0 PA1 C7 104 VDD R12 47K C8 104 D2 D3 VDC BAT+ Q3 D S G R10 10 PC1 PC0 L1 L2 L3 L4 R13 1K R14 1K C9 105 DC-DC R6 0.05/0.5W BATTERY BAT+ C4 104 R7 470 D S G D S G M2 M1 DW01 VCC GND CS OC OD C5 104 R4 100 R5 1K OPIN0 R9 0.05/0.5W C R8 470 OPIN1 OPIN1 PB3 AN8 4.7uF L1 D S G Q4 10 R11

47 Part No. L/016LU L/008MU Package 16L SOP 8L SOP 47

48 SOP 16L(150mil : / e Min Max Min Max A A A b c D E e 0.050(BSC 1.27(BSC H E L θ

49 SOP 8L : / b L c E HE? 4 D A 2 A e A1 Seating Plane See Detail F Min Max Min Max A A A b c D E e 0.050(BSC 1.27(BSC H E L θ

50 2.0 SOP8L