Design and analysis of an x-band MMIC "bus-bar" power combiner - High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO. 1999

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1 DESIGN AND ANALYSIS OF AN X-BAND MMIC BUS-BAR POWER COMBINER S. P. Marsh, D. K. Y. Lau*, R. Sloan**, L. E. Davis** GEC-Marconi Materials Technology Limited, Caswell, Towcester, Northamptonshire, 12 8EQ, UK *Roke Manor Research Limited, Romsey, Hampshire, SOS 1 OZN **Department of Electrical Engineering and Electronics, Communications and Electronics Group, UMIST, PO Box 88, Manchester, M60 lqd, UK ABSTRACT: A design procedure has been developed for the bus-bar MMIC power combiner. All the assumptions made during the design are tested and verified, and the amplitude and phase balances of such a combiner are analysed. The effects of power imbalance on the overall gain of a 4 W MMIC power amplifier are also investigated at 10 GHz. 1 INTRODUCTION: The so-called bus-bar MMIC power combiners have been extensively used in MMIC power amplifiers [l, 21, and their major advantages have been described in [3]. Up to the present time, the design technique and analysis of various types of power combiners have been published extensively in the literature. However, there are very few publications regarding the design procedure and analysis of the so-called bus-bar or manifold MMIC power combiners, which are commonly used in MMIC power amplifiers. The bus-bar combiner is a wide metal track which runs immediately across the output of the transistors. The power from the transistors is combined in the wide track, and is tapped-off symmetrically on the output side of the bus-bar and fed to a single output using a tree combining structure. The high levels of DC current needed to bias the drains are conveniently fed to all the devices from either end of the bus-bar, which is one of the major advantages among many others [3]. The main objectives of this work are to develop a design procedure for the bus-bar combineddivider; analyse their performance at the X-band; and verify all the assumptions made during the design, paying particular attention to combining imbalance and its effect on the overall amplifier performance. 2 DESIGN METHOD: The design method presented in this section is applicable to both the input divider and output combiner, but an output combiner is used as an example. The design of the bus-bar power combiner was broken down into three main parts: construction of the bus-bar linking the outputs of the eight transistors; matching the impedance at the bus-bar to 50 R using the tree combining structure; and feeding the DC bias current to the bus-bar with the minimum of perturbation. 2.1 Construction ofthe Bus-Bur: Assuming eight active devices are to be employed, the layout of the combiner can be constructed, as shown in Figure 1, using microstrip transmission line models for electrical simulation. The length and width of the connecting lines at ports A+H, and the centre-tocentre distance between the ports can be arbitrarily chosen to satisfy the layout requirements and separation of the power transistors. The width of the bus-bar is chosen to be wide enough to handle the DC current required to bias the drains/collectors of all the eight transistors through either end of the bar. Such a wide track will inherently present a low impedance to the devices which also possess a low output impedance. Power is then tapped off at symmetrical points (I+L) along the bus-bar, and combined by a tree structure combiner. The same principle can be applied to 2N transistors, where N=number of transistors. The assumptions that made during the design of this combiner are that all the ports are simultaneously driven by a signal with same amplitude and phase, and that the device X/99/$ IEEE 164

2 separation is much less than the wavelength at the highest frequency of interest. This ensures the electrical length between transistor outputs is very short and odd-mode oscillation [4] is not supported. Secondly, because the signals feeding the bus-bar are equal in phase and amplitude, and the electrical length is short, there is no RF current flowing between ports A+H. Therefore, all the points along the bus-bar at mid-way between the transistors (U+Y and I+L) are assumed virtual open-circuits for RF signals output from the transistors. Therefore, the structure in Figure 1 can be seen as a parallel connection of four independent 2: 1 combiners. 2.2 Multi-Section ImDedance Matchinn Using The Tree Structure: The combiner must be designed to present the correct impedance to the outputs of all the transistors. In this case the combiner was designed for optimum signal gain so the next step was to check the stability of the chosen transistor, and then calculate the simultaneous input and output conjugate match conditions required for optimum gain. These steps, and the design of the combiner which follows, were performed with the aid of a commercial simulator (HP Eesof Libra ). Assuming the simultaneous output reflection coefficient of the transistor is maglang, then for design purposes, each of the ports (A+H) along the bus bar is terminated with the conjugate (magl-ang) for optimum power gain. This impedance can then be transformed through the bus-bar to give the impedance at ports I+L. The power at ports I, J, K and L needs to be combined at the 50 f2 output port. This can be done by employing the corporate (tree) structure as shown in Figure 2(a). It can be seen from Figure 2(a) that the binary symmetry of the tree network is preserved, which is necessary for in-phase combining of power at the fial output port. The next step is to transform the impedances at I, J, K and L into 50 IR using the tree structure as the matching elements. An equivalent circuit of the tree structure is shown in Figure 2(b), where the magnitude of the impedances at I, J, K and L (Figure 2(a)) are all assumed to be &, and the lumped inductors and capacitors (L and C) serve as RF combiner, and also transforming the impedances to an intermediate value (2Z, = UCZ, - j/oc). Effectively, the whole tree structure can be seen as a twosection L-C network, and from the theory of multi-section impedance matching [5], it can be shown that maximum bandwidth for the transformation is obtained if the intermediate impedance is chosen to be z, = JE, which is analogous to the U4 transformer and indeed gives the same bandwidth. Note that other Z, values can also be chosen to give a particular passband ripple. Therefore, the first section LC network is used to transform the imaginary part of & to zero, and the real part of Z, into 2%. The second LC network transforms Z,into 2ZL (2x50 a). Note that other transformer networks such as T or Pi-networks can replace the LC sections, depending on which one is more appropriate for the circuit design and layout requirements. A similar technique can also be applied to more than two sections. These impedance matching procedures can be done in a simulator such as Libram, where the lumped inductors are replaced by foundry microstrip line models, and the lumped capacitors are replaced by foundry capacitors models. The whole combiner can then be optimised until the reflection coefficient at the final output port is minimum, using the physical dimensions of the microstrip lines and capacitors as the variables for optimisation (bus-bar width, and transistor port physical dimensions are fixed). The same approach is also applicable for the input divider, but additional matching elements can be symmetrically placed along the bus-bar at points U+Y to aid the impedance transformation, since the input impedance of most microwave power transistors is very low (this is demonstrated in the X-band MMIC design shown in next section). The input divider and output combiner can then be connected to the paralleled transistors, and the whole circuit is re-optimised. 2.3 Feeding DC Bias to the Bus-Bar: One of the attractive features of the bus-bar dividerkombiner is its ease of feeding the DC bias current to the transistors. An optimised 4W MMIC power amplifier chip layout is shown in Figure 3. The design was implemented using GMMT HEMT (H40) foundry passive elements, eight 8x40 pm HBTs, on a 100 pm thick GaAs substrate and simulated with Hp Eesof Libra, whilst the planar input divider and output combiner were simulated by the Momentum EM simulator. The DC bias current required by the bases of the HBTs is fed through the spiral inductors at each end of the input bus-bar. These inductors appear as good open-circuits to the RF 165

3 signals on the input bus-bar, and so do not perturb the balance of the design. Additional capacitors are placed on the bus-bar to transform the input impedance of the transistors to a higher value. Effectively, the input divider can be seen as a 3-section L-C network, and the technique described in section 2.1 has been used to obtain optimum matching and bandwidth. For the output combiner, the bias feed was a wide transmission line terminated in a capacitor to ground. Unless this transmission line is one quarter-wavelength long, it will not provide a good open circuit across a broadband, and could perturb the balance of the output combiner. The actual length of the bias feed line at each end of the bus-bar was chosen to be 600 pm, and the effect this has on the combiner imbalance, being less than M4, is explained and analysed in the next section. 3. COMBZNER IMBALANCES: Differences in impedances presented to the transistors will produce differences in the output power and gain of the transistors. Therefore it was decided to analyse the imbalances of the X-band design to test the design assumptions and the impact these have on the final MMIC performance. The effect on the transmission and phase characteristics, as a function of the length of the feed line, is shown in Figure 4(a) and (b) respectively at 10 GHz (port A, B, C & D referred to Figure 1). As can be seen from Figure 4(a) and (b), transmission amplitude and phase are equal when the stub length is 2700 pm (M4 wavelength). Amplitude and phase imbalance will only be negligible if at each line of symmetry, half-way between the devices actually appear as an open circuit. Under this condition a signal from port I (Figure 1) will only travel to A and B and not laterally to C and D. Hence the virtual open-circuits assumptions are valid. For stub length less than 2700 pm, the transmission amplitude deviates from -9.5 db amplitude (ideal split should be -9 db). Port A (Figure 1) is nearest to the stub line so it is most affected. The phase deviation between port A and D is greater than 10 as the stub length is reduced to below 600 p (Figure 4(b)). It was found that the loss of the input divider was 0.3 db, with no power imbalance at X-band. The effect of presenting an impedance different from the desired conjugate match impedance has an effect on the gain of the individual transistor. This effect is shown in Figure 5. Assuming that the variation in stub length has no effect on the impedances presented to the input divider, it can be seen from Figure 4 that if the stub length is within pm, the maximum drop in gain of the HBT at port A and D (Figure 1) are 0.2 and 0.05 db respectively (ideal gain is 8.6 db), which is small enough to be acceptable. For this reason, and for the most compact MMIC, the stub length used in the output combiner was chosen to be 600 p. Overall, this shows that the imbalance caused by the stub length only has a small effect on the gain of each HBT. The maximum drop in gain when the stub length is zero (i.e. ends of bus-bar short-circuited) at port A and D is 1.42 and 0.14 db respectively, so the least affected HBTs are those which are located furthest away from the end of the bus-bar, which is as expected. For all combinations of two signals (e.g. port A & B, A & C, A & D,... etc.), the average excess insertion loss due to power imbalance for the 8-port output bus-bar combiner is estimated [6]. The loss is 0.46 db and 0.05 db respectively, for stub length at 600 pm and 2700 pm. Similar values can be obtained by connecting an ideal splitter to the output combiner in the LibraTM simulator. The effect of combiner imbalances and HBT s gain degradations on the whole amplifier circuit is shown in Figure 6. It is known that the stable, maximum available gain of the 8x40 pm HBT power cell is 8.6 db at 10 GHz. The simulated gain of the amplifier at 10 GHz is 7.7 db, using the H40 microstrip elements as the dividedcombiner. This means the loss in gain is approximately 0.9 db at 10 GHz. It can be seen that the degradation in gain, input/output return loss and isolation due to shortening the stub length is small. The worst gain degradation is 0.4 db at 10 GHz, which is due to the use of zero stub length. The overall loss in gain is contributed by resistive loss of the 166

4 % output dividedcombiner; impedance mismatch; imbalances and the drop in gain of the individual transistor. These losses are tabulated in Table 1 for the two stub lengths used in the analysis. 4. CONCLUSION: The design of a microstrip bus-bar power combineddivider at X-band has been demonstrated. The concepts of virtual opencircuits at points mid-way between the devices was validated by the fact that negligible amplitude and phase imbalances were observed when the ends of the bus-bar are presented with opencircuits. A 4 W MMIC power amplifier has been designed, it was found that as long as the stub length is between pm (31116 to 3114 at 10 GHz, using GaAs substrate), the effects of combiner amplitude and phase imbalances on the overall gain of the amplifier is small enough to be acceptable. The combineddivider is not only very compact, it is very convenient for DC bias feeding and also suppression of odd-mode oscillations. REFERENCES [ 11 McQuiddy Jr D. N., The Challenge - Applying High Performance Military MMIC Fabrication Processes to Price Driven Commercial Products, IEEE MTT-S Symposium Digest, 1994, pp [2] Liu, W., Khatibzadeh, A., Kim T., Sweder, J., First Demonstration of High-PoweGaInP/GaAs HBT MMIC Power Amplifier With 9.9 W Output Power at X-Band, ZEEE Microwave and Guided Wave Letters, September 1994, vol. 4, no. 9. [3] Marsh, S. P., Power Splitting and Combining Techniques on MMICs, The GEC Journal of Technology, 1998, vol. 15, no. 1, pp [4] Freitag, R. G., A Unified Analysis of MMIC Power Amplifier Stability, ZEEE MZ-S Symposium Digest, 1992, pp [5] Bowick, C, RF Circuit Design, Howard U! Sams & Co., pp , [6] Franke, E. A, Excess Insertion Loss at the Input Ports of a Combiner Hybrid, RF Design, November 1985, pp I J 4* 4(. a I. * I.. e I. I I.. 1 II I II I II I II I [ I I II I II I II U V ~ W X ~ T. bus-barcombiner Parallel transistors Figure 1 Construction of the Bus-bar combiner 167

5 i I....,.... a :... I R Figure 2 (a) Tree structure combining (b) Equivalent circuit of the tree structure Dc Bias-feedlint -MIM capacitors Temimted to ground,transmission inductors lines modelled as Figure 3 4 WMMICpower amplijier using eight HBTpower cells stub length (urn) Figure 4 (a) Transmission amplitude & (b) phase variation caused by changes in stub length 168

6 Figure 5 Effects on gain of the HBT at port A and D 0 input rehim loss 0 isolation V forward gain A output return loss Frequency 0.5 GHz/DIV._ Figure 6 Effects on amplfler due to shortening the U4 short-circuited stub Table 1 Contributions to degradation in gain ut IO GHz (using HF' EEof LibraTM) 169

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