LM7WP_MB_V03_0414_1349

Transcription

1 irst International omputer,inc Protable omputer roup W epartment oard name : Mother oard chematic. chematic Page escription : Project : LMW+. PI & IRQ & M escription : Version : 0. Initial ate : pril, 00. lock iagram :. Nat name escription :. oard tack up escription :. chematic modify Item and istory :. power on & off & equence :. Layout uideline :. switch setting Manager ign by: rawing by : Tom_Lin Total confirm by: _TO LN ircuit check by: udio ircuit check by: irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <> 0. riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試

2 . chematic Page escription : LMW+ chematic Ver : 0... VT+ (/)..V/,./.VM/. chematic Page escription. VT+ (/). VM / VM. lock iagram. VT+ (/). VP/.VM. NNOTTION. Power ood & an ontroller. V / V / PMU/V. chematic Modify. 0 ardus ontroller. POW-ON ontroller. Timing iagram. 0 ardus Power W./NN 0. IN / attery NN. R Layout uideline. MINI PI. harge ircuit / IN. Yonah processor (/) 0. VT0L PY. Inverter ontroller. Yonah processor (/). U NN. udio board 0. POWR (PU OR). -T / -ROM NN. witch transfer board. Thermal / VR_PWR / RT. LP PMU0. Update list. lock enerator. LP K MX. lock uffer. INT K / P onnector. VN00 (/). M onnector. VN00 (/). IP witch & L. VN00 (/). irm Ware ub / LI witch. VN00 (/). Reset ircuit. R O-IMM 0. OVP / RW. R O-IMM0. L udio odec 0. VT LV Transmitter. +0 udio mplifier. L onnector..p. Out / udio NN. RT onnector. R PWR. PI & IRQ & M escription : IL PIINT IRQ IRQ IRQ IRQ IP IP UMTR RQ RQ0 / NT0 RQ / NT RQ / NT RQ / NT RQ / NT Mini PI(Wireless LN) ardus MiniPI/N MiniPI/ardus MiniPI IP MiniPI ardus Mini PI(Wireless LN) IRQ hannel IRQ0 IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ0 IRQ IRQ IRQ IRQ IRQ esciption ystem timer Keyboard (asacde) LN / MOM erial Port UIO / V / U LOPPY IK LPT RT PI (isable by default) IR (MOM/LN) ardbus P/ mouse PU ROM M hannel M0 evice IR M P M LOPPY IK M UIO M (ascade) M Unused M Unused M Unused (disable by default) (MOM / LN) irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <> 0. riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試

3 . lock iagram : LK I0 P IN P V/V P RT L Thermal ensor P P PMUV/V P V/V P R 0.VM P VP/.VM P attery charger T ON MT RJ- P0 VM/VM P.V/M P Over Voltage Protect P0 P attery elect P0 P0 attery Voltage sense P P LN Phy VT0L U, VT LV Tx U.0 udio XT board Mini PI P P0 P0 N 0 Ver:0 MII U U0, P PMI P P Intel Yonah eleron Mz it PI U P Processor VI VN00 ost us P~P VT P~P P, ub Interface LP U K/ TRL LP MX INT K/ P PMI LOT0 P Mem us I U -T P P ROM P -Link P P PU OR P0 PU VP P R 00/ INTR L ROM ( /W ub) M N NN P RT P RT P P,P P ' O L P M NN P LP PMU0 P udio MP PON Mic IN LK uffer R Pull up LI/IP W MIN W NN P udio XT board L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- P P,P P, P irst International omputer, Inc. LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <> 0. riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試

4 . Nat name escription :.oard tack up escription Voltage Rails IN PMUV PMUV V V V V VM VM Vcore_PU Primary system power supply.0v always on power rail by LT or IN.V always on power rail by LT or IN.0V always on power rail by ON or PU0.V always on power rail by ON or PU0.V power rail.0v power rail.v switched power rail.0v switched power rail ore Voltage for PU P Layers Layer Layer Layer Layer Layer Layer Layer Layer omponent ide, Microstrip signal Layer round Plane tripline Layer(TL,LOK,R) Power Plane round Plane tripline Layer(nalog,LV,other) round Plane older ide,microstrip signal Layer VP.VM R_0.VM.VM.V.V.V.0V for TL+ Termination Voltage.V for PU PLL Voltage 0.V R Termination Voltage.V switched power rail.v power rail.v always on power rail.v power rail for R Part Naming onventions N L Q R RP U Y = = = = = = = = = = apacitor onnector iode use Inductor Transistor Resistor Resistor Pack rbitrary Logic evice rystal and Osc Net Name uffix 0 = ctive Low signal ignal onditioning = _Q_ = _L_ = amped (by a resistor) Isolated (by a Q-switch) iltered (by an inductor or bead) irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <> 0. riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試

5 .chematic modify Item and istory : irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <> 0. riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試用版建立黸

6 . power on & off & equence : Power On equencing Timing iagram VI VR_ON Tsft_star_vcc Vcc-core Tboot Vboot Vid Tboot-vid-tr PU_UP Tcpu_up Vccp Vccp_UP Tvccp_up Vccgmch MPWR Tgmch_pwrgd LK_NL# IMVP_PWR Tcpu_pwrgd TTRY ONLY POWR ON TIMIN POWW0 PMUV/PMUV UPN N RUM TIMIN POWW0 ON V MINW0_I To I PMUV/PMUV ON V PM_RMRT0 PM_LP_0 To I_M rom I_M PM_RTRT0 PM_LP_0/0/0 PU0 UTT_0 VM,V PM_PWROK To I rom I rom I_0 rom I_0 PM_LP_0/0 PU0 UTT_0 V VM PM_PWROK Y_PWROK VRON_VP rom I_M rom I_0 rom I_0.V N R_PWR Y_PWROK VP,.VM VRON_VP VP/.VM VOR_ON VOR_ON VR_ON VR_ON VOR_PU VOR_PU K0_PWR0 To clock generator To OM and I K0_PWR0 PM_VT To clock enerator ToI and OM PM_VT rom I to PU PU_PWROO rom I to PU PU_PWR PI_RT0 TL+_PURT0 To OM/other PI device PI_RT0 TL+_PURT0 To OM/other PI device rom OM to PU rom OM to PU irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <> 0. riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試

7 . Layout uideline : Montara-M R Layout uidelines Note that all length matching formulas are based on M die-pad to O-IMM pin total length roup locks ata ontrol ommand P R ignal roups eedback ignal Name K[:0] K#[:0] Q[:0] Q[:0] M[:0] K[:0] #[:0] M[:,:0] [:0] R# # W# M[,,,] M[,,,] RVNOUT# RVNIN# lock ignals Topologies and Routing uidelines M Pin P Package Length Range L Min:0." Max:.0" Length Matching ormulas ignal roup Minimum Length Maximum Length ontrol to lock ommand to lock P to lock trobe to lock ata to trobe O-IMM P lock -.0" lock -.0" lock -.0" lock -.0" trobe - mils lock + 0." lock +.0" lock + 0." lock + 0." trobe + mils mil trace, mil pair space lock length tolerenve within the pair : +/- 0 mil lock to lock Length Matching : +/- mils Minimum Pair to Pair pacing : 0 mils Minimum pacing to other ignals : 0 mils LOK LKPU[..0] LKN[..0] LKITP[..0] MLK_I MLK_M PLK_TI PLKI PLK PLK PLKU0 PLKOP PLKW PLKIO PLKLN MLK_IO MLK_I MLK_ MLK_I MLK_ LNT " ~ "." ~.0 " MX :."."~.0"."~.0"." ~." TR / P NOT.ifferentials pairs with the same length / 0 mils (within 0 mil) ( mil space.pu & N trace between + & - ) mismatch within 0 mil / 0 mils / 0 mils / 0 mils / 0 mils * MLK_I & PLK_M PLK_TI Length mismatch within 00 mils.making PI length with minimum various.max skew = ns ata ignals Topolog ies and Routing uidelines M Pin P Package Length Range L L L L O-IMM0 P O-IMM P ohm % Minimun pacing to Trace Width Ratio, Q/M : to Q : to Minimum pacing to other ignals : 0 mils Trace Length L : Min 0.", Max." L : Max 0." L : Min 0.", Max.0" L : Max.0 " Length Matching : Q to K/K# Q OIMM0 P+L+L Q, OIMM P+L+L+L Min : lock -.0", Max : lock + 0." Q/M to Q : +/- mils Q/M to Q Mapping ignal Mask Relative To Q[..0] Q[..] Q[..] Q[..] Q[..] Q[..0] Q[..] Q[..] Q[..] M[0] M[] M[] M[] M[] M[] M[] M[] M[] Q[0] Q[] Q[] Q[] Q[] Q[] Q[] Q[] Q[] Mismatching +/- mil +/- mil +/- mil +/- mil +/- mil +/- mil +/- mil +/- mil +/- mil ontrol ignals Topolog ies and Routing uidelines M Pin P Package Length Range L O-IMM0, P ommand ignals To pologies and Routing uidelines M Pin P Package Length Range L L L 0 ohm % L L O-IMM P ohm % ohm % Trace spacing to trace width ratio : to Minimum pacing to other ignals : 0 mils Trace Length L : Min 0.", Max." L : Max.0" Length Matching : TRL(P+L) to K/K# Min : lock -.0", Max : lock + 0." Trace spacing to trace width ratio : to Minimum pacing to other ignals : 0 mils Trace Length L Min 0.", Max.0" L Max.0" L : Max.0" L+L : Max.0" L : Max.0" Length Matching : M to K/K# M OIMM0 P+L+L M, OIMM P+L+L Min : lock -.0", Max : lock +.0" P ignals Topologi es and Routing uidelines M Pin P Package Length Range L O-IMM0, P L ohm % Trace spacing to trace width ratio : to Minimum pacing to other ignals : 0 mils Trace Length L : Min 0.", Max." L : Max.0" Length Matching : P(P+L) to K/K# Min : lock -.0", Max : lock + 0." irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- O-IMM0 P LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <> 0. riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試

8 _NMI 0p V 0% MT00 XR LR(NU) TL+_PURT0 0p V 0% MT00 XR LR(NU) U Topology : RR# TL+_0 J _MI0 TL+_0 TL+_0 0p V 0% MT00 XR LR(NU) []# # L VP L L Rtt Transmission Line TL+_0 []# NR# TL+_NR0 M PU Im _0M0 TL+_0 TL+_PRI0 0p V 0% MT00 XR LR(NU) []# PRI# K 0." - " 0" -.0" +/-% Micro-strip TL+_0 []# M Rtt _INN0 TL+_0 TL+_R0 0 0p V 0% MT00 XR LR(NU) []# R# N L L 0." - " 0" -.0" +/-% trip-line TL+_0 []# RY# TL+_RY0 J _INTR TL+_00 TL+_Y0 0p V 0% MT00 XR LR(NU) []# Y# N TL+_0 [0]# P TL+_R00 TL+_0 []# R0# TL+_R00 P VP VP TL+_0 []# L 0 R Ω % /0W MT00 LR losed to PU TL+_0 []# IRR# _INIT0 VP,,,,, P PU IMVP L L L L Rtt Transmission Line TL+_0 []# INIT# _INIT0, P Rtt Rtt TL+_0[..] TL+_0 []# TL+_0[..] R []# LOK# TL+_LOK0 0." -." 0." -." 0" -.0" 0" -.0" 0 +/-% Micro-strip TL+_T00 L T[0]# TL+_PURT0 L L+L L 0." -." 0." -." 0" -.0" 0" -.0" 0 +/-% trip-line TL+_RQ00 RT# TL+_PURT0 K TL+_RQ0 RQ[0]# R[0]# TL+_R00 TL+_RQ0 RQ[]# R[]# TL+_R0 K TL+_RQ0 RQ[]# R[]# TL+_R0 J TL+_RQ0[..0] TL+_RQ0 RQ[]# TRY# TL+_TRY0 TL+_RQ0[..0] L RQ[]# Topology : PWROO Topology : PULP# TL+_0 IT# TL+_IT0 Y TL+_PURT0 TL+_0 TL+_ITM0 00p 0V % MT00 NPO LR(NU) []# ITM# U PU Im L Transmission Line PU M L Transmission Line TL+_0 []# R XP_PM0 _TPLK0 0p V 0% MT00 XR LR(NU) TL+_00 []# PM[0]# W XP_PM 0." - " Micro-strip 0." - " Micro-strip TL+_0 [0]# PM[]# U XP_PM L L _PULP0 0p V 0% MT00 XR LR(NU) TL+_0 []# PM[]# Y XP_PM 0." - " trip-line 0." - " trip-line TL+_0 []# PM[]# U XP_PRY,,,,, VP PU_PLP0 0p V 0% MT00 XR LR(NU) TL+_0 []# PRY# R XP_PRQ TL+_0 []# PRQ# T XP_TK Topology : INTR, NMI, 0M#, PLP#, INN#, INIT# MI#,, TPLK# Topology : RT# _INIT0 0p V 0% MT00 XR LR(NU) TL+_0 []# TK T XP_TI TL+_0 []# TI W XP_TO TL+_0 []# TO W XP_TM R losed to PU PU Im L Transmission Line M PU L Transmission Line TL+_0 []# TM Y XP_TRT0 Ω % /W MT00 LR TL+_00 []# TRT# W 0 XP_RT0 0." - " Micro-strip " - " Micro-strip TL+_0[..] TL+_0 [0]# R# TL+_0[..] Y []# L L TL+_T0 V T[]# PROOT# PROOT# 0 0." - " trip-line " - " trip-line _0M0 TRM TRM _0M0 _RR0 0M# TRM TRM _INN0 RR# _INN0 R INN# TRMTRIP# VP,,,,, Topology : TRMTRIP# _TPLK0 _TPLK0 0Ω % /W MT00 LR / hange to VP VP L L L+L L L Rss Rtt Transmission Line _INTR TPLK# _INTR M PU Im _NMI LINT0 _NMI " - " " - " " - " 0" -.0" 0" -.0" +/-% +/-% Micro-strip _MI0 LINT LK[0] PU_LK _MI0 MI# LK[] PU_LK0 L Rtt L L Rtt L " - " " - " " - " 0" -.0" 0" -.0" +/-% +/-% trip-line RV[0] T RV[0] RV[] RV[0] hould be connect to I and alistoga without T-ing(no stub) RV[0] M RV[0] RV[] N RV[0] RV[] T RV[0] RV[] V RV[0] RV[],,,,, VP No stub on _TPLK test point RV[0] RV[] XP P/U & P/ RV[0] RV[] XP_TO R Ω % /0W MT00 LR RV[] XP_TM R.Ω % /0W MT00 LR,,,,, VP RV[] RV[0] XP_TI R.Ω % /0W MT00 LR KT Molex ZI MT micro-p 0- Yonah PU Pin LR XP_PRQ R.Ω % /0W MT00 LR Micro-P XP_PRY R.Ω % /0W MT00 LR R ROUP 0 R ROUP RRV ONTROL XP/ITP INL LK TRM _0M0 PU_PLP0 _INN0 _INIT0 _INTR _TPLK0 _NMI _PULP0 _MI0 PI0 _RR0 TL+_R00 TL+_PURT0 PU_PWROO R R0 R R R R R R R R00 R0 R0 R0 R0 0Ω % /0W MT00 LR 0Ω % /0W MT00 LR 0Ω % /0W MT00 LR 0Ω % /0W MT00 LR 0Ω % /0W MT00 LR 0Ω % /0W MT00 LR 0Ω % /0W MT00 LR 0Ω % /0W MT00 LR 0Ω % /0W MT00 LR 0Ω % /0W MT00 LR(NU) Ω % /0W MT00 LR 0Ω % /0W MT00 LR Ω % /0W MT00 LR 00Ω % /0W MT00 LR Rout to TP via and place gnd via w/in 00mils #[-], PM#[0-]:Leave escape routing on for future functionality XP_PM0 XP_PM XP_PM XP_PM XP_RT0 XP_TRT0 XP_TK RP 0Ω % MT /W PR LR R 0Ω % /0W MT00 LR R 0Ω % /0W MT00 LR R0 Ω % /0W MT00 LR ommon lock ignal Layout uide : #, NR#, PRI#, R0#, Y#, R#, PWR#, RY#, IT#, ITM#, LOK#, R[..0]#, TRY#, RT#. Transmission Line Type Total Trace Length Normal Impedance pacing (mils) trip-line(int. Layer) Micro-strip(xt. Layer).0 ~. inch +/-% & mils & 0 mils,,0,,,,,.vm TL+_0[..0] U TL+_0[..0] TL+_0[..0] TL+_00 TL+_0 TL+_0[..0] ource ynchronous ata Length Variation and trobe Matching Requirements : TL+_0 [0]# []# TL+_0 TL+_0 []# []# ignals Name ignals Matching trobes associated with the group trobe-to-trobe omplement Matching V TL+_0 R TL+_0 []# []# V TL+_0 0KΩ % /W MT00 LR T#[..0], INV0# +/- 00 mils TP0#,TN0# +/- mils TL+_0 []# []# W TL+_0 TL+_0 []# []# U TL+_0 Q T#[..], INV# +/- 00 mils TP#,TN# +/- mils TL+_0 []# []# U TL+_0 TL+_0 []# []# U TL+_0 TR NPN MMT_NL 0V OT- PIN IRIL LR T#[..], INV# +/- 00 mils TP#,TN# +/- mils TL+_0 []# []# K TL+_00 _RR0 TL+_0 []# [0]# TL+_0 RR0 W T#[..], INV# +/- 00 mils TP#,TN# +/- mils TL+_00 []# []# J Y TL+_0 TL+_0 [0]# []# J TL+_0 TL+_0 []# []# Y TL+_0 TL+_0 []# []# ource ynchronous ata ignal Routing Topology# : Y TL+_0,,,,, VP TL+_0 []# []# TL+_0 VP,,,,, K R0 ignal Name Transmission Line Type Total Trace Length Normal Impedance Width & pacing (mils) TL+_0 []# []# TL+_0 0KΩ % /W MT00 LR []# []# TL+_TN00 W TN[0]# TN[]# TL+_TN0 ata-to-ata,trobe-to-strobe trobe-to-ata TL+_TP00 Y TP[0]# TP[]# TL+_TP0 TL+_INV00 J V INV[0]# INV[]# TL+_INV0 INV#[..0] trip-line 0. ~. inch +/-% & mils N/ R TL+_0[..0] TL+_0[..0] TL+_0[..0] T#[..0] trip-line 0. ~. inch +/-% & mils N/ TL+_0 TL+_0 TL+_0[..0] KΩ % /0W MT00 LR N TL+_0 []# []# K TL+_0 TN#[..0] trip-line 0. ~. inch +/-% & mils & mils TLR TL+_0 []# []# P TL+_00 TL+_0 []# [0]# R TL+_0 TP#[..0] trip-line 0. ~. inch +/-% & mils & mils TL+_00 []# []# L TL+_0 TL+_0 [0]# []# L TL+_0 R TL+_0 []# []# L 0 TL+_0 KΩ % /0W MT00 LR TL+_0 []# []# M TL+_0 Q TL+_0 []# []# P TL+_0 TL+_0 []# []# TL+_0 ource ynchronous ddress Length Variation and trobe Matching Requirements : P TR NPN MMT_NL 0V OT- PIN IRIL LR TL+_0 []# []# P TL+_0 _L TL+_0 []# []# TL+_0 _L ignals Name ignals Matching trobes associated with the group trobe to ssoc. ddress ignal Matching T TL+_0 []# []# R TL+_00 #[..], RQ#[..0] +/- 00 mils T0# +/- 00 mils TL+_0 []# [0]# L TL+_0 TL+_00 []# []# T TL+_0 #[..] +/- 00 mils T# +/- 00 mils TL+_0 [0]# []# N TL+_0 []# []# VP,,,,, TL+_TN0 M R0 TN[]# TN[]# TL+_TN0 *** No length matching requirements exist between T0# and T# TL+_TP0 N 0KΩ % /W MT00 LR TP[]# TP[]# TL+_TP0 TL+_INV0 M 0 INV[]# INV[]# TL+_INV0 u.v 0% MT00 XR LR TLR R OMP0 R.Ω % /0W MT00 LR TLR OMP[0] MI U OMP R.Ω % /0W MT00 LR OMP[] ignal Name Transmission Line Type Total Trace Length Normal Impedance Width & pacing (mils) U OMP R.Ω % /0W MT00 LR 0mils R _TT OMP[] V OMP R.Ω % /0W MT00 LR ddress#[..] trip-line 0. ~. inch +/-% & mils KΩ % /W MT00 LR(NU) TT OMP[] R _TT _PRTP0,,,,, VP RQ#[..0] trip-line 0. ~. inch +/-% & mils PU_PLP0 _PRTP0 0 Ω % /W MT00 LR TT PRTP# PLP# PU_PLP0 PWR# T#[..0] trip-line 0. ~. inch +/-% & mils PU_PWROO TL+_PWR0 R 0KΩ % /W MT00 LR,,,,, VP _L L[0] PWROO _PULP0 PU_PWROO R 0Ω % /W MT00 LR PI0 _PULP0 T L[] LP# L[] PI# PI0 0 u.v 0% MT00 XR LR(NU) 0p 0V 0% MT00 XR LR(NU) 0 0p 0V 0% MT00 XR LR(NU) R 0KΩ % /W MT00 LR Zo=ohm, 0." max for TLR, pace any other switch signals away from TLR with a minimum of mils. on't allow the TLR routing to create splits or discontinuities in the reference planes of the signals T RP 0 T RP T RP T RP KT Molex ZI MT micro-p 0- Yonah PU Pin LR Micro-P 0, PRLPVR ource ynchronous ddress ignal Routing : R _PRTP0 W 0 % /W 00 omp0, connect with Zo=.ohm, make trace Q length shorter than 0." and width is mils. TR NPN TUT0 0V 00m UMT(-0) PIN ROM LR omp, connect with Zo=ohm, make trace _PWR rise time : length shorter than 0." and width is mils Max : ns irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LMW+ < VI VN00 + VTR+ > ize ocument Number Rev Yonah Processor (/) 0. riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試

9 Place these inside socket cavity on L (North side secondary) Place these inside socket cavity on L (outh side secondary) 0,, VOR_PU U U P V[00] V[0] 0 P V[00] V[0] >00mils V[00] V[0] P V[00] V[0] V[00] V[0] 0 VP,,,,, R V[00] V[00] V[00] V[0] R V[00] V[0] V[00] V[0] R V[00] V[0] V[00] V[0] R V[00] V[0] V[00] V[0] + T V[00] V[0] V[00] V[0] T V[00] V[0] V[00] V[00] 0 T V[00] V[0] V[00] V[0] T V[00] V[0] V[0] V[0] U V[0] V[0] V[0] V[0] 0 0 U V[0] V[0] V[0] V[0] U V[0] V[00] V[0] V[0] U V[0] V[0] V[0] V[0] V V[0] V[0] V[0] V[0] V V[0] V[0] V[0] V[0] V V[0] V[0] V[0] V[0] 0 V V[0] V[0] Place these inside socket cavity on L V[0] V[00] 0 W V[0] V[0] V[00] V[0] 0 (North side secondary) W V[00] V[0] V[0] V[0] W V[0] V[0] V[0] V[0] W V[0] V[0] V[0] V[0] Y V[0] V[00] V[0] V[0] Y V[0] V[0] V[0] V[0] 0 Y V[0] V[0] V[0] V[0] Y V[0] V[0] V[0] V[0] 0 0 V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[] V[00] V[0] V[0] V[] V[0] V[0] V[0] V[] V[0] V[0] V[0] V[] 0 V[0] V[00] V[0] V[] V[0] V[0] V[] 0 V V[0] VP[0] V[0] V[] Place these inside socket cavity on L Place these inside socket cavity on L V[0] VP[0] V[0] V[] J V[0] VP[0] V[0] V[] (North side Primary) (outh side Primary) K V[0] VP[0] V[0] V[0] M V[0] VP[0] V[00] V[] J V[00] VP[0] V[0] V[] 0 K V[0] VP[0] V[0] V[] M V[0] VP[0] V[0] V[] N V[0] VP[0] V[0] V[] 0 N V[0] VP[0] V[0] V[] R V[0] VP[] V[0] V[] R V[0] VP[] T,,0,.VM V[0] V[] V[0] VP[] lose to PU V[0] V[] T V[0] VP[] V pin V[0] V[0] V[0] VP[] V[00] V[] 0 W V[00] VP[] 0mils V[0] V[] V[0] V[0] V[] V[0] V V[0] V[] 0 V[0] V[0] V[] V[0] V[0] V[] V[0] VI[0] _VI u 0V +0-0% MT00 YV LR 0u 0V +0-0% MT00 YV LR V[0] V[] V[0] VI[] _VI 0 V[0] V[] V[0] VI[] _VI 0 V[0] V[] V[0] VI[] _VI 0 V[0] V[0] 0 V[0] VI[] _VI 0 V[00] V[] V[00] VI[] _VI 0 J V[0] V[] 0 V[0] VI[] _VI 0 J V[0] V[] 0 J V[0] V[0] V[] J V[0] V[0] V[] K V[0] VN V[0] V[] K V[0] V[0] V[] K V[0] V[0] V[] K V[0] VN V[0] V[] L KT Molex ZI MT micro-p 0- Yonah PU Pin LR V[0] V[0] L Micro-P V[00] V[] L V[0] V[] L V[0] V[] M V[0] V[] M V[0] V[] VN 0 M V[0] V[] M V[0] V[] VN 0 N V[0] V[] N V[0] V[] N V[0] V[0] North side secondary outh side secondary N V[00] V[] P V[0] V[] 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0 0u.V 0% MT00 XR 0XR0J0K TK LR T0u V - to +0% mω MT X0Y PNONI LR + 0u.V 0% MT00 XR 0XR0J0K TK LR 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) T0u V - to +0% mω MT X0Y PNONI LR + 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR T0u V - to +0% mω MT X0Y PNONI LR(NU) + 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR 0u.V 0% MT00 XR 0XR0J0K TK LR 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR T0u V - to +0% mω MT X0Y PNONI LR + 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR T0u V - to +0% mω MT X0Y PNONI LR(NU) + 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) T0u V - to +0% mω MT X0Y PNONI LR + 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0 0u.V 0% MT00 XR 0XR0J0K TK LR 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR 0u.V 0% MT00 XR 0XR0J0K TK LR(NU) Route VN and VN traces at. ohms with 0mil spacing. Place PU and P within inch of PU 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR(NU) 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR(NU) 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR(NU) T00u V ± 0% R=mΩ MT 00R PNONI LR Via:. mil mil space KT Molex ZI MT micro-p 0- Yonah PU Pin LR Micro-P irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LMW+ < VI VN00 + VTR+ > ize ocument Number Rev Yonah Processor (/) 0. riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試

10 Rn =[Rparallel*(Rntc+Rserial)/(Rparallel+Rntc+Rserial) =[R*(R+R)]/(R+R+R) =.K ain factor =Rn/[R(eqv)+Rn]= Recommend R(eqv)=.K Rfb=[N*Rdroop/(R*)-]*Rin N:no. of phase R=[*.mV/(.m*0.)-]*K=.K Rdroop:Intel spec. -.m Ohms,,,,,,,0,,,,,,,,,,,,,,,,,,,,,,,,, VM IN V u V +0-0% MT00 YV 0YV0Z TK LR VOR_ IMVP IV Load line slope : -.mv/ VOR_PU or Yonah PU R R R,,,,, 0Ω % /0W MT00 LR 0Ω % /0W MT00 LR 0Ω % /0W MT00 LR IN 0.u V 0-0% MT00 YV LR 0.u 0V +0-0% MT00 YV LR R 0KΩ % /W MT00 LR 0, 00mils 0u V ± 0% MT0 XR XR0MT TK LR(NU) TR M-T-N IRR0ZPb 0V TO-(-Pak) PIN IR LR Q 0u V ± 0% MT0 XR XR0MT TK LR 0u V ± 0% MT0 XR XR0MT TK LR(NU) 0u V ± 0% MT0 XR XR0MT TK LR 0mils 0mils 0mils 0, 000mils Q R Q0 KΩ % /0W MT00 LR(NU) M-T-N IRR0ZPb 0V TO-(-PK) PIN IR LR M-T-N IRR0ZPb 0V TO-(-PK) PIN IR LR(NU) P N IO TKY M0-L 0V O-(M) PIN O LR oost Voltage.V eeper leep Voltage 0.V L 0.u± 0%.mΩ 0 MT.*0*mm PM0T-RMN YNT LR R 0Ω % /0W MT00 LR(NU) 000p 0V 0% MT00 XR LR(NU) R 0Ω % /0W MT00 LR R 0Ω % /0W MT00 LR 0.u V 0-0% MT00 YV LR P N IO ZNR RLZ.-.V m 00mW LL-(LL) ROM LR(NU) R0 VOR_PU,, mω % W MT0 LR R W 0 % /W 00 VR_POK,,,,,,,,0,,,,,,,,,,,,,,,,,, VM 0 U0 LNR-I ILRZ-T QN PIN INTRIL LR lose L V VIN V POO R0 KΩ % /W MT00 LR(NU) V UT OOT 0Ω % /0W MT00 LR R 0 0.u V 0% MT00 XR LR R W 0 % /W 00 P PI0 PI# R W 0 % /W 00 LT VOR_ON P_IN R KΩ % /0W MT00 LR P RI R W 0 % /W 00 IN PROOT# R0 VR_TT# R.0KΩ % /0W MT00 LR R TRMO-R 0KΩ % /0=00K± % /=0K MT00 NT RTJ0VJ PNONI LR 0KΩ % /0W MT00 LR NT 0.u 0V 0% MT00 XR LR 0.0u V 0% MT00 XR LR VOR_ 0.0u 0V +0-0% MT00 YV LR OT R PV V,, 0Ω % /0W MT00 LR R W 0 % /W 00 _VI0 VI0 UT R W 0 % /W 00 _VI 0Ω % /0W MT00 LR VI OOT R R W 0 % /W 00 _VI.u 0V +0-0% 00 YV LR VI R W 0 % /W 00 _VI 0 0.u V 0% MT00 XR LR VI R0 W 0 % /W 00 P _VI VI 0 R W 0 % /W 00 LT _VI VI R W 0 % /W 00 P _VI VI R W 0 % /W 00 IN, VRON_VP VR_ON R R W 0 % /W 00 0KΩ % /0W MT00 LR, PRLPVR PRLPVR 0.u 0V 0% MT00 XR LR R W 0 % /W 00 N _PRTP0 R KΩ % /W MT00 LR(NU) PRTP# 000p 0V 0% MT00 XR LR,,,,,,,0,,,,,,,,,,,,,,,,,, VM R W 0 % /W 00 LK_N LK_N# VOR_ VI R0 VI PWR 0 % /W 00 R0 R.KΩ % /0W MT00 LR R.KΩ % /0W MT00 LR.KΩ 0.% /0W MT00 LR 0p 0V 0% MT00 XR LR R KΩ % /W MT00 LR(NU) 0p 0V 0% MT00 XR LR 0 0.0u V 0% MT00 XR LR R.KΩ % /W MT00 LR p 0V % MT00 NPO LR 0 VI OMP VW RTN 0.0u 0V +0-0% MT00 YV LR VN ROOP R OT VUM VO R 0.u V ± 0% MT00 XR LR.KΩ % /0W MT00 LR R 0.0u V 0% MT00 XR LR.KΩ % /0W MT00 LR R.KΩ % /0W MT00 LR VUM KΩ % /0W MT00 LR R.KΩ % /0W MT00 LR 0.u 0V 0% MT00 XR LR lose L 0u V ± 0% MT0 XR XR0MT TK LR(NU) VUM R R 0, 00mils.KΩ % /0W MT00 LR 0KΩ % /0W MT00 LR IN,,,,, TR M-T-N IRR0ZPb 0V TO-(-Pak) PIN IR LR Q 0u V ± 0% MT0 XR XR0MT TK LR 0mils R TRMO-R 0KΩ % /0=0K± % /=00K MT00 NT RTJVR0J PNONI LR 0u V ± 0% MT0 XR XR0MT TK LR(NU) R 0u V ± 0% MT0 XR XR0MT TK LR Ω % /0W MT00 LR R KΩ % /0W MT00 LR(NU) 0mils 0mils 0, 000mils Q M-T-N IRR0ZPb 0V TO-(-PK) PIN IR LR Q P N 000p 0V 0% MT00 XR LR(NU) IO TKY M0-L 0V O-(M) PIN O LR M-T-N IRR0ZPb 0V TO-(-PK) PIN IR LR(NU) 0.u± 0%.mΩ 0 MT.*0*mm PM0T-RMN YNT LR L00 0Ω % /0W MT00 LR(NU) R 0Ω % /0W MT00 LR R R 0Ω % /0W MT00 LR 0 0.u 0V 0% MT00 XR LR VOR_,, VOR_PU 0.0u 0V +0-0% MT00 YV LR 0p 0V % MT00 NPO LR 0.0u 0V +0-0% MT00 YV LR VUM R R.KΩ % /0W MT00 LR 0KΩ % /0W MT00 LR R 00Ω % /W MT00 VOR_ LR VOR_ R Ω % /0W MT00 LR R 0Ω % /0W MT00 LR R 0Ω % /0W MT00 LR VN VOR_PU,, VN R0 mil mil space 0.0u V 0% MT00 XR LR(NU) R 00Ω % /W MT00 LR 0Ω % /0W MT00 LR R lose Output ap 0Ω % /0W MT00 LR alculation formula IO*Rdroop=Roc*0u If OP= R0=Roc=.Kohm ssume R=Rin=K Ohm R=Rfb=[N*Rdroop/(R*)-]*Rin=.K ~.K Rdroop:Intel spec. -.m Ohms L/R=[Rn//R(eqv)]*n +=n=l/r/[rn//r(eqv)]=0.u irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LMW+ < VI VN00 + VTR+ > ize ocument Number Rev ustompu ore Power 0. riday, pril, 00 ate: heet of 0 P 檔案以 "P 製作工廠 " 試

11 TRML NOR 0,,,,,,,0,,,,,,,,,,,,,,,,,, VM R KΩ % /0W MT00 LR N_ON V VM from OVP & ON_OTOWN,0,0 MLK_PMU MT_PMU 0,,,,,,,,,, OT_OWN0 0mil R W 0 % /W 00 R W 0 % /W 00 V R KΩ % /W MT00 LR R 0KΩ % /W MT00 LR(NU) R 0KΩ % /W MT00 LR(NU) R0 0KΩ % /W MT00 LR(NU) VM 0mil ULK L 0.u V 0-0% MT00 YV LR 0mil UTT_0,,,,,,,, 0Ω ±% 00Mz MT00 ML-00-00P-N M.LYR LR 0 U LNR-I U OP PIN MT LR Test V TRM# L LRT# LK N V TRM_T XP XP R XP R 0KΩ % /W MT00 LR TR 0MIL 0KΩ % /W MT00 LR V TRM Trace=0mil and together TRM L PWR 0 % /W 00 L PWR 0 % /W p 0V 0% MT00 XR LR u V +0-0% MT00 YV 0YV0Z TK LR IO TKY PT 0V 0. OT- PIN NMKO LR PP R 00Ω % /0W MT00 LR 0.u V 0-0% MT00 YV L R 00p 0V 0% MT00 XR LR P N N ON NTRY MT PIN P= ar away the RT,clock generator,memory bus,pi bus..s close PU as possible. 0 mil 0 mil ULK_ U R Ω % /W MT00 LR n ULK Place this TR closed to V hip. L-I NZPX -0 PIN IRIL LR RT ischarge ircuit RT_V,,,,,0, PMUV IO TKY PT 0V 0.0 OT- PIN NMKO LR 0mil 0mil 0mil 0mil 0u 0V +0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR, lose to VT R,,,0,,, V V,,,,,,,,,,,,, VM VM,,,,,0,,,,,,0,, V V TTRY V R RT NN N + - R 00Ω % /W MT00 LR V0. irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <Thermal / RT> 0. riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試

12 OT lock LK lock LK lock PI lock LK lock lock Latout uideline LOK PU_LK[..0] M_LK[..0] ITP_LK[..0] LK_I LK_M LK_P LK_IPI LK_IOPI LK_WPI LK_MINIPI LK_PI LK_PMU0PI LK_PI LK_IO LK_I LK_TV LK_I LK_M LNT " ~ "." ~.0 " MX :."." ~.0 "."~.0".0"~.0"." ~." TR / P / 0 mils ( mil space between & 0) / 0 mils / 0 mils / 0 mils / 0 mils / 0 mils,,0,,,,, NOT.VM. ifferentials pairs with the same length (within 0 mil).pu & N trace mismatch within 0 mil Length mismatch within 00 mils Length same as LK lock Length mismatch within 00mils.Making PI length with minimum various. Length Require LK-.". Length mismatch +/-.0". Length mismatch +/- 00 mils,,, I_MT,,, I_MLK 0,,,,,,,0,,,,,,,,,,,,,,,,,, VM 00Ω ±% 00Mz 000m MT00 ML P-N M.LYR LR L 0.u V 0-0% MT00 YV LR VM 0 R L LK_N >0mil lock Package Length anais Processor Package Length mils Montara-M M Package Length mils PU ocket quivalent Length mils VM_LK 00Ω ±% 00Mz 000m MT00 ML P-N M.LYR LR 0 0u 0V +0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR /0 MI add 0 VM_LK R00.KΩ % /W MT00 LR R0 I LOK I0L-T OP PIN I Lead-ree.Mz M- PIN 0p ± 0ppm X0K-O.L LR Y 0p 0V ± 0.p MT00 NPO LR 0 0.0u 0V +0-0% MT00 YV LR Q TRN M-T-N N00_NL 0V m OT- PIN IRIL LR u V +0-0% MT00 YV 0YV0Z TK LR 0 0.KΩ % /W MT00 LR 0 Ω % /0W MT00 LR L_M N_U_ LK_MO lock Layout :. lose to lock generator. Trace as short as possible and use mil. Place crystal within 00 mils of LK enerator 0p 0V ± 0.p MT00 NPO LR 0 PU P PI R M.M.M.M M.M.M.M M.M.M.M M.M.M.M M.M.M.M U VPI VPI V V VV VPU VR V. T LK RTT VTT_PWR/P IR Mhz_0 Mhz_ X X R0/ R/0 MZ/ _MZ/L_ V_0 V_ V_ PI_0/ PI_/ PI_ MO/PILK0 PILK PILK PILK PILK PILK PILK PULKT0 PULK0 PULKT PULK PULKT_ITP/PI_TOP PULK_ITP/PU_TOP 0 0 PITP0 PUTP0 / MI change R Ω % /0W MT00 LR R0 Ω % /0W MT00 LR R0 Ω % /0W MT00 LR R Ω % /0W MT00 LR R0 Ω % /0W MT00 LR R Ω % /0W MT00 LR R Ω % /0W MT00 LR R Ω % /0W MT00 LR R Ω % /0W MT00 LR R Ω % /0W MT00 LR R Ω % /0W MT00 LR R Ω % /0W MT00 LR R Ω % /0W MT00 LR R Ω % /0W MT00 LR R Ω % /0W MT00 LR R Ω % /0W MT00 LR R Ω % /0W MT00 LR R Ω % /0W MT00 LR R Ω % /0W MT00 LR Under 00mil PITP0 PUTP0 Under 00mil L_M Under 00mil Under 00mil R R R R R 0KΩ % /W MT00 LR(NU).Ω % /0W MT00 LR.Ω % /0W MT00 LR.Ω % /0W MT00 LR.Ω % /0W MT00 LR LKM_P LKM_IO PU_LK PU_LK0 LKN LKN0 hielding LK+ LK- hielding 0 mil space mil space 0 mil space mil space mil space mil space mil space ( mil width for differential signals and shiekding) LKM_ LKM_UI LKM_ LKM_ LKM_P LKM_N LKM_ LKM_IO LKM_ LKM_ LKM_PI LKM_ LKM_UI LKM_ LKM_ LKM_N LKM_ LKM_ LKM_ LKM_PI LKM_K LKM_W LKM_ LKM_MINI 0 0 p 0V ± 0.p - TO + MT00 NPO LR p 0V ± 0.p - TO + MT00 NPO LR p 0V ± 0.p - TO + MT00 NPO LR p 0V ± 0.p - TO + MT00 NPO LR p 0V ± 0.p - TO + MT00 NPO LR p 0V ± 0.p - TO + MT00 NPO LR p 0V ± 0.p - TO + MT00 NPO LR p 0V ± 0.p - TO + MT00 NPO LR p 0V ± 0.p - TO + MT00 NPO LR p 0V ± 0.p - TO + MT00 NPO LR p 0V ± 0.p - TO + MT00 NPO LR LKM_K p 0V ± 0.p - TO + MT00 NPO LR LKM_W p 0V ± 0.p - TO + MT00 NPO LR LKM_ p 0V ± 0.p - TO + MT00 NPO LR hielding IPLKI, IPLKO hielding 0 mil space 0 mil space mil space mil space mil space VM_LK LKM_MINI PU_LK PU_LK0 LKN p 0V ± 0.p - TO + MT00 NPO LR p 0V ± 0.p - TO + MT00 NPO LR p 0V ± 0.p - TO + MT00 NPO LR p 0V ± 0.p - TO + MT00 NPO LR LKN0 0 p 0V ± 0.p - TO + MT00 NPO LR IPLKO 0,,,,,,,0,,,,,,,,,,,,,,,,,, R R.KΩ % /W MT00 LR 0KΩ % /W MT00 LR / MI change U LKIN MR ON# V V R0 R ModOUT VM L 00Ω ±% 00Mz 000m MT00 ML P-N M.LYR LR 0mil 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR MI requst / / add _L LK_MO R0 0KΩ % /W MT00 LR(NU) R R 0KΩ % /0W MT00 LR.KΩ % /W MT00 LR R 0KΩ % /0W MT00 LR R0.KΩ % /W MT00 LR 0 R 0KΩ % /0W MT00 LR(NU) RP R 0KΩ % MT00 /W PR LR VM 0KΩ % /0W MT00 LR LNR-I P00-0R OI PIN L LR 0.u V 0-0% MT00 YV LR R Ω % /W MT00 LR IPLKI IPLKI IPLKO 0 p 0V ± 0.p - TO + MT00 NPO LR(NU) p 0V ± 0.p - TO + MT00 NPO LR(NU) 0,,,,,,,0,,,,,,,,,,,,,,,,,, VM VM irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <lock-en> 0. riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試

13 0 INPUT _OUT _IN RLK0 歐姆 0 歐姆 L: " WLKOU L:." 歐姆 0P L:L+L-L+." 0P L=LM+LM L: " VI VN00 IMM IMM,,0,,,,,.VM.VM_LK R LOK UR RLK0# RLK U RLK# RLK RLK# _open 0 V./. V./. V./. V V RT0 R0 RT R RT R RT0 R0 RT R RT R RP0 RP RP 0Ω % MT00 /W PR LR 0Ω % MT00 /W PR LR 0Ω % MT00 /W PR LR M_LK_R0 M_LK_R00 M_LK_R M_LK_R0 M_LK_R M_LK_R0 0 歐姆 RLK RLK# RLK RLK# RLK RLK# _open R lock uffer L: ",,, I_MT,,, I_MLK LKO+ LKO- RT R T RT R LK RT R U_INT U_IN OUT_T OUT_ I LOK-UR IPL-T OP PIN I LR RT RP 0Ω % MT00 /W PR LR R 0 /0 modify T request R0 Ω % /W MT00 LR 00 0p 0V ± 0.p MT00 NPO LR LKI 0p 0V ± 0.p MT00 NPO LR 0p 0V ± 0.p MT00 NPO LR 0p 0V ± 0.p MT00 NPO LR 0p 0V ± 0.p MT00 NPO LR 0 0p 0V ± 0.p MT00 NPO LR 0 0p 0V ± 0.p MT00 NPO LR 0 0p 0V ± 0.p MT00 NPO LR 0p 0V ± 0.p MT00 NPO LR M_LK_R M_LK_R0 / MI add.vm / R R R R change 0 Ohm, 0 0 change p, change 0p.VM_LK L 0 00Ω ±% 00Mz 000m MT00 ML P- N M.LYR LR >0 mil 0.u V 0-0% MT00 YV LR 0 0u 0V +0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <clock buffer> 0. 0 riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試

14 0,,,,, VP TL+_0[.. ] TL+_RQ0[..0] TL+_0[..0] L L L L L M N P R T U TL+_0 Y TL+_0 V TL+_0 TL+_0 Y TL+_0 Y TL+_0 TL+_0 TL+_00 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 T TL+_0 R TL+_0 N TL+_00 N TL+_0 P TL+_0 P TL+_0 R TL+_0 N TL+_0 T TL+_0 P TL+_0 R TL+_0 N TL+_0 N TL+_00 R TL+_0 T VN00_NU U VN00_NT T TL+_T00 W T W TL+_T0 R T0 N TL+_0 M TL+_NR0 M TL+_PRI0 T TL+_R00 K TL+_Y0 M TL+_R0 U TL+_RY0 M TL+_IT0 L TL+_ITM0 U TL+_LOK0 L TL+_TRY0 M TL+_RQ00 TL+_RQ0[..0] W TL+_RQ0 V TL+_RQ0 V TL+_RQ0 W TL+_RQ0 V TL+_R00 TL+_R0[..0] L TL+_R0 M TL+_R0 K T0P T0N & P T P0 NR PRI RQ0 Y R RY IT ITM LOK TRY RQ0 RQ RQ RQ RQ R0 R R VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT OT PU INTR K K J K J J J J TL+_00 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_00 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_00 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_00 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_00 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_00 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_00 TL+_0 TL+_0 TL+_0,,,,, 0/ ost down 0/ ost down VP 0 Place these parts near N. as close as possible. 0u 0V +0-0% MT00 YV LR 0u 0V +0-0% MT00 YV LR(NU) 0u 0V +0-0% MT00 YV LR 0u 0V +0-0% MT00 YV LR 0u 0V +0-0% MT00 YV LR 0u 0V +0-0% MT00 YV LR 0u 0V +0-0% MT00 YV LR(NU) u V +0-0% MT00 YV 0YV0Z TK LR 0.0u 0V +0-0% MT00 YV LR 0.0u 0V +0-0% MT00 YV LR 0.0u 0V +0-0% MT00 YV LR 0.0u 0V +0-0% MT00 YV LR 0.0u 0V +0-0% MT00 YV LR 0.0u 0V +0-0% MT00 YV LR 0.0u 0V +0-0% MT00 YV LR TL+_INV00 TL+_INV0 TL+_INV0 TL+_INV0 I0 I I I TP0 TN0 TP TN TL+_TP00 TL+_TN00 TL+_TP0 TL+_TN0 TL+_PURT0 PURT LKN LKN0 Y W LK+ LK- TP TN TL+_TP0 TL+_TN0 TLVR_N TLVR_N R V VR0 VR VR0 VR VR VR TP TN TL+_TP0 TL+_TN0 make sure?? L TLVR R.Ω % /0W MT00 LR ROMP OMPVR 0MPVR VK K PWR K TL+_PWR0,,,,, VP,,,,, VP U I N VN00 PIN VI TLVR_N R R.Ω % /0W MT00 LR TLVR_N 00Ω % /0W MT00 LR 0.0u 0V +0-0% MT00 YV LR R R0.Ω % /0W MT00 LR 00Ω % /0W MT00 LR 0.0u 0V +0-0% MT00 YV LR V V_LK V_LK > 0 mil V L VM 0,,,,,,,0,,,,,,,,,,,,,,,,,, 0Ω ±% 00Mz MT00 ML P-N M.LYR LR u V +0-0% MT00 YV 0YV0Z TK LR V_LK L0 0Ω % /0W MT00 LR,,,,, VP OMPVR R0 R0 Place these parts near N. 00Ω % /0W MT00 LR as close as possible. nd.ω % /0W MT00 LR place each capacitor per 0.0u 0V +0-0% MT00 YV LR pin. / MI change irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <VN00 host> 0. 0 riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試

15 0,,,,.V_IMM V V W W W W W W W W W, M_[..0] M_K0_R0 M_K_R0 M_K_R0 M_K_R0 M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ J J J J J J J J0 0 J J J0 J J 0 J J J J J J J M00 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M M M M M M M M M M0 M M M M M M M M M M0 M M M M M M M M M M0 M M M M M M M M M M0 M M M M M M M M M M0 M M M K0 K K K V/MM V/MM V/MM V/MM V/MM V/MM V/MM V/MM V/MM V/MM V/MM R RM INTR M00 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M M M 0 R W 0 Q0 Q Q Q Q Q Q Q QM0 QM QM QM QM QM QM QM MOMP MMT J J J J 0 J 0 J J J J M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_0 M_ M_R M_ M_W M_Q_P0 M_Q_P M_Q_P M_Q_P M_Q_P M_Q_P M_Q_P M_Q_P M_QM0 M_QM M_QM M_QM M_QM M_QM M_QM M_QM MOMP MMT M_[..0], M_[..0], M_R, M_, M_W, R W 0 % /W 00 These packs and resistor,please close to IMM M_0_R0 MMT MOMP,,,, >0MIL.V_IMM R W 0 % /W u V 0% MT00 XR LR(N U) M R0 R W 0 % /W 00 R W 0 % /W 00 M_Q_P[..0], M_QM[..0], M R0 M R0,,,, R_.V,,,, R R0 0Ω % /0W MT00 LR R.V_IMM 0KΩ % /W MT00 LR 0KΩ % /W MT00 LR(NU) MMT 0 =>R =>R 0.0u 0V +0-0% MT00 YV LR 0.0u V 0% MT00 XR LR(N U) 0 u 0V 0-0% MT0 YV YVZ TK LR(NU).u 0V +0-0% 00 YV LR.u 0V +0-0% 00 YV LR 0.0u 0V +0-0% MT00 YV LR 0 0.0u V 0% MT00 XR LR(N U) 0.0u 0V +0-0% MT00 YV LR 0 0.0u V 0% MT00 XR LR(N U) 0.0u 0V +0-0% MT00 YV LR 0.0u 0V +0-0% MT00 YV LR 0.0u V 0% MT00 XR LR(N U) 0.0u 0V +0-0% MT00 YV LR 0.0u 0V +0-0% MT00 YV LR 0.0u V 0% MT00 XR LR(N U) 0.0u 0V +0-0% MT00 YV LR 0.0u 0V +0-0% MT00 YV LR 0.0u 0V +0-0% MT00 YV LR MVR_N MMVR MMVR MMVR MMVR OT0 OT OT OT 0 M_OT0 M_OT M_OT M_OT VMK MK MLKI MLKO+ MLKO- R R U I N VN00 PIN VI Ω % /0W MT00 LR Ω % /0W MT00 LR LKI LKO+ LKO- LKI = L_R + ". LKO as short as possible.,,,,.v_imm 0Ω % /0W MT00 LR R R 0Ω % /0W MT00 LR 0/ NU 0 0u 0V ± 0% MT00 XR T=.mm 0XR0KT TK LR(NU) > 0 mil u V +0-0% MT00 YV 0YV0Z TK LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 000p 0V 0% MT00 XR LR 000p 0V 0% MT00 XR LR MVR_N V_LK V V_LK p 0V ± 0.p - TO + MT00 NPO LR(NU) p 0V ± 0.p - TO + MT00 NPO LR(NU) > 0 mil V V_LK 0.u V 0-0% MT00 YV L R 000p 0V 0% MT00 XR LR L VM 0,,,,,,,0,,,,,,,,,,,,,,,,,, 0Ω ±% 00Mz MT00 ML P-N M.LYR LR u V +0-0% MT00 YV 0YV0Z TK LR LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <VN00 R> 0. irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試

16 0 P_L0 P_L P_L P_L P_L P_L P_L P_L Ω % MT00 /W PR LR RP N_LP0 N_LP N_LP N_LP Ω % MT00 /W PR LR RP N_LP N_LP N_LP N_LP 0 P_L[..0].VM VVL.VM R0 VM_X 00Ω ±% 00Mz 000m MT00 ML P- N M.LYR LR 0.u V 0-0% MT00 YV L R VU VM.V,,0, V-LINK Vref= 0..VM VM_X 0.u 0V +0-0% 00 YV LR 0.0u 0V +0-0% MT00 YV LR 0.0u 0V +0-0% MT00 YV LR 0.0u 0V +0-0% MT00 YV LR Ω % MT00 /W PR LR RP P_L0 N_LP0 P_L N_LP P_L N_LP P_L0 N_LP0 Ω % MT00 /W PR LR N_LP0 P RP N_LP P P_L N_LP VN00_NR R P_L N_LP N_LP R P_L N_LP N_LP R P_L N_LP N_LP N N_LP P N_LP R Ω % MT00 /W PR LR M RP M P_L N_LP N_LP N P_L N_LP N_LP L P_L N_LP N_LP0 L P_L N_LP N_LP N N_LP K N_LP0 R N_LP J Ω % /W MT00 LR n N_LP N_LP R0 0 P_ K N_LP R Ω % /0W MT00 LR 0 P_LK_P Ω % MT00 /W PR LR N_LP K RP N_LP P_L N_LP VN00_NJ J P_L N_LP VN00_NK K P_L N_LP VN00_NJ J P_L N_LP VN00_N VN00_NJ J VN00_N VN00_N VN00_N N_LP M VN00_NK K N_LP J VN00_NL L /TV /TV0 /TV0 /TV0 /TV0 /TV0 /TV0 /TV 0/TV0 /TVLK /TV0 /TV0 /VP_ /VP_0 /VP_ /VP_ /VP_ 0/VP_ /VP_T 0 /TV0 /VP_ M N P R T VP VP VP VP VP VVL U0 U VVL VVL V0 L L L VX VX VX V-LINK INTR VU VU V00 V0 V0 V0 V0 V0 V0 V0 V UPT+ UPT- NT+ NT- UPM NM VLOMPP VLVR UT TTIN RT PWROK "XIN V U Y Y T T U W W V V W T V R VL_0 VL_ VL_ VL_ VL_ VL_ VL_ VL_ VLR_N VL_0 VL_UPT VL_UPT0 VL_NT VL_NT0 VL_UPM VL_NM VL_[..0] Ω % /0W MT00 LR R0,,,, UT0_N.KΩ % /W MT00 LR PIRT0_N, PWROK_N.V_IMM.KΩ % /0W MT00 LR R R KΩ % /0W MT00 LR VLR_N > 0 mil LKM_UI.VM 0 0.u V 0-0% MT00 YV LR 0 0.u V 0-0% MT00 YV LR 0Ω ±% 00Mz MT00 ML P-N M.LYR LR > 0 mil V_ L VM V_ 0 0 u V +0-0% MT00 YV 0YV0Z TK LR.u 0V +0-0% 00 YV LR 0.0u 0V +0-0% MT00 YV LR 0.0u 0V +0-0% MT00 YV LR 0.0u 0V +0-0% MT00 YV LR L PWR 0 % /W 00 R0 Ω % /W MT00 LR n 0 P_ L VN00_NM M VN00_NK K R0 Ω % /W MT00 LR n 0 P_V J VN00_NM M VN00_NP P VN00_N R Ω % /0W MT00 LR 0 P_LK_N VN00_N p 0V % MT00 NPO L R VN00_N VN00_NM M VN00_N,,0,.VM R.KΩ % /W MT00 LR VN00_N R 0Ω % /W MT00 LR(NU) PX_T0 RM/TV IRY/PLLK TRY VL/TVV TOP PR R W/TVLK# RQ/LK NT/T RR I/PIP IL PXT RT "INT "R " " "VYN "YN "RT "PT OR RT (.V I/O) "PLK "IPLKO ITIN R W 0 % /W 00 R IPLKO_N R LU RN VYN YN 0.Ω % /0W MT00 LR R PI_INT0, VT VLK IPLKO 0 0p 0V ± 0.p MT00 NPO LR(NU) 0 mil 0Ω ±% 00Mz MT00 ML P-N M.LYR LR > 0 mil V_ L VM u V +0-0% MT00 YV 0YV0Z TK LR V_ NV NV NKL VN00_N VN00_N N_LP N_LP N_LP VN00_N VN00_N VN00_N VN00_N VN00_N VN00_N VN00_N VN00_N VN00_N N N T0/NV T/NV T/NLT T/VP_ T/VP_ T0 T0 T/TV0 T/TVLKIN 0/VP_V /VP_ /VP_0 /VP_ /VP_ /VP_ /VP_LK /VP_LK# VP0 "IPLKI "TV00/VP000 "TV0/VP00 "TV0/VP00 "TV0/VP00 "TV0/VP00 "TV0/VP00 "TV0/VP00 "TV0/VP00 "TV0/VP00 "TV0/VP00 "TV0/VP00 "TV/VP0 "TV/VP0 "TV/VP0 "TVLK/VP0LK "TVLKR "VP0T "TVV/VP0V TV0 TV TV TV TV TV TV TV TV TV TV0 TV VN00_N0 VN00_N0 VN00_N VN00_N0 VN00_N VN00_N0 Ω % /W MT00 LR n IPLKI IPLKO 00 IPLKI p 0V ± 0.p - TO + MT00 NPO LR(NU) p 0V ± 0.p - TO + MT00 NPO LR(NU) u V +0-0% MT00 YV 0YV0Z TK LR VM 0Ω ±% 00Mz MT00 ML P-N M.LYR LR > 0 mil V_PLL L VM V_PLL L PWR 0 % /W 00 0Ω ±% 00Mz MT00 ML P-N M.LYR LR > 0 mil V_PLL L VM.VM P_VR LKM_N R 0.Ω % /0W MT00 L R R 0.Ω % /0W MT00 L R N R PVR PVR LK POMPN POMPP (.V I/O) "PT "PLK raphics controll PLL "V "V 0 L_PT L_PLK V_ V_ L_PT 0, L_PLK 0, TV0 TV TV TV RP 0KΩ % MT00 /W PR LR u V +0-0% MT00 YV 0YV0Z TK LR V_PLL P_UY0 T PUY POUT PO0 "PLL "VPLL "PLL "VPLL " " V_ V_,,0,.VM.VM VI / recommend P.0 Vref=0..VM VN00_N VN00_N V_PLL V_PLL V_PLL V_PLL U TV TV TV TV RP RP 0KΩ % MT00 /W PR LR 0KΩ % MT00 /W PR LR,,,0,,,,,.VM.VM 0,,,,,,,0,,,,,,,,,,,,,,,,,, VM P_VR R R.KΩ % /W MT00 LR.KΩ % /W MT00 LR I N VN00 PIN VI RP TV TV TV0 TV.KΩ % MT00 /W PR LR irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- VM u V +0-0% MT00 YV 0YV0Z TK LR LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <VN00 vedio> 0. 0 riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試

17 0,,0,.VM,,0,.VM 0 / + T00u V ± 0% R=mΩ MT 00R PNONI LR K0 K K K K K K K0 L0 M0 N0 P0 R0 T0 V0 W0 Y0 Y Y Y Y Y0 V V V V V V V V V V V V V V V V V V V V V V L L L L M M M M M M M N N N N N N N P P P P P P P P P P P R R R R R R R T T T 0 u 0V 0-0% MT0 YV YVZ TK LR(NU).u 0V +0-0% 00 YV LR u V +0-0% MT00 YV 0YV0Z TK LR u V +0-0% MT00 YV 0YV0Z TK LR 0.u V 0-0% MT00 YV L R 0 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV L R 0.0u V 0% MT00 XR LR(N U) 0.0u V 0% MT00 XR LR(N U) 0.0u V 0% MT00 XR LR(N U) 0.0u V 0% MT00 XR LR(N U) 0.0u V 0% MT00 XR LR(N U) 0.0u V 0% MT00 XR LR(N U) 0.0u V 0% MT00 XR LR(N U) 000p 0V 0% MT00 XR LR (NU) 000p 0V 0% MT00 XR LR (NU) 000p 0V 0% MT00 XR LR (NU) 000p 0V 0% MT00 XR LR (NU) T T T T U U U U U U U U U U U V V V V V V V Y Y Y 0 U I N VN00 PIN VI irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <VN00 power> 0. 0 riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試

18 0 N, M_[..0], M_[..0] M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_, M_[..0] M_ M_0 M R0 M R0 M_LK_R M_LK_R0 M_LK_R M_LK_R0 M_K_R0 M_K_R0,,,0,,,,,,,,,,,,,,,,,, VM, M_, M_R, M_W R 0KΩ % /W MT00 LR,,, I_MLK,,, I_MT M_OT M_OT, M_QM[..0] M_QM0 M_QM M_QM M_QM M_QM M_QM M_QM M_QM, M_Q_P[..0] M_Q_P0 M_Q_P 0Ω % MT00 /W PR 0.mm LR M_Q_P M_Q_P RP M_Q_P M_Q_N0 M_Q_P M_Q_N M_Q_P M_Q_N M_Q_P M_Q_N[..0] M_Q_N M_Q_N0 M_Q_N M_Q_N RP M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N 0Ω % MT00 /W PR 0.mm LR,,,, R_.V 0/ NU 0,,,,,,,0,,,,,,,,,,,,,,,,,, VM 0, R_VR 0.u V 0-0% MT00 YV LR O IMM.u V 0-0% MT00 YV 0YVZ TK LR 0.u V 0-0% MT00 YV LR.u 0V ± 0% MT00 XR 0XRKT TK LR(NU) 0 M_0 0 Q0 0 M_ Q 00 M_ Q M_ Q M_ Q M_ Q M_ Q M_ Q M_ Q M_ Q 0 M_0 0/P Q0 0 M_ Q 0 M_ Q M_ Q M_ Q M_ Q M Q M_ Q 0 M_ Q 0 M_ 0 Q 0 M_0 0# Q0 M_ # Q 0 M_ K0 Q M_ K0# Q M_ K Q M_ K# Q M_ K0 Q 0 M_ K Q M_ # Q 0 M_ R# Q 0 M_0 W# Q0 M_ 0 Q 00 M_ Q M_ L Q M_ Q M_ Q M_ OT0 Q M_ OT Q M_ Q 0 M_ M0 Q M_0 M Q0 M_ M Q M_ M Q 0 M_ M Q 0 M_ M Q 0 M_ M Q M_ M Q M_ Q0 Q M_ Q Q M_ Q Q 0 M_0 Q Q0 M_ Q Q M_ Q Q 0 M_ Q Q M_ Q Q M_ Q0# Q M_ Q# Q M_ Q# Q M_ Q# Q M_ Q# Q 0 M_0 Q# Q0 M_ Q# Q M_ Q# Q M_ Q V V V V V V V V V V V V V V V V 0 V0 V V V 0 V V0 V VP V V N V 0 N V 0 N V N V NTT V V VR V0 V 0 0 V 0 V 0 V V V V V V V V V V V V0 V V V V V V V0 V V V 0 V V V V 0 V V V V 0 V V0 RV TYP V V KT OXONN MT R O-IMM =. T 0-MN- Lead-free & Ro, M_[..0],, M_0 M_, M_K_R0 M_K_R0 M_[..0],, M R0 M R0,,,, M_W M_R M_ M_OT M_OT R_.V.u 0V ± 0% MT00 XR 0XRKT TK LR(NU) 0mil.u 0V ± 0% MT00 XR 0XRKT TK LR(NU) 0.u 0V ± 0% MT00 XR 0XRKT TK LR(NU) Place these.u caps near o-imm Place one cap close to every pullup resistors terminated to 0.vddm M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ RP M_0 M_0 RP RP NOT: RP 00 mils LL terminal close IMM.u 0V ± 0% MT00 XR 0XRKT TK LR(NU) RP0 RP RP.u 0V ± 0% MT00 XR 0XRKT TK LR(NU) RP / MI Place these 0.u caps near o-imm R_0.VM, Ω % MT00 /W PR RN-R0-JN YNT LR 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR 0.mm L R 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR 0.mm L R 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV LR(NU) Ω % MT00 /W PR RN-R0-JN YNT LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR 0.mm L R 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR 0.mm L R 0.u V 0-0% MT00 YV L R 0 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR Ω % MT00 /W PR RN-R0-JN YNT LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR 0.mm L R 0 0.u V 0-0% MT00 YV LR(NU) 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV LR(NU) 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0 0.u V 0-0% MT00 YV LR 0 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR Place these i-req decoupling caps near M irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <R-dimm-> 0. riday, pril, 00 ate: heet of 0 P 檔案以 "P 製作工廠 " 試

19 0 N, M_[..0], M_[..0] M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_, M_[..0] M_ M_0 M_0_R0 M R0 M_LK_R0 M_LK_R00 M_LK_R M_LK_R0 M_K0_R0 M_K_R0, M_, M_R, M_W,,, I_MLK,,, I_MT M_OT0 M_OT, M_QM[..0] M_QM0 M_QM M_QM M_QM M_QM M_QM M_QM M_QM, M_Q_P[..0] M_Q_P0 M_Q_P M_Q_P M_Q_P M_Q_P M_Q_P M_Q_P M_Q_P M_Q_N[..0] M_Q_N0 M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N,,,, R_.V 0/ NU 0,,,,,,,0,,,,,,,,,,,,,,,,,, VM, R_VR 0 0.u V 0-0% MT00 YV LR O IMM 0.u V 0-0% MT00 YV 0YVZ TK LR 0.u V 0-0% MT00 YV LR.u 0V ± 0% MT00 XR 0XRKT TK LR(NU) 0 M_0 0 Q0 0 M_ Q 00 M_ Q M_ Q M_ Q M_ Q M_ Q M_ Q M_ Q M_ Q 0 M_0 0/P Q0 0 M_ Q 0 M_ Q M_ Q M_ Q M_ Q M Q M_ Q 0 M_ Q 0 M_ 0 Q 0 M_0 0# Q0 M_ # Q 0 M_ K0 Q M_ K0# Q M_ K Q M_ K# Q M_ K0 Q 0 M_ K Q M_ # Q 0 M_ R# Q 0 M_0 W# Q0 M_ 0 Q 00 M_ Q M_ L Q M_ Q M_ Q M_ OT0 Q M_ OT Q M_ Q 0 M_ M0 Q M_0 M Q0 M_ M Q M_ M Q 0 M_ M Q 0 M_ M Q 0 M_ M Q M_ M Q M_ Q0 Q M_ Q Q M_ Q Q 0 M_0 Q Q0 M_ Q Q M_ Q Q 0 M_ Q Q M_ Q Q M_ Q0# Q M_ Q# Q M_ Q# Q M_ Q# Q M_ Q# Q 0 M_0 Q# Q0 M_ Q# Q M_ Q# Q M_ Q V V V V V V V V V V V V V V V V 0 V0 V V V 0 V V0 V VP V V N V 0 N V 0 N V N V NTT V V VR V0 V 0 0 V 0 V 0 V V V V V V V V V V V V0 V V V V V V V0 V V V 0 V V V V 0 V V V V 0 V V0 RV TYP V V KT OXONN MT R O-IMM =. T 0-NN- Lead-free & Ro M_0_R0,,,, M_K0_R0 M_K_R0 M R0 M_OT0 M_OT NOT: 0mil Place these.u caps near o-imm Place one cap close to every pullup resistors terminated to 0.vddm LL terminal close IMM R_.V.u 0V ± 0% MT00 XR 0XRKT TK LR(NU).u 0V ± 0% MT00 XR 0XRKT TK LR(NU).u 0V ± 0% MT00 XR 0XRKT TK LR(NU).u 0V ± 0% MT00 XR 0XRKT TK LR(NU) RP 0.u V 0-0% MT00 YV LR 00 mils Ω % MT00 /W PR RN-R0-JN YNT LR.u 0V ± 0% MT00 XR 0XRKT TK LR(NU) RP / MI 0.u V 0-0% MT00 YV LR Place these 0.u caps near o-imm R_0.VM, 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR RN-R0-JN YNT LR RP 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR RN-R0-JN YNT LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0 0.u V 0-0% MT00 YV LR(NU) 0.u V 0-0% MT00 YV LR(NU) Place these i-req decoupling caps near M irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <R-dimm-> 0. riday, pril, 00 ate: heet of 0 P 檔案以 "P 製作工廠 " 試

20 0 P_L[..0] P_LK_P,,, P_LK_N RP VR near to VR chip 0KΩ % MT00 /W PR LR LVV 0.u V 0-0% MT00 YV LR 0 0.u V 0-0% MT00 YV LR 0p 0V ± 0.p MT00 NPO LR(NU).VM 0 u V +0-0% MT00 YV 0YV0Z TK LR 0p 0V ± 0.p MT00 NPO LR(NU) 0 LV R,,, V P_L0 P_L P_L P_L P_L P_L P_L P_L P_L P_L P_L0 P_L P_L P_L P_L P_L P_L P_L P_L P_L P_L0 P_L P_L P_L >0MIL PWR 0 % /W 00 0,,,,,,,,,,,,,,,,,,,,,,,,, 0.u V 0-0% MT00 YV LR.VM P_ P_LK_P P_LK_N P_ P_V 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR u V +0-0% MT00 YV 0YV0Z TK LR PLL LV V LVV VI / recommend VM R LKINP LKINM YN VYN VR PLL PLL PLL U LV LV LV LV V V V LVV LVV LVV I VT LV TQP 00PIN VI LR PWR 0 % /W 00 PR RV RV N N N PIO- PIO- PIO- PIO- RV 0 RV IL ILK L/IT TT TT R_ P UL MN LKP LKM LKP LKM P M P M P M P M P M P M P M 0P 0M IV PLLV PLLV V MOL P_PR RV RV R R R0 R R P_L TT LV_TXLK_UP LV_TXLK_UN P M P M P_R_ P_P P_UL P_MN LV_TXOUT_UP LV_TXOUT_UN LV_TXOUT_UP LV_TXOUT_UN LV_TXOUT_U0P LV_TXOUT_U0N V PLLV V P_MOL 0Ω % /W MT00 LR(NU) 0Ω % /W MT00 LR(NU) 0Ω % /W MT00 LR(NU) 0Ω % /W MT00 LR(NU) 0Ω % /W MT00 LR T T T T LV_TXOUT_LP LV_TXOUT_LN LV_TXOUT_LP LV_TXOUT_LN LV_TXOUT_L0P LV_TXOUT_L0N T T P_IL INVN LV_TXLK_LP LV_TXLK_LN LV_TXLK_LP LV_TXLK_LN LV_TXOUT_LP LV_TXOUT_LN LV_TXOUT_LP LV_TXOUT_LN LV_TXOUT_LP LV_TXOUT_LN P_NPV 0.u V 0-0% MT00 YV L R.VM_LV L L L L PLL RP0 VM.VM_LV UPPORT "I" L_PLK, L_PT, RV RV 00Ω ±% 00Mz 000m MT00 ML P- N M.LYR LR 00Ω ±% 00Mz 000m MT00 ML P- N M.LYR LR L PWR 0 % /W 00 L PWR 0 % /W 00.KΩ % 00 /W PR LR 00Ω ±% 00Mz 000m MT00 ML P- N M.LYR LR 00Ω ±% 00Mz 000m MT00 ML P- N M.LYR LR L PWR 0 % /W 00 VI / recommend mount.vm V LVV PLLV PLL R0 R LV IL(pin) etting 0Ω % /W MT00 LR(NU) 0Ω % /W MT00 LR(NU) R W 0 % /W 00 R W 0 % /W 00 Pull down(r:remove;r:mount) is ardware ontrolled LV Tx Note: If using.w. control,please do some reworkings. ===>Tx ide: R:Remove;R:Mount;R:Remove L(pin0) setting Pull down Pull igh.v(r) (pin) setting Pull down(r0) Pull igh.v *UL(pin) setting Pull down(r) Pull igh.v(r) VM *VTL:ree choice VT:Please tie to down ifferential LK in ingle-ended LK in Rising edge alling edge ignal hannel UL hannel Pull igh.v(r:mount;r:remove) is oftware ontrolled LV Tx Note: If using.w. control,please do some reworkings. ===>Tx ide: R:Mount;R:Remove;R:Mount The signals of L,UL and are ontrolled by I. NV P_NPV Q M-T-N NN_NL 0V. OT- IRIL LR R W 0 % /W 00 R0.KΩ % /0W MT00 LR NV.KΩ % MT00 /W PR LR RP P_P P_MN P_R_ P_PR P_MOL P_L P_UL P_IL.VM_LV 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR Place close to VT Powerown ontrol KT VI / recommend R.KΩ % /W MT00 LR.VM Q P_P TRN M-T-N N00_NL 0V m OT- PIN IRIL LR R.KΩ % /W MT00 LR,,,.VM RP.KΩ % MT00 /W PR LR TR NPN MMT_NL 0V OT- PIN IRIL LR R NV KΩ % /W MT00 LR Q 0,,,,,,,,,,,,,,,,,,,,,,,,, VM,,,.VM.KΩ % /W MT00 LR TRPPIN PULL-UP PULL-OWN, LI0 NKL NV R IO TKY UPT 0V 0.0 OT- PIN NMKO LR R.KΩ % /0W MT00 LR Q M-T-N NN_NL 0V. OT- IRIL LR INVN P_PR P_UL P_IL P_MN P_P P_L Pull high (efault) Two hannel I active (efault) Interrupt active (efault) Normal Mode (efault) ingle-nd LK (efault) Reserve ingle hannel (efault) I Inactive Interrupt Inactive Power own Mode ifferential-nd LK,,,,,,,.VM.VM irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- P_R_ P_MOL ailling dge bit Mode (efault) Rising dge (efault) bit Mode 0,,,,,,,,,,,,,,,,,,,,,,,,, VM VM LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <LV > 0. 0 riday, pril, 00 ate: heet of 0 P 檔案以 "P 製作工廠 " 試

21 0,,,,,,,,, V Min : 0 MIL or Power Plane Min : 0 MIL or Power Plane I_MX= PTTRN WIT=MIN. MM(0MIL) 0.u 0V +0-0% MT00 YV L R 0 NV mil R KΩ % /0W MT00 LR mil Q M-T-P O0-0V - TOP PIN O LR L 0Ω ±% 00Mz MT00 ML-00-00P-N M.LYR LR R.KΩ % /0W MT00 LR Q NPN PTU OT- PILIP LR L_V / MI VM 00Ω ±% 00Mz 000m MT00 ML P- N M.LYR LR L 0p 0V ± 0.p MT00 NPO LR Min : 0 MIL or Power Plane 0p 0V ± 0.p MT00 NPO LR 0u 0V ± 0% MT00 XR VXTVXR0K0T VX LR(NU) u V +0-0% MT00 YV 0YV0Z TK LR 0.u V 0-0% MT00 YV LR(NU) N 0 LV_TXLK_LN 0 LV_TXLK_LP 0 LV_TXOUT_LN 0 LV_TXOUT_LP 0 LV_TXOUT_LN 0 LV_TXOUT_LP 0 LV_TXOUT_L0N 0 LV_TXOUT_L0P L L0 L L OK 0Ω 00Mz.Ω 00m TM0-00-P-T T K LR OK 0Ω 00Mz.Ω 00m TM0-00-P-T T K LR OK 0Ω 00Mz.Ω 00m TM0-00-P-T T K LR OK 0Ω 00Mz.Ω 00m TM0-00-P-T T K LR L L L L L_PT,0 L_PLK,0 LV_TXLK_LN 0 OK 0Ω 00Mz.Ω 00m TM0-00-P-T TK LR(NU) LV_TXLK_LP 0 LV_TXOUT_LN 0 OK 0Ω 00Mz.Ω 00m TM0-00-P-T TK LR(NU) LV_TXOUT_LP 0 LV_TXOUT_LN 0 OK 0Ω 00Mz.Ω 00m TM0-00-P-T TK LR(NU) LV_TXOUT_LP 0 LV_TXOUT_LN 0 OK 0Ω 00Mz.Ω 00m TM0-00-P-T TK LR(NU) LV_TXOUT_LP ON MT WIR.0P 0PIN R/ 0-000L Lead-free & Ro 0.u V 0-0% MT00 YV L R / MI LV Interface ignal LV LNT 0" able MX " TR mils (stripline) mils (microstrip) P TR MUTIN 0 mils +/-0 mils mils (edge (data to to edge) +/-0 clock) mils (with a 0 mils (pair clock pair) to pair) X +/-0 mils 0 mils (to non (clock to LV signal) clock) Impedance 00 ohms +/-% Note reakout region from N should be less than 00 mils irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu 0,,,,,,,,0,,,,,,,,,,,,,,,,, VM TIPI, TIWN,RO (-)- VM LMW+ < VI VN00 + VTR+ > ize ocument Number Rev <L connecter> 0. 0 riday, pril, 00 ate: heet of P 檔案以 "P 製作工廠 " 試