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1 AUO 台达 MSDI HTR-DE 原理图及接线图 R.K R 00K R.K R.K Q 0 Q AO0A C uf /0.uF Q 0 R0 00K C 0.uF V panel POWER C 0.uF C0.nF R 00K C0 0nF R.K EN FB OUT BST SS COMP U MP C 0nF R.K/% R.K R K R0 K/% V C 0uF C 0.uF C 0.uF L uh CA 00uF/V L FB/A VIN VOUT U AMS-.V R R.K C 0.uF R 0 R /0/% R0 /0 R.K R /00/% L /FB/A C.uF Q 0 C.uF/ C 0.uF H0 Q 0 H Q 0 C 0uF C 0.uF C.uF VIN VOUT U AMS-.V R 00 Q 0 VSENSE R /0 SOT C 0.uF R.K R K C 0uF R K R /0 C 0.uF.V_DDR=.*(R/R) V_Normal=.*(R/R) CA 00uF/V R.K R K R.K 更改 V 上电时间, 要求大于 ms V V Vstb V.Vstb Vstb.V_Normal V BRT_CNTL_IN BRT_CNTL_OUT BRI_ADJ-PWM ON_PBACK PWR-ON/OFF PANEL_ON/OFF PWR-ON/OFF MAX 0MA R C 0uF 0 0 CN Power_Main R 00 V V PB-ADJUST PW-ON/OFF-INV PB-ON/OFF Standby:L Normal: H Vstb CN FB H H H H H H H H HOLE H H CA 00uF/V CA 00uF/V BRT_CNTL_IN PB-ADJUST PB-ON/OFF ADJ-PWM H R0.K H ON_PBACK PW-ON/OFF-INV C 0.uF I 00MA C.nF D /N R 00K R 0 C0 0.uF C0 0.uF EN FB OUT BST SS COMP U MP TO R R VIN VOUT U AP0-ADJ R.K CA 0uF/V C 0nF R K/% R.K/% V.V_DDR C.uF CA 0uF/V C0 0.uF I=00mA Max C 0.uF TO V R /% R /% VIN VOUT U AP0-ADJ V CA 00uF/V V_Normal FB C0.uF L uh I=00mA Max C0 0.uF C 0.uF V H R /.ohm D N00 D0 N00 L uh.0v_ H POWER INPUT H H C 0nF C0 /0.uF C 0.uF R K/% C 0.uF EN FB OUT BST SS COMP shield U MP R 00K R.K/% R.K C.nF C 0.uF V V_USB PANEL_ON V R /0 USB0_PWR_CTRL USB0_PWR_CTRL USB POWER SOT

2 .V_Standby V_Normal R 0K DSMB_STAS DSMB_STAS R 0K DSMB-D-LINE-ON CVBSO_OUT DSMB-D-LINE-ON HDMI-ARC HDMI-CLKP.V_Standby HDMI-CLKN HDMI-RX0P HDMI-RXN HDMI-RX0N HDMI- HDMI-RXP HDMI-RXP HDMI-RXN HDMI-SDA HDMI-RXN HDMI-RXN HDMI-CLKP HDMI- HDMI-RX0P HDMI-SDA HDMI-RX0N HDMI-RXP HDMI-CLKN HDMI-RXP HDMI-RXN HDMI_HP HDMI_HP HDMI-RXN HDMI-CLKP HDMI- HDMI-CLKN HDMI-RX0P HDMI-SDA HDMI_HP HDMI-RX0N HDMI-RXP VGA_HS HDMI-CEC HDMI-RXP YPbPr_SOY YPbPr_PR- YPbPr_PR VGA_VS R0 YPbPr_PB- YPbPr_PB VGA-B YPbPr_Y- VGA-G- YPbPr_Y XTALO VGA-R- VGA-R VGA-G AV-CVBSP AV-CVBS0P VGA-B- VGA/YUV-RIN-IC AV-CVBSP VCOM0 AV-LIN-IC AV-RIN-IC VGA/YUV-LIN-IC AV_AUOUTR AV_AUOUTL VIFM 0 VIFP 0 SPDIF_OUT, USB0_PWR_CTRL CVBSO_OUT BRI_ADJ-PWM PWR-ON/OFF BODY Y PbPr_PR PANEL_ON/OFF RSTN_LAN-PHY ON_PBACK Y PbPr_PB YPbPr_PR- YPbPr_Y - YPbPr_Y YPbPr_PB- HD_RIN-IC R HD_LIN-IC HDMI-RXP HDMI-RXN HDMI-SDA HDMI-RXN HDMI-CLKP HDMI- HDMI-RX0P HDMI-RX0N HDMI-RXP HDMI-CLKN R.K HDMI_HP R Demod_RST IS-OUT_BCK, R IS-OUT_SD,.V_Standby R.K IS-OUT_MCK, IS-OUT_WS, UART_TX UART_RX R 0K R 0K LED_R DSMB_VS DSMB_HS AMP-MUTE KEY-in KEY0-in C 0.uF KEY0-in KEY-in VIF R K R 0K LED-B Q0 0 HDMI-ARC R 0K Q 0 VGA-G VGA-B VGA-R- VGA_VS VGA_HS VGA-R R R D N PCM_D PWR-ON/OFF R YPbPr_PR- YPbPr_PB- YPbPr_Y- D0 VGA-G- YPbPr_Y YPbPr_SOY YPbPr_PR YPbPr_PB DSMB-D-LINE-ON GPIO_IR C0 0.uF BODY VGA-B-.V_Standby DSMB_STAS DSMB_GPO VIDEO-TYPE V Vstb.V_Standby Vstb FOR DSMB CN IR_LED VIDEO-TYPE VIDEO-TY PE VIDEO-TY PE VIDEO-TYPE R R 0K TP R 0K Close to MSTAR IC with width trace PM-RX HD_RIN-IC HD_LIN-IC B-TMDMU AV-LIN-IC AV-RIN-IC VGA/YUV-LIN-IC VGA/YUV-RIN-IC PM-TX B-TMBA B-TMB B-TMCASB B-TMODT AUDIO INPUT B-TMDML B-TMWEB B-TMDQSLB B-TMCKB B-TMDQSUB B-TMBA B-TMDQSL B-TMDQSU B-TMCK B-TMCKE R R B-TMRESETB B-TMRASB B-TMDQL[0:] V_IF NAND_CLE B-TMA[0:] B-TMBA B-TMDQU[0:] B-TMDQU0 B-TMCKB B-TMCK TP B-TMDQL B-TMDQL0 B-TMDQL B-TMDQU B-TMDQU B-TMDQU B-TMDQU B-TMDQU B-TMDQSU B-TMDQSUB B-TMDQL B-TMDQL B-TMDQU B-TMDQU B-TMDQL B-TMDQL B-TMA B-TMA B-TMA B-TMA B-TMA B-TMDQL VIF INPUT B-TMA B-TMWEB B-TMA B-TMCKE B-TMA B-TMA B-TMCASB B-TMODT B-TMA B-TMDQSLB B-TM B-TMA B-TMB B-TMRASB B-TM B-TMA B-TMDMU B-TMDML B-TMBA B-TMDQSL B-TMA B-TMRESETB B-TMA A_DDR_/DDR_A D A_DDR_A/DDR_A B A_DDR_A/DDR_A D A_DDR_A/DDR_A E A_DDR_A/DDR_ E A_DDR_A/DDR_A D A_DDR_A/DDR_A D A_DDR_A/DDR_A E A_DDR_A/DDR_A E A_DDR_A/DDR_A E A_DDR_/DDR_ODT D A_DDR_A/DDR_A D A_DDR_A/DDR_CASZ C A_DDR_A/DDR_A D0 A_DDR_DQL0/DDR_DQL B A_DDR_DQL/DDR_DQL B A_DDR_DQL/DDR_DQL C A_DDR_DQL/DDR_DQU C A_DDR_DQL/DDR_CKE B A_DDR_DQL/DDR_DQL0 B A_DDR_DQL/DDR_DQL C A_DDR_DQL/DDR_DQL C A_DDR_DQU0/DDR_DQSUB C A_DDR_DQU/DDR_DQU B A_DDR_DQU/DDR_DQU0 B A_DDR_DQU/DDR_DQU C A_DDR_DQU/DDR_DQSU C A_DDR_DQU/DDR_DQU C A_DDR_DQU/DDR_DQU B A_DDR_DQU/DDR_DQU B A_DDR_CASZ/DDR_B D A_DDR_RASZ/DDR_WEZ D A_DDR_WEZ/DDR_BA E A_DDR_DML//DDR_DQU C A_DDR_DMU/DDR_DQL B A_DDR_ODT/DDR_BA E A_DDR_B/DDR_ D A_DDR_BA/DDR_RASZ C A_DDR_BA/DDR_A D A_DDR_RESETB D A_DDR_CKE/DDR_DQL C A_DDR_MCLK/DDR_MCLK B A_DDR_MCLKZ/DDR_MCLKZ B A_DDR_DQSU/DDR_DQSL B0 A_DDR_DQSL/DDR_DMU C A_DDR_DQSUB/DDR_DQSLB B A_DDR_DQSLB/DDR_DML C0 B_DDR_/DDR_A T B_DDR_A/DDR_A G B_DDR_A/DDR_A R B_DDR_A/DDR_A M B_DDR_A/DDR_ J B_DDR_A/DDR_A N B_DDR_A/DDR_A J B_DDR_A/DDR_A N B_DDR_A/DDR_A H B_DDR_A/DDR_A P B_DDR_/DDR_ODT L B_DDR_A/DDR_A H B_DDR_A/DDR_CASZ K B_DDR_A/DDR_A R B_DDR_CASZ/DDR_B T B_DDR_RASZ/DDR_WEZ R B_DDR_WEZ/DDR_BA T B_DDR_DML/DDR_DQU F B_DDR_DMU/DDR_DQL M B_DDR_ODT/DDR_BA R B_DDR_B/DDR_ M B_DDR_BA/DDR_RASZ K B_DDR_BA/DDR_A T B_DDR_RESETB P B_DDR_CKE/DDR_DQL E B_DDR_MCLKZ/DDR_MCLKZ B B_DDR_MCLK/DDR_MCLK C B_DDR_DQSL/DDR_DMU K B_DDR_DQSU/DDR_DQSL J B_DDR_DQSLB/DDR_DML J B_DDR_DQSUB/DDR_DQSLB H B_DDR_DQL0/DDR_DQL N B_DDR_DQL/DDR_DQL E B_DDR_DQL/DDR_DQL N B_DDR_DQL/DDR_DQU E B_DDR_DQL/DDR_CKE P B_DDR_DQL/DDR_DQL0 D B_DDR_DQL/DDR_DQL P B_DDR_DQL/DDR_DQL D B_DDR_DQU0/DDR_DQSUB G B_DDR_DQU/DDR_DQU K B_DDR_DQU/DDR_DQU0 F B_DDR_DQU/DDR_DQU L B_DDR_DQU/DDR_DQSU H B_DDR_DQU/DDR_DQU M B_DDR_DQU/DDR_DQU G B_DDR_DQU/DDR_DQU L B_DDR_A/DDR_A G A_DDR_A/DDR_A B MIU0 MIU UA MSDISV A-TMBA A-TMB A-TMDMU A-TMRESETB A-TMODT A-TMCKB A-TMDQU A-TMBA R0 0K R 0K A-TMCASB A-TMDQU0 A-TMDQSUB A-TMDQSU A-TMCK A-TMDQU A-TMDQU A-TMDQU A-TMDQL A-TMDQL A-TMDQU A-TMDQL0 A-TMDQL A-TMDQL A-TMDQL V_NER A-TMDQU A-TMDMU A-TMDQSLB A-TMDQSL A-TMDML A-TMCKE A-TMWEB A-TMA A-TMDQU A-TMDQL A-TMDQL R PCM_DR A-TMA A-TM A-TMA A-TMA A-TMA A-TMODT A-TMA A-TMA A-TMBA A-TMB A-TMCASB A-TMA A-TMA A-TMA A-TM A-TMA A-TMA A-TMA A-TMRASB SPI_SCK SPI_SDI A-TMWEB A-TMDQSUB A-TMDML EEPROM-WP A-TMDQSU A-TMDQSLB A-TMCKB A-TMBA A-TMDQSL A-TMCKE A-TMCK A-TMRESETB A-TMDQL[0:] A-TMRASB A-TMA A-TMA[0:] A-TMDQU[0:] FLASH_WP Demod_RST SPDIF_OUT USB0_PWR_CTRL VIFP VIFM VIDEO-TYPE C.u close to nand flash u SPI_CSN C pf C pf C0 0.u R PCM_DR SPI_SDO R R PCM_D0 R R V_Normal IC- IC-SDA CNE PH-A R R DSMB_WAKEUP DSMB_WAKEUP RSTN_LAN-PHY C 0.u NAND_WEZ NAND_CEZ C pf R0 PCM_DR R R NAND_WPZ #F_WP EEPROM-WP ON_PBACK BRI_ADJ-PWM EEPROM HDMI-CLKP HDMI-RXP UART_TX HDMI-RXP HDMI-CLKN HDMI-RX0P HDMI-RXN HDMI_HP HDMI-SDA HDMI-RXN HDMI-RX0N HDMI- IS-OUT_WS HDMI-CEC EEPROM-WP IC-SDA IC- IS-OUT_BCK IS-OUT_SD IS-OUT_MCK LAN-PHY _MDC AV-RIN-IC AV-LIN-IC VGA/YUV-RIN-IC VGA/YUV-LIN-IC R AV-AUOUTL YPbPr_PR YPbPr_PB YPbPr_PB- YPbPr_Y- HDMI-ARC AV-AUOUTR USB_D USB_D- YPbPr_Y YPbPr_SOY YPbPr_PR- USB_D- HDMI- HDMI-RXP HDMI-RXN System-RST USB_D HDMI-SDA HDMI-RXN HDMI-CLKP CVBSO_OUT HDMI-RX0N HDMI-RXP HDMI-CLKN HDMI-RX0P AV-CVBS0P VCOM0 DSMB_VS RSTN_LAN-PHY V_Normal VGA_VS VGA_HS VGA-R VGA-G VGA-B HDMI-CLKP HDMI-RXP VGA-R- HDMI-HP AV-CVBSP CVBSO_OUT HDMI- HDMI-RXP HDMI-CLKN HDMI-RX0P HDMI-RXN LAN-PHY_TXEN HDMI-SDA HDMI-RXN HDMI_HP HDMI-RX0N R 0K IR_SW J_MDC Q 0 SYS_CLK MIC_IN R 0K Q 0 R0 V_Normal V BIN0M H GIN0P H GIN0M J SOGIN0 H RIN0M J HSY0 N VSY0 N BINM K GINP L SOGIN K RINM M HSY R VSY P BINM M GINM N RINM P SOGIN N CVBS0P T CVBSP T CVBSP R CVBSP R CVBSP R VCOM T CVBS_OUT U CVBS_OUT U MPIF_BUSY_ERR/ ET_COL J MPIF_D/ ET_TXD0 H MPIF_D0/ ET_TXD J MPIF_CSN/ ET_TX_EN H MPIF_CLK/ ET_TX_CLK H MPIF_D/ ET_RXD0 K MPIF_D/ ET_RXD L ET_MDC/SPDIF_OUT G ET_MDIO/SPDIF_IN G RESET E XTALIN AC XTALOU T AC IRIN M DM_P0 B DP_P0 C /DM_P C /DP_P D RIN0P J BIN0P G RINP L GINM L RINP P GINP N BINP M BINP K RTC_XIN D RTC_XOUT D DM_P AC DP_P AB TESTPIN J CVBSP P DM_P AC DP_P AC EFUSE K AVLINK M /TP AE /TN AF /RP AE /RN AF /A_TX W /A_RX AD ET_MDIO J ET_MDC K RGB CVBS RMII MPIF USB UE MSDISV MICIN C.u C.u HDMI_HP LINE_OUT_0L AB LINE_OUT_ AB LINE_OUT_L AA LINE_OUT_R AA HP_OUT_L AB HP_OUT_R AC LINE_IN_0L T LINE_IN_ T LINE_IN_L Y LINE_IN_R AA LINE_IN_L V LINE_IN_R W LINE_IN_L W LINE_IN_R W LINE_IN_L Y LINE_IN_R Y VRP U VAG V VRM V /SPDIF_OUT/LED U IS_OUT_BCK V IS_OUT_MCK V IS_OUT_WS V IS_OUT_SD U A_RX0N AE A_RX0P AD A_RXN AF A_RXP AE A_RXN AD A_RXP AF A_RXCN AD A_RXCP AF DDCDA_CK AB DDCDA_DA Y HOTPLUGA AE B_RX0N AD B_RX0P AF B_RXN AE B_RXP AD B_RXN AF B_RXP AE B_RXCN AF B_RXCP AE DDCDB_CK AA DDCDB_DA AB HOTPLUGB Y C_RX0N AE C_RX0P AD C_RXN AF C_RXP AE C_RXN AD C_RXP AF0 C_RXCN AD C_RXCP AF DDCDC_CK Y DDCDC_DA Y HOTPLUGC AA D_RX0N AF D_RX0P AE D_RXN AD D_RXP AF D_RXN AE D_RXP AD D_RXCN AE0 D_RXCP AD0 DDCDD_CK AB DDCDD_DA AC HOTPLUGD AD CEC AF IS_IN_SD W IS_IN_WS Y IS_IN_BCK W /SPDIF_IN/LED0 U /MICINL R /MICINR R ARC AC IS_OUT_SD/MUTE W HDMI Analog Audio IS SPDIF UC MSDISV AUVRM AUVAG AUVRP Close to MST IC DSMB_HS LAN-PHY_TXD C p YPbPr_PB- YPbPr_Y YPbPr_Y- Close to MST IC YPbPr_PB C0 p LAN-PHY_TXD0 YPbPr_PR YPbPr_PR- LAN-PHY_TXD0 LAN-PHY_TXEN LAN-PHY_TXD VGA-G- LAN-PHY_MDIO TP XTALI XTALO R / RP RN TN R / J_MDIO TN HDMI-RXP HDMI-CLKP HDMI-RXN HDMI-RXP HDMI-CEC HDMI-RX0P HDMI-CLKP HDMI-RXN HDMI- RP RN TP HDMI- HDMI-RX0P HDMI-RXP HDMI-SDA HDMI-RXN HDMI-CLKN R0 PCM_DR HDMI-RXN HDMI-RXP HDMI_HP HDMI-RX0N HDMI-CLKN LAN-PHY_MDIO HDMI-RX0N HDMI-SDA LAN-PHY_MDC IC-,, IC-SDA,,.V_Standby C 0.u.Vstb IRIN.V_Standby C 0.u IS-OUT_BCK IS-OUT_SD IS-OUT_MCK IS-OUT_WS.VNORMAL C0 0.u.VNormal R R R0 R R R L FB0/00mA C 0.u SPDIF_OUT close MSTAR IC R R close LDO VGA-B- C 0.u IR&KEYB close LDO C 0.u.V_Normal SPDIF_OUT close MSTAR IC.VNormal R R R /.0V_ USB_D close MSTAR IC MIUP_DDR USB_D-.V_DDR C 0.u USB_D- USB_D- USB_D L FB0/00mA USB_D USB_D- USB_D C 0.u C 0.u.V_Standby C0 0.u.V Normal.0V_.V Standby.0V_ PANEL_ON/OFF C 0.u.V_Normal close MSTAR IC.0V_ C 0.u.V_Normal C 0.u V_Normal.0Vcore AVDD_PGA L C 0.u C 0.u.VNormal A_PGA.V_Normal C 0.u close MSTAR IC close MSTAR W UART-TX UART-RX UART-TX UART-RX VIF VIF nd UART LED_B Vstb R K IR CON /CON-.0 D_FLAG 0 UART_RX FLASH D_FLAG 0 D_FLAG TP V_Normal HD_LIN-IC HD_RIN-IC IC- PANEL_S UART-RX PANEL_S PANEL_S PANEL_S PANEL_S PANEL_S R.K CN Key Audio Line Out R R YPbPr_PB YPbPr_PR- YPbPr_PB- YPbPr_Y- NAND_RBZ UART-TX YPbPr_Y YPbPr_PR AMP-MUTE UART-RX RGB/YPBPR Interface IS-OUT AV-CVBSP AUVRP AUVRM HDMI-RXN HDMI-CLKP HDMI- HDMI-RXP HDMI-RXN HDMI-RX0N HDMI-RXP HDMI-CLKN HDMI-RX0P HDMI-SDA HDMI-RXN HDMI-RXP HDMI_HP HDMI-HP HDMI-CLKP HDMI-RXN HDMI- HDMI-RXP HDMI-CLKP HDMI-RXP HDMI-SDA HDMI-RXN HDMI-CLKN HDMI-RX0P HDMI- HDMI-RX0P HDMI-RXN HDMI-RXP HDMI_HP HDMI-RX0N HDMI-CLKN AV-CVBSP AV-CVBS0P VCOM0 HDMI-SDA HDMI-RX0N R0.K IC-SDA R0 0K IF-AGC-SEL IF-AGC-SEL G0_RXE PCM_A PCM_A G_RXE- G_RXE0 G_RXE0- NAND_WEZ IP IM NAND_RBZ NAND_ALE NAND_WPZ DSMB_HS DSMB_VS NAND_CLE NAND_REZ NAND_CEZ PCM_A R0 0K IR-in VIF PCM_A PCM_A QH_IF_OUT- VIFM RF_AGC_T UART-TX UART-RX C00 0.u IP USB0_PWR_CTRL C0 0.u R 00 D_SY _OUT KEY-in IM R k PCM_A Demod_RST RST_AMP QH_IF_OUT T_SDA PCM_A PCM_A LED-R BRI_ADJ-PWM VIFP PCM_ C0 p IRIN C /n PCM_A UART-TX IR R_RXOC- R_RXO0 R_RXO0- R_RXO LED-B R_RXO R_RXO- VIF R_RXO- R 0K CN IR_LED R /0K C nf C pf R 0K PCM_A[:0] PCM_D[:0] CN IR_LED TS_MDO[:0] TS_MOCLK TS_MOCLK TS_MDO C0 n C nf R K TS_MOVAL TS_MDO[:0] TS_MDO0 TS_MDO TS_MDO Vstb TS_MDO TS_MDO TS_MDO TS_MDO V_IF TS_MOVAL B_RXE B_RXE- B0_RXE B_RXE- B_RXEC B_RXEC- B_RXE AV_AUOUTL C /n AV_AUOUTR B_RXE- AV-AUOUTR AV-AUOUTL R0 K R0 C0 /n CVBS Interface TAGC PCM_A SPI_SCK PCM_A PCM_A DTV-IF_AGC DSMB_GPO SPI_SDI SPI_SDO R 0K DSMB_GPO AMP-MUTE R 00 VSY B HSY A LDE C LCK B SAR0 P SAR P SAR N SAR P PWM0 AB PWM AA PWM AA PWM AB PWM AA PM_SPI_CK G PM_SPI_CZ F PM_SPI_DI G PM_SPI_DO F DDCA_CK/UART0_RX N DDCA_DA/UART0_TX M DDCR_CK Y DDCR_DA Y UART_TX AC UART_RX AC PM_UART_TX/PM L PM_UART_RX/PM E GPIO_PM0/SPI_CS H GPIO_PM L LVB0N/ RLVN/ RED[] A LVB0P/ RLVP/ RED[] C LVBN/ RLVN/ RED[] B LVBP/ RLVP/ RED[] A LVBCLKN/ RLVN/ RED[0] A LVBCLKP/ RLVP/ RED[] C LVBN/ RLVN/ RED[] C LVBP/ RLVP/ RED[] B LVBN/ RLVN/ GREEN[] B LVBP/ RLVP/ GREEN[] A LVBN/ LLV0N/ GREEN[] C LVBP/ LLV0P/ GREEN[] B LVN/ LLVN/ GREEN[] A LVP/ LLVP/ GREEN[] C LVAN/ LLVN/ GREEN[0] B LVAP/ LLVP/ GREEN[] A LVAN/ LLVN/ BLUE[] C LVAP/ LLVP/ BLUE[] B LVACLKN/ LLVN/ BLUE[] A LVACLKP/ LLVP/ BLUE[] C0 LVAN/ LLVN/ BLUE[] B0 LVAP/ LLVP/ BLUE[] LVAN/ LLVN/ BLUE[0] D LVAP/ LLVP/ BLUE[] C TCON D TCON0 E TCON D TCON F0 TCON F TCON E TCON G TCON D TCON F TCON G0 TCON D TCON0 G TCON F TCON F TCON D TCON E TCON E TCON D0 GPIO_PM/SPI_CS F GPIO_PM/PM_PWM J GPIO_PM0 K RTS0 AB0 CTS0 AC GPIO_PM L GPIO_PM M GPIO_PM K GPIO_PM E TCON E0 TCON E TCON F TCON0 G PWM SAR SPI UART IC GPIO LVDS UD MSDISV PF_D[0]/ NAND_AD[0]/PCM_D[0] Y PF_D[]/ NAND_AD[]/ PCM_D[] Y PF_D[]/ NAND_AD[]/ PCM_D[] AA PF_D[]/ NAND_AD[]/ PCM_D[] AA PF_D[]/ NAND_AD[]/ PCM_D[] AA PF_D[]/ NAND_AD[]/ PCM_D[] AC PF_D[]/ NAND_AD[]/ PCM_D[] AB PF_D[]/ NAND_AD[]/ PCM_D[] AB PF_A[0]/ PCM_A[0] AE PF_A[]/ PCM_A[] AF PF_A[]/ PCM_A[] AD PF_A[]/ PCM_A[] AD PF_A[]/ PCM_A[] AE PF_A[]/ PCM_A[] AD PF_A[]/ PCM_A[] AE PF_A[]/ PCM_A[] AE PF_A[]/ PCM_A[] AD PF_A[]/ PCM_A[] AE PF_A[0]/ PCM_A[0] AD PF_A[]/ PCM_A[] AC PF_A[]/ PCM_A[] Y PF_A[]/ PCM_A[] AC PF_A[]/ PCM_A[] Y PF_A[]/ AC PF_D[]/ AE0 PF_A[]/ AE PF_A[0]/ AF PF_D[0]/ AD PF_D[]/ AE PF_D[]/ AD PF_D[]/ AF0 PF_D[]/ AE PF_D[]/ AF NAND_ALE AB NAND_CLE AC NAND_REZ AA NAND_WEZ AC0 PF_A[]/ NAND_WPZ AB PF_A[]/ NAND_RBZ AB NAND_CE0Z Y TS_CLK Y TS_SY AB TS_VLD Y0 TS_D0 AA TS_D Y TS_D AB0 TS_D A TS_D AC0 TS_D AA TS_D AC TS_D AC TS0_CLK AB TS0_SY AC TS0_VLD AB TS0_D0 AB TS0_D AA TS0_D AA TS0_D AC TS0_D AA TS0_D AC TS0_D Y TS0_D AC IP AE IM AF TGPIO0 AE TGPIO AD TGPIO/NER_IC_CLK AD TGPIO/NER_IC_SDA AD IFAGC AC VIFP AF VIFM AE RF_TAGC AD SSIF/SIFM AE SSIF/SIFP AF NAND_CEZ Y TS_CLK AB TS_SY AB TS_VALID AA TS_D0 AA PF_D[] AC PF_A[] AB PF_A[] AA PF_A[] Y PF_A[] AF PF_WEZ AF PF_OEZ AD0 PF_CE0Z AF PF_CEZ AD NOR NAND CI TS (In/Out) (In) TS0 Front End UB MSDISV R k KEY0-in AV-CVBSP PCM_ UART-TX UART-RX RF_AGC_T TS_MOSTART DSMB_WAKEUP TS_MOSTART PCM_A R 0K TS_VLD, Closed to MSTIC IS-OUT_MCK TS_SY, TS_D[0:], TS_VLD TS_SY TS_D TS_D IS-OUT_SD TS_D0 TS_D TS_CLK, TS_D TS_CLK TS_D TS_D TS_D IR_SW IS-OUT_BCK G_RXO R0_RXOC G_RXO- GPIO_IR GPIO_IR CFG-PWM PM-TX G_RXO- V_IF R 0 Mode Selection R 0K CFG-PWM0 CFG-PWM IC-SDA IC- SPI_CSN LED_R C0 p R / T_ C C pf R0.K C C 0.uF C L0 EEPROM-WP R R C0 0.u R PCM_D R.K R 0K R0 0K C 0.u NAND_REZ R 0 R 0 R /.K R R R.K R PM-RX R 0 A A SDA WP U /ATC0 L 0uH PWR-ON/OFF FLASH_WP R Closed to MSTIC V_IF R 00K R / RF_AGC_SEL IF-AGC-SEL ON_PBACK PCM_PWR_CTL VIFP PANEL_ON/OFF UART_TX UART_RX VIFM R0 R R0 00K R M Sy stem-rst C 0uF R.K C 0uF R C 0.uF CE# SO WP# SI SCK HOLD# VDD U MXL0D B_RXE MIUP_DDR RXE B0_RXE R0_RXOC B_RXE- R_RXOC- R_RXO0 G_RXE0-.0V_ R_RXO0- B_RXEC G_RXE0 B_RXEC- G_RXO R_RXO R_RXO- G0_RXE G_RXE- G_RXO- R_RXO B_RXE B_RXE- G_RXO- G_RXO R_RXO- B_RXE- RXE- RXE RXE- RXEC R R C nf PCM_D C 0.uF RXO RXO- RXO0 RXO0- C 0pF RXOC- RXO RXO- RXO- RXO RXO- RXOC R0 00K RXE- RXE0 RXE0- RXO RXE C pf RXEC- RXE RXE- Q0 MMBT0 C 0.uF R0 R 0K LED_B EMAC-RXDV EMAC-TXCLK EMAC-RXD EMAC-RXD0 EMAC-RXD0 EMAC-RXD EMAC-TXCLK EMAC-RXDV H H G H H H T0 V T W Y0 A AA AVDD_REF U AVDD_PGA T 0_C K _D L AVDD_MOD T 0_D K _D M 0_D K _D M AVDDP0/ W0 DVDD_DDR U J J J J J J J K0 K K K K K G G L L L L L L L0 M M0 M M M M M H H M M0 N N N N N N N N J N P P R AVDDP_ADC U P P P R R R DVDD_NODIE R H V J 0_D L J V0 W R P L0 M A_PGA R R W G G H H J0 G H0 L M N0 P N0 N P0 P P P P R0 R P0 AVDDP_ADC U G W W0 G H0 H K V R R W 0_D K _D N DVDD_DDR0 V L V U U U U U U T R T T T T U0 T T G0 W W W W K0 D Y E J0 A E F A G F G A A A A A A A A A D A A E A A N R M P K F T L H J G F G H J K L M N P T F F F F F F F F F0 _VSENSE R R0 /AVDD_LAN T /AVDD_AU U AVDD_NODIE U AVDD_DVI V AVDD_DVI V AVDD_DVI V AVDDP_MPLL V AVDD_DMPLL V AVDD_AU T AVDD_EAR U /AVDD_LAN Y VDDP Y VDDP Y W AA AA /AVDD_LAN AB AB AB T0 U0 U U V0 V V V W W U AA T U _C L UF MSDISV R.K R.K R R C 0uF R.K R.K C.uF R 0K R 0K C pf R 0K R0 0K R 0K R.K BODY RESET CIRCUIT R 0K C pf C 0.uF DEBUG L FB0/00mA VIF R 0 R.K RST_AMP CFG-PWM0 A_PGA.VNormal LED-R.V_Normal R R AVDD_PGA.V_Normal NAND_ALE.uC.VNormal.V_Standby.V_Standby R VSENSE R 00K R.K R 0K Close to MST IC R 0 C n R.K R C.uF.V_Normal G_RXO C 0.uF R 0K Y XTAL-MH z R 0K D BAV C 0pF R0 0 HDMI Interface R.K Audio AUVAG CON CON-.0 A A SDA WP U ATC UART-RX IC-SDA IC- UART-TX V_Normal Vstb V_Normal XTALI A-MRASB A-MODT A-MCASB B-MB B-MWEB B-MBA B-MBA B-M B-MA B-MA B-MA B-MVREFCA B-M B-MA B-MA B-MA B-MA B-MA B-MA B-MA B-MA R R B-MA R R B-MODT B-MRASB B-MCASB B-TMA B-MCKB B-MVREFCA 0 B-MVREFDQ B-TMRASB A-MVREFDQ B-TMA B-MA R R B-MA C 0n R0 R B-TM B-TMA Close to DDR POWER PIN Close to DDR POWER PIN B-TMCKE B-TMDQL C n CB 0.u CB 0.u CB 0.u CB 0.u CB 0.u CB 0.u C0 n C n N A P A P A N A P A P A R A R A T A R L A R A N DQU0 D DQU C DQU C DQU C DQU A DQU A DQU B DQU A DQSU C /DQSU B DMU D DQL0 E DQL F DQL F DQL F DQL H DQL H DQL G DQL H DQSL F /DQSL G DML E B M BA N BA M /CS L /RAS J /CAS K /WE L CK J /CK K CKE K ODT K /RESET T VREFCA M VREFDQ H ZQ L VDDQ A VDDQ A VDDQ C VDDQ C VDDQ D VDDQ E VDDQ F VDDQ H VDDQ H Q B Q B Q D Q D Q E Q E Q F Q G Q G VDD B VDD D VDD G VDD K VDD K VDD N VDD N VDD R VDD R A E G J J M M P P T T J J L L M A T T B U KBGE-HCK CB 0.u CB 0.u A-MDQL A-MDQL A-MDQL CB 0.u A-MDQL A-MDQL A-MDQL0 R _% A-MCK A-MVREFDQ A-MDQL A-MDQL A-MDQU A-TMA B-MRESETB A-MDQU0 A-MCKB A-MDQU A-MA A-MDQU A-MDQU A-MDQU A-MDQU A-MDMU A-MDQSL A-MDQU A-MCKE A-MRESETB B-TMA A-MDQSLB A-MDML A-MDQSU A-MDQSUB CB0 0.u B-MDQL CB 0.u B-MDQL B-MDQL B-MDQL0 B-MDQL CB 0.u B-MDQL CB 0.u B-MVREFDQ B-MCK B-MDQL B-MDQL CB 0.u CB 0.u B-MDQU B-MDQU B-MDQU B-MDQU B-MCKB B-MDQU B-MRESETB B-MCKE B-MDQU0 B-MDQU B-MDQU B-MDQSUB B-MDQSU B-MDML B-MDQSLB B-MDMU B-MDQSL RP RX B-TMBA A-TMA B-MA RP RX A-TMB A-MA R R C 0n B-TMDMU B-MA B-TMODT B-TMBA B-TMB B-TMCASB B-TMDML A-TMDQL[0:] B-TMWEB B-TMDQSLB B-TMCKB B-TMDQSUB B-TMBA B-TMDQSL B-TMDQSU B-TMRESETB B-TMCK B-TMCKE B-TMRASB B-TMDQL[0:] B-TMDQU[0:] B-TMA[0:] B-TMDQU0 B-TMCKB B-TMCK B-TMBA A-MA A-TMA A-MA A-TMA B-MCKB B-MCK RP RX B-TMCK B-TMCKB A-TMA A-MA A-TMA A-MA A-TMA A-MA A-TMCKB A-TMCK RP RX B-TMDQU B-TMDQU A-MCK A-MCKB B-TMDQL B-TMDQL0 B-TMDQL B-TMDQU B-TMDQL B-TMDQU B-TMDQU B-TMDQSU B-TMDQSUB B-TMDQL B-TMDQL B-TMDQL B-TMDQU B-TMDQU B-TMDQL B-TMA B-TMA B-TMA B-TMA B-TMA B-TMODT B-TMA B-TMA B-TMWEB B-TMA B-TMCKE B-TMRASB B-TM B-TMA B-TMA B-TMCASB B-TMDQSL B-TMDQSLB B-TM B-TMA B-TMB B-TMA B-TMRESETB B-TMA B-TMDMU B-TMDML B-TMBA L0 A-TMDMU L A-TMB A-TMBA A-TMRESETB A-TMBA A-TMA[0:] A-TMCKB A-TMDQU A-TMODT A-TMDQU0 A-TMDQSUB A-TMDQSU A-TMCK A-TMCASB A-TMDQU A-TMDQU A-TMDQL A-TMDQL A-TMDQL0 A-TMDQL A-TMDQL A-TMDQL A-TMDQU A-TMDMU A-TMDQSLB A-TMDQSL A-TMDML A-TMDQU A-TMWEB A-TMA A-TMDQU A-TMDQL A-TMDQL A-TMDQU A-TM A-TMA A-TMA A-TMA A-TMCKE A-TMA A-TMA A-TMBA A-TMB A-TMA A-TMA A-TMA A-TMA A-TM A-TMA A-TMODT A-TMA A-TMA A-TMRASB A-TMCASB A-TMDML A-TMWEB A-TMDQSLB A-TMCKB A-TMDQSUB A-TMBA A-TMDQSL A-TMDQSU A-TMCK A-TMCKE A-TMA A-TMRESETB A-TMDQU[0:] A-TMRASB A-MDQL A-TMDQL A-MDQL A-TMDQL A-MDML A-TMDML A-MCASB A-TMCASB A-TMWEB A-MWEB B-MA A-TMRASB A-MRASB A-MODT A-TMODT B-TMA B-TMB RP0 RX A-TM 0 B-MA.V_DDR RP RX CB 0.u B-MA B-TMRESETB A-TMA B-MDQU B-TMDQU 0 A-MDQU A-TMDQU B-MBA B-TMA B-TMA.V_DDR RP RX B-MDQL B-TMDQL B-TMA B-M B-TMWEB A-TMA A-MB RP RX A-TMA B-TMA 0 B-MCK A-TMBA B-MB B-MDQU B-TMDQU B-MDQU B-TMDQU B-TMCASB B-MDQU0 B-TMDQU0 R R RP RX A-MCKB A-MCK B-MA A-MBA A-MA A-M R R A-MA R R A-MDQU A-TMDQU A-MDQU0 A-TMDQU0 A-MDQU A-TMDQU A-MA A-MRESETB RP RX A-MA B-TMBA A-TMRESETB B-TMA B-TMA B-MBA B-MA A-MDQL A-TMDQL B-MA R R B-MA B-TMODT A-TMA B-MWEB B-MRASB B-MODT B-MCASB Close to MST IC A-MA RP RX R R RP RX A-TMA CB0 0.u CB0 0.u CB 0.u R K/% R K/% CB 0.u R R R K/% R K/% CB 0.u R K/% CB 0.u R R CB 0.u CB 0.u R0 R R K/% R0 _% B-MDQL B-TMDQL CB 0.u B-MDQL B-TMDQL CB 0.u R K/% B-MDML B-TMDML R K/% CB 0.u CB 0.u CB 0.u CB 0.u CB 0.u C n B-TM A-MBA A-TMBA B-MA R R CB 0.u N A P A P A N A P A P A R A R A T A R L A R A N DQU0 D DQU C DQU C DQU C DQU A DQU A DQU B DQU A DQSU C /DQSU B DMU D DQL0 E DQL F DQL F DQL F DQL H DQL H DQL G DQL H DQSL F /DQSL G DML E B M BA N BA M /CS L /RAS J /CAS K /WE L CK J /CK K CKE K ODT K /RESET T VREFCA M VREFDQ H ZQ L VDDQ A VDDQ A VDDQ C VDDQ C VDDQ D VDDQ E VDDQ F VDDQ H VDDQ H Q B Q B Q D Q D Q E Q E Q F Q G Q G VDD B VDD D VDD G VDD K VDD K VDD N VDD N VDD R VDD R A E G J J M M P P T T J J L L M A T T B U KBGC-HCK B-MDQL B-TMDQL B-MDQL B-TMDQL CB0 0.u B-MDQL B-TMDQL B-MCKE B-MDQL B-MDQL0 B-TMDQL0 B-MDQSL B-TMDQSL B-MDQSU B-TMDQSU B-MDQU B-TMDQU B-MDQSLB B-TMDQSLB B-MDQU B-TMDQU B-MDQU B-TMDQU B-MDQU B-TMDQU B-MDQSUB B-TMDQSUB A-MA B-MA B-M B-MDMU B-TMDMU A-TM A-TMCKE A-TMDQL B-TMA A-TMA Close to DDR A-MDQL A-TMDQL A-MDQL A-TMDQL A-MDQL0 A-TMDQL0 A-MDQU A-TMDQU A-MDQSU A-TMDQSU A-MDQSL A-TMDQSL A-MDQL A-TMDQL Close to MST IC A-MDQU A-TMDQU A-MDQU A-TMDQU A-MDQSLB A-TMDQSLB A-MCKE A-MDQSUB A-TMDQSUB A-MDMU A-TMDMU A-MDQU A-TMDQU A-M A-MA A-MDQL B-MA A-MVREFCA R _% Close to DDR B-TMA A-MA A-M A-MBA A-MB A-MBA A-MWEB A-MA A-MVREFCA A-MA A-MA A-M A-MA A-MA A-MA 0 A-MA A-MA A-MA A-MA A-MA R _%

3 R0 0 HDMI Connector CN HDMI Connector V POWER HOT PLUG HDMI_0 R 00K HDMI0_RX HDMI0_RX0- HDMI0_RXC HDMI0_RX- HDMI0_RX HDMI0_RX- HDMI0_RX0 HDMI0_RXC- HDMI0_CEC HDMI0-V R K HDMI0_HPDIN HDMI0_ HDMI0_SDA HDMI0-V Q R0 0 R 0K R K R 0K HDMI_HP DATA DATA 0 DATA- DATA DATA DATA- DAT DAT DAT- 0 CLK CLK CLK- CEC SDA DDC/CEC HDMI0_RX R 0 HDMI0_RX- R 0 HDMI0_RX R 0 HDMI0_RX- R 0 HDMI0_RX0 R 0 HDMI0_RX0- R 0 HDMI0_RXC R 0 HDMI0_RXC- R 0 HDMI0_ R 00 HDMI0_SDA R 00 R 0K C 0.uF HDMI-RXP HDMI-RXN HDMI-RXP HDMI-RXN HDMI-RX0P HDMI-RX0N HDMI-CLKP HDMI-CLKN HDMI- HDMI-SDA CN HDMI_ DATA DATA 0 DATA- DATA DATA DATA- DAT DAT DAT- 0 CLK CLK CLK- CEC SDA DDC/CEC V POWER HOT PLUG R 00K D HDMI_RX R0 0 HDMI_RX- R 0 HDMI_RX R 0 HDMI_RX- R 0 HDMI_RX0 R 0 HDMI_RX0- R 0 HDMI_RXC R 0 HDMI_RXC- R 0 HDMI_ R 00 HDMI_SDA R 00 HDMI_RX D0 HDMI_RX- D HDMI_RX D HDMI_RX- D HDMI_RX0 D HDMI_RX0- D HDMI_RXC D HDMI_RXC- D HDMI_CEC D HDMI-V R K HDMI_HPDIN HDMI_ HDMI_SDA HDMI-V Q R0 0 R 0K R K R 0K D R 0K D HDMI_HP C 0.uF HDMI-RXP HDMI-RXN HDMI-RXP HDMI-RXN HDMI-RX0P HDMI-RX0N HDMI-CLKP HDMI-CLKN HDMI- HDMI-SDA HDMI Connector HDMI Connector V POWER HOT PLUG HDMI_RX D HDMI_RX- D HDMI_RX D HDMI_RX- D HDMI_RX0 D HDMI_RX0- D HDMI_RXC D0 HDMI_RXC- D HDMI_CEC D HDMI_ARC HDMI-V HDMI_RX HDMI_RX- R 0 HDMI_RX R 0 HDMI_RX- R 0 HDMI_RX0 R 0 HDMI_RX0- R 0 HDMI_RXC R 0 HDMI_RXC- R 0 HDMI_ R 00 HDMI_SDA R0 00 HDMI-RXP HDMI-RXN HDMI-RXP HDMI-RXN HDMI-RX0P HDMI-RX0N HDMI-CLKP HDMI-CLKN HDMI- HDMI-SDA CN HDMI_ DATA DATA 0 DATA- DATA DATA DATA- DAT DAT DAT- 0 CLK CLK CLK- CEC SDA DDC/CEC V POWER HOT PLUG HDMI_RX R 0 HDMI_RX- R 0 HDMI_RX R 0 HDMI_RX- R0 0 HDMI_RX0 R 0 HDMI_RX0- R 0 HDMI_RXC R 0 HDMI_RXC- R 0 HDMI_ R 00 HDMI_SDA R 00 HDMI_RX D0 HDMI_RX- D0 HDMI_RX D0 HDMI_RX- D0 HDMI_RX0 D0 HDMI_RX0- D0 HDMI_RXC D0 HDMI_RXC- D00 HDMI_CEC D HDMI-V CN0 HDMI_ DATA DATA 0 DATA- DATA DATA DATA- DAT DAT DAT- 0 CLK CLK CLK- CEC SDA DDC/CEC HDMI-RXP HDMI-RXN HDMI-RXP HDMI-RXN HDMI-RX0P HDMI-RX0N HDMI-CLKP HDMI-CLKN HDMI- HDMI-SDA R K HDMI_HPDIN HDMI_ HDMI_SDA R 0K R 0K C 0.uF R K HDMI_HPDIN HDMI_ HDMI_SDA R 0K R 0K C 0.uF R 00K D Q 0 HDMI-V R D R00 0K D R 00K D0 Q 0 HDMI-V R D0 R0 0K D0 R0 K HDMI_HP R0 K HDMI_HP HDMI_ARC C.u R HDMI-ARC HDMI-ARC HDMI_CEC R0 0 HDMI_CEC R0 0 HDMI_CEC R0 0 HDMI0_CEC R 0 To MST IC R0 00 HDMI-CEC HDMI-CEC CVBS_RCA D PB Y PR D0 D CN YUV PR Y PB R C nf AV-CVBSP R R0 0 R C R0 R C0 R0 R R R R R D Y R AV-V AV-V RGB/YPBPR Interface R DSMB_GPO DSMB_GPO 0K C nf YPbPr_SOY nf YPbPr_PB C nf YPbPr_Y nf YPbPr_PR V_Normal R 0K DSMB_COME_IN CN DSMBCON-* V VGA_R/PR 0 VGA_B/PB VGA_G/Y VGA_H_SY GPIO_IR VGA_V_SY 0 CVBS_RCA DSMB-L 0 DSMB-R DSMB_CVBSO DSMB_CVBSO, LINEOUTL LINEOUTR LINEOUTL DSMB_IR LINEOUTR, 0 UART-TX R 0 0 R 0UART-RX DSMB_STAS R 0DSMB_WAKEUP DSMB_D_LINE_ON R 0 R 0DSMB_COME_IN DSMB_WAKEUP VIDEO_TYPE R 0 0 R 0VIDEO_TYPE 0 DSMB_D_LINE_ON R K DSMB-D-LINE-ON VIDEO_TYPE R K VIDEO-TYPE VIDEO_TYPE R K VGA_G/Y VIDEO-TYPE R C nf YPbPr_Y UART-TX VGA_B/PB UART-TX UART-RX VGA_R/PR UART-RX D D D R0 C nf YPbPr_PR- R C0 nf YPbPr_Y- R C nf YPbPr_PB- R C nf YPbPr_Y- R C nf YPbPr_PB- R C nf YPbPr_PR- DSMB-L R 0K R C nf YPbPr_PB R C nf YPbPr_PR R R R C.uF HD_LIN-IC DSMB-R R 0K C.uF HD_RIN-IC R 0K VGA_H_SY VGA_V_SY V V_Normal R R 0K DSMB_IR Q IR-in Q 0 0 R 00 R0 00 R0 R.K.K IR-in DSMB_HS DSMB_VS R K C0 R0 0pF K C 0pF R C nf VGA-B- R C nf VGA-G- R C nf VGA-R- VGA-B- VGA-G- VGA-R- VGA-TX D CN VGA R G B VGA-RX VGAV D 0 V_VGA R C nf VGA-R R C nf VGA-G R0 C nf VGA-B D D0 D RR VGA-R VGA-G VGA-B CN0 VGA-R/L R R D D 0K 0K R K C R 0pF K C.uF C0.uF C 0pF VGA/YUV-LIN-IC VGA/YUV-LIN-IC VGA/YUV-RIN-IC VGA/YUV-RIN-IC SPDIF OUT(Vertical) Top View V C J 0.uF D D D D R.K R0.K R.K R.K VGA-RX R 00 VGA-TX R 00 DDC D R UART-RX DDC_SDA_D R UART-TX UART-RX UART-TX R 00 VGA_HS R 00 VGA_VS V_VGA V D BAV0 VGAV VGAV C 0.uF V_VGA R C U0 0.uF VCLK R 00 R 00 SDA /C0 R.K DDC D DDC_SDA_D IN SPDIF_V, SPDIF_OUT R D R 0K SPDIF_OUT 0 SPDIF_OUT C CLOSE TO MST IC

4 V_NER AV SIDE VIDEO R / V_out CN AV AV-L R R AV-V AV-R C nfvcom0 CVBSO_OUT VCOM0 R 00uF/V C R.K R.K C.uF Q 0 R R 00 R Q 0 C R R 00uF/V R 0K R0 K Q 0 R K R R AVOUT-V DD AV-V R0 C nf AV-CVBS0P V_out AV-L AV-R D R R R 0K 0K C C.uF.uF AV-Lin-IC AV-RIN-IC CA R R 00uF/V R 0K R Q 0 R R R DSMB_CVBSO DD DSMB_CVBSO 0 D0 D R0 K C 0pF R K C 0pF K K AV-V AV-V BACK VIDEO OUTPUT CN AV_OUT R AVOUT-V AV-V R / R C0 nf AV-CVBSP LINEOUTL R, LINEOUTL AVOUT-V R / R LINEOUTR / LINEOUTR, LINEOUTL, T_IC_T T_IC_TSDA R R 0_TV 0SDA_TV SDA R R R R _TV SDA_TV C pf C pf C C /p /p U VAECD0 V_NER 0 T /HFT-H-HR ANT POWER RF-SW RF-SW R ANT_POWE RFSW T_SDA T_ QH_IF_AGC T_ R C pf T_SDA C /0.uf R /0K SDA_TV V_NER R /0K _TV IF_AGC_T DTV-IF_AGC NER_RF_AGC AGC BT SDA V IFout SDA IF_TV V_NER DTV-IF_AGC 0 B(V) B(V) IF-AGC 0 SDA IF OUT RF AGC IF IF (AS) T_B T_IC_T T_IC_TSDA C R 0p / IF_TV QH_IF_AGC NER_RF_AGC C 0p QH_IF_OUT QH_IF_OUT- QH_IF_OUT QH_IF_OUT- V_IF DMBT_IFAGC DMBT_IFAGC L, DVB-C R0 C K V 0.u RClose to I H, DMB-T 0K Q R DTV-IF_AGC IF_AGC_DVB 0 IF_AGC_T /00 C VIF_V n V_NER R 00K V_NER V_NER R R 0K R C C.K L R 0 0K.uF 0nF 0.uH C R R0 0 R0 K 0.u RFSW R 00K Q 0 R 00K C R C IF-AGC-SEL R 0K Q IF_TV 0nF 0nF Q 0 SC R DMBT_IFAGC / R R /00 0 K NER_RF_AGCR 00 R / Q C 0nF R 0 U IN SAWOUT ING OUT N R0 0 VIF VIF L /.uh R 0 VIF VIF C C /0.uF /0.uF Q MMBT0 RF_AGC_T RF_AGC_T C 0.u V_NER R 0K R 00K Q R0 0K RF_AGC_SEL MMBT0 V R //W C CA 0.uF /00uF/V V L0 0uH U /LM0 VIN VOUT C C 0.uF 0.uF V_NER V_NER C NF CA 0uF/V V_NER L ANT_POWE L /FB/0 T_B C C C C C NF /0uF NF 0uF 00uF/V FB V_NER

5 REGOUT LAN-PHY_MDC LAN-PHY_MDIO LAN-PHY_TXD0 LAN-PHY_TXD LAN-PHY_TXEN LAN-PHY_MDC LAN-PHY_MDIO LAN-PHY_TXD0 LAN-PHY_TXD LAN-PHY_TXEN VDD R.K U IP0ALFX AVDD EMAC-TXCLK LAN-PHY _MDC EMAC-TXCLK LAN-PHY _MDIO EMAC-RXDV LAN-PHY_TXD0 EMAC-RXDV EMAC-RXD0 LAN-PHY_TXD EMAC-RXD0 EMAC-RXD EMAC-RXD LAN-PHY _TXEN R 必须靠近 PHY CLK 必须包地 EMAC-TXCLK R 0MHz_CLKOUT 0/REMAC-RXDV C0 EMAC-RXD0 /pf EMAC-RXD 0 0MHz CLOCK OUT 0MHz_CLKOUT Generate by IP0A VDD R0.K R.K ET_RX_ER X_INPUT Set IP0A X_OU TPUT to RMII Mode VDD VDD R.K/ ET_INT_LAN * PHY AD0/LED0 PHY AD/LED 0 use M crystal Y PHY AD/LED MHz PHY AD/LED X_OUTPUT X_INPUT PHY AD/LED MDC MDIO TXD0 TXD TXD TXD TX_EN REF_CLK CRS_DV RXD0 RXD RXD RXD C0M_O COL CRS/LEDMOD RX_ER X X DVDD INTR PHYAD0/LED0 PHYAD/LED PHYAD/LED PHYAD/LED PHYAD/LED IP0A AVDD REGIN REGOUT A A ISET MDI_TP MDI_TN MDI_RP MDI_RN 0 TEST_ON AN_ENA DPLX SPD RPTR 0 APS ISOL MII/SNIB AVDD REGIN REGOUT BANDGAP RESISTOR R.K/.0K/% TXP TXN RXP RXN R.R/% R.R/% C00 0.uF.R/% R.R/% R REGOUT C0 0nF R R R R C0 nf/kv C 0.uF U HST-00SAR TD TCT TD- RD RCT RD- C0 0nF TX TX- TCM R RX RX- 0 R TCM- TX TX- RX CMT CMT RX- CMT CMT 0 DATALED_N DATALED_P LINKLED_P LINKLED_N RJ-LED P R R R0 R C0 pf C0 pf D D D RESET_N RST_LAN CRYSTAL as close as to chip Pin could be short VDD if interrupt funtion is not used. TP TN RP RN R R R R / / / / RXP RXN TXP TXN.V_Normal R00 /,,,,,0, V_Normal V_Normal V_Normal L ICC < 00mA L FB/A C.uF As close to IP0A Pin as possible FB/A C0 0.uF VDD AVDD D N VDD RSTN_LAN-PHY VDD R0 00K RST_LAN R 0K R /0K R C 0.uF 0K Q 0 R0 / REGOUT C0 0.uF C 0uF As close to IP0A Pin as possible R L * * C C uf 0nF FB/A As close to IP0A Pin as possible REGIN ** Bead should be placed as close to IP0A as possible and in the same side as IP0A. * : Optional,but recommended LED and PHY address Configuration This schematic sets PHY address to 0000b. VDD PHYAD0/LED0 R.K PHYAD/LED R.K LED R /0 /LED/Green/00 PHYAD/LED R.K LED R /0 /LED/Green/00 C0.uF As close to IP0A Pin as possible C 0.uF LAN ID R R C U stc nc /K /K /0.uF WP n.c SDA R R C 0.uF /R /R IC- IC-SDA V_Normal IC-,,, IC-SDA,,, PHYAD/LED PHYAD/LED LED R /LED/Green/00 R.K R.K /0 LED0 LED LED LED LED Link Dupx 0Act 00Act COL /DM0 C C DM0 DP0 V_USB DD CN D- D USB_P USB_D- USB_D USB_D- USB_D R0.R DM0 R.R DP0 V_USB USB_D- USB_D USB_D- USB_D V_USB USB_D- USB_D USB_D- USB_D R.R DM R.R DP R.R DM R.R DP V_USB DM DP DD CN USB_P D- D CA 00uF/V C 0.uF CA 00uF/V C 0.uF C 0.uF V_USB DM DP DD0 CN USB_P D- D

6 IS-OUT_MCK MUTE Circuit V L FB V_amp Vstb R00 0 V R0 D BAV R.M R0 00 CA 00uF/V AMP-MUTE AMP-MUTE R 0: Normal :Mute R M R C.uF V 0K Q 0 K B SOT PWD_MT R C E R K E B R Q 0 SOT R 00 C 0K Q 0 K B SOT R 00 C E C /.uf EN=HIGH: OPERATING EN=LOW: MUTE HP_MUTE_AMP V_amp IS-OUT_MCK R IS-OUT_BCK IS-OUT_BCK R IS-OUT_WS IS-OUT_WS R 0 IS-OUT_SD IS-OUT_SD R,, IC- R,, IC-SDA R HP_MUTE_AMP C 00pF R0 0 C nf C 0.0uF C 00pF 0 R 0 C nf V_Normal R R 0 K C0.uF R0 R C 0.uF C /00pF K R K R R 0K V_Normal R 0K 0.uF/0V C0 0.uF/0V C 00uF/V CA P_A P_A P_B P_C P_D 0 P_D A P P_AB P_AB P_CD P_CD DO A D C0 0.uF OUT_B R0 0 C C V_Normal 0uF 0.uF C0.uF/.uF/V C.uF/.uF/V C L 0nF/V uh C 0nF/V L uh RST_AMP U CC0CC IS-OUT_MCK IS-OUT_MCK R0 IS-OUT_BCK MCLK IS-OUT_BCK R IS-OUT_WS 0 K IS-OUT_WS R IS-OUT_SD LRCLK IS-OUT_SD R0 SDIN,, IC- R R,, IC-SDA HP_MUTE_AMP SDA PDN C 00pF R 0 C nf PLL_FLTP C 0.0uF VR_ANA C 00pF 0 R 0 C nf PLL_FLTM V_Normal R R 0 OSC_RES K C.uF R0 R0 C 0.uF VR_DIG C /00pF K R K SSTIMER OC_ADJ R0 R0 V_Normal 0K R 0K RST_AMP RST_AMP R 00 CA 00uF/V C.uF 0.uF/0V C 00uF/V C 0nF/V C 0nF/V C 0nF/V C 0nF/V L uh L uh OP_ U 0.uF/0V C MCLK K LRCLK SDIN SDA PDN PLL_FLTP VR_ANA PLL_FLTM OSC_RES VR_DIG SSTIMER OC_ADJ FAULT RESET C TAS0A 0.uF/0V R 0 AVDD DVDD C A STEST 0 V_Normal 0uF OUT_A BST_A BST_B VCLAMP_AB VCLAMP_CD FAULT RESET C 0.uF/0V C 0.uF/0V C 00uF/V CA C P_A P_A P_B P_C P_D 0 P_D A P P_AB P_AB P_CD P_CD DO A D TAS0 0.uF/0V R 0 C 0uF AVDD DVDD C A STEST 0 V_Normal 0.uF OUT_A BST_A BST_B OUT_B VCLAMP_AB VCLAMP_CD E OUT_C BST_C BST_D OUT_D VREG R 0 C0 C V_Normal 0uF 0.uF L uh C.uF/.uF/V C.uF/.uF/V C.uF/.uF/V L uh CN Speaker AMP-Rout AMP-Rout- AMP-Lout- AMP-Lout R /R C /0nF AMP-Lout C C0 0NF 0NF C C C0 0NF 0NF AMP-Lout- R0 /R C /0nF /0nF R /R C AMP-Rout C C 0NF 0NF C0 C C 0NF 0NF AMP-Rout- R /R C /0nF V R CA 00 VBuf 00uF/V R0 R C k C OP_ 0uF 0.uF k AV_AUOUTL AV_AUOUTL C R 0K.uF UA RC - R0 K C 00pF VBuf OP_ C 0.uF AV_AUOUTR AV_AUOUTR C0 R 0K -.uf Near MST.IC R C Ground in the middle of the L/R RC UB K 00pF R 0K R 0K C R K LINEOUTL, 0uF R D.K ESD C R K LINEOUTR, 0uF R0 D.K ESD E OUT_C BST_C BST_D OUT_D VREG C 0nF/V C 0nF/V C.uF/.uF/V R /R C /0nF Woof er C C0 0NF 0NF C C C 0NF 0NF Woof er- R /R C0 /0nF Woofer- Woofer CN Woofer RST_AMP R0 00 C.uF B0_RXE B_RXE- B_RXE B_RXE- B0_RXE B_RXE- B_RXE B_RXE- Ursa_RXE Ursa_RXE- Ursa_RXE Ursa_RXE- B_RXEC B_RXEC- B_RXE B_RXE- B_RXEC B_RXEC- B_RXE B_RXE- Ursa_RXEC Ursa_RXEC- Ursa_RXE Ursa_RXE- G0_RXE G_RXE- G_RXE0 G_RXE0- G0_RXE G_RXE- G_RXE0 G_RXE0- Ursa_RXE Ursa_RXE- Ursa_RXE0 Ursa_RXE0- G_RXO G_RXO- G_RXO G_RXO- R0_RXOC R_RXOC- R_RXO R_RXO- R_RXO R_RXO- R_RXO0 R_RXO0- G_RXO G_RXO- G_RXO G_RXO- R0_RXOC R_RXOC- R_RXO R_RXO- R_RXO R_RXO- R_RXO0 R_RXO0- CN LVDS_ Ursa_RXE Ursa_RXO- Ursa_RXE Ursa_RXO- Ursa_RXOC- Ursa_RXEC Ursa_RXE Ursa_RXO- 0 Ursa_RXO- 0 Ursa_RXE Ursa_RXO0- D_SY_OUT D_SY_OUT R Localdimming/SY Ursa_RXE0 R0 IC-, R0 BRT_CNTL_OUT C0 CA 0.uF 00uF/V Ursa_RXO Ursa_RXO- Ursa_RXO Ursa_RXO- Ursa_RXOC Ursa_RXOC- Ursa_RXO Ursa_RXO- Ursa_RXO Ursa_RXO- Ursa_RXO0 Ursa_RXO0- Ursa_RXE- Ursa_RXE- Ursa_RXEC- Ursa_RXE- Ursa_RXE- LVDSSEL/D_ON Ursa_RXE0- R0, IC-SDA BRT_CNTL_IN R0 CN LVDS_ LVDS OUT Ursa_RXO Ursa_RXO Ursa_RXOC Ursa_RXO Ursa_RXO Ursa_RXO0 R Localdimming/SY R0 D_f lag D_f lag, V_Normal Localdimming/SY Localdimming/SY R R panel_s R0 0k R /0k Q /0 /0k Localdimming/SY R panel_s R 0k R LVDSSEL/D_ON R Q0 /0 LVDSSEL/D_ON,

7 TS_D R V.R/W.V.V.V.V.V L.V L.V.V Ursa_.V CON L L PIN/.0MM R.V.V AVDD_MPLL FB//A C C.uF 0.uF FB//A R 00 R 00 U AMS-ADJ VIN VOUT R.K_% C0 C.uF 0.uF AVDD_MEMPLL C 0uF C 0.uF Ursa_VDDP FB//A C C C0.uF 0.uF 0.uF FB//A.V AVDD C C C 0.uF 0.uF 0.uF Ursa_.V RR C C 0.uF 0.uF R V_Normal C C 0.uF 0.uF C C0 C0 0.uF 0.uF 0.uF.K.K R 00ICS_ R 00ICS_SDA IC- IC-SDA IC- IC-SDA.K_% L FB//A C0.uF C00 C 0.uF 0.uF C0 0.uF.V C0 0.uF.V D_SY_OUT.V C C C C C C C 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF New add to C0.V LR_SYCNK C0 /.uf D_SY_OUT R New add to PIN G_RXO G_RXO G_RXO- G_RXO- G_RXO G_RXO G_RXO- G_RXO- R0_RXOC R0_RXOC R_RXOC- R_RXOC- R_RXO R_RXO R_RXO- R_RXO- R_RXO R_RXO R_RXO- R_RXO- R_RXO0 R_RXO0 R_RXO0- R_RXO0- B0_RXE B0_RXE B_RXE- B_RXE- B_RXE B_RXE B_RXE- B_RXE- B_RXEC B_RXEC B_RXEC- B_RXEC- B_RXE B_RXE B_RXE- B_RXE- G0_RXE G0_RXE G_RXE- G_RXE- G_RXE0 G_RXE0 G_RXE0- G_RXE0-.V R K R0 R /0K.V R /.K Q 0 D_sy cn V R 00 Ursa_.V Ursa_RXE0- Ursa_RXE0 Ursa_RXE- Ursa_RXE Ursa_RXE- Ursa_RXE Ursa_RXEC- Ursa_RXEC Ursa_RXE- Ursa_RXE Ursa_RXE- Ursa_RXE Ursa_.V TP SPI_DA TP SPI_CK TP0 SPI_DI SPI_CK SPI_CZ New modify! SPI_DO GPIO K GPIO BRI_ADJ-PWM R U_PWM D_sy cn R U_PWM0 TP BRI_ADJ-PWM Ursa_RXE R 00 Ursa_RXE- Ursa_RXE R 00 Ursa_RXE- Ursa_RXEC R 00 Ursa_RXEC- Ursa_RXE R 00 Ursa_RXE- Ursa_RXE Ursa_RXE- Ursa_RXE0 Ursa_RXE0- Ursa_RXO Ursa_RXO- Ursa_RXO Ursa_RXO- Ursa_RXO Ursa_RXO- Ursa_RXO0 Ursa_RXO0- C 00uF/V C 0.uF R0 00 R 00 R 00 Ursa_RXOC R 00 Ursa_RXOC- Ursa_RXO R 00 Ursa_RXO- Ursa_VDDP R 00 R0 00 AVDD R0 C.nF R.K 00K ICS_SDA ICS_ Ursa_RXO0- Ursa_RXO0 Ursa_RXO- Ursa_RXO Ursa_RXO- Ursa_RXO Ursa_RXOC- Ursa_RXOC Ursa_RXO- Ursa_AM Ursa_AM Ursa_ACKM Ursa_AM Ursa_AM LVDSSEL/D_ON R0,, LVDSSEL/D_ON Ursa_M R,, IC-SDA BRT_CNTL_IN R C0 0.uF U0 MP EN COMP SS VDDP OUT BST FB U_XTALO R U MSTM0S Ursa_.V C 0nF R00 R VD VD M_S_PIF_FC M_S_PIF_CLK M_S_PIF_D M_S_PIF_DA ICS_SDA ICS_ AVDD RO0N RO0P RON ROP RON ROP ROCKN ROCKP RON ROP RON ROP AVDD DVDD_HF RE0N RE0P REN REP REN REP RECKN RECKP REN REP REN REP AVDD VDD VSY_Like SPI_DI SPI_CK SPI_DI SPI_CK SPI_DI SPI_CK SPI_CZ VD SPI_DO GPIO[] GPIO[] PWM PWM0 GPIO[] R0 New add! L.K/%.K/% R M Y MHz/DIP U_XTALI C0 C 0pF 0pF CN LVDS_ uh Ursa_.V AVDD_MPLL R CA 0uF/V A A A A A CN LVDS_ Ursa_AP Ursa_BM Ursa_BP Ursa_DM Ursa_AP Ursa_BM Ursa_BP Ursa_DM Ursa_BCKM Ursa_BCKP Ursa_DCKM Ursa_ACKP Ursa_BP Ursa_AP Ursa_BM 0 Ursa_DM Ursa_BM 0 Ursa_BP Ursa_DM Ursa_AP Ursa_B0M Ursa_B0P Ursa_D0M D_SY_OUTR R0 LR_SYCN R Localdimming/SY Ursa_CM Ursa_P Ursa_CM R Ursa_CCKM IC-,, R BRT_CNTL_OUT, Ursa_CM Ursa_CM Ursa_C0M C 0.uF D_SY_OUT D_SY_OUT Ursa_.V C 0.uF Localdimming/SY Localdimming/SY D_f lag D_f lag AVDD_MEMPLL.V R D R BAV R /.K 00K R.K C.uF CCKP CP CP D0P DP MOD_GPIO MOD_GPIO DP DCKP DP DP LPLL_OUTCLK ICM_SDA ICM_ OP_SY _L SOFT_RST_L VD DDR_A DDR_A DDR_A DDR_A DDR_A DDR_A DDR_ DDR_CASZ DDR_RASZ DDR_ODT DDR_MCLKZ DDR_MCLK DDR_DQ[] DDR_DQ[] DDR_DQ[0] DDR_DQ[] Q0 0/0 R K R Ursa_.V Ursa_.V VDDP Ursa_DP Ursa_DP Ursa_DCKP Ursa_DP Ursa_DP Ursa_D0P Ursa_CP Ursa_CP Ursa_CCKP Ursa_CP Ursa_CP Ursa_C0P A A A A A A ODT CLKZ CLK DQ DQ DQ0 DQ C nf Ursa_CM Ursa_CCKP Ursa_CCKM Ursa_CP Ursa_CM Ursa_CM Ursa_CP Ursa_D0M Ursa_D0P Ursa_DM Ursa_DP Ursa_DM Ursa_DP Ursa_DCKP Ursa_DCKM Ursa_DP Ursa_DM Ursa_DP Ursa_DM CN U_RESET C /0uF.V GPIO0 R.V R.K R0 /.K U0 KTQI-HCF DDR_.V GPIO GPIO: two chip use H: Master L: Slave CHIP_CONF: {GPIO, PWM, PWM0} CHIP_CONF= ˇd: 0 : boot from internal SRAM CHIP_CONF= ˇd: 0 : boot from EEPROM CHIP_CONF= ˇd: : boot from SPI Flash U_PWM0 U_PWM GPIO CA C 00uF/V 0uF SPI_CZ R SPI_DO R R0 0K A E J M R C 0.uF CA C 00uF/V0uF R 0K R0 /0K DDR_.V U CE# SO WP# HOLD# SCK SI ENF-00GIP/SOP MDQM B MDQM0 F UDM LDM MDQS0 F J MDQSB0 E LDQS A Vref MDQS B LDQS# CKE K Vdd Vss UDQS# VddQ MDQSB CLK J A UDQS B K UDQS# DQ UDM UDQS DQ CLK# MDQ D C B MDQ D DQ VddQ DQ VddQ VddQ DQ VddQ DQ C MDQ C DQ D DQ D MDQ B DQ DQ DQ DQ0 DQ DQ0 D DQ E DQ MDQ F Vdd Vss LDQS# VddQ F MDQ G DQ F DQ G MDQ H DQ DQ LDM LDQS DQ DQ0 H MDQ H DQ G DQ H DQ VddQ DQ VddQ VddQ DQ0 VddQ DQ H K DQ DQ DQ DQ ODT K MBA L J RAS# L MB L BA VddL Vref Vss VssDL CK Vdd CS# L B K CAS# MA M CKE WE# RAS# CK# ODT M M M A L M MA N RFU B BA CAS# CS# A N A M A N A A Vdd A MA P N P MA R A Vss A A A A A P MA P A P A K MA N A A A A A Vss WE# A R R Vdd A RFU RFU MBA L RFU R RFU RFU R A E J A E J N P R 0K R /0K R 0K R /0K R 0K R /0K C 0.uF.V A B B D D E F F H H J.V R R C0 C0 C C C 0.uF 0.uF 0.uF 0.uF 0.uF C 0.uF R0 R C 0nF C00 SPI_CK SPI_DI C C C C C C 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF C 0.uF R R MVREF MCKE MCLK R MCLKZ MDQ MDQ MDQ0 MDQ MDQ MODT MRASZ MCASZ M MA MA MWEZ C 0.uF MCLK MCLKZ C 0.uF C 0.uF MA MA MA MA MA M MA MBA MB MBA MCKE MWEZ MDQ MDQ MDQ MDQ MDQ MDQ MDQ MDQ MDQM0 MDQM MDQS0 MDQSB0 MDQSB MDQS MDQ MDQ MDQ0 MDQ MDQ MDQ0 MDQ MDQ MCLK MCLKZ MODT MRASZ MCASZ M MA MA MA MA MA MA C C 0.uF 0.uF R R RP RP RP RP RP RP RP RP RP R R RP R R RP/R/00 A A A A RP/R/00 A A BA RP/R/00 B BA CKE WEZ RP/R/00 DQ DQ DQ DQ RP/R/00 DQ DQ DQ DQ RP/R/00 RP/R/00 DQ0 DQ DQ RP/R/00 CLK CLKZ RP/R/00 ODT RASZ CASZ RP/R/00 A A R R DQM0 DQM DQSB0 DQS0 DQS DQSB RP0 RP/R/00 DQ DQ DQ0 DQ RP RP/R/00 DQ DDR_.V C R0 R0 C0 0.uF 0K 0K 0.uF A A A A MVREF, IC-, IC-SDA R DMBTJ_ DMBTJ_SDA R QH_IF_OUT R 0 C 0.uF VIN- VDD_CORE R 0 AD-VREF DMBT_IFAGC R 0 R0 K AGCPDM QH_IF_OUT- R 0 C 0.uF VIP C C 0.uF C 0.0uF C R0 0 C 0.uF VDD_CORE L0 0nH C L0 0.uF C00 0uF 0nH L0 C 0.uF VDD_CORE L0 C0 TS_CLK TS_VLD TS_SY TS_D TS_D TS_D TS_D TS_D TS_D TS_D0 R TS_CLK R TS_BCLK TS_VLD R TS_VALID TS_SY R TS_PSY TS_D TS_TS R TS_D R TS_TS TS_D R TS_TS TS_D R TS_TS TS_D TS_TS R0 TS_D R TS_TS TS_D R TS_TS TS_D0 TS_TS0 V_Normal R 0K Lx_STDBY demo_standby Demod_RST C 0nH 0.uF AD-VREF R.K R0.K DMBTJ_ DMBTJ_SDA AGCPDM Lx_STDBY Lx_RESET C 0.uF R.K VIP VIN- B B C C C D A B G C D B K L K L K J J H H G AVDD_ADC A A AVDD_PLL F AVDD_PLL D DVDD_PLL VDD C0 VDD D VDD G VDD G A A_PLL A_ADC B E A_PLL C D_PLL D B0 IO C IO E IO E IO E IO F F IO H IO H IO H H J Q K Q L Q L Q K L J J VIP VIN VIP VIN VDDQ Please refer to the below difference VDDQ VDDQ SDA when you want to swap the chip HDL VDDQ SVDDQ for HDL! _T SVDDQ SDA_T NET name HDL HDL TS_D0 IC_A_SEL VDD_core.v.0v TS_D TS_D AGC_PDM AVDD_PLL.V U0 TS_D HDL TS_D STDBY_N TS_D RST_N TS_D TS_D AD0 AD TS_CLK AD TS_VLD AD TS_SY AD AD SCAN_EN AD TEST_MODE AD AD CLK_OUT AD CLK0M DEMOD_.V J D E E0 F F G H L L K J K K D0 TS_TS0 H0 TS_TS J0 TS_TS K0 TS_TS G TS_TS L0 TS_TS H TS_TS J TS_TS K TS_BCLK F TS_VALID E TS_PSY J D B CLK_OUT A CLK_IN VDDQ_.V C C C0 0.uF 0.uF 0.uF H ADC_SEL E PLL_SEL V_Normal B A PROB0 B PROB C PROB A PROB D PROB A PROB B PROB C PROB D PROB A PROB PROB0 B PROB C PROB D PROB PROB A L LED0 LED F F0 G G0 H J L K L C CLK 0_Mhz R0 M Y R0 V_Normal L0 DEMOD_.V R k R K C 0pF 0.MHz C0 0pF 0nH V_Normal L0 VDDQ_.V D0 LED D0 LED 0nH A VDD_CORE DEMOD_.V C 00uF C C C 0.uF 0.uF 0.uF C C0 0.uF 0uF C00 0uF C C C 0.uF 0.uF 0.uF C 0.uF ADD V_Normal C00 0uF U AMS-ADJ VIN VOUT C 0.uF C 0.uF L0 FB/A VDD_CORE V U AMS-ADJ VIN VOUT C 0.uF SOT V_Normal R 0/% C00 C R.uF 0.uF 00/% Chip Config Close to M0 Close to M0 HW RESET IC ADD Debug : 0xB, ISP : 0x Debug Port Reserve pwm control backlight function Ursa_RXO Ursa_RXO- Ursa_RXO GPIO0 TP D_flag TESTPIN U_RESET U_XTALO U_XTALI A Ursa_P Ursa_M Ursa_AP Ursa_AM Ursa_AP Ursa_AM Ursa_ACKP Ursa_ACKM Ursa_AP Ursa_AM Ursa_AP Ursa_AM Ursa_B0P Ursa_B0M Ursa_BP Ursa_BM BA B BA CKE WEZ DQ DQ DQ DQ DQ DQ Ursa_BP Ursa_BM Ursa_BCKP Ursa_BCKM Ursa_BP Ursa_BM Ursa_BP Ursa_BM Ursa_C0P Ursa_C0M Ursa_CP Ursa_CM Ursa_CP E M_S_PIF_CS S_M_PIF_CS S_M_PIF_FC S_M_PIF_CLK S_M_PIF_D S_M_PIF_DA 0 TESTPIN 0 RESET 0 GPIO[](LTD_D) 0 GPIO[](LTD_CLK) 0 VDD 0 AVDD_MPLL 0 XTALO 0 XTALI 0 0 LPLL_REFIN 00 LPLL_FBCLK P M AP AM AP AM 0 ACKP ACKM AP AM AP AM B0P B0M BP BM 0 MOD_GPIO0 MOD_GPIO AVDDL_MOD BP BM BCKP BCKM BP BM 0 BP BM C0P C0M CP CM CP GPIO[0] GPIO[] GPIO[0] VD SPI_DI SPI_CK SPI_DI SPI_CK SPI_CZ SPI_DO SPI_DI SPI_CK GPIO[](LTD_DE) GPIO[](LTD_DA) VDD DDR_A DDR_A DDR_A DDR_A DDR_A DDR_ DDR_A DDR_BA DDR_B DDR_BA DDR_CKE DDR_WEZ DDR_DQ[] DDR_DQ[] DDR_DQ[] DDR_DQ[] DDR_DQ[] DDR_DQ[] DDR_DQ[] DDR_DQ[] DDR_DQM[] DDR_DQM[0] DVDD_DDR DDR_DQS[0] DDR_DQSB[0] 00 DDR_DQS[] 0 DDR_DQSB[] 0 AVDD_PLL 0 0 DDR_DQ[] 0 DDR_DQ[] 0 DDR_DQ[0] 0 DDR_DQ[] 0 MSTM0SL -CH LVDS in / -CH LVDS out DDR- DQ DQ DQM DQM0 DQS0 DQSB0 DQS DQSB DQ DQ DQ0 DQ CM CCKM 0 CM AVDDL_MOD CM D0M DM DM DCKM DM DM 0 SOFT_RST_R OP_SY_R VDD CASZ RASZ For Local dimming function, use M bit(k byte)spi flash DDR : 0Mbps,Mbit MA A Vdd Vdd Vdd Vdd Vdd VddL Vss Vss Vss Vss Vss VDD VddQ A VddQ C VddQ C VddQ C VddQ C VddQ E VddQ G VddQ G VddQ G VddQ G VssDL Place Close to DRAM MDQ MDQ MDQ0 MA MA MA LVDS OUT.V Power for DDR Reserve pwm0 for D vsycn control function Reserve GPIO0 For frame interlace D MODE L,R Flag control R R =Vrefx((R/R))IadjxR =.x((k/.k))uaxk=.v

8 R 原始设计上拉在排阻后 R0 V_Normal R0 C0 0.uF PCM_A[:0] R /k R 0 PCM_D[:0] V R K R0 K PCM_A[:0] TS_MDO PCM_D[:0] TS_MOCLK TS_MDO TS_MDO TS_MDO TS_MDO TS_MDO0 TS_MDO[:0] TS_MDO TS_MDO TS_MOSTART DD0 BATC TS_MOVAL TS_MDO[:0] PCM_PWR_CTL Q MMBT0 L /FB0/00mA R0.k R0 /K R K Q 0A R 0K R 00K -PCMCIA Q MMBT0 R 0k C 0.u R.k V R R0 R NAND_RBZ NAND_CEZ NAND_REZ PCM_D PCM_D NAND_WPZ NAND_WEZ NAND_ALE PCM_D PCM_D PCM_D PCM_D PCM_D PCM_D0 R/B RE CE /CE 0 CLE ALE WE WP D D D D 0 D D D 0 D0 0/WPZ U HUGFBTR C 0uF C 0.uF C 0.uF C0 0.uF L FB0/00mA V_Normal NAND_RBZ NAND_FLASH_PWR-.V NAND_FLASH_PWR-.V NAND_FLASH_PWR-.V NAND_CLE NAND_CEZ NAND_REZ NAND_WPZ NAND_WEZ NAND_ALE PCM_D[:0] NAND_CLE PCM_D[:0] R0 TS_MOCLK R0 R0 C /0p TS_VLD, TS_CLK, TS_SY, CA 00uF/V C 0.u PCM_A PCM_A PCM_A PCM_A PCM_A PCM_ PCM_A PCM_A PCM_A PCM_A PCM_A PCM_ PCM_A PCM_A PCM_A R.K PCM_D PCM_D0 PCM_D PCM_D PCM_D PCM_D PCM_D PCM_D TS_D0 TS_D TS_D TS_D TS_D TS_D TS_D TS_D D D D D D CE# OE# A 0 A A A A WE# READY VPP MIVAL MICLK 0 A A A A A A A A D0 0 D D WP CD# MDO MDO MDO MDO 0 MDO CE# VS# IORD# IOWR# MISTRT MDI0 MDI MDI MDI 0 VPP MDI MDI MDI MDI MOCLK RESET WAIT# INPACK 0 REG# MOVAL MOSTART MDO0 MDO MDO CD# 0 CONN PCMCIA_CNT -PCMCIA TS_MDO TS_MDO TS_MDO -PCMCIA TS_MDO TS_MDO TS_MDO TS_MDO TS_MDO0 TS_MOSTART TS_MOVAL TS_D[0:], -PCMCIA -PCMCIA R.K

9

10 . 接线图 AV 输入 网口 USB 高频头 模拟 数字信号 HST-00SAR USB 声表 CI 卡 TAS0 接中高音箱 USB IP0A TAS0A 接重低音箱 VGA DDR M VGA\YUV AUDIO MSDI M0 LVDS 输出 YUV DDR G 光纤 DDR G 视频 声音 Nor Flash Nor Flash M AV 输出 RC HDMI HDMI HDMI Nand Flash G 电视原理框图如上图所示, 主要由以下几个部分组成 : )RF 电视射频信号处理模块, 该模块与普通电视机中的电视信号处理部分功能相同,

11 其可接受多种输入信号格式, 如 PAL NTSC SECAM RF 电视射频信号的接收使用 FS 高频头进行处理, 处理后可输出 M 的 IF 信号 IF 信号经过声表输出伴音中频和图像中频直接输给主芯片内置的中频解调模块 )CVBS 处理模块, CVBS 信号直接提供给 I 主芯片的 VD& Comb 模块, 经过对信号钳位后, 该模块把 CVBS 信号进行梳状滤波 分离, 进入 VIDEO DECODER 处理 / 数字信号转换模块, 转变为数字 YUV 信号及同步信号 )YPbPr 输入处理模块, 该模块把隔行 / 逐行模拟 YPbPr 信号进行钳位后, 经过 A/D 转换, 转换为数字 YUV 及同步信号 )RGB 信号转换模块 该模块主要用把 PC 输出的标准模拟 VGA 视频信号进行 A/D 转换, 转变成并行数字 VGA 视频信号 )HDMI/DVI 数字信号接收处理处理模块 这部分的功能主要由 HDMI 接收器来实现 其接收 HDMI 输出的标准串行数字视频 HDMI 信号, 然后将其转变为 位 ( 或 位 ) 并行数字视频信号及伴音信号 ) 数字多媒体处理模块,USB HOST 将读取的内容送到 M 内置的 H. RealMedia Mpeg/ 进行解码, 输出相应并行数字 YUV/RGB 视频信号 )LED 图像处理模块 (SCALER D NR ACE-) 该模块的可对前端进来的多种格式数字 YUV 视频信号进行处理, 输出平板显示模块可接受的平板图像显示数据格式 其主要功能有 : 数字色度亮度处理 彩色 γ 校正 图像大小缩放 画质改善 运动补偿 边缘平滑等 ) 声音输入处理及放大模块, 模拟伴音经过 A/D 转换得到的数字音频, 与 HDMI 及其他数字音频送入音频处理 DSP, 经过 Pre-scaler AVC Loudness Bass Treble equalizer 等系列处理, 再将信号编码成 IS 信号送入功放放大及进行 D/A 转换输出给耳机 )LVDS 输出模块, 该模块是将 BIT/0BIT 的数字 YUV 信号进行色彩空间转换 (CSC) 得到 BIT/0BIT 的数字 RGB 信号, 再编码成 LVDS 信号, 输出给 LVDS 接口的屏或 FRC 处理芯片, FRC 处理芯片将 LVDS 信号解码成数字 RGB 信号, 经过 CSC 色彩空间转换后的数字 YUV 信号送入 MFC 进行运动估算及运动补偿 (MEMC) 0)CPU 模块 提供人机接口及对电路的各个功能模块进行功能设置和控制 ) 屏显示模块 该模块是 LED-TV 的显示终端, 其接收平板图像处理器输出的 LVDS 平板图像显示数据, 经内部时序控制电路转换后驱动 LED 屏显示出正确的视频图像 ) 供电模块 对电源接口输入的 V V 直流电进行线形变压或 DC/DC 转换后, 提供系统需要的各种不同电压 如主芯片 CORE POWER.V DDR POWER.V USBPOWER V 等