RSL10CN - 超低功率®多协议蓝牙5无线片上系统(SoC)

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1 5 (SoC) 2.4 GHz, ARM Cortex M3 LPDSP32 DSP, 2.4 GHz, Rx ( ) (,1 Mbps): 94 dbm : kbps : dbm Rx( ) = 5.6 ma (1.25 V VBAT) Rx( ) = 3.0 ma (3 V VBAT) Tx( ) (0 dbm) = 8.9 ma (1.25 V VBAT) Tx( ) (0 dbm) = 4.6 ma (3 V VBAT) 5, LE 2M PHY ARM Cortex M3, 48 MHz LPDSP32( ) : V (1.25 V VBAT):,IO :50 na,8 kb RAM ( ):300 na 7 khz : 1.8 ma RX,1.8 ma TX (3 V VBAT):,IO :25 na,8 kb RAM ( ):100 na 7 khz :0.9 ma RX,0.9 ma TX 384 kb (SoC) FOTA (Firmware Over The Air, ) AWLYYWWG (QFN48) WLCSP51 CASE 567MT XXXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot Y or YY = Year WW = Work Week G or = Pb Free Package Device Package Shipping NCH 101WC51 ABG NCH 101Q48 ABG (Note 1) 1 ORDERING INFORMATION WLCSP51 (Pb Free) QFN48 (Pb Free) 5000 / Tape & Reel 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 48 QFN48 CASE 485BA AWLYWW (WLCSP51) 1. QFN48 version: production ready: July 2017 Semiconductor Components Industries, LLC, 2016 August, 2017 Rev. 1 1 Publication Order Number: CN/D

2 ARM Cortex M3 :32,, LPDSP32:32 Harvard DSP,, : 2.4 GHz,RFFE : 5, 2 Mbps, SoC: RAM DMA, :,, : IO, 50 na (1.25 V VBAT) 32 khz, 90 na (1.25 V VBAT), 8 kb RAM, 300 na (1.25 V VBAT) IO,, (VBAT ) :,, 30 A : LPDSP32 ARM Cortex M3, :,VBAT V :I 2 C UART SPI PCM GPIO (ASRC), RTC :, XTAL/PLL 48 MHz /, 48 MHz XTAL RC 32 khz RTC (32 khz) XTAL RC : 76 kb SRAM 88 kb SRAM 384 kb, ARM Cortex M3 SRAM / IP :, : :IDD < 1.8 VBAT 1.25 V (Rx ),, 7 khz SPI :IDD 1.3 A, 5 (VBAT 3 V,DCDC ) : ARM Cortex M3 Eclipse (IDE) Synopsys ( ) LPDSP32 RoHS 2

3 1 RF Power Management Radio PHY Battery Timers DMA Baseband controller Bluetooth 5 (LE 2M) and custom protocol IP Protection XTAL_32 khz LPDSP32 32 bit Dual Harvard core JTAG XTAL_48 MHz ADC (4x) Oscillators ADC RAMs and Flash Bus Arbiters ARM Cortex -M3 Processor SWJ DP Sample Rate Converter Audio Sink Clock Counters Interfaces I2C SPI (2x) PCM PWM (2x) DMIC (2x) OD UART GPIO Figure 1. Block Diagram Table 1. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Unit VBAT Power supply voltage 3.63 V VDDO I/O supply voltage 3.63 V VSSRF RF front end ground 0.3 V Analog ground 0.3 V VSSD Digital core and I/O ground 0.3 V Vin Voltage at any input pin VSSD 0.3 VDDC V T functional Functional temperature range C T storage Storage temperature range C Caution: Class 2 ESD Sensitivity, JESD22 A114 B (2000 V) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ( ),,,, Table 2. RECOMMENDED OPERATING CONDITIONS Description Symbol Conditions Min Typ Max Units Supply voltage operating range VBAT Input supply voltage on VBAT pin V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. :,, 3

4 Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS Unless otherwise noted, the specifications mentioned in the table below are valid at 25 C at VBAT = VDDO = 1.25 V. Description Symbol Conditions Min Typ Max Units OVERALL Current consumption RX, V BAT = 1.25 V Current consumption TX, V BAT = 1.25 V Deep sleep current, example 1, V BAT = 1.25 V Deep sleep current, example 2, V BAT = 1.25 V Deep sleep current, example 3, V BAT = 1.25 V Standby Mode current, V BAT = 1.25 V Current consumption RX, V BAT = 3 V Current consumption TX, V BAT = 3 V Deep sleep current, example 1, V BAT = 3 V Deep sleep current, example 2, V BAT = 3 V Deep sleep current, example 3, V BAT = 3 V Standby Mode current, V BAT = 3 V I VBAT RX Mode, ON Semiconductor proprietary audio streaming protocol at 7 khz audio BW, 5.5 ms delay. 1.8 ma I VBAT TX Mode, ON Semiconductor proprietary 1.8 ma audio streaming protocol at 7 khz audio BW, 5.5 ms delay. Ids1 Wake up from wake up pin. 50 na Ids2 Ids3 Embedded 32 khz oscillator running with interrupts from timer or external pin. As Ids2 but with 8 kb RAM data retention. 90 na 300 na Istb Digital blocks and memories are not clocked and are powered at a reduced voltage. 30 A I VBAT RX Mode, ON Semiconductor proprietary 0.9 ma audio streaming protocol at 7 khz audio BW, 5.5 ms delay. I VBAT TX Mode, ON Semiconductor proprietary 0.9 ma audio streaming protocol at 7 khz audio BW, 5.5 ms delay. Ids1 Wake up form wake up pin. 25 na Ids2 Ids3 Istb Embedded 32 khz oscillator running with interrupts from timer or external pin. As Ids2 but with 8 kb RAM data retention. Digital blocks and memories are not clocked and are powered at a reduced voltage. EEMBC CoreMark BENCHMARK for the ARM Cortex M3 Processor and the LPDSP32 DSP ARM Cortex M3 processor running from RAM LPDSP32 running from RAM ARM Cortex M3 processor and LPDSP32 running from RAM, VBAT = 1.25 V ARM Cortex M3 processor and LPDSP32 running from RAM, VBAT = 3 V At 48 MHz SYSCLK Using the IAR C compiler At 48 MHz SYSCLK Using the release of the Synopsys LPDSP32 C compiler 40 na 100 na 17 A Core Mark Core Mark At 48 MHz SYSCLK Core Mark/ ma At 48 MHz SYSCLK Core Mark/ ma INTERNALLY GENERATED VDDC: Digital Block Supply Voltage Supply voltage: operating range VDDC (Note 2) Supply voltage: trimming range VDDC RANGE V Supply voltage: trimming step VDDC STEP 10 mv INTERNALLY GENERATED VDDM: Memories Supply Voltage Supply voltage: operating range VDDM (Note 3) V Supply voltage: trimming range VDDM RANGE V Supply voltage: trimming step VDDM STEP 10 mv INTERNALLY GENERATED VDDRF: Radio Front end supply voltage Supply voltage: operating range VDDRF (Notes 4 and 5) V V 4

5 Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS Unless otherwise noted, the specifications mentioned in the table below are valid at 25 C at VBAT = VDDO = 1.25 V. Description Symbol Conditions Min Typ INTERNALLY GENERATED VDDRF: Radio Front end supply voltage Supply voltage: trimming range VDDRF RANGE V Supply voltage: trimming step VDDRF STEP 10 mv INTERNALLY GENERATED VDDPA: Optional Radio Power Amplifier Supply Voltage Supply voltage: operating range VDDPA V Supply voltage: trimming range VDDPA RANGE V Supply voltage: trimming step VDDPA STEP 10 mv Supply voltage: trimming step DCDC STEP 10 mv VDDO PAD SUPPLY VOLTAGE: Digital Level High Voltage Digital I/O supply VDDO V BAT V INDUCTIVE BUCK DC DC CONVERTER VBAT range when the DC DC DCDC V converter is active (Note 6) IN_RANGE VBAT range when the LDO is LDO V active IN_RANGE Output voltage: trimming range DCDC V OUT_RANGE Supply voltage: trimming step DCDC STEP 10 mv POWER ON RESET POR voltage VBAT POR V RADIO FRONT END: General Specifications RF input impedance Z in Single ended 50 Input reflection coefficient S 11 All channels 8 db Data rate FSK / MSK / GFSK R FSK OQPSK as MSK kbps Data rate 4 FSK 4000 kbps On air data rate bps GFSK kbps RADIO FRONT END: Crystal and Clock Specifications Xtal frequency F XTAL Fundamental 48 MHz Equiv. series Res. ESR XTAL Differential equivalent load CL XTAL pf capacitance Settling time ms RADIO FRONT END: Synthesizer Specifications Frequency range F RF Supported carrier frequencies MHz RX frequency step RX Mode frequency synthesizer resolution 100 Hz TX frequency step TX Mode frequency synthesizer resolution Max Units 600 Hz PLL Settling time, RX t PLL_RX RX Mode s PLL Settling time, TX t PLL_TX TX mode, BLE modulation 5 10 s RADIO FRONT END: Receive Mode Specifications Current consumption at 1 Mbps, V BAT = 1.25 V IBAT RFRX VDDRF =1.1 V, 100% duty cycle 5.6 ma Current consumption at 2 Mbps, V BAT = 1.25 V Current consumption at 1 Mbps, V BAT = 3 V, DC DC Current consumption at 2 Mbps, V BAT = 3 V, DC DC IBAT RFRX VDDRF =1.1 V, 100% duty cycle 6.2 ma IBAT RFRX VDDRF =1.1 V, 100% duty cycle 3.0 ma IBAT RFRX VDDRF =1.1 V, 100% duty cycle 3.4 ma RX Sensitivity, 0.25 Mbps 0.1% BER (Note 7) 97 dbm 5

6 Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS Unless otherwise noted, the specifications mentioned in the table below are valid at 25 C at VBAT = VDDO = 1.25 V. Description Symbol Conditions Min Typ RADIO FRONT END: Receive Mode Specifications RX Sensitivity, 0.5 Mbps 0.1% BER (Note 7) 96 dbm RX Sensitivity, 1 Mbps, BLE 0.1% BER (Note 7) Single ended on chip antenna match to dbm RX Sensitivity, 2 Mbps, BLE 0.1% BER (Note 7) 92 dbm RSSI effective range Without AGC 60 db RSSI step size 2.4 db RX AGC range 48 db RX AGC step size Programmable 6 db Max usable signal level 0.1% BER 0 5 dbm RADIO FRONT END: Transmit Mode Specifications Tx peak power consumption at VBAT = 1.25 V (Note 8) Tx peak power consumption at VBAT = 3 V (Note 8) IBAT RFTX Tx power 0 dbm, VDDRF = 1.07 V, VDDPA: off, LDO mode Tx power 3 dbm, VDDRF = 1.1 V, VDDPA = 1.26 V, LDO mode Tx power 6 dbm, VDDRF = 1.1 V, VDDPA = 1.65 V, LDO mode IBAT RFTX Tx power 0 dbm, VDDRF = 1.07 V, VDDPA: off, DC DC mode Tx power 3 dbm, VDDRF = 1.1 V, VDDPA = 1.26 V, DC DC mode Tx power 6 dbm, VDDRF = 1.1 V, VDDPA = 1.65V, DC DC mode Max Units 8.9 ma 17.4 ma 25 ma 4.6 ma 8.6 ma 12 ma Transmit power range BLE or OQPSK dbm Transmit power step size Full band. 2 db Transmit power accuracy Tx power 3 dbm. Full band. Relative to the typical value db Tx power 0 dbm. Full band. Relative to the typical value db Power in 2 nd harmonic 0 dbm mode. 50 for Typ value. PT dbm for Max value (Note 9) Power in 3 rd harmonic 0 dbm mode. 50 for Typ value. PT dbm for Max value (Note 9) Power in 4 th harmonic 0 dbm mode. 50 for Typ value. PT dbm for Max value (Note 9) ADC Resolution ADC RES bits Input voltage range ADC RANGE 0 2 V INL ADC INL 2 +2 mv DNL ADC DNL 1 +1 mv Channel sampling frequency ADC CH_SF For the 8 channels sequentially, SLOWCLK = 1 MHz khz 32 khz ON CHIP RC OSCILLATOR Untrimmed Frequency Freq UNTR khz Trimming steps Steps 1.5 % 3 MHz ON CHIP RC OSCILLATOR Untrimmed Frequency Freq UNTR MHz Trimming steps Steps 1.5 % Hi Speed mode Fhi 10 MHz 32 khz ON CHIP CRYSTAL OSCILLATOR (Note 10) Output Frequency Freq 32k Depends on xtal parameters Hz 6

7 Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS Unless otherwise noted, the specifications mentioned in the table below are valid at 25 C at VBAT = VDDO = 1.25 V. Description Symbol Conditions Min Typ 32 khz ON CHIP CRYSTAL OSCILLATOR (Note 10) Startup time 1 3 s Internal load trimming range Steps of 0.4 pf pf External load Capacitance Maximum external capacity allowed (package, routing, etc.) 3.5 pf ESR 100 k Duty Cycle % DC CHARACTERISTICS OF THE DIGITAL PADS With VDDO = 2.97 V 3.3 V, nominal: 3.0 V Logic Voltage level for high input V IH 2 VDDO+0.3 V Voltage level for low input V IL VSSD V DC CHARACTERISTICS OF THE DIGITAL PADS With VDDO = 1.1 V 1.32 V, nominal: 1.2 V Logic Voltage level for high Input V IH 0.65* VDDO Voltage level for low input V IL VSSD 0.3 Max VDDO+0.3 Units V 0.35* VDDO V DIO DRIVE STRENGTH DIO drive strength IDIO ma FLASH SPECIFICATIONS Endurance of the 384 kb of flash 100,000 write/ erase cycles Endurance for sections NVR1, NVR2, and NVR3 (6 kb in total) 1000 write/ erase cycles Retention 25 years 2. The maximum VDDC voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter. 3. The maximum VDDM voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter. 4. The maximum VDDRF voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter. 5. The VDDRF calibrated targets are: 1.10 V (TX power > 0 dbm, with optimal RX sensitivity) 1.07 V (TX power = 0 dbm) 1.26 V (TX power = 3 dbm) The VDDPA calibrated targets are: 1.30 V 1.26 V (TX power = 3 dbm, assumes VDDRF = 1.10 V) 1.65 V (TX power = 6 dbm, assumes VDDRF = 1.10 V) 6. The LDO can be used to regulate down from VBAT and generate VCC. For VBAT values higher than 1.5 V, the LDO is less efficient and it is possible to save power by activating the DC DC converter to generate VCC. 7. Signal generated by RF tester 8. All values are based on evaluation board performance at the antenna connector, including the harmonic filter loss 9. Harmonics need to be filtered with an external filter (See RF Filter on Table 5). 10. These specifications have been validated with the Epson Toyocom MC 306 crystal Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. ( ),, 7

8 Table 4. RECOMMENDED VDDC and VDDM LEVEL Operating Frequency (MHz) Minimum VDDC Voltage (V) VDDM Voltage (V) Restriction The ADC will be functional in low frequency mode and between 0 and 85 C only None None NOTE: The VDDC and VDDM regulators have to be trimmed at least 10 mv above the minimum voltages indicated in Table 4. Table 5. RECOMMENDED EXTERNAL COMPONENTS Components Function Recommended typical value Tolerance Cap (VBAT ) VBAT decoupling 4.7 F +100 nf pf (Note 11) ±20% Cap (VDDO VSSD) VDDO decoupling 1 F ±20% Cap (VDDRF VSSRF) VDDRF decoupling 2.2 F ±20% Cap (VCC ) VCC decoupling Low ESR 2.2 F (Note 12) or 4.7 F ±20% Cap (VDDA ) VDDA decoupling 1 F ±20% Cap (CAP0 CAP1) Pump capacitor for the charge pump 1 F ±20% Inductor (DC DC) DC DC converter inductance Low ESR 2.2 H (See Table 6 below) ±20% Xtal_32 khz Xtal for 32 khz oscillator MC 306, Epson CM8V T1A, Micro Crystal Switzerland Xtal_48 MHz Xtal for 48 MHz oscillator 8Q MEEV T, TXC Corporation, Taiwan RF filter External harmonic filter 1.5 pf / 3 nh / 1.5 pf / 1.8 nh ±20% NOTE: All capacitors used must have good RF performance. 11. The recommended decoupling capacitance uses 3 capacitors with the values specified 12. Example: AMK105BJ225_P, Taiyo Yuden Table 6. RECOMMENDED DC DC CONVERTER INDUCTANCE TABLE Manufacturer Part Number Case Size Comments Taiyo Yuden CKP2012N_2R SMD with T max = 1.0 mm Taiyo Yuden CBMF1608T2R2M 0603 SMD with T max = 1.0 mm NOTE: Values have been measured on the QFN version of the development board. A degradation of 1 db in the RX sensitivity is expected in DC DC mode (Vbat = 3.3 V) versus LDO mode operation. A degradation of <1 db in RX sensitivity is expected in DC DC mode (Vbat = 3.3 V) versus LDO mode operation. Also, the current drawn from the battery will be 4 10% higher than when the CKP2012N_2R2 is used depending on operation mode and settings. PCB PCB, 6. PCB,, 7.,, ( PCB ) DC DC DC DC RX : PCB, 8

9 Table 7. BUMP AND COATING SPECIFICATIONS Subject Bump metallization Sn 97.7%/Ag 2.3% Backside coating specification Lintec Adwill LC2850 Backside coating thickness 25 m Specification V 4.7uF 100nF 100pF 4.7uF 2.2uH 2.2uF 1uF 1uF VBAT VBAT VCC VDC VDDRF VDDA Cpump 1uF cap1 cap0 VDDM VDDC VSSD VDDO 1.8nH 1.5pF 3nH RF 1.5pF XTAL48_P XTAL32k_IN XTAL48_N XTAL32k_OUT VSS VSSRF VSSPA VSSD VDDSYN_SW VDDRF_SW Figure 2. Application Diagram, 3.3 V 1.25V 4.7uF 100nF 100pF 4.7uF 2.2uF 1uF 1uF VBAT VBAT VCC VDDRF VDDA Cpump 1uF cap1 cap0 VDDM VDDC VSSD VDDO 1.8nH 1.5pF 3nH RF 1.5pF XTAL48_P XTAL32k_IN XTAL48_N XTAL32k_OUT NOTE: DC DC inductance is not needed. should be configured in LDO mode and the DC DC converter should not be used. VSS VSSRF VSSPA VSSD VDDRF_SW VDDSYN_SW Figure 3. Application Diagram, 1.25 V 9

10 Table 8. CHIP INTERFACE SPECIFICATIONS Pad Name Description Power Domain I/O A/D Pull Pad #, WLCSP VBAT Battery input voltage VBAT I P K5,K7,K10 9 VDC DC DC output voltage to external LC filter O A J11 10 VCC DC DC filtered output I P/A K11 12 XTAL32_IN Xtal input pin for 32 khz xtal I/O A L10 14 XTAL32_OUT Xtal output pin for 32 khz xtal I/O A L11 13 Analog ground I/O P E10 8 RES RESERVED I D D F8 11 VDDA Charge pump output for analog and flash supplies VDDA I/O P/A F11 5 VDDRF LDO s output for radio voltage supply I/O P/A A11 48 CAP0 Pump capacitor connection O A H11 7 CAP1 Pump capacitor connection O A G10 6 AOUT Analog test pin O A L6 4 VDDRF_SW Supply pin for the RF VDDRF_SW P/A A9 47 VDDSYN_SW Supply pin for the radio synthesizer P/A B8 45 VSSRF RF analog ground I/O P B9 46 XTAL48_N Negative input for the 48 MHz xtal block I/O A A6 43 XTAL48_P Positive input for the 48 MHz xtal block I/O A A8 44 VDDPA Radio power amplifier voltage supply VDDPA I/O P/A C11 2 VSSPA Radio power amplifier ground I/O P D11 3 RF RF signal input/output (Antenna) RF I/O A B11 1 VPP Flash high voltage access VPP I/O A J6 17 Pad #, QFN48 10

11 Table 8. CHIP INTERFACE SPECIFICATIONS Pad Name Description Power Domain I/O A/D Pull Pad #, WLCSP NRESET Reset pin VDDO I D U L9 16 WAKEUP Wake up pin for power modes I A L8 15 VDDC LDO output for Core logic voltage supply I/O P H6 19 VDDM LDO output for memories voltage supply I/O P F4 21 VDDO Digital I/O voltage supply I P B4 36 Pad #, QFN48 VSSD Digital ground pad for I/O I/O P F3, D6, F9 28, 35 VSS (*) Substrate connection for the RF part I/O P B6 42 EXTCLK External clock input / Internal clock output I/O D U F1 31 DIO[0] Digital input output / ADC 0 I/O A/D U/D L4 18 DIO[1] Digital input output / ADC 1 I/O A/D U/D L3 20 DIO[2] Digital input output / ADC 2 I/O A/D U/D L2 23 DIO[3] Digital input output / ADC 3 I/O A/D U/D L1 25 DIO[4] Digital input output 4 I/O D U/D K2 24 DIO[5] Digital input output 5 I/O D U/D K1 27 DIO[6] Digital input output 6 I/O D U/D J1 29 DIO[7] Digital input output 7 I/O D U/D H1 30 DIO[8] Digital input output 8 I/O D U/D G2 26 DIO[9] Digital input output 9 I/O D U/D E2 22 DIO[10] Digital input output 10 I/O D U/D D1 32 DIO[11] Digital input output 11 I/O D U/D B2 38 DIO[12] Digital input output 12 I/O D U/D A1 37 DIO[13] Digital input output / CM3 JTAG Test Reset I/O D U/D A2 39 DIO[14] Digital input output / CM3 JTAG Test Data In I/O D U/D A3 41 DIO[15] Digital input output / CM3 JTAG Test Data Out I/O D U/D A4 40 JTCK CM3 JTAG Test Clock I/O D U C1 33 JTMS CM3 JTAG Test Mode State I/O D U B1 34 *VSS should be connected to VSSRF at the PCB level. NOTE: It is recommended that the QFN package metal slug be left open/floating for optimal Rx sensitivity performance Legend: Type: A = analog; D = digital; I = input; O = output; P = power Pull: U = pull up; D = pull down Pull up: selectable between 10 k and 250 k Pull down: 250 k All digital pads have a Schmitt trigger input. All DIO pads have a programmable I 2 C low pass filter. 11

12 4 RF front end SPI interface APB bridge ACS bridge Baseband controller SPI[0:1] Arbiter PCM UART BB_DRAM0 BB_DRAM1 I 2 C Audio Sink Clock Counters DIO & GPIO PBus bridge PBus DSS DMA 8 channels LPDSP32 JTAG Loop Cache PMEM DMEM0 DMEM1 NVIC Watchdog TIMER[0:3] Processor access DSP access Command Generator DMA access Interrupt Controller ARM Cortex M3 Processor Arbiter CRC System Control JTAG DRAM0 DBus IBus DRAM1 DRAM2 PROM 4KB 40 32/40 DMA BUS Arbiter DMIC 32/40 ASRC 32 ACS Arbiter SBus BB access DSP_DRAM0 DSP_DRAM1 DSP_DRAM2 DSP_DRAM3 DSP_DRAM4 DSP_DRAM5 Loop Cache 32 Arbiter 40 PRAM3 PRAM2 Flash Copier CBus DSP_PRAM0 10 KB DSP_PRAM1 10 KB DSP_PRAM2 10 KB DSP_PRAM3 10 KB PRAM1 PRAM0 ECC Flash KB Figure 4. Architecture 12

13 , : 1.,, 2., 3., 1.4 V, DC DC,, VBAT 1.4 V, LDO DC DC LDO : (VDDC) (VDDM) (VDDA) (VDDRF) (VDDPA) : +6 dbm, +3 dbm 1.4 V, VDDPA, VDDRF (SYSCLK) : 48 MHz, RC, 3 12 MHz,,, : 32 khz RC 32 khz DIO0 DIO3 JTAG,, JTCK, EXTCLK,,, / RTC, IC 2kHz, 2.4 GHz 2.4 GHz ISM ( GHz) : 5, LE 2M PHY, : IEEE ,, ZigBee Thread 2.4 GHz, : 50 LNA ( ) +3 dbm PA ( ), OQPSK, +6 dbm, PA ADC RSSI ( ), 60 db, 2.4 db ( AGC),, ( ) 48 MHz XTAL ( ) FSK, (DBB), CRC Rx Tx 128 FIFO 2.4 GHz : IEEE GHz ( ), OQPSK DSSS, 62.5 kbps 2 Mbps FSK 2.4 GHz IEEE : CRC, CRC 2x 128 FIFO 13

14 , (DTM), 5, LE 2 Mbps :,,,,,, ARM Cortex M3 IP, 5 Find me Heart rate SMP Application Glucose Mon. Blood Pres. GAP, GATT L2CAP Rezence Link layer Baseband + RF Front-End HID ATT... Figure 5. Bluetooth Protocol Implementation Software Stack, HID over GATT (HOG) Rezence (AirFuel Alliance, ) ARM Cortex M3 ARM Cortex M3 ARM Cortex M3,,, ARM Cortex M3 ARM Cortex M3 32, ALU, C, ARM v7 M,,, (NVIC), LPDSP32 LPDSP32 32 DSP, C LPDSP32 Harvard DSP, (32 ) (64 ) LPDSP32 MAC, : 72 ALU, 32 / 64, 8 ( ) LPDSP32 ( ) : 16 khz, 7 khz ( SBC G.722 msbc ) 24 khz, 11 khz ( OPUS G.722 CELT ) ARM Cortex M3 C, Synopsys 14

15 : SPI, PCM I 2 C UART PWM ( ), (DMIC), ARM Cortex M3 SWJ DP LPDSP32 JTAG 16 DIO ( / ),, DIO : DMA ( ),,, SRAM, CRC (ADC), ARM Cortex M3 ADC 4 (DIO[0] DIO[3]) AOUT VDDC VBAT/2 ADC (CRC), (ASRC),, 32, ARM Cortex M3 LPDSP32 IP,,,, RAM 9, Table 9. MEMORY STRUCTURES Memory type Data Width Memory Size Accessed by Program memory (ROM) 32 4 kb ARM Cortex M3 processor Program memory (RAM) 32 4 instances of 8 kb ARM Cortex M3 processor Program memory (RAM) 40 4 instances of 10 kb LPDSP32 / ARM Cortex M3 processor Data memory (RAM) 32 1 instances of 8 kb ARM Cortex M3 processor Data memory (RAM) 32 2 instances of 8 kb ARM Cortex M3 processor / LPDSP32 Data memory (RAM) 32 6 instances of 8 kb LPDSP32 / ARM Cortex M3 processor Data memory (RAM) 32 2 instances of 8 kb Baseband / ARM Cortex M3 processor Flash kb ARM Cortex M3 processor / Flash copier, : :0x09 :0x01 :0x01 (ESD) :ESD ESD,,, dsp.support@onsemi.com 15

16 PACKAGE DIMENSIONS 2X 2X PIN ONE LOCATION NOTE C 0.10 C 0.10 C 0.08 C DETAIL A 13 D ÉÉÉÉ ÉÉÉÉ TOP VIEW DETAIL B SIDE VIEW D2 A B E A (A3) A1 K C L1 QFN48 6x6, 0.4P CASE 485BA ISSUE A SEATING PLANE DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS EXPOSED Cu L ÉÉÉ MOLD CMPD DETAIL B ALTERNATE CONSTRUCTION L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A A A REF b D 6.00 BSC D E 6.00 BSC E e 0.40 BSC K 0.20 MIN L L SOLDERING FOOTPRINT* X E2 48X L e e/2 BOTTOM VIEW 48X b 0.07 C A B 0.05 C NOTE 3 PKG OUTLINE 0.40 PITCH 48X 0.25 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 16

17 PACKAGE DIMENSIONS WLCSP51, 2.364x2.325 CASE 567MT ISSUE A 2X PIN A1 REFERENCE 2X 0.05 C 0.05 C 0.08 C ÈÈ E TOP VIEW A3 A B D A A2 A1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. 4. PACKAGE CENTER AND FOOTPRINT CENTER ARE NOT COINCIDENT. REFER TO DIMENSION F FOR OFFSETS. MILLIMETERS DIM MIN NOM MAX A A A A b D BSC E BSC e BSC F BSC NOTE 3 51X 0.03 C b 0.05 C A B 0.03 C L K J H F D C B A G E SIDE VIEW F e/2 e C e e/2 SEATING PLANE NOTE 4 RECOMMENDED SOLDERING FOOTPRINT* A PITCH PITCH 51X 0.10 DIMENSIONS: MILLIMETERS BOTTOM VIEW *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 17

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