LC709203FCN - 智能电量计电池电量计LSI(适用于单节锂离子/聚合物电池(Li+))

Transcription

1 LSI ( / (Li+)) LC709203F /, (HG CVR) RSOC ( ) HG CVR, RSOC, ( ) RSOC LC709203F, PCB HG CVR 2.8% RSOC RSOC 3 A ±7.5 mv ±3.5% RSOC / I 2 C I 2 C ( 400 khz) / BFR, RoHS /PDA MP3 USB 1 WDFN8 CASE 509AF WLCSP9 CASE 567JH MARKING DIAGRAMS WDFN8 9203F ** ASWLYW 9203F** = Specific Device Code ** = 01 (LC709203FQH 01TWG) 02 (LC709203FQH 02TWG) 03 (LC709203FQH 03TWG) 04 (LC709203FQH 04TWG) AS = Assembly Location WL = Lot Number YW = Work Week = Pb Free Package (Note: Microdot may be in either location) WLCSP9 203** YMXXX 203** = Specific Device Code ** = 01 (LC709203FXE 01MH) 02 (LC709203FXE 02MH) 03 (LC709203FXE 03MH) 04 (LC709203FXE 04MH) 05 (LC709203FXE 05MH) Y = Year M = Month Code XXX = Lot Number ORDERING INFORMATION See detailed ordering and shipping information on page 19 of this data sheet. Semiconductor Components Industries, LLC, 2015 November, 2018 Rev Publication Order Number: LC709203FCN/D

2 System V DD 10 k 10 k I 2 C Bus V DD Master T Battery Pack SCL SDA T SENSE T SW ASIC LC709203F TEST V SS V DD ALARMB 10 k PACK PACK+ 1 F Interrupt Input V SS System System V SS Figure 1. Example of an Application Schematic using LC709203F (Temperature Input via I 2 C) System V DD 10 k 10 k Battery Pack 10 k Thermistor T k (same as Thermistor Resistance Value) I 2 C Bus V DD Master SCL SDA T SENSE T SW ASIC LC709203F TEST V SS V DD ALARMB 10 k PACK PACK+ 1 F Interrupt Input V SS System System V SS Figure 2. Example of an Application Schematic using LC709203F (The Temperature is Measured Directly by a Thermistor) 2

3 SDA SCL I 2 C Interface ALARMB TEST T SW T SENSE ADC V DD Drv Look Up Table for Internal Battery Impedance & OCV Processing Unit V DD V SS Voltage Sense Timer Reference Voltage Power On Reset Figure 3. Simplified Block Diagram WDFN8 3x4, 065P Pb-Free, Halogen Free Type (Top View) WLCSP9 1.60x1.76 Pb-Free, Halogen Free Type (Bottom View) SCL SDA T SENSE T SW C T SENSE 3B T SW 3A V DD LC709203F 2C 2B 2A SCL NC ALARMB C 1B 1A SDA TEST V SS TEST V SS V DD ALARMB Figure 4. Pin Assignment 3

4 Table 1. PIN FUNCTION WDFN8 WLP9 Pin Name I/O Description 1 1B TEST I Connect this pin to V SS. 2 1A V SS Connect this pin to the battery s negative ( ) pin. 3 3A V DD Connect this pin to the battery s positive (+) pin. 4 2A ALARMB O This pin indicates alarm by low output(open drain). Pull-up must be done externally. Alarm conditions are specified by registers (0x13 or 0x14). Connect this pin to V SS when not in use. 5 3B T SW O Power supply output for thermistor. This pin goes HIGH during temperature read operation. Resistance value of TSW (for thermistor pull-up) must be the same value as the thermistor. (Note 1) 6 3C T SENSE I Thermistor sense input. If you connect this pin to thermistor, insert 100 resistance between them for ESD. (Note 1) 7 1C SDA I/O I 2 C Data pin (open drain). Pull-up must be done externally. 8 2C SCL I/O I 2 C Clock pin (open drain). Pull-up must be done externally. 2B NC Don t care. 1. T SW and T SENSE must be disconnected as Figure 1 when not in use. Table 2. ABSOLUTE MAXIMUM RATINGS (T A = 25 C, V SS = 0 V) Parameter Symbol Pin/Remarks Conditions V DD (V) Specification Min Typ Max Maximum Supply Voltage V DD max V DD V Input Voltage V I (1) T SENSE 0.3 V DD Output Voltage V o (1) T SW 0.3 V DD V o (2) ALARMB 0.3 Input/Output Voltage V IO (1) SDA, SCL Allowable Power Dissipation P d max WDFN8 T A = 40 to 480 mw WLP9 +85 C 210 Operating Ambient Temperature T opr C Storage Ambient Temperature T stg Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ( ),,,, Unit Table 3. ALLOWABLE OPERATING CONDITIONS (T A = 40 to +85 C, V SS = 0 V) Parameter Symbol Pin/Remarks Conditions V DD (V) Specification Min Typ Max Operating Supply Voltage V DD (1) V DD V High Level Input Voltage V IH (1) T SENSE 2.5 to V DD V DD V IH (2) ALARMB, SDA, SCL 2.5 to Low Level Input Voltage V IL (1) T SENSE 2.5 to 4.5 V SS 0.25 V DD V IL (2) ALARMB, SDA, SCL 2.5 to Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. :,, Unit 4

5 Table 4. ELECTRICAL CHARACTERISTICS (T A = 40 to +85 C, V SS = 0 V) Parameter Symbol Pin/Remarks Conditions V DD (V) High Level Input Current I IH (1) SDA, SCL V IN = V DD (including output transistor off leakage current) Low Level Input Current I IL (1) SDA, SCL V IN = V SS (including output transistor off leakage current) Specification Min Typ Max Unit 2.5 to A 2.5 to High Level Output Voltage V OH (1) T SW I OH = 0.4 ma 3.0 to 4.5 V DD 0.4 V V OH (2) I OH = 0.2 ma 2.5 to 4.5 V DD 0.4 Low Level Output Voltage V OL (1) T SW, I OL = 3.0 ma 3.0 to ALARMB, V OL (2) SDA, SCL I OL = 1.3 ma 2.5 to Hysteresis Voltage VHYS(1) SDA, SCL 2.5 to V DD Pin Capacitance CP All pins Pins other than the pin under test V IN = V SS T A = 25 C Reset Release Voltage (Note 2) 2.5 to pf V RR V DD 2.4 V Initialization Time after Reset Release (Note 2) T INIT 2.4 to ms Auto Sleep Set Time T ATS 2.4 to s Time Measurement Accuracy T ME T A = 20 C to +70 C 2.5 to % Consumption Current (Note 3) Voltage Measurement Accuracy I DD (1) V DD Operational mode 2.5 to A I DD (2) Sleep mode 2.5 to V ME (1) V DD T A = +25 C mv/cell V ME (2) T A = 20 C to +70 C 2.5 to Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. ( ),, 2. Once V DD voltage exceeds over the V RR, this LSI will release RESET status. And the LSI goes into Sleep mode T INIT after it. 3. Consumption current is a value in the range of 20 C to +70 C. 5

6 Table 5. I 2 C SLAVE CHARACTERISTICS (T A = 40 to +85 C, V SS = 0 V) Parameter Symbol Pin/Remarks Conditions V DD (V) Clock Frequency T SCL SCL Bus Free Time between STOP condition and START condition Specification Min Max Unit 400 khz T BUF SCL, SDA (See Figure 5) 1.3 s Hold Time (repeated) START condition. First clock pulse is generated after this interval T HD:STA SCL, SDA (See Figure 5) 0.6 s Repeated START Condition Setup Time T SU:STA SCL, SDA (See Figure 5) 0.6 s STOP Condition Setup Time T SU:STO SCL, SDA (See Figure 5) 0.6 s Data Hold Time T HD:DAT SCL, SDA (See Figure 5) s Data Setup Time T SU:DAT SCL, SDA (See Figure 5) 100 ns Clock Low Period T LOW SCL (See Figure 5) 2.5 to s Clock High Period T HIGH SCL (See Figure 5) 0.6 s Clock/Data Fall Time T F SCL, SDA C B 300 ns Clock/Data Rise Time T R SCL, SDA C B 300 ns Time-out Interval (Notes 4, 5) T TMO SCL, SDA (See Figure 6) 9 11 s Wake Up Time from Sleep Mode T WU SDA (See Figure 7) 400 s SDA Low Pulse Width to Wake Up T SP SDA (See Figure 7) 0.6 s Wake Up Retention Time from the Falling Edge of SDA T WR1 SDA (See Figure 7) 500 ms Wake Up Retention Time from STOP Condition T WR2 SCL, SDA (See Figure 7) 500 ms 4. This LSI resets I 2 C communication if the communication takes more than T TMO. It initializes an internal timer to measure the interval when it detects ninth clock pulse. It can receive a new START condition after the reset. 5. This LSI may lose I 2 C communication at this reset operation. Then if a master can t receive a response it must restart transaction from START condition. T BUF SDA T HD;STA T R T LOW T HD;DAT T HIGH T SU;DAT T SU;STA T F T SU;STO SCL P S Figure 5. I 2 C Timing Diagram S P SDA T TMO SCL S ACK Figure 6. I 2 C Time-out Interval ACK 6

7 I 2 C Communication protocol type: I 2 C Frequency: Supported up to 400 khz IC address [Slave Address]: 0x16 (It becomes X when you write a binary, because the slave address is 7 bits. [X] = Rd/Wr.) This LSI will stretch the clock. Bus Protocols S : Start Condition Sr : Repeated Start Condition Rd : Read (bit value of 1) Wr : Write (bit value of 0) A : ACK (bit value of 0) N : NACK (bit value of 1) P : Stop Condition CRC 8 : Slave Address to Last Data (CRC 8 ATM : ex.3778 mv : 0x16, 0x09, 0x17, 0xC2, 0x0E 0x86) : Master-to-Slave : Slave-to-Master : Continuation of protocol Read Word Protocol S Slave Address Wr A Command Code A Sr Slave Address Rd A Data Byte Low A Data Byte High A CRC 8 N P * When you do not read CRC 8, there is not the reliability of data. CRC 8 ATM ex: (5 bytes) 0x16, 0x09, 0x17, 0xC2, 0x0E 0x86 Write Word Protocol S Slave Address Wr A Command Code A Data Byte Low A Data Byte High A CRC 8 A P * When you do not add CRC 8, the Written data (Data byte Low/High) become invalid. CRC 8 ATM ex: (4 bytes) 0x16, 0x09, 0x55, 0xAA 0x3B 7

8 TPS Disable I 2 C Communication Sleep Mode Enable I 2 C Communication Disable I 2 C Communication SDA TWU TWR1 (Not to Scale) Sleep Mode Enable I 2 C Communication Disable I 2 C Communication SCL TWR2 SDA (Not to Scale) STOP Condition Figure 7. I 2 C Wake up Timing Diagram, I 2 C, SDA, I 2 C LSI TWU I 2 C, DA,, 1. TWR1 ( SDA ), LSI I 2 C,, TWR2 ( ) 2. TWR2 ( I 2 C Bus ) LSI, SDA,, I 2 C, I 2 C, I 2 C I 2 C ( LSI ), I 2 C, LSI 8

9 Table 6. FUNCTION OF REGISTERS Command Code Register Name R/W Range Unit Description 0x04 Before RSOC W 0xAA55: Initialize RSOC Executes RSOC initialization with sampled maximum voltage when 0xAA55 is set. 0x06 Thermistor B R/W 0x0000 to 0xFFFF 1K Sets B constant of the thermistor to be measured. 0x07 Initial RSOC W 0xAA55: Initialize RSOC Executes RSOC initialization when 0xAA55 is set. Initial Value 0x0D34 0x08 Cell Temperature R 0x0000 to 0xFFFF 0.1K W 0x09E4 to 0x0D04 (I 2 C mode) (0.0 C = 0x0AAC) Displays Cell Temperature Sets Cell Temperature in I 2 C mode 0x0BA6 (25 C) 0x09 Cell Voltage R 0x0000 to 0xFFFF 1 mv Displays Cell Voltage 0x0A Current Direction R/W 0x0000: Auto mode 0x0001: Charge mode 0xFFFF: Discharge mode Selects Auto/Charge/Discharge mode 0x0000 0x0B 0x0C APA (Adjustment Pack Application) APT (Adjustment Pack Thermistor) R/W 0x0000 to 0x00FF 1 m Sets Parasitic impedance R/W 0x0000 to 0xFFFF Sets a value to adjust temperature measurement delay timing 0x001E 0x0D RSOC R/W 0x0000 to 0x0064 1% Displays RSOC value based on a scale 0x0F ITE (Indicator to Empty) R 0x0000 to 0x03E8 0.1% Displays RSOC value based on a scale 0x11 IC Version R 0x0000 to 0xFFFF Displays an ID number of an IC 0x12 Change Of The Parameter R/W 0x0000 or 0x0001 Selects a battery profile 0x0000 0x13 Alarm Low RSOC R/W 0x0000: Disable 0x0001to0x0064: Threshold 1% Sets RSOC threshold to generate Alarm signal 0x0008 0x14 Alarm Low Cell Voltage R/W 0x0000: Disable 0x0001to0xFFFF: Threshold 1 mv Sets Voltage threshold to generate Alarm signal 0x0000 0x15 IC Power Mode R/W 0x0001: Operational mode 0x0002: Sleep mode Selects Power mode (Note 6) 0x16 Status Bit R/W 0x0000: I 2 C mode 0x0001: Thermistor mode Selects Temperature obtaining method 0x0000 0x1A Number of The Parameter NOTE: 0xXXXX = Hexadecimal notation 6. See Power-on Reset/Battery Insertion Detection and Figure 17. R 0x0301 or 0x0504 Displays Battery profile code Before RSOC (0x04) LSI (OCV) RSOC 0.025C OCV ( 3000 mah 75 ma) LSI RSOC, RSOC, Before RSOC (0x04 = AA55) Initial RSOC (0x07 = AA55) RSOC Before RSOC RSOC ( 9), Thermistor B (0x06) B, 9

10 Initial RSOC (0x07) Before RSOC (0 04 = AA55) Initial RSOC (0 07 = AA55), LSI RSOC Cell Voltage (0x09) V DD ( 1 mv) Current Direction (0x0A) RSOC Auto Mode, RSOC Charge Mode, RSOC Discharge Mode,RSOC, Auto Mode, RSCO Discharge Mode, Charge Mode ; RSOC Figure 8. RSOC Automatic Initialization Figure 10. Initial RSOC Command Figure 9. Before RSOC Command LSI Initial RSOC RSOC ( 10) RSOC 1.5 ms Cell Temperature (0x08) 20 C (0 09E4) +60 C (0 0D04), 0.1 C Thermistor Mode (0 16 = 01),LSI, Thermistor Mode, 2 LSI TSW TSENSE, LSI,, I 2 C Mode (0 16 = 00), /, 1 C, Figure 11. Discharge Mode (An example with increasing in temperature. A warm cell has more capacity than a cold cell. Therefore RSOC increases without charging in Auto mode) 10

11 Table 7. TYPICAL APA Design Capacity of Battery APA(0x0B) Type 01, Type 03 Type 06 Type mah 0x08 0x0D 0x mah 0x0B 0x15 0x0C 500 mah 0x10 0x20 0x mah 0x19 0x mah 0x2D 0x mah 0x36 0x4D Figure 12. Charge Mode (An example with decreasing in temperature. A cold cell has less capacity than a warm cell. Therefore RSOC decreases without discharging in Auto mode) Adjustment Pack Application (0x0B), RSOC 13 7 APA ( 1 ), APA 8 RSOC, APA Design Capacity of Battery Type 04 APA(0x0B) Type mah 0x1A 0x0D Figure 14. An Example of a Capacitor Across the Thermistor Figure 13. Typical APA Adjustment Pack Thermistor (0x0C) 14, RSOC (0x0D) 1% 0% 100% RSOC Operational Mode, RSOC Sleep Mode, ITE(0x0F) Indicator to Empty (0x0F) RSOC, 0.1%, 0.0% 100.0% IC Version (0x11) LSI ID 11

12 Change of the Parameter (0x12) LSI 8 (0x1A), /, Sleep Mode,,RSOC, Operational Mode RSOC, Sleep Mode Operational Mode, Operational Mode RSOC Alarm Low RSOC (0x13) RSOC,ALARMB, RSOC, 15 Figure 16. Alarm Low Cell Voltage Figure 15. Alarm Low RSOC Alarm Low Cell Voltage (0x14) VDD,ALARMB, VDD, 16 IC Power Mode (0x15) LSI Sleep Mode (0x15=02) Operational Mode (0x15=01) Sleep Mode, I 2 C Operational Mode,, RSOC Status Bit (0x16) Thermistor Mode Thermistor Mode (0x16=01),LSI, Cell Temperature I 2 C Mode (0x16=00), Number of the Parameter (0x1A) LSI, Change of the Parameter (0x12) 8,,, 12

13 Table 8. BATTERY PROFILE VS. REGISTER IC Type Battery Type Nominal/Rated Voltage Charging Voltage Design Capacity Number of the Parameter (0x1A) Change of the Parameter (0x12) LC709203Fxx 01xx V 4.35 V 500 mah 0x0301 0x V 4.2 V 0x0001 LC709203Fxx 03xx V 4.35 V < 500 mah 0x0601 0x V 4.2 V 0x0001 LC709203Fxx 04xx 05 ICR H (SAMSUNG) 0x0504 0x UR18650ZY (Panasonic) 0x0001 LC709203Fxx 05xx V 4.4 V 0x0706 0x V 4.35 V < 500 mah 0x0001 HG CVR - HG CVR, RSOC HG CVR LC709203F,, (OCV) OCV OCV, V(VARIED) V(MEASURED) OCV (eq. 1) I V(VARIED) (eq. 2) R(INTERNAL),V( ), V( ),R( ) LSI OCV LSI HG CVR ( ) ( ) /,, (FCC), FCC (RM) RSOC RSOC RM 100% (eq. 3) FCC FCC HG CVR RSOC HG CVR FCC LSI RSOC RSOC FCC RSOC FCC ( 300 /, 80% FCC), HG CVR LSI RSOC, 27,,, HG CVR,,, LC709203F, LSI,,,, 3 A LSI /,,, RSOC / LSI, V RR,, T INIT LSI, I 2 C, T ATS,LC709203FXE 0xMH,, LC709203FQH 0xTW G 17, V RR, LSI, Change of the Parameter (0x12), LSI, 18 13

14 LSI RSOC, V DD /V SS LSI LSI 19,RSOC LC709203F, V DD /V SS,, 20 21,,, LC709203FQH 0xTWG Reset Initialization Operation Mode V DD V RR T INT LC709203FXE 0xMH Reset Initialization Operation Mode Sleep Mode V DD V RR T INT T ATS (Not to Scale) Figure 17. Power On Timing Diagram LC709203FQH 0xTWG SCL 0x12 Command Initialization Operation Mode T INIT SDA Stop Condition LC709203FXE 0xMH 0x12 Command Initialization Operation Mode Sleep Mode SCL T INIT T ATS SDA (Not to Scale) Stop Condition Figure 18. Timing Diagram after 0x12 Command 14

15 Application Application Processor LC709203F Battery or Battery Pack V SS V DD The components that the resistance must be measured. Figure 19. An Example of Parasitic Resistance 15

16 Power On Initial RSOC Set 0xAA55 to Register 0x04 or 0x07 (Note 8) Input SDA Pulse (Note 7) Wake Up from Sleep Mode Set Thermistor Mode Set 0x0001 to Register 0x16 Set 0x0001 to Register 0x15 (Note 7) Set Operational Mode Set B-constant of Thermistor Set 0xZZZZ to Register 0x06 Set 0xZZZZ to Register 0x0B Set APA Initialization End Set 0x000Z to Register 0x12 Set Battery Profile 7. It s unnecessary if initial power mode is Operational mode. SDA pulse can be substituted in some kind of commands. Ex: Input Set Operational mode twice. 8. It s unnecessary if OCV can be get at automatic initialization. Figure 20. Starting Flow at Thermistor Mode Power On Initial RSOC Set 0xAA55 to Register 0x04 or 0x07 (Note 10) Input SDA Pulse (Note 9) Wake Up from Sleep Mode Set via I 2 C Mode Set 0x0000 to Register 0x16 Set 0x0001 to Register 0x15 (Note 9) Set Operational Mode Set Temperature Set 0xZZZZ to Register 0x08 Set 0xZZZZ to Register 0x0B Set APA Initialization End Set 0x000Z to Register 0x12 Set Battery Profile 9. It s unnecessary if initial power mode is Operational mode. SDA pulse can be substituted in some kind of commands. Ex: Input Set Operational mode twice. 10.It s unnecessary if OCV can be get at automatic initialization. Figure 21. Starting Flow at I 2 C Mode 16

17 Figure 22. Discharge Characteristics by Temperature Change Figure 23. Discharge Characteristics by Load Change 17

18 Figure 24. Discharge/Charge Cycle Figure 25. Battery Capacity Deterioration Figure 26. Discharge Characteristics of Deterioration Battery 18

19 Figure 27. Convergent Characteristic from the Initialize Error This Graph is the Example for Starting Point 48% (Includes 52% Error Case) Instead of 100% (No Error) Table 9. ORDERING INFORMATION Device Package Shipping LC709203FQH 01TWG WDFN8 3x4, 0.65P (Pb-Free / Halogen Free) 2,000 / Tape & Reel LC709203FQH 02TWG WDFN8 3x4, 0.65P (Pb-Free / Halogen Free) LC709203FQH 03TWG WDFN8 3x4, 0.65P (Pb-Free / Halogen Free) LC709203FQH 04TWG WDFN8 3x4, 0.65P (Pb-Free / Halogen Free) 2,000 / Tape & Reel 2,000 / Tape & Reel 2,000 / Tape & Reel LC709203FXE 01MH LC709203FXE 02MH LC709203FXE 03MH LC709203FXE 04MH WLCSP9, 1.60x1.76 (Pb-Free / Halogen Free) WLCSP9, 1.60x1.76 (Pb-Free / Halogen Free) WLCSP9, 1.60x1.76 (Pb-Free / Halogen Free) WLCSP9, 1.60x1.76 (Pb-Free / Halogen Free) 5,000 / Tape & Reel 5,000 / Tape & Reel 5,000 / Tape & Reel 5,000 / Tape & Reel LC709203FXE 05MH WLCSP9, 1.60x1.76 (Pb-Free / Halogen Free) 5,000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ( ): IC, ON Semiconductor is licensed by the Philips Corporation to carry the I 2 C bus protocol. All other brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders. 19

20 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS 1 SCALE 2:1 WDFN8 3x4, 0.65P CASE 509AF ISSUE C DATE 06 MAY 2014 PIN ONE REFERENCE 2X 0.10 C 2X 0.10 C 0.10 C D ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ TOP VIEW DETAIL B A B E (A3) A L1 L DETAIL A ALTERNATE CONSTRUCTIONS EXPOSED Cu ÉÉ L MOLD CMPD DETAIL B ALTERNATE CONSTRUCTIONS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL AS THE LEADS. MILLIMETERS DIM MIN MAX A 0.80 A A REF b D 3.00 BSC D E 4.00 BSC E e 0.65 BSC L L GENERIC MARKING DIAGRAM* 0.08 C NOTE 4 DETAIL A 8X L SIDE VIEW D2 1 4 A C A B C SEATING PLANE 0.10 C A B XXXXX XXXXX AYWW A = Assembly Location Y = Year WW = Work Week = Pb Free Package (Note: Microdot may be in either location) 8 5 e/2 e BOTTOM VIEW E2 8X b 0.10 C A B 0.05 C NOTE 3 *This information is generic. Please refer to device data sheet for actual part marking. Pb Free indicator, G or microdot, may or may not be present. RECOMMENDED SOLDERING FOOTPRINT* 1.96 ÇÇÇÇ 8X PITCH ÇÇÇÇ 1 8X 0.35 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: STATUS: NEW STANDARD: Semiconductor Components Industries, LLC, 2002 October, 2002 Rev. 0 DESCRIPTION: 98AON80983E ON SEMICONDUCTOR STANDARD WDFN8 3X4, 0.65P 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped CONTROLLED COPY in red. Case Outline Number: PAGE 1 OF XXX 2

21 DOCUMENT NUMBER: 98AON80983E PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION FROM SANYO ENACT# S 569 TO ON 31 MAY 2012 SEMICONDUCTOR. REQ. BY D. TRUHITTE. A REDREW TO ON/JEDEC STANDARDS. ADDED GENERIC MARKING DIAGRAM. REQ. BY I. CAMBALIZA. B CORRECTED DIMENSION E FROM 3 TO 4MM. CHANGED DIMENSION L TO MM. REQ. BY I. CAMBALIZA. C CORRECTED SOLDER FOOTPRINT TO ADD LENGTH DIMENSION. CHANGED DESCRIPTION TO WDFN8. REQ. BY I CAMBALIZA. 23 JUL OCT MAY 2014 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Semiconductor Components Industries, LLC, 2014 May, 2014 Rev. C Case Outline Number: 509AF

22 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SCALE 4:1 WLCSP9, 1.60x1.76 CASE 567JH ISSUE B DATE 23 JAN X PIN A1 REFERENCE 2X 0.05 C 0.05 C ÈÈ E TOP VIEW A B D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO THE SPHERICAL CROWNS OF THE SOLDER BALLS. MILLIMETERS DIM MIN MAX A 0.51 A b D 1.60 BSC E 1.76 BSC e 0.50 BSC 0.10 C BACKCOAT A RECOMMENDED SOLDERING FOOTPRINT* NOTE C A1 SIDE VIEW C SEATING PLANE A1 PACKAGE OUTLINE 9X b 0.05 C A B 0.03 C C B A BOTTOM VIEW e e 0.50 PITCH 0.50 PITCH 9X 0.25 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: STATUS: NEW STANDARD: Semiconductor Components Industries, LLC, 2002 October, 2002 Rev. 0 DESCRIPTION: 98AON79525F ON SEMICONDUCTOR STANDARD WLCSP9, 1.60X Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped CONTROLLED COPY in red. Case Outline Number: PAGE 1 OF XXX 2

23 DOCUMENT NUMBER: 98AON79525F PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION. REQ. BY I. CAMBALIZA. 28 OCT 2013 A ADDED BACKSIDE COATING OPTION. REQ. BY E. KUROSE. 19 DEC 2013 B UPDATED DIMENSIONS A AND A1. REQ. BY E. KUROSE. 23 JAN 2014 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Semiconductor Components Industries, LLC, 2014 January, 2014 Rev. B Case Outline Number: 567JH

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