Microsoft Word ³¯¨Ø¿·.doc

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6 !! wíã lîû~n ô ß lf Metric functional/code coverage µû bug rate Ùx ÛŽ n ß!! wís Ã lî ~ Šn ß nùl ô ñ 1. ~Ü sq iñ lí vã Verification Component ð v Verification IP VIP n Synopsys Ã CoreAssembler µ Mentor Ã Platform Express }ô ln sqãõx 2. ~ testbench/testcase iñ 2.2 STC ýi}!! wí STC ~ Verification iñãlî ýi }~¹ÍïÃ Ü lîƒ VIP Ã î e Ã v testbench Ã lfv Ü Ã bus composer!! VIP v ß Bus Protocol [9] nùwí Ã bus AMBA PCI USB VIP ÃÜ ole Master Slave «Monitor e eµx v VIP ol î~ protocol iñã µ l v¹ VIP Û BFM bus functional model ~ Öü¹ «õ testbench v Ã HVL, Hardware Verification Language Verisity e language, Synopsys vera, SystemVerilog µû Ã methodology constrained random stimulus Master VIP Slave VIP generation n testbench Ã qr testbench migration Û ¹ iñã 3. ~ ˆ iñ á n Îƒ hardware accelerators Cadence Ã palladium µû FPGA Emulation Aptix Ã System Explorer qr Mentor Ã Seamless ÐÎ ~ hardware/software co-simulation Ãn!! wí ð~ n îûžƒ bug t bug n bug n ~ îãùô e Îj gep ~á eãß t j f wíolvã methodology assertion[7, 8]µÛ tool Novas Ã Verdi ol iñƒµ Monitor VIP e! Verification sqü!! v¹ VIP ~ bus protocol Ã wís ƒ ý VIP Ãep Synopsys[10] Verisity «Denali ep eã VIP Ûl behavior level Ã [11] q v~ workstation Logic simulation Ã ß STC ýã VIP ƒ behavior version r á Ã ~ ý o} ÃÁt vä design VIP testbench ~ FPGA ˆ ol v ¹ Hardware accelerator µä Hardware Emulation SoC Technical Journal!!

7 3.!! IP Qualification Û Ë IP Ð Ãsî Ê me z qƒ}l IP Qualification f IP Ð IP ü¹ } t IP Qualification VSIA IP å e} [12] Digital Hard IP & Digital Soft IP å IP Qualification ð VSIA QIP Metrics AMS IP Software IP {} n v¹ IP ß Ã} IP Quality!! ~ IP Verification iñ wí d~ g Ã epr edt ½ Ãh ~ ôiñ ã ¹ rˆ ƒ Ã þ Verification Engineer ~ d dûv î ø mõz ð Õ [4] Motorola, Semiconductor Reuse Standard V3.0.1, Dec [5] Prakash Rashinkar. SYSTEM-ON-A-CHIP Verification : Methodology and Techniques, February [6] Janick Bergeron. Writing Testbenches : Functional Verification of HDL Models, Second Edition, February, 2003 [7] Harry D. Foster. Assertion-Based Design, June, [8] Verplex. Assertion Based Technology Seminar, February, [9] David Dempster. Verification Methodology Manual : Techniques for verifying HDL Designs, June, [10] FAISAL I. HAQUE. The ART of Verification æ k ý h q with VERA, äãj n SoC Ã ñ Ð t î Ã î fq Á ~{ Ã ç Á ðîã [11] Lionel Bening Principles of verifiable RTL Design, [12] VSIA, Virtual Component Transfer, Version 2.1 VCT 1 2.1, Oct ˆ 4. i Ä d [1] Reuse Methodology Manual RMM, 3rd Edition,M. Keating and P. Bricaud, Kluwer Academic Publishers Group, [2] Synopsys and Mentor Graphics, Open More Measure Of Reuse Excellence Assessment Program, 2000 [3] STARC, Design Style Guide revised version, hd Lab, inc. Apr xy æ µ æ k ý h IP î þ 2003 z IP Qualification ø phchen@itri.org.tw!! k! 001

k x n æ µ æ k ý h IP î þ 2003 z IP Qualification ø E-mail: Bryanwang@itri.org.

8 k x n æ µ æ k ý h IP î þ 2003 z IP Qualification ø Bryanwang@itri.org.tw Ž¼ x æ µ æ k ý h IP î þ 2003 z IP Qualification ø hlwu@itri.org.tw Ì x æ µ æ k ý h IP 2003 z IP Qualification ø jmlu@itri.org.tw SoC Technical Journal!!

Microsoft Word - IV 民用航空法-講義-01~12.doc

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