VHDL (Sequential Logic)
D-Type entity D_FF is D :in std_logic; CLK :in std_logic; Q :out std_logic); end D_FF; architecture a of D_FF is process(clk,d) if CLK'EVENT and CLK = '1' then Q <= D; 2
D-Type entity DFF_SR is nrst :in std_logic; CLK :in std_logic; D :in std_logic; Q :out std_logic); end DFF_SR; architecture a of DFF_SR is process(nrst,clk,d) if CLK'EVENT and CLK = '1' then if nrst = '0' then Q <= '0'; else Q <= D; 3
D-Type entity DFF_AR is nrst :in std_logic; CLK :in std_logic; D :in std_logic; Q :out std_logic); end DFF_AR; architecture a of DFF_AR is process(nrst,clk,d) if nrst = '0' then Q <= '0'; elsif CLK'EVENT and CLK = '1' then Q <= D; 4
D-Type entity DFF_PR is nrst :in std_logic; npreset :in std_logic; CLK :in std_logic; D :in std_logic; Q :out std_logic); end DFF_PR; architecture a of DFF_PR is process(nrst,npreset,clk,d) if nrst = '0' then Q <= '0'; elsif npreset = '0' then Q <= '1'; elsif CLK'EVENT and CLK = '1' then Q <= D; 5
RS-Type entity RS_FF is nrst :in std_logic; nset :in std_logic; Q :out std_logic; nq :out std_logic); end RS_FF; architecture a of RS_FF is signal Q_S: std_logic; signal nq_s: std_logic; Q_S <= nrst nand nq_s; nq_s <= nset nand Q_S; Q <= Q_S; nq <= nq_s; 6
(Negative Level) entity LATCH is nena :in std_logic; D :in std_logic; Q :out std_logic); end LATCH; architecture a of LATCH is signal Q_S: std_logic; process(nena,d) if nena = '0' then Q_S <= D; else Q_S <= Q_S; Q <= Q_S; 7
T- entity TFF is T :in std_logic; CLK :in std_logic; Q_O :out std_logic); end TFF; architecture a of TFF is signal Q: std_logic; process(clk,t) if CLK'EVENT and CLK = '1' then if T = '1' then Q <= not(q); else Q <= Q; Q_O <= Q; 8
2 entity DIV2 is CLK_IN :in std_logic; CLK_OUT :out std_logic); end DIV2; architecture a of DIV2 is signal CLK_2: std_logic; process(clk_in) if CLK_IN'EVENT and CLK_IN = '1' then CLK_2 <= not(clk_2); CLK_OUT <= CLK_2; 9
D- entity DFF_ena is D :in std_logic; CLK :in std_logic; Enable :in std_logic; Q :out std_logic); end DFF_ena; architecture a of DFF_ena is process(clk,d) if CLK'EVENT and CLK = '1' then if Enable = '1' then Q <= D; 10
entity SFT_PIPO is D_IN 0); CLK :in std_logic_vector(7 downto :in std_logic; :out std_logic_vector(7 downto D_OUT 0)); end SFT_PIPO; architecture a of SFT_PIPO is signal Q: std_logic_vector(7 downto 0); process(clk) if CLK'EVENT and CLK = '1' then Q <= D_IN; D_OUT <= Q; 11
entity SFT_PISO is D_IN :in std_logic_vector(7 downto 0); CLK :in std_logic; nload :in std_logic; D_OUT :out std_logic); end SFT_PISO; architecture a of SFT_PISO is signal Q: std_logic_vector(7 downto 0); process(nload,clk) if nload = '0' then Q <= D_IN; elsif CLK'EVENT and CLK = '1' then for I in 7 downto 1 loop Q(I-1) <= Q(I); end loop; process(nload,clk) if nload = '0' then D_OUT <= '0'; elsif CLK'EVENT and CLK = '1' then D_OUT <= Q(0); 12
/ (Serial- In/Parallel-Out) entity SFT_SIPO is D_IN :in std_logic; CLK :in std_logic; D_OUT :out std_logic_vector(7 downto 0)); end SFT_SIPO; architecture a of SFT_SIPO is signal Q: std_logic_vector(7 downto 0); process(clk) if CLK'EVENT and CLK = '1' then Q(0) <= D_IN; for I in 1 to 7 loop Q(I) <= Q(I-1); end loop; D_OUT <= Q; 13
/ (Serial- In/Serial-Out) entity SFT_SISO is D_IN :in std_logic; CLK :in std_logic; D_OUT :out std_logic); end SFT_SISO; architecture a of SFT_SISO is signal Q: std_logic_vector(7 downto 0); process(clk) if CLK'EVENT and CLK = '1' then Q(0) <= D_IN; for I in 1 to 7 loop Q(I) <= Q(I-1); end loop; D_OUT <= Q(7); 14
8 (Ripple Counter) entity rip_cnt8 is nclr :in std_logic; 0)); end rip_cnt8; architecture a of rip_cnt8 is component DIV2_AR CLK :in std_logic; Q_O :out std_logic_vector(7 downto CLK_IN :in std_logic; nclr :in std_logic; CLK_OUT :out std_logic); end component; signal Q: std_logic_vector(7 downto 0); FF1: DIV2_AR port map (CLK,nCLR,Q(0)); FF2_8: for I in 1 to 7 generate T1: DIV2_AR port map (Q(I-1),nCLR,Q(I)); end generate FF2_8; Q_O <= Q; 15
(Up Counter) use ieee.std_logic_unsigned.all; entity UPCNT8 is nclr :in std_logic; CLK :in std_logic; CO :out std_logic; Q_O :out std_logic_vector(7 downto 0)); end UPCNT8; architecture a of UPCNT8 is signal Q: std_logic_vector(7 downto 0); process(nclr,clk) if nclr = '0' then Q <= "00000000"; CO <= '0'; elsif CLK'EVENT and CLK = '1' then if Q = "11111111" then CO <= '1'; else CO <= '0'; Q <= Q + '1'; Q_O <= Q; 16
(Up/Down Counter) use ieee.std_logic_unsigned.all; entity UPDNCNT8 is nclr :in std_logic; CLK :in std_logic; UP_DN :in std_logic; --'1':Up Counter;'0':Down Counter; Q_O :out std_logic_vector(7 downto 0)); end UPDNCNT8; architecture a of UPDNCNT8 is signal Q: std_logic_vector(7 downto 0); process(nclr,clk) if nclr = '0' then Q <= "00000000"; elsif CLK'EVENT and CLK = '1' then if UP_DN = '1' then Q <= Q + '1'; else Q <= Q - '1'; Q_O <= Q; 17
/ (UD/Down Counter With Load) use ieee.std_logic_unsigned.all; entity UDLCNT8 is nclr :in std_logic; CLK :in std_logic; UP_DN :in std_logic; --'1':Up Counter;'0':Down Counter; nload :in std_logic; --Asychronous Load Data; D_IN : in std_logic_vector(7 downto 0); Q_O :out std_logic_vector(7 downto 0)); end UDLCNT8; architecture a of UDLCNT8 is signal Q: std_logic_vector(7 downto 0); process(nclr,clk) if nclr = '0' then Q <= "00000000"; elsif nload = '0' then Q <= D_IN; elsif CLK'EVENT and CLK = '1' then if UP_DN = '1' then Q <= Q + '1'; else Q <= Q - '1'; Q_O <= Q; 18
(State Machine) (Finite State Machine FSM) 2 Moore Mealy Mealy (Glitch) 19
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type STATE_TYPE is (State_A, State_B, ); signal Present_State: STATE_TYPE; signal Next_State: STATE_TYPE; 21
VHDL PROCESS PROCESS : PROCESS PROCESS : PROCESS PROCESS PROCESS PROCESS : PROCESS PROCESS PROCESS 22
Moore 23
Mealy 24
(State Encoding) One-Hot Gray S0 00 0001 00 S1 01 0010 01 S2 10 0100 11 S3 11 1000 10 25
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