Schematic Files-PDF F8TR MB_0M-AS R1.1.pdf

FTr/Z0Z.0 lock iagram FN + ENOR PE 0 M PU PE,,, PU VORE PE 0 R 00-00 ual hannel R O-IMM x PE,, _IN & T ON W & LE YTEM PWR PE 0 PE PE V aughter HT.0.HZ LOK ILPRLFT T & HRER PE HMI RT PE PE TI M PI-E x M R0M R 00MHz PI-E LN RTL PE PE Other PWR PE,,,, 0,,,, RJ,RJ ON PE LV & INV PE PE 0 PE 0,,,,, TV Turner ard PE -LINK Interface PI MHz MINIR WLN PE INTERNL KEYOR TOUH P PE IR PE IO PI ROM PE 0 TPM E ITE/IT PE PE 0, LP MHz zalia M 00 PE 0,,,, Neward/ebugard ardus RIOH R PE 0, PE R REER MI IN HP&PIF OUT PE OPMP PE Internal MI ON PE zalia odec Realtek/L PE,, U.0 ON x PE PE, aughter zalia M Header PE amera U PE ON HP&PIF OUT T O Fingerprint PE U.0 ON x MI IN T H PE luetooth PE PE ET PE PE PE PE UTeK OMPUTER IN. N lock iagram Wing_heng ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

E 0 RN00,RN00 to 00 0 add newcard wake# signal pull up p X00 change to. high remove PJP0 because VU is not neet change LE circuit p del HMI data signal E protect, add HMI E protect RT E protect link to connect prearrange 0ohm resister between O#_O and NV_OVERT# P remove P0 P0 0 remove HP blocking capacitors E00 E0 add PU_THRMTRIP#_.V P add FN0_PWM_R E protect p0 prearrange PU_THRMTRIP# to 00 0 change sata TX serial resister from.k to. add 00 PIO PU P memory swap K cap for 000 add HMI data signal E protect divide TR power from HMI correct smbus of lvds on page add colay and 000 change as word document 000 add R0 add netname:+vu_rein,+vu_rein,ref_mil delete net:+.v_re(pu) change newcard pcie lane from to HNE L00 P/N 00 E-T pin0,pin link to N 000 R0,R0 00 R,Q 00 R,,, FOR Mbus 00 change c0 to uf 00 Q0,R,R 00 change R00 to ohm 00 change fingerprint to usb 00 change pg0 pm_rsmrst# and PM_PWROK sequence 00 add EMI cap on page 0 and page for pci and M/M clk 00 add re-driver for E-T 0 0* FOR EMI 0 R0 FOR EMI 0 REERVE P 0 delete R0/R0/R0 0 add c0 0 add R0 for safety 000 the U and L of LV exchange p change Q to Q0 add R0 0 0 HNE TO PF add R0 R0 R0 L0 L0 L0 from OHM/00M to NH add L L L NF add PF 0 from pf to pf and option change to R00 R0 from 0HM to OHM R0 from 0OHM to 0OHM for R0 0 0 0 from pf to pf del R00 R0 R0 R0 add R0 U0 R0 X X X X option change to N del R0 R0 R0 R0 add R0 00OHM add X X 0pf and X X00.0uf R0 R0 R0 R R R from.ohm to 0OHM 00 R0 optional change to, R0 change to N/ R0 optionsl change to R0 optional change to N/ R0 optional change to N/ 000 add R optional to ON00 part number from 0000 to 00000 add 0 optional to R R optional to / 000 add d0 optional is 000 del IO P R00 R0 R0 PN to 00000000 del R0 del IO_MI# net p del LP_RQ0# net p0 U00 PN to 0000 00 PN to 00 add 00 optonal is 000 add 00 0 R optional to N/ R0, R0, R0, R, R, R, R, R change to 0OHM 0 0 00 0 0 0 change to pf,optional is N/ add 00 optional is 00 add 00 00 optional is add 0 0 optional is UTeK OMPUTER IN. N <Orgddr> ustom Z0Z/FTr Wednesday, March, 00 ate: heet of E 0.

E F H J K L M N P R T U V W Y E F H J K L M N P R T U V W Y E E F H J K L M N P R T U V W Y E F E F H J K L M N P R T U V W Y E F E F H J K L M N P R T U V W Y E F E F H J K L M N P R T U V W Y E F 0 0 0 0 E 0 F 0 H 0 J 0 K 0 L 0 M 0 N 0 P 0 R 0 T 0 U 0 V 0 Y 0 0 0 0 0 E 0 F 0 E F H J K L M N P R T U V Y E F E F H J K L M N P R T U V W Y E F E F H J K L M N P R T U V W Y E F E F H J K L M N P R T U V W Y E F E F H J K L T U V W Y E F E F H J K L T U V W Y E F E F H J K L T U V W Y E F E F H J K L T U V W Y E F E F H J K L M N P R T U V W Y E F 0 0 0 0 E 0 F 0 0 H 0 J 0 K 0 L 0 M 0 N 0 P 0 R 0 T 0 U 0 V 0 W 0 Y 0 0 0 0 0 E 0 F 0 E F H J K L M N P R T U V W Y E F E F H J K L M N P R T U V W E F E F H J K L M N P R T U V W E F E F H J K L M N P R T U V W Y E F E F H J K L M N P R T U V W Y E F E F H J K L M N P R T U V W Y E F E F H J K L M N P R T U V W Y E E F H J K L M N P R T U V W Y E E F H J K L M N P R T U V W Y _0_Q OEM. PU_VLT U00 PU_VLT VLT_ VLT_ VLT_ VLT_ HT LINK E VLT_ VLT_ E VLT_ E VLT_ E 0 HT_PU_RX[0..] 0 HT_PU_RX#[0..] HT_PU_RX0 HT_PU_RX#0 HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX0 HT_PU_RX#0 HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# E L0_IN_H[0] L0_OUT_H[0] E L0_IN_L[0] L0_OUT_L[0] E L0_IN_H[] L0_OUT_H[] F L0_IN_L[] L0_OUT_L[] L0_IN_H[] L0_OUT_H[] L0_IN_L[] L0_OUT_L[] L0_IN_H[] L0_OUT_H[] H L0_IN_L[] L0_OUT_L[] J W L0_IN_H[] L0_OUT_H[] K L0_IN_L[] L0_OUT_L[] W L L0_IN_H[] L0_OUT_H[] V L L0_IN_L[] L0_OUT_L[] U L L0_IN_H[] L0_OUT_H[] U M U L0_IN_L[] L0_OUT_L[] N L0_IN_H[] L0_OUT_H[] T N L0_IN_L[] L0_OUT_L[] R E L0_IN_H[] L0_OUT_H[] F L0_IN_L[] L0_OUT_L[] F L0_IN_H[] L0_OUT_H[] F L0_IN_L[] L0_OUT_L[] L0_IN_H[0] L0_OUT_H[0] H L0_IN_L[0] L0_OUT_L[0] H L0_IN_H[] L0_OUT_H[] H L0_IN_L[] L0_OUT_L[] K L0_IN_H[] L0_OUT_H[] Y K L0_IN_L[] L0_OUT_L[] W L L0_IN_H[] L0_OUT_H[] V M L0_IN_L[] L0_OUT_L[] V M L0_IN_H[] L0_OUT_H[] V M U L0_IN_L[] L0_OUT_L[] N L0_IN_H[] L0_OUT_H[] T P T L0_IN_L[] L0_OUT_L[] HT_PU_TX0 HT_PU_TX#0 HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX0 HT_PU_TX#0 HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX[0..] 0 HT_PU_TX#[0..] 0 0 HT_PU_RX_LK0 0 HT_PU_RX_LK#0 0 HT_PU_RX_LK 0 HT_PU_RX_LK# HT_PU_RX_LK0 HT_PU_RX_LK#0 HT_PU_RX_LK HT_PU_RX_LK# J L0_LKIN_H[0] J L0_LKIN_L[0] J L0_LKIN_H[] K L0_LKIN_L[] Y L0_LKOUT_H[0] L0_LKOUT_L[0] W L0_LKOUT_H[] Y L0_LKOUT_L[] Y HT_PU_TX_LK0 HT_PU_TX_LK#0 HT_PU_TX_LK HT_PU_TX_LK# HT_PU_TX_LK0 0 HT_PU_TX_LK#0 0 HT_PU_TX_LK 0 HT_PU_TX_LK# 0 0 HT_PU_RX_TL0 0 HT_PU_RX_TL#0 0 HT_PU_RX_TL 0 HT_PU_RX_TL# HT_PU_RX_TL0 HT_PU_RX_TL#0 HT_PU_RX_TL HT_PU_RX_TL# N L0_TLIN_H[0] P L0_TLIN_L[0] P L0_TLIN_H[] P L0_TLIN_L[] L0_TLOUT_H[0] R L0_TLOUT_L[0] R L0_TLOUT_H[] T R L0_TLOUT_L[] HT_PU_TX_TL0 HT_PU_TX_TL#0 HT_PU_TX_TL HT_PU_TX_TL# HT_PU_TX_TL0 0 HT_PU_TX_TL#0 0 HT_PU_TX_TL 0 HT_PU_TX_TL# 0 OKET 00 0 o not cross plane. +.V Irat= /00Mhz L00 PU_VLT 00 00.UF/.V.UF/.V N 00 00.UF/.V 0.UF/.V 00 0.UF/.V 00 0PF/0V 00 0PF/0V N Place close to socket * If VLT is connected only on one side, one.uf cap should be added to the island side UTeK.omputer.IN riffin HT I/F <Orgddr> ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

place close to PROEOR within. inch place close to PROEOR within. inch MEM_M0_LK MEM_M0_LK_H MEM_M0_LK MEM_M0_LK_H TPT T00 TPT T00,, PLE THEM LOE TO PU WITHIN " T00 +.V MEM_M0_#0 MEM_M0_# MEM_M_OT0 MEM_M_OT,,,, MEM_M_KE0 MEM_M_KE MEM_M0_OT0 MEM_M0_OT 0 0 0 0.OHM M_ZP F0 M_ZN E0.OHM MEM_M_REET# H VTT_ENE MEM_M_REET# MEM_M_OT0 T00 TPT N T00 TPT M_LK_H[] M_LK_H[] P TPT T0 N0 MEM_M0_LK_H M_LK_L[] M_LK_L[] R TPT T0 E MEM_M0_LK_H MEM_M0_LK_L M_LK_H[] M_LK_H[] F MEM_M0_LK_L MEM_M0_LK_H M_LK_L[] M_LK_L[] Y F MEM_M0_LK_H MEM_M0_LK_L M_LK_H[] M_LK_H[] MEM_M0_LK_L M_LK_L[] M_LK_L[] F T00 TPT P M_LK_H[] M_LK_H[] R TPT T0 T00 TPT P0 M_LK_L[] M_LK_L[] R TPT T0, MEM_M_[0..] MEM_M_[0..], MEM_M_0 N P MEM_M_0 MEM_M_ M_[0] M_[0] M0 MEM_M_ MEM_M_ M_[] M_[] N N MEM_M_ MEM_M_ M_[] M_[] P M MEM_M_ MEM_M_ M_[] M_[] N M MEM_M_ MEM_M_ M_[] M_[] N L0 L MEM_M_ MEM_M_ M_[] M_[] M MEM_M_ MEM_M_ M_[] M_[] N L L MEM_M_ MEM_M_ M_[] M_[] L MEM_M_ MEM_M_ M_[] M_[] M K MEM_M_ MEM_M_0 M_[] M_[] K R MEM_M_0 MEM_M_ M_[0] M_[0] T L MEM_M_ MEM_M_ M_[] M_[] L K0 MEM_M_ MEM_M_ M_[] M_[] L V MEM_M_ MEM_M_ M_[] M_[] W K MEM_M_ MEM_M_ M_[] M_[] J K MEM_M_ M_[] M_[] J,,,,,, N TPT R00 KOhm % R00 KOhm % MEM_M_NK0 MEM_M_NK MEM_M_NK MEM_M_R# MEM_M_# MEM_M_WE# +.V T00 T00 R00 R00 +0.V TPT TPT LMVIVR 00 000PF/V +VU + - V+ 0. R00 00 T V U V T0 U U0 V0 J J0 R0 R J R T T 0.UF/V V- U00 U00 VTT VTT VTT VTT M_ZP M_ZN RV M0_OT[0] M0_OT[] M_OT[0] M_OT[] M0 L[0] M0 L[] M L[0] M L[] M_KE[0] M_KE[] M_NK[0] M_NK[] M_NK[] M_R_L M L M_WE_L OKET N N R00 R00 MEM:M/TRL/LK R00 R00 0KOhm sensing point for op-amp feedback routed near PU N VTT VTT VTT VTT VTT VTT_ENE M_VREF RV M0_OT[0] M0_OT[] M_OT[0] M0 L[0] M0 L[] M L[0] M_KE[0] M_KE[] M_NK[0] M_NK[] M_NK[] M_R_L M L M_WE_L 00 0.UF/V W0 0 0 0 0 Y0 W W W Y V W U J H R U J U U U TPT 00 000PF/V +0.V PU_M_VREF PLE LOE TO PU MEM_M_Q[0..] MEM_M_Q#[0..] MEM_M_Q[0..] MEM_M_Q#[0..] 0 T0 TPT T0 TPT T00 T0 TPT MEM_M_KE0, MEM_M_KE, MEM_M_NK0, MEM_M_NK, MEM_M_NK, MEM_M_R#, MEM_M_#, MEM_M_WE#, PU_M_VREF MEM_M0_OT0, MEM_M0_OT, MEM_M0_#0, MEM_M0_#, MEM_M0_LK# MEM_M0_LK MEM_M0_LK# 00.PF/0V ML/+/-0.PF MEM_M0_LK_L MEM_M0_LK_H 00.PF/0V ML/+/-0.PF MEM_M0_LK_L MEM_M0_LK_L MEM_M0_LK_H MEM_M0_LK_L MEM:T MEM_M_T[0..] MEM_M_T[0..] MEM_M_T0 MEM_M_T0 MEM_M_T M_T[0] M_T[0] MEM_M_T MEM_M_T M_T[] M_T[] F MEM_M_T MEM_M_T M_T[] M_T[] H MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T MEM_M_T M_T[] M_T[] H E MEM_M_T MEM_M_T M_T[] M_T[] H MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T MEM_M_T M_T[] M_T[] E MEM_M_T MEM_M_T M_T[] M_T[] H MEM_M_T MEM_M_T0 M_T[] M_T[] E MEM_M_T0 MEM_M_T M_T[0] M_T[0] E 0 H MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T MEM_M_T M_T[] M_T[] E MEM_M_T MEM_M_T M_T[] M_T[] F MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T MEM_M_T M_T[] M_T[] 0 MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T MEM_M_T0 M_T[] M_T[] E0 0 MEM_M_T0 MEM_M_T M_T[0] M_T[0] E 0 F MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T MEM_M_T M_T[] M_T[] E MEM_M_T MEM_M_T M_T[] M_T[] F0 E MEM_M_T MEM_M_T M_T[] M_T[] F MEM_M_T MEM_M_T M_T[] M_T[] H MEM_M_T MEM_M_T M_T[] M_T[] J MEM_M_T MEM_M_T M_T[] M_T[] E MEM_M_T MEM_M_T0 M_T[] M_T[] E MEM_M_T0 MEM_M_T M_T[0] M_T[0] H0 MEM_M_T MEM_M_T M_T[] M_T[] H Y MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T MEM_M_T M_T[] M_T[] E MEM_M_T MEM_M_T M_T[] M_T[] W MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T MEM_M_T M_T[] M_T[] W MEM_M_T MEM_M_T M_T[] M_T[] Y E MEM_M_T MEM_M_T0 M_T[] M_T[] MEM_M_T0 MEM_M_T M_T[0] M_T[0] Y0 MEM_M_T MEM_M_T M_T[] M_T[] 0 E0 MEM_M_T MEM_M_T M_T[] M_T[] F0 MEM_M_T MEM_M_T M_T[] M_T[] F MEM_M_T MEM_M_T M_T[] M_T[] F MEM_M_T MEM_M_T M_T[] M_T[] 0 MEM_M_T MEM_M_T M_T[] M_T[] 0 Y MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T MEM_M_T M_T[] M_T[] E W MEM_M_T MEM_M_T0 M_T[] M_T[] MEM_M_T0 MEM_M_T M_T[0] M_T[0] W Y MEM_M_T MEM_M_T M_T[] M_T[] F MEM_M_T MEM_M_T M_T[] M_T[] Y MEM_M_T MEM_M_T M_T[] M_T[] F MEM_M_T MEM_M_T M_T[] M_T[] F MEM_M_T MEM_M_T M_T[] M_T[] F MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T MEM_M_T M_T[] M_T[] Y Y MEM_M_T MEM_M_T0 M_T[] M_T[] W E MEM_M_T0 MEM_M_T M_T[0] M_T[0] F MEM_M_T MEM_M_T M_T[] M_T[] F MEM_M_T MEM_M_T M_T[] M_T[] MEM_M_T M_T[] M_T[] MEM_M_M[0..] MEM_M_M[0..] MEM_M_M0 MEM_M_M0 MEM_M_M M_M[0] M_M[0] E MEM_M_M MEM_M_M M_M[] M_M[] MEM_M_M MEM_M_M M_M[] M_M[] E E MEM_M_M MEM_M_M M_M[] M_M[] F MEM_M_M MEM_M_M M_M[] M_M[] E MEM_M_M MEM_M_M M_M[] M_M[] Y MEM_M_M MEM_M_M M_M[] M_M[] Y MEM_M_M M_M[] M_M[] MEM_M_Q0 MEM_M_Q#0 MEM_M_Q MEM_M_Q# MEM_M_Q MEM_M_Q# MEM_M_Q MEM_M_Q# MEM_M_Q MEM_M_Q# MEM_M_Q MEM_M_Q# MEM_M_Q MEM_M_Q# MEM_M_Q MEM_M_Q# 0 MEM_M0_LK# MEM_M0_LK MEM_M0_LK# Processor Memory Interface F E F F E F E U00 M_Q_H[0] M_Q_L[0] M_Q_H[] M_Q_L[] M_Q_H[] M_Q_L[] M_Q_H[] M_Q_L[] M_Q_H[] M_Q_L[] M_Q_H[] M_Q_L[] M_Q_H[] M_Q_L[] M_Q_H[] M_Q_L[] 00.PF/0V ML/+/-0.PF 00.PF/0V ML/+/-0.PF M_Q_H[0] M_Q_L[0] M_Q_H[] M_Q_L[] M_Q_H[] M_Q_L[] M_Q_H[] M_Q_L[] M_Q_H[] M_Q_L[] M_Q_H[] M_Q_L[] M_Q_H[] M_Q_L[] M_Q_H[] M_Q_L[] H 0 Y W W W MEM_M_Q0 MEM_M_Q#0 MEM_M_Q MEM_M_Q# MEM_M_Q MEM_M_Q# MEM_M_Q MEM_M_Q# MEM_M_Q MEM_M_Q# MEM_M_Q MEM_M_Q# MEM_M_Q MEM_M_Q# MEM_M_Q MEM_M_Q# OKET UTeK.omputer.IN riffin R MEM I/F <Orgddr> ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

0 PU_PWR PU_PWR PU_LT_TOP#,0 PU_LT_TOP# keep trace from caps to PU_LT_RT# PU within." N 00 REFER FZ R 0 PU_LT_RT# N 00 +.V PU_PWR +V PU_LKIN_P R_PU_HT_LKP 00PF/0V U00 0. R0,0 N_LLOW_LTTOP PU_LT_REQ#_PU 0KOhm UF_PLT_RT#,0,0,,,,,0 R0 R0 F R Ohm V V KEY M F 0KOhm +.V V KEY W 0 0.UF/0V 00 PU_LK_H_ PU_V R0 R0 N 00 change to.k PU_LKIN_N PU_LK_L_ V R LKIN_H Q0 PU_V R_PU_HT_LKN 00PF/0V V N00 LKIN_L 0 0 0 FORE_OFF# 0,,, R00.KOhm PU_I R0 PU_LT_RT# L R00.KOhm PU_I R0 PU_PWR REET_L PU_LT_TOP# PWROK F0 PU_THRMTRIP#_.V THRMTRIP#_.V, PU_LT_REQ#_PU LTTOP_L THERMTRIP_L F PU_PROHOT# PU_PROHOT# 0 PU_LERT LTREQ_L PROHOT_L KOhm R0 PU_MEMHOT#_.V PU_I MEMHOT_L Q0 F PM0 +.V place them to PU within." PU_I I F PU_LERT I E PU_THRM_ 0 +.V LERT_L THERM W PU_THRM_ 0 N PU_HTREF0 THERM W R0.Ohm R PU_REQ# R 0 PU_VLT R0 PU_HTREF HTREF0.Ohm P HTREF N R00 KOhm R00 0OHM R00 KOhm R00 0OHM R00 0 N_LLOW_LTTOP +.V route as diff pair //,0mil PU_V PU_V erial VI Interface clock/data 00 R00 0 +V Q0 N00 R 0KOhm R00 0 R0 0 PU_LT_REQ#_PU 00.0.0 add 0 optional to PU_PWR 0 T0 TPT PF/0V N PU_V0_RUN_F_H PU_V0_RUN_F_L PU_V_RUN_F_H PU_V_RUN_F_L N R0 LYOUT: ROUTE V TRE PPROX. 0 mils WIE (UE x mil TRE TO EXIT LL FIEL) N 00 mils LON. keep trace fromresistor to PU within 0." T00 TPT T00 TPT T00 TPT T00 TPT T00 TPT T00 TPT T00 TPT T00 TPT T00 TPT T00 TPT T0 TPT T0 TPT PU_RY PU_TM PU_TK PU_TRT# PU_TI PU_TET PU_TET PU_TET PU_TET_H PU_TET_L PU_TET PU_TET0 PU_TET PU_TET PU_TET PU_TET PU_TET_NLOIN PU_TET_IERKMON F E Y 0 F H0 E E F E E F V0_F_H V0_F_L V_F_H V_F_L RY TM TK TRT_L TI TET TET TET TET_H TET_L TET TET0 TET TET TET TET TET TET RV RV0 RV RV RV OKET VIO_F_H VIO_F_L VN_F_H VN_F_L REQ_L TO TET_H TET_L TET TET TET TET TET TET0 TET TET_H TET_L RV RV RV RV RV W Y H E0 E J H E F K H H PU_VIO_U_F_H PU_VIO_U_F_L PU_VN_RUN_F_H PU_VN_RUN_F_L PU_REQ# PU_TO PU_TET_H PU_TET_L PU_TET PU_TET PU_TET PU_TET PU_TET_NLO_T TPT T0 PU_TET0_NLOOUT TPT T0 PU_TET_I_T PU_TET_H_FLKOUT_P PU_TET_L_FLKOUT_N move to power circuit T0 T0 TPT TPT PU_VN_RUN_F_H PU_VN_RUN_F_L TPT T0 TPT T0 TPT T0 TPT T0 TPT T0 TPT T0 TPT T00 +.V_PU_V /00Mhz L00 TPT T0 TPT T0 00.UF/.V 00 0.UF/.V V 00 00PF/0V PU_TET PU_TET0 PU_TET PU_TET PU_TET 00 change R0 R0 R0 TO 00ohm PU_TET_H PU_TET_L PU_TET PU_TET PU_TET PU_TET PU_TET T0 TPT T0 TPT T0 TPT T0 TPT T0 TPT T0 TPT T00 TPT T0 TPT R0 R0 R0 R0 R0 R0 R00 R0 R0 R0 R0 R0 PU_LK_H_ PU_LK_L_ PU_LT_TOP# PU_PWR PU_V0_RUN_F_H PU_V0_RUN_F_L PU_V_RUN_F_H PU_V_RUN_F_L 0 0 0 0 0 0 0 0 0 0 N +.V N +V to PU P00 PU_LT_RT# N N PU_PWR R REQ_L N R PU_REQ# RY N PU_RY REQ_L N PU_TK RY N 0 PU_TM REQ_L N PU_TI RY N PU_TRT# REQ_L N PU_TO RY RY REQ_L REQ_L 0 +.V RY RY REQ_L N N0 P_00_0_K +V R 0KOhm +.V R0 0KOhm PU_LT_RT# Q0 PM0 0, PWRLIMIT# E to PU/PWR 00 PU_PROHOT# RV-0 Q00 N00 N Q00 R0 0KOhm UMKN THRO_PU 0 From E. Q00 UMKN PM_THERM#_E 0 N UTeK.omputer.IN Title riffin : NT//THERM <Orgddr> ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

+.V +0.V +.V +.V +.V +0.V +0.V +0.V PU_V0 PU_V PU_V0 PU_V PU_VN N N N N N N N N N N N N N +.V PU_VN ate: heet of ustom Wednesday, March, 00 UTeK.omputer.IN riffin Power 0. Z0Z/FTr <Orgddr> ate: heet of ustom Wednesday, March, 00 UTeK.omputer.IN riffin Power 0. Z0Z/FTr <Orgddr> ate: heet of ustom Wednesday, March, 00 UTeK.omputer.IN riffin Power 0. Z0Z/FTr <Orgddr> ottom side decoupling ecoupling between Processor and IMMs, Place close to Porcessor as possible place close to socket 00 add 00 0 0PF/0V 0 0PF/0V 00 0.UF/.V 00 0.UF/.V 0 UF/.V 0 UF/.V 0 0PF/0V 0 0PF/0V 00.UF/.V 00.UF/.V 0 UF/.V 0 UF/.V 00 0.0UF/V 00 0.0UF/V 0.UF/.V 0.UF/.V 00.UF/.V 00.UF/.V 0 UF/.V 0 UF/.V 00 UF/.V 00 UF/.V 0.UF/.V 0.UF/.V 00 0.0UF/V 00 0.0UF/V 0 0PF/0V 0 0PF/0V 0 0PF/0V 0 0PF/0V 0 UF/.V 0 UF/.V 0 000PF/V 0 000PF/V 00.UF/.V 00.UF/.V 0 0.UF/.V 0 0.UF/.V 00 000PF/V 00 000PF/V 00 0.0UF/V 00 0.0UF/V 0 UF/.V 0 UF/.V 0.UF/.V 0.UF/.V 0 0.UF/.V 0 0.UF/.V 0 0.UF/.V 0 0.UF/.V 0.UF/.V 0.UF/.V 0 UF/.V 0 UF/.V 0 000PF/V 0 000PF/V 0 0PF/0V 0 0PF/0V 0 0.UF/.V 0 0.UF/.V 00 0.UF/.V 00 0.UF/.V 0 0.UF/.V 0 0.UF/.V 00 UF/.V 00 UF/.V 0 UF/.V 0 UF/.V 0 0.UF/.V 0 0.UF/.V 0 0PF/0V 0 0PF/0V 0 0.UF/.V 0 0.UF/.V 0 0PF/0V 0 0PF/0V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 00.UF/.V 00.UF/.V 0 000PF/V 0 000PF/V 0 0PF/0V 0 0PF/0V V V V V V V V V V0 V V V V V V V V V0 V V V E V E V E V E V E V0 E V E V V V V V V V0 V V V V V V V V V V V V V V V V V E V F V F V F V F V0 F V F V F V F V F V H V H V H V H V J V0 J V J V J0 V J V J V J V J V K V K V K V K V K V K V K V0 L V L V L0 V L V00 L V0 L V L V M V M V V0 M V N V N V0 N0 V0 N V N V P V P V P V0 P V0 P V R V0 R0 V0 R V R V T V T V0 T V0 T V T V T V0 U V U V U V U0 V U V0 U V U V U V V V0 V V V V V V V V V V V V W V Y V Y V N U00F OKET U00F OKET V_ V_ V0_ V0_ H V0_ J V0_ J V0_ J V0_ K V0_ K0 V0_ K V0_ K V0_ L V0_0 L V0_ L V0_ L V0_ L V0_ M V0_ M V0_ M V0_ M0 V0_ N V0_ N V0_0 N V_ P V_0 P0 V_ R V_ R V_0 R V_ R V_ T V_ T V_ T V_ T0 V_ T V_ T V_ U V_ U V_ U V_ U V_ V V_ V V_ V0 V_ V V_ V V_ W V_ Y V0_ J VN K V0_ L VN M VN P VN T V_ U VN V VIO H VIO J VIO K VIO K VIO K VIO K VIO0 L VIO M VIO M VIO0 M VIO M VIO N VIO P VIO P VIO P VIO P VIO R VIO T VIO T VIO T VIO T VIO U VIO V VIO V VIO V VIO V VIO Y U00E OKET U00E OKET 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 00 0.UF/.V 00 0.UF/.V 0 0.UF/.V 0 0.UF/.V 0 0.0UF/V 0 0.0UF/V 00 0.UF/.V 00 0.UF/.V 0 0PF/0V 0 0PF/0V

MEM_M_T MEM_M_M MEM_M_M MEM_M_M MEM_M_Q MEM_M_Q MEM_M_Q MEM_M_Q MEM_M_Q0 MEM_M_Q MEM_M_Q MEM_M_Q MEM_M_Q# MEM_M_Q# MEM_M_Q# MEM_M_M MEM_M_M MEM_M_M0 MEM_M_M MEM_M_M MEM_M_Q# MEM_M_Q#0 MEM_M_Q# MEM_M_Q# MEM_M_Q# MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M0_#0 MEM_M0_# MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T M_VREF_IMM0 MEM_M_NK, MEM_M0_OT, MEM_M0_OT0, MEM_M_M[0..] MEM_M_Q[0..] MEM_M_Q#[0..] MEM_M_NK0, MEM_M0_LK MEM_M0_LK MEM_M0_LK# MEM_M0_LK# MEM_M_NK, MEM_M_KE0, MEM_M_WE#, MEM_M_R#, MEM_M_KE, MEM_M_#, MEM_M_T[0..] MLK_RM,, MT_RM,, MEM_M_[0..], MEM_M0_#[0..], +.V +V +.V N ate: heet of ustom Wednesday, March, 00 UTeK OMPUTER IN R O-IMM0 0. Z0Z/FTr <Variant Name> ate: heet of ustom Wednesday, March, 00 UTeK OMPUTER IN R O-IMM0 0. Z0Z/FTr <Variant Name> ate: heet of ustom Wednesday, March, 00 UTeK OMPUTER IN R O-IMM0 0. Z0Z/FTr <Variant Name> 0 High 00 0.UF/0V 00 0.UF/0V 00 0.UF/0V 00 0.UF/0V 00 0.UF/V 00 0.UF/V V V V V V V V V V V0 0 V V 0 VP N N 0 N 0 N NTET VREF N0 0 N 0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V 0 V V V V V V0 V V V V V V 0 V V V V0 V V V V V V V V V V0 V V V V 0 V V 0 V NP_N 0 NP_N 0 J00 R_IMM_00P J00 R_IMM_00P 0 0.UF/0V 0 0.UF/0V 00.UF/.V 00.UF/.V 00 0.UF/0V 00 0.UF/0V + E00 0UF/.V + E00 0UF/.V 00.UF/.V 00.UF/.V 0 0 0 00 0/P 0 0 0 0 0 0# 0 # K0 0 K0# K K# KE0 KE 0 # R# 0 WE# 0 0 00 L OT0 OT M0 0 M M M M 0 M M 0 M Q0 Q Q Q 0 Q Q Q Q Q#0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q _ Q J00 R_IMM_00P J00 R_IMM_00P 0 0.UF/V 0 0.UF/V 00.UF/.V 00.UF/.V 00.UF/.V 00.UF/.V 0.UF/.V 0.UF/.V 00 0.UF/0V 00 0.UF/0V R00 KOhm % R00 KOhm % 00.UF/.V 00.UF/.V 0 000PF/V 0 000PF/V R00 KOhm % R00 KOhm %

MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M0_# MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M0_#0 MEM_M_ MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M0 MEM_M_M MEM_M_Q MEM_M_Q MEM_M_Q MEM_M_Q MEM_M_Q MEM_M_Q MEM_M_Q0 MEM_M_Q MEM_M_Q# MEM_M_Q# MEM_M_Q# MEM_M_Q# MEM_M_Q# MEM_M_Q# MEM_M_Q#0 MEM_M_Q# MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T M_VREF_IMM MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MLK_RM,, MT_RM,, MEM_M0_OT, MEM_M0_OT0, MEM_M_NK, MEM_M_[0..], MEM_M_NK0, MEM_M_NK, MEM_M_Q[0..] MEM_M_Q#[0..] MEM_M_M[0..] MEM_M_KE0, MEM_M_KE, MEM_M0_LK MEM_M0_LK MEM_M0_LK# MEM_M_#, MEM_M_R#, MEM_M0_LK# MEM_M_WE#, MEM_M_T[0..] MEM_M0_#[0..], N +.V +V +V +.V N ate: heet of ustom Wednesday, March, 00 UTeK OMPUTER IN R O-IMM 0. Z0Z/FTr ate: heet of ustom Wednesday, March, 00 UTeK OMPUTER IN R O-IMM 0. Z0Z/FTr ate: heet of ustom Wednesday, March, 00 UTeK OMPUTER IN R O-IMM 0. Z0Z/FTr 0 low 00 0.UF/V 00 0.UF/V 0 0 0 00 0/P 0 0 0 0 0 0# 0 # K0 0 K0# K K# KE0 KE 0 # R# 0 WE# 0 0 00 L OT0 OT M0 0 M M M M 0 M M 0 M Q0 Q Q Q 0 Q Q Q Q Q#0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q _ Q J00 R_IMM_00P J00 R_IMM_00P 00.UF/.V 00.UF/.V 00.UF/.V 00.UF/.V 0 0.UF/0V 0 0.UF/0V 00 0.UF/0V 00 0.UF/0V 00.UF/.V 00.UF/.V R00 KOhm % R00 KOhm % R00.KOhm R00.KOhm 0 0.UF/0V 0 0.UF/0V 0 0.UF/V 0 0.UF/V 00.UF/.V 00.UF/.V 00 0.UF/0V 00 0.UF/0V 00 0.UF/0V 00 0.UF/0V 00.UF/.V 00.UF/.V V V V V V V V V V V0 0 V V 0 VP N N 0 N 0 N NTET VREF N0 0 N 0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V 0 V V V V V V0 V V V V V V 0 V V V V0 V V V V V V V V V V0 V V V V 0 V V 0 V NP_N 0 NP_N 0 J00 R_IMM_00P J00 R_IMM_00P 00.UF/.V 00.UF/.V R00 KOhm % R00 KOhm % 0 000PF/V 0 000PF/V

+0.V, MEM_M_KE0, MEM_M_KE, MEM_M_NK, MEM_M_, MEM_M_, MEM_M_ R00 Ohm R0 Ohm MEM_M_NK R0 Ohm MEM_M_ R0 Ohm MEM_M_ R0 Ohm MEM_M_ R0 Ohm 0., MEM_M_NK, MEM_M_, MEM_M_0 MEM_M_NK MEM_M_ MEM_M_0 Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00 00 0.UF/V +.V, MEM_M0_OT, MEM_M0_OT0, MEM_M0_#, MEM_M0_#0, MEM_M_#, MEM_M_R# RN00 Ohm RN00 Ohm Ohm RN00 Ohm RN00 Ohm RN00E Ohm RN00F 0 Ohm RN00 Ohm RN00H 00 0.UF/V 00 0.UF/V 0 0.UF/V +.V +.V +.V, MEM_M_, MEM_M_, MEM_M_, MEM_M_, MEM_M_, MEM_M_, MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ RN00 Ohm RN00 Ohm Ohm RN00 Ohm RN00 Ohm RN00E Ohm RN00F 0 Ohm RN00 Ohm RN00H 0 0.UF/V 0 0.UF/V +.V +.V, MEM_M_0, MEM_M_, MEM_M_, MEM_M_, MEM_M_NK0 MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_NK0 RN00 Ohm RN00 Ohm Ohm RN00 Ohm RN00 Ohm RN00E Ohm RN00F 0 Ohm RN00 Ohm RN00H 0 0.UF/V 0 0.UF/V +.V +.V +0.V, MEM_M_WE# R0 Ohm 00 0.UF/V 00 0.UF/V 00 0.UF/V 00 0.UF/V 00 0.UF/V 00 0.UF/V 00 0.UF/V 0 0.UF/V +0.V N, MEM_M_NK, MEM_M0_OT, MEM_M_KE0 R0 Ohm R0 Ohm R0 Ohm 0., MEM_M_, MEM_M0_#, MEM_M_#, MEM_M_WE#, MEM_M_, MEM_M_NK0, MEM_M_, MEM_M_KE, MEM_M_0, MEM_M_, MEM_M_, MEM_M_, MEM_M_, MEM_M_, MEM_M_, MEM_M_, MEM_M_, MEM_M_, MEM_M_0, MEM_M_, MEM_M_R#, MEM_M_NK MEM_M_ MEM_M_ MEM_M_NK0 MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_NK RN00 Ohm RN00 Ohm Ohm RN00 Ohm RN00 Ohm RN00E Ohm RN00F 0 Ohm RN00 Ohm RN00H RN00 Ohm RN00 Ohm Ohm RN00 Ohm RN00 Ohm RN00E Ohm RN00F 0 Ohm RN00 Ohm RN00H RN00 Ohm RN00 Ohm Ohm RN00 Ohm RN00 Ohm RN00E Ohm RN00F 0 Ohm RN00 Ohm RN00H 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 00 0.UF/V 0 0.UF/V +.V +.V +.V +.V +.V +.V +.V +0.V 00 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0 0.UF/V 0.UF/V N, MEM_M0_#0, MEM_M0_OT0, MEM_M_ MEM_M_ Ohm RN00 Ohm RN00 Ohm RN00 Ohm RN00 0.UF/V +.V +.V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V PLE LOE TO OKET( PER EMI/EM) N UTeK OMPUTER IN R_TERMINTION ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

HT_PU_TX[0..] HT_PU_TX0 HT_PU_TX#0 HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# U00 Y HT_RX0P HT_TX0P Y HT_RX0N PRT OF HT_TX0N V HT_RXP HT_TXP E V HT_RXN HT_TXN E V HT_RXP HT_TXP F V HT_RXN HT_TXN F U HT_RXP HT_TXP F U HT_RXN HT_TXN F T HT_RXP HT_TXP H T HT_RXN HT_TXN H P HT_RXP HT_TXP J P HT_RXN HT_TXN J P HT_RXP HT_TXP K P HT_RXN HT_TXN K N HT_RXP HT_TXP K N HT_RXN HT_TXN K HT_PU_RX0 HT_PU_RX#0 HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX[0..] HT_PU_RX#[0..] HT_PU_TX#[0..] HT_PU_TX HT_PU_TX# HT_RXP HT_PU_TX HT_RXN HT_PU_TX# HT_RXP HT_PU_TX0 HT_RXN HT_PU_TX#0 HT_RX0P HT_PU_TX HT_RX0N Y HT_PU_TX# HT_RXP Y HT_PU_TX HT_RXN W HT_PU_TX# HT_RXP W0 HT_PU_TX HT_RXN V HT_PU_TX# HT_RXP V0 HT_PU_TX HT_RXN U0 HT_PU_TX# HT_RXP U HT_PU_TX HT_RXN U HT_PU_TX# HT_RXP U HT_RXN HT_TXP F HT_TXN HT_TXP 0 HT_TXN H HT_TX0P J0 HT_TX0N J HT_TXP J HT_TXN K HT_TXP L HT_TXN J HT_TXP M HT_TXN L HT_TXP M HT_TXN P HT_TXP P HT_TXN M HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX0 HT_PU_RX#0 HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_TX_LK0 HT_PU_TX_LK#0 HT_PU_TX_LK HT_PU_TX_LK# HT_PU_TX_LK0 HT_PU_TX_LK#0 HT_PU_TX_LK HT_PU_TX_LK# T HT_RXLK0P T HT_RXLK0N HT_RXLKP HT_RXLKN HT_TXLK0P H HT_TXLK0N H HT_TXLKP L HT_TXLKN L0 HT_PU_RX_LK0 HT_PU_RX_LK#0 HT_PU_RX_LK HT_PU_RX_LK# HT_PU_RX_LK0 HT_PU_RX_LK#0 HT_PU_RX_LK HT_PU_RX_LK# HT_PU_TX_TL0 HT_PU_TX_TL#0 HT_PU_TX_TL HT_PU_TX_TL# HT_PU_TX_TL0 M HT_PU_TX_TL#0 HT_RXTL0P M HT_PU_TX_TL HT_RXTL0N R HT_PU_TX_TL# HT_RXTLP R0 HT_RXTLN HT_TXTL0P M HT_TXTL0N M HT_TXTLP P HT_TXTLN R HT_PU_RX_TL0 HT_PU_RX_TL#0 HT_PU_RX_TL HT_PU_RX_TL# HT_PU_RX_TL0 HT_PU_RX_TL#0 HT_PU_RX_TL HT_PU_RX_TL# R00 HT_RXLP HT_RXLN HT_RXLP HT_RXLN R0M HT_TXLP HT_TXLN HT_TXLP HT_TXLN R00 000000 UTeK.omputer.IN R0M-HT LINK I/F <Orgddr> ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0 0.

PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP 0 PIEN_TXN 0 PIEN_TXP 0 PIEN_TXN 0 PIEN_TXP 0 PIEN_TXN 0 PIEN_TXP 0 PIEN_TXN 0 aps on V card PIEN_RXN[0..] 0 PIEN_RXP[0..] 0 PIEN_RXP PIEN_RXN PIEN_RXP PIEN_RXN PIEN_RXP PIEN_RXN PIEN_RXP PIEN_RXN PIEN_RXP PIEN_RXN PIEN_RXP0 PIEN_RXN0 PIEN_RXP PIEN_RXN PIEN_RXP PIEN_RXN PIEN_RXP PIEN_RXN PIEN_RXP PIEN_RXN PIEN_RXP PIEN_RXN PIEN_RXP PIEN_RXN PIEN_RXP PIEN_RXN PIEN_RXP PIEN_RXN PIEN_RXP PIEN_RXN PIEN_RXP0 PIEN_RXN0 PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP0 PIEN_TXN0 PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP0 PIEN_TXN0 _TX0P TX0N TXP TXN TXP TXN TXP TXN_ PIEN_TXN0 PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN0 PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIE_RXN0 PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN0 PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PP_TX0P_ PIE_RXP0_TV E PP_RX0P PP_TX0P 0 0.UF/0V PIE_TXP0_TV PP_TX0N_ PIE_RXN0_TV PP_RX0N PP_TX0N 0 0.UF/0V PIE_TXN0_TV PP_TXP_ PIE_RXP_LN E PP_RXP PP_TXP 0 0.UF/0V PIE_TXP_LN PP_TXN_ PIE_RXN_LN PP_RXN PP_TXN 0 0.UF/0V PIE_TXN_LN PP_RXP PP_TXP PP_RXN PIE I/F PP PP_TXN PP_TXP_ PIE_RXP_WLN V 0.UF/0V PP_RXP PP_TXP Y PIE_TXP_WLN PP_TXN_ PIE_RXN_WLN W PP_RXN PP_TXN Y 0.UF/0V PIE_TXN_WLN U PP_RXP PP_TXP Y U PP_RXN PP_TXN Y PP_TXP_ 0 PIE_RXP_NEWR U 0.UF/0V PP_RXP PP_TXP V PP_TXN_ PIE_TXP_NEWR 0 PIE_RXN_NEWR U 0.UF/0V PP_RXN PP_TXN V PIE_TXN_NEWR 0 0 0 0 0 0 0 0 PIE N_RX0P PIE N_RX0N PIE N_RXP PIE N_RXN PIE N_RXP PIE N_RXN PIE N_RXP PIE N_RXN E F H H J J J J L L M L P M P M R P R R P P T T Y Y W Y U00 FX_RX0P FX_RX0N FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RX0P FX_RX0N FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN FX_RXP FX_RXN _RX0P _RX0N _RXP _RXN _RXP _RXN _RXP _RXN R0M PI-E: 0~ HMI@ R0M ~ N ~ Vx PRT OF PIE I/F FX_TX0P FX_TX0N FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TX0P FX_TX0N FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN _TX0P _TX0N _TXP _TXN _TXP _TXN _TXP _TXN PE_LRP PE_LRN Refer to R0M datasheet Table -0 E E F F F F H H H H J J K K K K M M M M N N P P E E E.KOHM KOHM 0 0 0 R0 R0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V +.V_N 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V N 0 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V PIE_N TX0P 0 PIE_N TX0N 0 PIE_N TXP 0 PIE_N TXN 0 PIE_N TXP 0 PIE_N TXN 0 PIE_N TXP 0 PIE_N TXN 0 PIEN_TXP0 PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP0 PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP 0 PIE_RXN[0..] 0 PIE_RXP[0..] 00 for bios 0 0 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V PIE_RXP0 PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP0 PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP UTeK.omputer.IN R0M-PIE LINK I/F <Orgddr> ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

+.V_PLL L0 /00Mhz VHTPLL +V L0 /00Mhz V L0 /00Mhz VPIEPLL +.V_PLL +.V r00_h R0 0 +.V R0 0.UF/.V N VI 0 0.UF/.V 0.UF/.V N UF/.V.UF/.V U00 +.V_PLL F LV_U0P_M 0 N N V TXOUT_L0P E VQ_L V PRT OF TXOUT_L0N LV_U0N_M 0 F VI TXOUT_LP LV_UP_M 0 N LV_UN_M 0 L0 /00Mhz 0 VI TXOUT_LN H VQ TXOUT_LP 0 LV_UP_M 0 N H LV_UN_M 0.UF/.V VQ TXOUT_LN 0 TXOUT_LP E 00.0.0 TXOUT_LN F add R0 R0 R0 N Y F R0 0OHM for R0 OMP TXOUT_U0P LV_L0P_M 0 N_PWR 0R termination < inch trace LV_L0N_M 0 00.0.0 TXOUT_U0N IN.V IN 0 RT_RE_M LV_LP_M 0 the U and L of LV exchange R0 % RE TXOUT_UP N RE# TXOUT_UN LV_LN_M 0 LLOW_LTTOP 0 RT_REEN_M E LV_LP_M 0 OUT(default)/IN O/.V IN R0 % REEN TXOUT_UP 0 N F REEN# TXOUT_UN LV_LN_M 0 0 RT_LUE_M E R0 N % LUE TXOUT_UP N F LUE# TXOUT_UN LT_TOP# IN(default)/IN.V IN/O,0 RT_HYN_M _HYN TXLK_LP LV_ULKP_M 0,0 RT_VYN_M _VYN TXLK_LN LV_ULKN_M 0 0 N_ E _ TXLK_UP LV_LLKP_M 0 0 N_L F _L TXLK_UN LV_LLKN_M 0 +.V_PLL +.V_PLL +.V_N R0 Ohm L0 /00Mhz _RET VLTP_PLL_L L0 /00Mhz PLLV VLTP N PLLV PLLV VLTP +.V PLLV N VLTP_L L0 /00Mhz L0 /00Mhz 0 0 PLLV VLT_ R0 POWEROO VHTPLL VLT_ H T0 TPT.UF/.V.UF/.V VHTPLL VLT_ T0 TPT is.v rail U0 +.V VPIEPLL VLT_ VPIEPLL E VLT for 0 only 0 R N N VLT VPIEPLL N V R0 0 R0,0 PM_PWROK VLT.UF/.V 0 N_RT# PM_PWROK_E_UF YREET# VLT 0.UF/0V.UF/.V _N_PWROK Y N 0 N_LT_TOP# POWEROO VLT 0 N_LLOW_LTTOP_N LTTOP# VLT 0 LLOW_LTTOP VLT E0 NLVKR N R N_HT_REFLKP VLT R_N_HT_LKP N_HT_REFLKN HT_REFLKP R_N_HT_LKN HT_REFLKN N N N N_O E N_REFLKN REFLK_P F REFLK_N LV_ION E LV_V_EN 0 +.V_N N R LV_LON F LV_K_EN 0 T FX_REFLKP LV_EN_L R O_M_N R0.KOhm R0.KOhm T 00 PE has pu FX_REFLKN R_N_FX_REFLKP.V R/0.R 00 R_N_FX_REFLKN U change backlight enable T0 TPT PP_REFLKP U pin from LV_EN_L to T0 TPT PP_REFLKN LV_LON +V R.KOhm R_N_PIE_RLKP V.KOhm PP_REFLKP R_N_PIE_RLKN V R PP_REFLKN 0 EI_T I_T 0 EI_LK I_LK MI. TM_HP N_TM_HP 0 0 N_VI_T T0 TPT _T0/UX0N HP 0 0 N_VI_LK R _LK0/UX0P _LK/UXP U_TT# U_TT#, T TPT _T/UXN PU@ conn side. T0 TPT E TRP_T THERMLIOE_P 0 TRP_T THERMLIOE_N 0 UF_PLT_RT#,0,0,,,,,0 REERVE TETMOE TRP_T 0 UX_L V_N.0V.V 00.0.0 R optional to N/ R % R0M R.KOHM N_THRM N_THRM N_THRM N_THRM 00 +V N 00 Q0,R,R +V N,0 PU_LT_TOP# +.V N00 Q0 R.KOhm N_LT_TOP# R TRP_T R 00KOhm Q0 N00 N_TRP_T R,0 N_LLOW_LTTOP N_LLOW_LTTOP_N N R?? for external graphic UTeK.omputer.IN R0M-Y I/F <Orgddr> Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

FT_PIO: LO_EEPROM_TRP elects Loading of TRP from EPROM U00 : ypass the loading of EEPROM straps and use Hardware efault Values 0 : I Master can load strap values from EEPROM if connected, or use default values if not connected R0:U_TT PR OF MEM_0 E MEM_ V MEM_ E MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_0 E MEM_ MEM_ Y MEM_ MEM_0 E MEM_ MEM_ W MEM_R# Y MEM_# MEM_WE# MEM_# MEM_KE V MEM_OT V MEM_KP W MEM_KN E MEM_OMPP MEM_OMPN MEM_Q0 MEM_Q 0 MEM_Q MEM_Q Y MEM_Q V MEM_Q MEM_Q MEM_Q Y MEM_Q 0 MEM_Q MEM_Q0 E MEM_Q MEM_Q 0 MEM_Q MEM_Q MEM_Q Y MEM_Q0P MEM_Q0N W 0 MEM_QP MEM_QN E W MEM_M0 E MEM_M E IOPLLV IOPLLV E IOPLLV MEM_VREF E +.V_PLL +.V_N TRP_EU_U_PIE_ENLE Enables the Test ebug us using PIE bus: : isable ( an still be enabled using nbcfg register access ) 0 : Enable R0: configurable thru register setting only R0/R0: Enables ide port memory R0:HYN# elects if Memory IE PORT is available or not = Memory ide port Not available 0 = Memory ide port available Register Readback of strap: N_LKF:LK_TOP_PRE_[] R0M N,0 RT_VYN_M KOHM R0 KOHM R0 +V N,0 RT_HYN_M KOHM R0 KOHM R0 +V N UTeK.omputer.IN R0M-PMEM/TRP <Orgddr> Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

+.V_N.V(R0).V(RX0;R0) /00Mhz L0 N_V_MUX_L 0. 0 0 0 0.UF/.V 0.UF/0V 0.UF/0V 0.UF/0V /00Mhz N.V(R0).V(RX0;R0) L0 VHTRX +.V /00Mhz 0. L0.UF/.V 00 m +.V /00Mhz L0.UF/.V.UF/.V +.V R0 UF/.V N 0.UF/.V 0.UF/0V 0.UF/0V 0.UF/0V N VHTTX 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V N VPIE 0 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V N V_R +.V V_MEM_R R0 UF/.V U00E J VHT K VHT PRT / L VHT M VHT P VHT R VHT T VHT H VHTRX VHTRX F0 VHTRX E VHTRX VHTRX VHTRX VHTRX E VHTTX VHTTX VHTTX VHTTX VHTTX Y0 VHTTX W VHTTX V VHTTX U VHTTX T VHTTX0 R VHTTX P VHTTX M VHTTX J0 VPIE P0 VPIE K0 VPIE M0 VPIE L0 VPIE W VPIE H VPIE T0 VPIE R0 VPIE Y VPIE0 VPIE VPIE VPIE E VPIE U0 VPIE F V_ V_ E V_MEM V_MEM R0M VPIE VPIE VPIE VPIE VPIE E VPIE F VPIE VPIE H VPIE J VPIE0 K VPIE M VPIE L VPIE P VPIE R VPIE T VPIE V VPIE U K V J V U V J V K V M V L V L V M V M V0 N V N V P V P V P V V R V R V T V T V0 U V T V J V_MEM E0 V_MEM V_MEM Y V_MEM 0 V_MEM 0 V_MEM 0 V_ H V_ H +.V_N.V(R0)/.V(RX0;R0). V_PIE 0 0 0 0 0 0.UF/0V 0.UF/0V UF/.V UF/.V.UF/.V N V_R 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V N M recommended: side port not used, connect to N N +V V_R R0 0.UF/0V 0.UF/0V 0UF/.V 0UF/.V +V_N. N N N +V 0 V +.V 0 V.V rails ramp high relative to.v isplay and PLL rails. max.v N U00F R0M ROUN N UTeK.omputer.IN R0M-POWER <Orgddr> Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

UTeK OMPUTER IN. N <Orgddr> Z0Z/FTr ate: Wednesday, March, 00 heet of 0.

UTeK OMPUTER IN LNK Z0Z/FTr ate: Wednesday, March, 00 heet of 0.

UTeK OMPUTER IN LNK Z0Z/FTr ate: Wednesday, March, 00 heet of 0.

UTeK OMPUTER IN LNK Z0Z/FTr ate: Wednesday, March, 00 heet of 0.

UTeK OMPUTER IN LNK Z0Z/FTr ate: Wednesday, March, 00 heet of 0.

00 change R00 TO ohm PIE N_RX0P PIE N_RX0N PIE N_RXP PIE N_RXN PIE N_RXP PIE N_RXN PIE N_RXP PIE N_RXN _RT# 00 00 00 00 _RT# 0.UF/0V 00 0.UF/0V 00 0.UF/0V 00 0.UF/0V 00 R0 _RX0P_ 0.UF/0V _RX0N RXP_ 0.UF/0V _RXN RXP_ 0.UF/0V _RXN RXP_ 0.UF/0V _RXN_ U00 N _RT# V PIE_TX0P V PIE_TX0N V PIE_TXP V PIE_TXN U PIE_TXP U PIE_TXN T PIE_TXP T PIE_TXN 00 Part of P PILK0 P PILK P PILK P PILK T PILK T PILK/PIO N PIRT# LK_TPMPI_R R00 LK_KPI_R R00 LK_PI_R R00 LK_PI_R R00 PI_LK_R R0 PI_LK_R R0 R0 Ohm Ohm LK_TPMPI Ohm LK_PI 0 LK_IOPI Ohm PI_LK, PI_LK PI_LK PI_RT#,0,, 00.0.0 R00 R0 R0 PN to 00000000 PIE_N TX0P PIE_N TX0N PIE_N TXP PIE_N TXN PIE_N TXP PIE_N TXN PIE_N TXP PIE_N TXN R00 % Ohm PIE_VR N PIE_LRP +.V PIE_LRN /00Mhz R00.0KOHM % PIE_PV_L L00 00 00 0UF/.V UF/.V 00 HNE P/N R PIE_RLKP R PIE_RLKN T0 TPT T0 TPT T0 TPT T00 TPT T0 TPT T0 TPT T0 TPT T0 TPT T0 TPT T0 TPT T0 TPT T0 TPT T0 TPT T00 TPT T0 TPT T0 TPT T0 TPT T0 TPT T0 TPT U PIE_RX0P U PIE_RX0N U PIE_RXP V PIE_RXN R0 PIE_RXP R PIE_RXN R PIE_RXP R PIE_RXN T PIE_LRP T PIE_LRN P PIE_PV P PIE_PV N PIE_RLKP/N_LNK_LKP N PIE_RLKN/N_LNK_LKN K N_IP_LKP K N_IP_LKN M N_HT_LKP M N_HT_LKN P PU_HT_LKP M PU_HT_LKN M LT_FX_LKP M LT_FX_LKN J PP_LK0P J PP_LK0N L0 PP_LKP L PP_LKN M PP_LKP M0 PP_LKN N PP_LKP P PP_LKN L M_M_M_O J M_X J0 M_X 0 U P V T V U V V T W 0 T R R R U U Y W V Y 0 Y Y Y 0 E0# W E# U E# E# Y FRME# EVEL# W IRY# TRY# Y PR U TOP# W PERR# W ERR# V REQ0# REQ# REQ# E REQ#/PIO0 REQ#/PIO NT0# E NT# NT# NT#/PIO E NT#/PIO LKRUN# V LOK# INTE#/PIO INTF#/PIO E INT#/PIO E INTH#/PIO PI_[:0] 0 PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_/E#[:0] PI_/E#[:0] 0 PI_/E#0 PI_/E# PI_/E# PI_/E# PI_FRME# PI_FRME# 0 PI_EVEL# PI_EVEL# 0 PI_IRY# PI_IRY# 0 PI_TRY# PI_TRY# 0 PI_PR PI_PR 0 PI_TOP# PI_TOP# 0 PI_PERR# PI_PERR# 0 PI_ERR# PI_ERR# 0 PI_REQ#0 PI_REQ#0 0 PI_REQ# T0 TPT PI_REQ# T0 TPT PI_REQ# T0 TPT PI_REQ# T0 TPT PI_NT#0 PI_NT#0 0 PI_NT# T0 TPT PI_NT# T0 TPT PI_NT# T00 TPT PI_NT# T0 TPT PM_LKRUN# PM_LKRUN# 0,0, T0 TPT PI_INT# PI_INT# 0 PI_INT# PI_INT# 0 PI_INT# T0 TPT PI_INT# T0 TPT 0 PF/0V LK_TPMPI 0 PF/0V LK_PI 0 PF/0V LK_IOPI 00 PF/0V PI_LK 0 PF/0V LP_LKEU 0 PF/0V LP_LKE N 00 00.0. 0 0 00 0 0 0 change to pf,optional is N/ internal Pull Up.K PU_PWR HT_PU_PWR +V PM0 Q000 R0 0KOhm R00 KOhm +.V, N_LLOW_LTTOP PU_PROHOT#, PU_LT_TOP# PU_LT_RT# K_XIN X K_XOUT X R0 F LLOW_LTTP F PROHOT# F LT_P LT_TP# LT_RT# 00 0000000 K_XIN K_XOUT LPLK0 LPLK E L0 H L H L J L J LFRME# H LRQ0# H LRQ#/NT#/PIO MREQ#/REQ#/PIO ERIRQ V RTLK INTRUER_LERT# VT LP_LK0_R LP_LK_R PIO R0 R0 TPT T0 TPT T0 TPT T0 INTRUER_LERT# 0 0.UF/0V N 0 UF/.V Ohm LP_LKEU, Ohm LP_LKE,0 LP_0 0,, LP_ 0,, LP_ 0,, LP_ 0,, LP_FRME# 0,, INT_ERIRQ 0,0, RT_LK R0 JRT TPT T0 L_JUMP N +V_RT 00 RF R0 +V_RT R0 MOhm INTRUER_LERT# +V +RTT R0 00 add for safety KOhm 00.0.0 00 R0 optional change to, R0 change to N/ J00 TT_HOLER X00.KHZ PN:0000 N R0 0MOHM 000N R0 0MOHM 0 PF/0V 0 PF/0V _RT# R0.KOhm R00 +VU U00 N V Y N LVW R0 Ohm R0 Ohm N_RT# UF_PLT_RT#,,0,,,,,0 N UTeK.omputer.IN 00_PU/PIE/LP/LK <Orgddr> Z0Z/FTr Wednesday, March, 00 ate: heet of 0 0.

U00, T0 THRMTRIP#_.V 0 0 TPT T0 EXT_MI# EXT_I# 0 PM_U# 0 PM_U# 0 PM_PWRTN#,0 PM_PWROK, U_TT# TPT R 0 0TE_E 0 R_IN#_E, PPE#,, Y_RET# 0 PIE_WKE# THRMTRIP# _N_PWROK PM_RMRT# T TET TET TET0 T0 TPT TPT R0 R0 R0 R0 T0 TPT E E H F H H K H H H Y W K K F J H F J W 00 Part of PI_PME#/EVENT# RI#/EXTEVNT0# ULK/M_M_M_O LP_/PM# LP_# U_ROMP LP_# PWR_TN# PWR_OO U_TT# TET U_FP TET U_FN TET0 0IN/EVENT0# U_FP KRT#/EVENT# U_FN LP_PME#/EVENT# LP_MI#/EXTEVNT# U_HP _TTE/EVENT# U_HN Y_REET#/PM# WKE#/EVENT# U_H0P LINK/PM# U_H0N MLERT#/THRMTRIP#/EVENT# N_PWR U_HP U_HN RMRT# U_HP U_HN E E F E H J0 E F 0 0 U_ROMP R0.KOhm r00_h ULK_ N U_PP U_PN U_PP U_PN U_PP U_PN Finger Printer luetooth TV turner 0 power +V T TPT T0 TPT T0 TPT T0 TPT T0 TPT _PKR,, MLK_RM,, MT_RM 00 R,,, FOR Mbus,, M_LK_,, M_T_ T_ET# 0 _# T TPT T_IO# PIO P_I R T P_I TPT PIO0 R R E W V W0 W W K K 0 Y Y T_I0#/PIO0 LK_REQ#/T_I#/PIO MRTVOLT/T_I#/PIO LK_REQ0#/T_I#/PIO0 LK_REQ#/T_I#/FNOUT /PIO LK_REQ#/T_I#/FNIN /PIO0 PKR/PIO L0/PO0# 0/PO# L/PO# /PO# _L/PIO _/PIO LL#/PIO MRTVOLT/HUTOWN#/PIO R_RT#/EVENT# U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN H E E H H U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN WLN conn. amera U onn -. Newcard U onn -. U onn -. U_TT# R0.KOhm MLK_RM R.kOHM MT_RM R.kOHM U_HP U_HN U_PP U_PN U onn - Up. P_I0 internal pu.k P_I P_I P_I0 res. value 0k ->.k to get LOW level < Vih(.V) 00 R.KOhm R.KOhm R.KOhm T0 TPT U_O# U_O# U_O# U_O0# Z_IN0_U Z_IN_M T TPT T TPT T TPT T Z_LK Z_OUT Z_YN Z_RT# TPT PM# PI_# E F E M M J J L M L M L H H0 H F E E U_O#/IR_TX/EVENT# U_O#/IR_TX0/PM# U_O#/IR_RX0/PM# U_O#/IR_RX/PM# U_O#/PM# U_O#/PM# U_O0#/PM0# Z_ITLK Z_OUT Z_IN0/PIO Z_IN/PIO Z_IN/PIO Z_IN/PIO Z_YN Z_RT# Z_OK_RT#/PM# IM_PIO0 IM_PIO PI_#/IM_PIO IE_RT#/F_RT#/IM_PO IM_PIO IM_PIO IM_PIO IM_PIO U_H0P U_H0N IM_PIO IM_PIO IM_PWM0/IM_PIO0 L/IM_PIO /IM_PIO L_LV/IM_PIO _LV/IM_PIO IM_PWM/IM_PIO IM_PWM/IM_PO IM_PWM/IM_PO IM_PIO IM_PIO IM_PIO0 IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO0 IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO0 IM_PIO F F E0 E E E 0 0 0 0 0 _P _P U_PP0 U_PN0 for strap U onn - own. 00 R,,, FOR Mbus R M_LK_ M_T_ R L M_LK_ R M_T_ R EXT_I# R0 00 change R0 to 00 OPTION TET TET TET0.0 00.0.0 +VU R0 optional change to N/ R R R.kOHM.kOHM.kOHM @.kohm @.kohm @.kohm Follow FZ U 0 U onn - own. U U onn - Up. U U onn -. U U onn -. U Newcard U U onn -. U amera U WLN conn. U N Z_IN0_U R0 0KOhm 00 U TV turner Z_IN_M R0 0KOhm U 0 N +V. U U U Finger Printer luetooth N 00 Z_RT# Z_RT# PUT T 00 IE 0 F0JE R Z_RT#_U_R 00 R 0KOhm R Ohm R Ohm 00 E enable trap Workaround Z_RT#_M Z_RT#_U, R0 0KOhm 0 PF/0V /EMI Z_LK Z_YN Z_OUT R Ohm R Ohm R Ohm R Ohm R0 Ohm R Ohm Z_LK_M Z_LK_U Z_YN_M Z_YN_U Z_OUT_M Z_OUT_U UTeK.omputer.IN 00_PIO/U/H/PI <Orgddr> Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

00.0.0 R0 R0 R0 R R R from.ohm to 0OHM for sata II close sb in 0." U00 for T H for T O for E- T T_TXP0 T_TXN0 T_RXN0 T_RXP0 T_TXP T_TXN T_RXN T_RXP ET_TXP ET_TXN ET_RXN ET_RXP R0 T_TXP0_R R0 T_TXN0_R R0 T_TXP_R R T_TXN_R R T_TXP_R R T_TXN_R Place T_L RE very close to ball of 00 R0 KOhm N % % T_L T_TX0P E T_TX0N 0 T_RX0N 0 T_RX0P E0 T_TXP 0 T_TXN T_RXN E T_RXP T_TXP T_TXN E T_RXN T_RXP T_TXP E T_TXN T_RXN T_RXP E T_TXP T_TXN T_RXN E T_RXP T_TXP T_TXN E T_RXN T_RXP V T_L 00 Part of IE_IORY IE_IRQ IE_0 IE_ IE_ IE_K# IE_RQ IE_IOR# IE_IOW# IE_# IE_# IE_0/PIO IE_/PIO IE_/PIO IE_/PIO IE_/PIO IE_/PIO0 IE_/PIO IE_/PIO IE_/PIO IE_/PIO IE_0/PIO IE_/PIO IE_/PIO IE_/PIO IE_/PIO IE_/PIO0 PI_I/PIO PI_O/PIO PI_LK/PIO PI_HOL#/PIO PI_#/PIO Y Y Y Y E E0 0 E 0 0 E E F F PIO PIO PIO PIO T TPT T0 TPT TV_ON# T_ON# WLN_ON# R0 _ON# R0 PIO0 R RTLN_M# R RTLN_M_EN R WLN_LE_ON R0 TLE_ON R0 TEMPIN_N R +V +VU.kOHM.kOHM 0KOhm 0KOhm 0KOhm N 0KOhm 0KOhm N N_THRM R0 0MOhm X0 Mhz 0 0PF/0V T_X T_X T_LE# PLLV_T XTLV_T 0 0PF/0V Y T_X T_X W T_T#/PIO PLLV_T W XTLV_T LN_RT#/PIO ROM_RT#/PIO FNOUT0/PIO FNOUT/PIO FNOUT/PIO FNIN0/PIO0 FNIN/PIO FNIN/PIO TEMP_OMM TEMPIN0/PIO TEMPIN/PIO TEMPIN/PIO TEMPIN/TLERT#/PIO U J M M M P P R PIO PIO PIO PIO0 PIO PIO WLN_ON# _ON#, TEMP_OMM PIO T TPT TEMPIN_N PIO T0 TPT PIO T TPT P_I0 T TPT T TPT T TPT T TPT T TPT 0.0UF/V TEMP_OMM R R N N_THRM N +.V L0 /00Mhz close to the ball of 00 PLLV_T UF/0V UF/0V 0.UF/0V 00 VIN0/PIO VIN/PIO VIN/PIO VIN/PIO VIN/PIO VIN/PIO VIN/PIO VIN/PIO0 V V F PIO PIO PIO PIO0 T TPT T TPT T TPT V_HWM T TPT 0.UF/V RTLN_M_EN WLN_LE_ON TLE_ON RTLN_M# R0.UF/0V +VU +V XTLV_T L0 N trace at least 0mil N wide /00Mhz close to the ball of 00 UF/0V 0.UF/0V PIO 0 F0JE _RT# 0 00.0.0 add d0 optional is UTeK.omputer.IN 00_PT/T <Orgddr> Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

V R V_VREF VQ_R +V +.V PIE_VR N +.V N N V_T +VU N V_U N V_R +.V +.V +.V_KV VK_.V N N VK_.V +VU +.VLW_R N +.VU +.VLW_R N +.VU +.V_U_PHY_R N N +V +V VK_.V +V N VK_.V +.V_V N +.V_V N N +V +.V_KV +.V_U_PHY_R +VU N ate: heet of Wednesday, March, 00 UTeK.omputer.IN 00_POWER 0. Z0Z/FTr <Orgddr> ate: heet of Wednesday, March, 00 UTeK.omputer.IN 00_POWER 0. Z0Z/FTr <Orgddr> ate: heet of Wednesday, March, 00 UTeK.omputer.IN 00_POWER 0. Z0Z/FTr <Orgddr> IE and Flash Interface Not Implemented: Tied to +.V_0. 0.UF/0V 0.UF/0V UF/0V UF/0V UF/0V UF/0V 0 0.UF/0V 0 0.UF/0V L0 /00Mhz L0 /00Mhz L0 /00Mhz L0 /00Mhz 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V UF/0V UF/0V 0 TW 0 TW 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V UF/0V UF/0V 0 UF/.V 0 UF/.V UF/0V UF/0V 0 UF/0V 0 UF/0V 0UF/.V 0UF/.V 0.UF/0V 0.UF/0V V_ V_ V_ M V_0 K V_ L V_ V_ L V_ K V_ K V_ V_ L0 V_ L V_ L V_ L V_ M V_ M0 V_0 M V_ M V_ N V_ P V_ P V_ P0 V_ P V_ R V_ R V_ R V_ R0 V_ R V_ V_ R V_0 P V_T_ V_T_ V_T_ V V_T_ Y V_T_ V_ P V_ N V_T_ V_T_ U0 V_T_ U V_T_ T0 V_T_ V_T_ U V_T_ V_T_ V V_T_0 Y V_T_ W V_T_ Y V_T_ V_T_0 E V_T_ V_U_ V_U_ V_U_ V_U_ V_U_ V_U_ V_U_ V_U_ K0 V_U_0 E V_U_0 J V_U_ K V_U_ F V_U_ F V_U_ K V_U_ J V_U_ H V_U_ J V_U_ H V_U_ V_U_ K V_ L V_U_ J V_U_ J V_ H V_ N V_ V_U_ V_U_ VK L PIE_K_V_ J PIE_K_V_ U0 PIE_K_V_ U PIE_K_V_ T PIE_K_V_ W PIE_K_V_ M PIE_K_V_ R PIE_K_V_ P PIE_K_V_ M PIE_K_V_ V PIE_K_V_ V0 PIE_K_V_ V V_0 E PIE_K_V_ W PIE_K_V_ W PIE_K_V_0 W V F PIE_K_V_ J PIE_K_V_ H PIE_K_V_ K V_ F0 PIE_K_V_ M PIE_K_V_ P PIE_K_V_0 R V_ E V_ V V_ Y V_ U V_ V_ V_ T V_ U V_ R V_ T V_0 T V_T_ Y 00 Part of U00E 00 00 Part of U00E 00 UF/.V UF/.V UF/0V UF/0V R0 R0 L0 /00Mhz L0 /00Mhz 0.UF/0V 0.UF/0V R0 KOhm R0 KOhm UF/0V UF/0V L0 /00Mhz L0 /00Mhz UF/0V UF/0V.UF/.V.UF/.V R0 R0 UF/.V UF/.V 0.UF/0V 0.UF/0V L0 /00Mhz L0 /00Mhz UF/.V UF/.V UF/0V UF/0V R0 R0 UF/.V UF/.V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V R0 R0 0.UF/0V 0.UF/0V L0 /00Mhz L0 /00Mhz VQ_ M VQ_ U VQ_ T VQ_ VQ_ L VQ_ U VQ_ U VQ_ VQ_0 VQ_ V VQ_ W VQ_ Y _.V.V.V.V_ J _.V_ J _.V.V_ U_PHY_.V_ 0 U_PHY_.V_ 0 V_VREF E VK_.V J VK_.V K V E VTX_0 VTX_ VTX_ VTX_ VTX_ E VTX_ VRX_ F VRX_0 F VRX_ VRX_ PIE_VR_ P PIE_VR_ P0 PIE_VR_ R PIE_VR_ P PIE_VR_ R PIE_VR_ P PIE_VR_ R V_T_ V_T_ V_T_ V_T_ V_T_ V_T_ V_T_ E V_ L V_ M V_ M V_ N V_ P V_ P V_ R V_ T V_ R VRX_ F VRX_ V V E V V Y0 KV_.V_ L KV_.V_ L KV_.V_ L KV_.V_ L _.V_ L _.V_ L Part of 00 POWER U00 00 Part of 00 POWER U00 00 0 0.UF/0V 0 0.UF/0V UF/.V UF/.V 0 0UF/.V 0 0UF/.V 0.UF/0V 0.UF/0V 0 UF/.V 0 UF/.V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0 UF/.V 0 UF/.V UF/.V UF/.V 0UF/.V 0UF/.V 0.UF/0V 0.UF/0V R0 r00_h R0 r00_h 0 UF/.V 0 UF/.V UF/0V UF/0V UF/.V UF/.V 0.UF/0V 0.UF/0V L0 /00Mhz L0 /00Mhz UF/.V UF/.V.UF/.V.UF/.V UF/0V UF/0V 0.UF/0V 0.UF/0V UF/0V UF/0V 0 UF/.V 0 UF/.V 0.UF/0V 0.UF/0V.UF/.V.UF/.V 0.UF/0V 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V

NOTE: 00 H INTERNL K PULL UP REITOR FOR RT_LK +V +V +V +V +VU +VU +VU +VU +VU +VU R0 0KOhm R0 0KOhm R0 0KOhm R0 0KOhm R0 0KOhm R0 0KOhm R0 0KOhm R0 0KOhm R.kOHM R.kOHM (PI_LK) 0 LK_IOPI 0, PI_LK 0 PI_LK 0 PI_LK 0, LP_LKEU 0,0 LP_LKE 0 RT_LK Z_RT# _P _P 00 REQUIRE TRP R0 R R R R R R R R0 0KOhm 0KOhm.kOHM 0KOhm 0KOhm 0KOhm.kOHM 0KOhm.kOHM EXT N N N N N N N N N R0.kOHM N PI_LK PI_LK PI_LK PI_LK LP_LKEU LP_LKE RT_LK Z_RT# P P PULL HIH OOTFIL TIMER ENLE UE EU TRP REERVE REERVE ENLE PI MEM OOT LKEN ENLE INTERNL RT EFULT E ENLE H,H = Reserved H,L = PI ROM PULL LOW OOTFIL TIMER ILE EFULT INORE EU TRP EFULT ILE PI MEM OOT EFULT LKEN ILE EFULT EXT. RT (P on X, apply KHz to RT_LK) E ILE EFULT L,H = LP ROM (efault) L,L = FWH ROM WITH 00, TRP PIN FOR MEM OOT N E ENLE WPE. I.E. LP_LK0 FOR E ENLE, Z_RT# FOR MEM OOT ENLE. UTeK.omputer.IN 00_TRP <Orgddr> Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

UTeK OMPUTER IN. N <Orgddr> Z0Z/FTr ate: Wednesday, March, 00 heet of 0.

UTeK OMPUTER IN LNK Z0Z/FTr ate: Wednesday, March, 00 heet of 0.

UTeK OMPUTER IN LNK Z0Z/FTr ate: Wednesday, March, 00 heet of 0.

UTeK OMPUTER IN LNK Z0Z/FTr ate: Wednesday, March, 00 heet of 0.

+.V_LK 00 HNE TO 0PF 0 0 N 00.0.0 HNE TO PF PF/0V X0 R0.Mhz 0MOhm PF/0V XTL_LK XTL_LK ULK_ N_O EL_HTT R0 0KOhm R0 0KOhm R0 R 0KOhm 0KOhm LN_LKREQ# WLN_LKREQ# LK_NEWR_REQ# P# EL_ EL_HTT 0 0 00 MHz differential pread R clock MHz.V MHz spread clock 00 MHz differential HTT clock MHz.V single ended HTT clock IO-.Mhz 00.0.0 del R0 0PF/0V /EMI 0PF/0V /EMI 0 0PF/0V /EMI +.V_LK +.V_LK N-.Mhz 00 R 0 N R0 R N_O VREF_LK.KOhm.KOhm VU_LK +.V_LK R 0 U0 EL_HTT EL_ EL_ ET_T REF/EL_ VREF EL_HTT REF/EL_T VHTT REF0/EL_HTT HTT0T_LPR/M R R_N_HT_LKP R_N_HT_LKN N XTL_LK NREF HTT0_LPR/M R N-HT R XTL_LK X NHTT R P# X P#.KOhm V PUK0T_LPR 0 R.KOhm R_PU_HT_LKP R0 ULK_ Ohm MHz_0 PUK0_LPR R R_PU_HT_LKN PU N VPU,, MLK_RM 0 MLK NPU,, MT_RM MT LKREQ#* LK_NEWR_REQ# V_LK V_LK LN_LKREQ# V V N N R 0 LK_TI R_LPR/MHz_N N R WLN_LKREQ# 0 LK_TI RT_LPR/MHz_ N PIE P0: Minicard N V R0 WLN_LKREQ# LK_PIE_WLN# R_LPR LKREQ#* R0 LK_PIE_WLN RT_LPR _R0T_LPR 0 R R_N_PIE_RLKP R_N_PIE_RLKN N-PI-E,-Link R0 NR _R0_LPR PIE P: Minicard R0 R0 VR V_R change.k->.k R LK_PIE_TV# 0 R_LPR N_R R LK_PIE_TV R PIE_RLKP 0 RT_LPR _RT_LPR R VR _R_LPR R PIE_RLKN 0 PIE P: Newcard R NR TI0T_LPR R R_N_FX_REFLKP R R LK_PIE_NEWR# R_LPR TI0_LPR R_N_FX_REFLKN N-FX R LK_PIE_NEWR RT_LPR VTI N N R LK_PIE_LN# R LK_PIE_LN R0_LPR NTI LK_PIE_PE 0 LN_LKREQ# R0T_LPR TIT_LPR 0 R *LKREQ0# TI_LPR LK_PIE_PE# 0 MXM-FX PIE P: LN R ILPRLFT N +.V_LK N 0 FOR EMI +V +V L0 0/00Mhz 0 0.UF/V 0 0.UF/V +.V_LK 0.UF/V 0.UF/V +V VU_LK +V VREF_LK +V L0 L0 0/00Mhz 0/00Mhz 0 0 0 0.UF/0V 0.UF/V.UF/0V 0.UF/V L0 0/00Mhz 0 UF/.V V_LK 0 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V /EMI /EMI /EMI /EMI N N N N N N N N N N +.V_LK N UF/.V 0.UF/V 0.UF/V 0.UF/V 0.UF/V <Variant Name> N N N N N ILPRLFT UTeK OMPUTER IN Richard_Lu ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

For IT Power +V_E +VPLL +V_E +VPLL +V +V +V L00 /00Mhz +V_E +V_E 00 0UF/0V 00 0.UF/0V 00 0.UF/0V 00 0UF/0V R00 r00_h 00 0.UF/0V 0,, 0,, 0,, 0,, E# K I O LP_0 LP_ LP_ LP_ 0, 0,, 0,0, INT_ERIRQ EXT_MI# EXT_I# R00 R0 R0 att Thermal sensor T0 PM_PWROK_E OHM RNX00 OHM RNX00 OHM RNX00 OHM RNX00 LP_LKE LP_FRME# UF_PLT_RT#_E LUETOOTH# WLN# MRTHON# 0 M0_LK 0 M0_T 0,0 M_LK 0,0 M_T THRO_PU RX0 TEL_P# L_L_ 0TE R_IN# E_RT# Ohm Ohm Ohm T0 TP_LK TP_T T0 KI0 KI KI KI KI KI KI KI KO0 KO KO KO KO KO KO KO KO KO KO0 KO KO KO KO KO E_LK_EN E#_E K_E I_E E_XIN E_XOUT RX0 T0 LUETOOTH# T0 T0 ITP# 0 0 0 0 0 00 0 0 0 U00 L0 L L L LPLK LFRME# LPRT#/WUI/P ERIRQ EMI#/P EI#/P 0/P KRT#/P WRT# E# K I O KI0/T# KI/F# KI/INIT# KI/LIN# KI KI KI KI KO0/P0 KO/P KO/P KO/P KO/P KO/P KO/P KO/P KO/K# KO/UY KO0/PE KO/ERR# KO/LT KO KO KO KK KKE RX0/P0 TX0/P PLK0/PF0 PT0/PF PLK/PF PT/PF PLK/PF PT/PF MLK0/P MT0/P MLK/P MT/P MLK/PF MT/PF 0/PJ0 /PJ /PJ /PJ /PJ /PJ ITE_L 00 FOR x 00 FOR x N 0 UF/0V 00 0.UF/V E# O N E_N R0 Ohm KO/P TMRI0/WUI/P KO/P TMRI/WUI/P PWUREQ#/P +V_PI 0/PI0 /PI /PI /PI /PI /PI /PI /PI PWM0/P0 PWM/P PWM/P PWM/P PWM/P PWM/P PWM/P PWM/P RX/P0 TX/P RIN#/PWRFIL#/LPRT#/P RI#/WUI0/P0 RI#/WUI/P INT/P TH0/P TH/P L0HLT/PE0 E/PE E#/PE ELK/PE PWRW/PE WUI/PE LPP#/WUI/PE L0LLT/PE LKRUN#/PH0/I0 RX/PH/I TX/PH/I PH/I PH/I PH/I PH/I R0.KOhm O_ROM ROM_WP# 0 0 0 WUI/P0/TM P/I P P WUI/PK0 WUI/PK WUI0/PK WUI/PK WUI/PK WUI/PK WUI/PK WUI/PK PL0 PL PL PL PL PL_ PL_ PL 0 0 0 0 0 0 0 0 R0 U00 K_I0 K_I T0 T00 T00 T00 OLOREN# T0 T00 T00 T0 T0 T00 T0 T0 T0 T0 P_K# IR_TX0_ET# IR_TX_ET# T0 K_I0 K_I T00 E_LPRT_TE# T0 T0 TVF00 (Mb) T0 T0 T0 E# V O HOL# WP# K V I T0 T0 T0 ROM_H# NV_OVERT# NV_OVERT# 0,0 U_PWR LL_YTEM_PWR PUPWR_,, T0 T0 PWR_LE# H_LE# L_L_PWM FN0_PWM 0 H_EN# PREH PM_PWRTN# _IN_O# OP_# T_IN_O# RF_ON_W# PWRLIMIT#, PM_U# L_KOFF# FN0_TH 0 OLOREN# VU_ON, U_E# U_E#,, PU_VRON PWR_W#_E LI_W#,, INTNT_ON# PM_THERM#_E PM_U# PM_LKRUN# 0,0, T_LERN NUM_LE# P_LE# +V_PI K I R0.KOhm PM_RMRT#_E T0 R0 0 0.UF/V +V_E For PU / P +V_E +VU +V R00 R0 R00 R00 RN00 R0 R00 R0 R0 R0 R0 RN00 RN00 RN00 RN00 RN00 RN00 RN00 R0 R0 R0 R00 R00 PM_U# PM_U# U_E# U_E# For X'tal 0KOhm E_XIN l00 Irat=00m N _IN_O# T_IN_O# M0_LK M0_T IR_TX0_ET# IR_TX_ET# P_K# PWRLIMIT# hange pull up resistor from 0K to K ohm 0KOhm KOhm.KOhm.KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm.KOHM.KOHM.KOHM.KOHM 0 PF/0V KOhm 0KOhm 0KOhm 0KOhm.KOhm.KOhm PM_PWRTN# U_PWR 0TE R_IN# TP_T TP_LK NV_OVERT# K_I0 K_I M_LK M_T RN00 00KOhm RN00 00KOhm RN00 00KOhm RN00 00KOhm.KOhm R0.KOhm R00 R0 0MOhm X00.KHz +/-0ppm/.PF Note: load=.pf place close to E E_XOUT R0 0 PF/0V R00,,, +V +V_E E_N THERML_TRIP# FORE_OFF# 0 +V For E Reset O#_O +V_E OLOREN# MRTHON# LUETOOTH# WLN# ITP# For E Hardware trap INTNT_ON# +V E_N E_RT# For Instant el OLOREN# Key Pin at RN00 0 Note: lose to E R0 I/O ase ddress hare Memory PP Enable from Reset W 0.UF/.V Note: It can be programmable by E fireware Note: It can be programmable by E fireware. Note: efault Int. Pull-Low Note: close to the WRT# (ITE pin) R0 0KOhm RN00 0KOhm RN00 0KOhm RN00 0KOhm RN00 0KOhm 0KOhm 00 0.UF/0V R0 00 R00 r00_h R0 U00 RT/OUT N 00 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V E Reset kts: Option : Mount U00,00,0 NI: 00,00,R0,R0 Option : Mount 00,00,R0,R0 NI: U00, 00, 0 N00 Q00 0KOhm 00.UF/0V For imt pin name V/V N RNV0 00 0.UF/0V _PREENT PM TTE# _TTE_ON PM_LP_M# LP_M_ON E_WLN_PWR MP_PWR _PREENT LN_WOL_EN +VM_P +.VM_+VMLK_P UPWR_K N00 Q00 E_RT# R0 0KOhm 00 0.UF/0V +V_E +V 00 to meet T>ns E heck ( uto oot Issue) Reserve for current leakage issue (Reference to FR) 0TE_E +V Q00 0TE E_LPRT_TE# +V R0 0KOhm UF_PLT_RT#_E PM_RMRT# PM_RMRT#_E R0 R0 U_PWR 00 KOhm 0 UF/0V N/ UMKN R00 Ohm,,0,,,,,0 UF_PLT_RT# Q00, PM_PWROK 00 PM_PWROK_E R0 +V R0 +V R0 0KOhm R_IN#_E Q00 R_IN# R0 00KOhm Q00 N00 PM_PWROK_E Reserve "uto power on" solution for TI hipset UMKN R00 Ohm Q00 N00 U_PWR UTeK OMPUTER IN. N E_IT (/) <Orgddr> ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0 0.

Touch Pad +V L00 /00Mhz TP_W_L 0 W00 TP_W_R 0 W0 J0 IE 0 IE 0 0 0.UF/V L0 /00Mhz L0 /00Mhz TP_W_L TP_W_R 00PF/0V TP_T 0 TP_LK 0 TT_WITH_P 00PF/0V TT_WITH_P FP_ON_P 00 For witch PWR WITH +V_E R0 0KOhm 0 PWR_W#_E PWR_W# R0 0KOhm 0 0.0UF/V Layout note:close to IT J0 LI WITH +V_E R0 0KOhm 0,, LI_W# LIW# R0 0KOhm 0 Layout note:close to IT 0.0UF/V +V_E LIW# close to connector Note: 0 LI_W# is easy to cause high voltage damage when V plugging inverter board connector to M/ with present. Need to add bidirectional diode to protect this pin. KT KT0 Matrix U 0 UK 0 JP IE 0 0 IE 0 0 0 KI KO KI KO0 KI KO KI KO KI KO KI KI KO KO KI0 KO KO KO KO KO KO0 KO KO KO K_I0 K_I KI 0 KO 0 KI 0 KO0 0 KI 0 KO 0 KI 0 KO 0 KI 0 KO 0 KI 0 KI 0 KO 0 KO 0 KI0 0 KO 0 KO 0 KO 0 KO 0 KO 0 KO0 0 KO 0 KO 0 KO 0 K_I0 0 K_I 0 FP_ON_P +V THERML_TRIP# 0 R0 00KOHM 00 cap for 0,, PUPWR_, THRMTRIP#_.V PU/N THERMTRIP# 0 R0 Q0 N00 Q0 PM0 E / / / / / / / / / / / / / / // // / / / / / / / UTeK OMPUTER IN. N E_IT (/) <Orgddr> ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

UTeK OMPUTER IN LNK Z0Z/FTr ate: Wednesday, March, 00 heet of 0.

0 mil +V close to pin within 00 mil R0 r00_h +VR R0 ENR +V 0 0UF/0V 0 0.UF/0V close to pin XIN_LN XOUT_LN +V +V +V +V.KOhm R0 U0 +V_LN +V +V R0 RTLN_M# RTLN_M_EN +VU L0 /00Mhz l00_h Irat= 0 mil 0 UF/.V +V +V L_TP L_TN L_RP L_RN L_TRP L_TRM L_TRP L_TRM ROUT +V F 0 ROUT V_ MIP0 MIN0 F MIP MIN V_ MIP MIN V_ MIP MIN V_ N V_ RTL_V_R EEK EEI/UX V_ EEO EE V_ N N 0 N N V_ V_ IOLTE N N LKREQ EEK EEI EEO EE LKREQ R0 R0 Q0 N00 +V R0 KOhm R0 KOhm R0 KOhm U_E# 0,, close to pin with in 00 mil please change:00x.uh/0% N R0 0mil N +V 0 0 0.UF/0V 0.UF/0V N +V +EV,, PIE_WKE# R,,0,0,,,,0 UF_PLT_RT# R 0,0,, PI_RT# without R, 0u leakage when R KOhm close to LN HIP N_N_ LN_TXN_ X 0.UF/0V LN_TXP_ X 0.UF/0V PIE_RXN_LN PIE_RXP_LN LK_PIE_LN# LK_PIE_LN PIE_TXN_LN PIE_TXP_LN )/PLTRT# and RTL are in Vccus_ well )PLTRT# will be low before PM_U# go low N be high after PM_U# go high )UF_PLT_RT# could be or 0 pwr well.uh L0 ROUT R F +V._LN F F close to pin with in 00 mil E0 UF/V close to L0 with in 00 mil 0 mil + 0.UF/0V L0 /00Mhz +V l00_h Irat= 0 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V N +EV L0 N /00Mhz l00_h Irat= 0.UF/0V 0.UF/0V 0mil R r00_h N_N_L N_N_ +V +V R.KOhm +V XIN_LN XOUT_LN PF/0V X0 Mhz PF/0V N_N_ R EE EEK EEI EEO U0 K I O T V OR N 0.UF/0V N <Variant Name> UTeK OMPUTER IN N igaln ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

0 have issue after IR reflow, alternative part:l-0- U00 TT MT L_MT L_TRM T+ MX+ L_TRLM L_TXN RN0 LTXN 00 0.0UF/0V L_TRP L_TRM L_TRP L_RN L_RP L_TN L_TP 0 0 0.0UF/0V 0.0UF/0V MX- T- TT T+ T- TT T+ T- TT 0 T+ T- L_0_ 0 0.0UF/0V L_MT L_MT L_MT L_MT0 0 Transformer close ON MX+ MX+ MX+ MX-L_TRLP MT L_MT MX- MT MX- MT L_TRLM L_TRLP L_MT L_RXN L_RXP L_MT0 L_TXN L_TXP L_TXP L_RXN L_RXP L_TXN L_TXP L_RXP L_RXN L_TRLP L_TRLM L_TRLM L_TRLM L_TRLP RN0 RN0 RN0 /00Mhz LTXP LRXP /00Mhz LRXN LTRLP /00Mhz LTRLM L_TRLP RN0 LTRLP Ohm RN00 Ohm RN00 L_TRLM RN0 LTRLM Ohm RN00 Ohm RN00 FN L_TRLP RN0 LTRLP L00 L0 L0 L0 LTXN LTRLM /00Mhz LTRLP RN0 LTXP LRXN LRXP LTRLM FOR EMI o-layout LTRLM LTRLP LRXN LTRLM LTRLP LRXP LTXN LTXP TIP RIN L0 KOhm/00Mhz L0 KOhm/00Mhz 0 0 000PF/KV J00 0 IE P_N NP_N NP_N P_N IE MOULR_JK_P 0 J0 IE IE WTO_ON_P 000PF/KV PF/0V PF/0V WWN PF/0V PF/0V R00 0 00PF/KV LN FOR EMI o-layout Modem 00.0. add 0 0 optional is P M P P0 M M P M0 RingTip <Variant Name> ustom RJ+ UTeK OMPUTER IN Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

ZLI M onnector +V Z_OUT_M Z_YN_M Z_IN_M Z_RT#_M R0 J0 RX0 Ohm 0 0 0 0.UF/0V TO_ON_P Z_LK_M UTeK OMPUTER IN M Z0Z/FTr ate: Wednesday, March, 00 heet of 0.

00 N MI_VREFOUT_L MI_VREFOUT VREF_OE 00 R00 MOUNT.K FOR L 0000 MOUNT.K FOR L 00.UF/V N_UIO / _HP_R_OE _HP_L_OE 0 0UF/0V PF/0V MI_VREFOUT_L 0 0UF/0V PF/0V 0 0UF/.V c00 0 0.UF/V c00 _OUT_L _OUT_R.KOhm 00 HP_J R00 ENE HP_J / % UF/V UF/V X R0 X FRONT-L R0 FRONT-R X UF/V X UF/V E.ER R0 R0 0KOhm 0KOhm % % N_UIO N_UIO +V_UIO.UF/V 0 0 / UF/V 0.UF/V c00_h c00 N_UIO N_UIO U0 L-R LINE_VREFOUT_OE X N_UIO // UF/0V N_UIO N_UIO 00 LINE_R R PIF_OUT N_UIO +V_UIO R0 0KOhm % 0 T0 T0 N_UIO T0 MI_LK EPOP# EPOP# MONO-OUT V URR-L(PORT--L) JREF URR-R(PORT--R) V ENTER(PORT--L) LFE(PORT--R) PIFO MI-LK/ EP PIFO LINE-R(PORT--R) LINE-L(PORT--L) MI-R(PORT--R) MI-L(PORT--L) LINE-VREFO 0 MI-VREFO LINE-VREFO MI-R(PORT-F-R) MI-L(PORT-F-L) LINE-R(PORT-E-R) LINE-L(PORT-E-L) ense LINE_VREFOUT_OE X // X UF/0V //X UF/0V X0 UF/0V X0 UF/0V LINE_VREFOUT_OE MI_VREFOUT_OE LINE_VREFOUT_OE X UF/0V X UF/0V LINE_R LINE_L MI_J 0KOhm R % // UF/0V MI_JK R _PKP MI_JK INTMI_P MI_LK _HP_R_OE _HP_L_OE LINE_L / R R0 R / / / _HP_R _HP_L 00PF/0V ense MI ense HP /MI N R N +V_OE 00 0_MUTE# MI_VREFOUT_OE X // UF/0V / UF/0V _PKN MI_VREFOUT_OE / R / MI_VREFOUT Z_OUT_U Z_LK_U PF/0V R / Z_IN0_U Z_YN_U, Z_RT#_U RX Ohm N_UIO P_EEP INTMI_N N/MI R N_UIO R 0_MUTE# /MI/ R0 R0 R +V U00 No symbol in data base, modify manually UF/V c00_h 0.UF/0V HN# ET N IN OUT -0TUF 0000 R L00 000PF/0V R 00KOhm UF/V c00_h +V_UIO /00Mhz 0.UF/0V 0.UF/V c00 0.UF/V c00 _PKR 0 0.UF/V c00 R KOHM R0.KOHM 0.UF/V c00 P_EEP 00PF/V N_UIO N N N N N diust able Vout=.*(+(00K/K)) N_UIO N_UIO N_UIO +V L0 /00Mhz +V_OE PIF_J# R % ENE 0KOhm <Variant Name> 000PF/0V 0 000PF/0V UF/V UF/V UTeK OMPUTER IN OE-L0 N N N N ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

R00.KOhm MI_VREFOUT Internal MI J00 INTMI_P MI_JK 00 +V_UIO IE INTMI_N 00 IE 00PF/0V N_UIO Wto_ON_P N_UIO MI_VREFOUT_L R0 / INT_MI_JK To external JK 0 00PF/0V / N_UIO R / MI_JK R R0.KOhm KOhm 0 MI_VREFOUT_L % / R0 EXT_MI_JK 0 00PF/0V R0 +V_UIO R0 0KOhm / R0 0KOhm / +V_UIO 0 0.UF/V / + N_UIO - U00 0 LMMX UF/V / / +V_UIO N_UIO N_UIO N_UIO U00 LMMX / + - N_UIO R 00KOHM / 0 00PF/0V / R0 0KOhm / R0 0KOhm / 0 UF/V / R0.KOhm / EXT_MI_JK R.KOHM R.KOHM N_UIO _MI_P R / R 0 0.UF/V c00.kohm Reserved the external MI bias(t filter). N_UIO R0 MI_J MI_J_JK UTeK OMPUTER IN UIO-MI ustom Z0Z/FTr ate: Wednesday, March, 00 heet of 0.

V_MP R00 0KOhm r00 JK_W# LY_OP_E# MP_HN Q00 N00 Q0 N00 V_MP R 0KOhm MP_HN# Q0 N00, Z_RT#_U 0 OP_# 0_MUTE# EPOP# R0 +V MOhm r00_h R0 +V 00KOhm R0 +V 00KOhm r00 LY_OP_E# R0 0 TW 0 Q0 N00 R0 Q0 N00 ER_POP REERVE FOR R ELY TO MUTE POP. 00 UF/V _HP_L _HP_R Q0 N00 Q0 Q0 N00 Q0 ER_POP ER_POP FL FR 00 EPOP E00 N00 N00 R0 00KOhm JK_W# V_MP V_MP Q0 PM0 R0 R0 00KOhm +V 0 0.UF/V 0KOhm R0 Q0 PM0 V_PIF PIF_OUT V_PIF L0 /00Mhz 0 0.UF/V c00 L0 mil width 0 0.UF/V c00 0 00PF/0V OPTI_V_JK PIF_O_JK FL FR without blocking capacitors / uf/.v R R E0 / uf/.v / / / R 0KOhm N_UIO / R 0KOhm R Ohm / / R Ohm L0 /00Mhz L0 /00Mhz 0 c00 0.0UF/V 00 N_UIO R,R /ohm for /ohm for on demo sch 0 0.0UF/V c00 HP_JK_L HP_JK_R N_UIO JK_W# JK_W# 00.0.0 R R optional to / PIF_J# V_MP R 0KOhm R 0KOhm PV_MP 0 0.UF/V V_MP L0 L0 /00Mhz /00Mhz 0 0 UF/V UF/V c00_h c00_h +V V_PIF 0KOhm R Q N00 N_UIO R 0KOhm R 0KOhm IN0 IN _OUT_L N_UIO 0 0.UF/V N_UIO 0.UF/V PV_MP INTPKL+ N_UIO 0.UF/V N_UIO N_UIO 0 N_UIO U0 INTPKR- INTPKR+ INTPKL- INTPKL+ N IN0 IN LOUT+ LIN- PV RIN+ LOUT- LIN+ YP FU N_UIO N N 0 HUTOWN# ROUT+ RIN- V PV ROUT- N N N N_UIO MP_HN# INTPKR+ V_MP IN0IN 0 0 0 0 v(inv) d 0 d. d. d _OUT_R N_UIO INTPKL- INTPKR- L0 L0 L0 L0 <Variant Name> UTeK OMPUTER IN PKR-_M_ON PKR+_M_ON PKL-_M_ON PKL+_M_ON UIO-OP /00Mhz /00Mhz /00Mhz /00Mhz Z0Z/FTr Wednesday, March, 00 ate: heet of J0 N N Wto_ON_P 0.

UTeK OMPUTER IN LNK Z0Z/FTr ate: Wednesday, March, 00 heet of 0.

+V 00 00 00 000 0UF/.V 0.0UF/V 0.0UF/V 0.0UF/V +V U00 +V 00 0UF/.V 00 0.UF/0V 00 0.0UF/V 0 0 V_PIV_ V_PIV_ V_PIV_ V_PIV_ V_PIV_ V_PIV_ V_V 00 0.0UF/V 00 0UF/.V V_RIN 00 0.0UF/V 00 0.0UF/V 0 0.UF/V 0 0.UF/V 0 V_ROUT V_ROUT V_ROUT V_ROUT V_ROUT V_M PI_ +V --> _RT# ms < T < 00ms R00 0 0 R00 00KOhm PI_[0..] +V _IEL 0 0 0 0 0 0,,, PI_PR PI_/E# PI_/E# PI_/E# PI_/E#0 0 PI_REQ#0 0 PI_NT#0 0 PI_FRME# 0 PI_IRY# 0 PI_TRY# 0 PI_EVEL# 0 PI_TOP# 0 PI_PERR# 0 PI_ERR# _RET# PI_RT# PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 _IEL 0 0 0 0 0 0 0 PR /E# /E# /E# /E0# IEL REQ# NT# FRME# IRY# TRY# EVEL# TOP# PERR# ERR# RT# PIRT# N N N N N N N N N N0 N N 0 N 0 N 0 N HWPN# MEN XEN UIO UIO UIO UIO UIO 0 UIO0/RIRQ# INT# INT# +V R000 0KOhm 00 _UP# 0KOhm +V R00 0KOhm R00 +V R00 0KOhm R00 00KOhm UIO UIO INT_ERIRQ 0,0, PI_INT# 0 PI_INT# 0 _# R00 0KOhm N/ R00 0KOhm N/ +V erial EEPROM 0 0.UF/0V U000 N/ V 0 WP L N T0N N/ 0 UF/.V 00 change to uf 0,0, 0 PM_LKRUN# LK_PI R0 R0 00KOhm PILK 0 PME# LKRUN# R_TQFP TET R00 00KOhm <Variant Name> UTeK OMPUTER IN RIOH R/PI_ ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0 0.

+V U00 0 0 L00 /00Mhz 0 as close as possible to R 00 PF/V X00 PF/V 0 R : 0=0.0u R : 0= No stuff 0 _FILO 0.0UF/V.Mhz _REXT R00 0KOhm % 0 XI XO FIL0 REXT V_PHYV_ V_PHYV_ V_PHYV_ V_PHYV_ TPI0 TPN0 TPP0 TPN0 TPP0 0 0 0 0 0 0 0.0UF/V 0.UF/0V 0UF/.V LOE POILE TO R/ 0 0.0UF/V R0 R0 Ohm Ohm 0 0.UF/0V TP0- TP0+ TP0- TP0+ 0 R0 R0 0PF/0V Ohm Ohm remove for X0Z LOE POILE TO ONNETOR. R0 R0 L0 ommon hoke IEEE.R R0 R0 TP0-_ TP0+_ TP0-_ TP0+_ TP0-_ TP0+_ TP0-_ TP0+_ 0 _VREF 00 0.0UF/V VREF R0.KOhm ircuit area : s small as possible. MIO MIO MIO MIO MIO MIO MIO MIO0 MIO0 0 MIO_XT MIO_XT MIO_XT MIO_XT /MT /MT /MT /MT0 MIO0_XWP# MIO0--> xe# MIO0--> Power ontrol / xwp MIO0--> x/m/ LE ontrol MIO--> x ata MIO--> x ata MIO--> x ata MIO--> x ata MIO--> x LE MIO--> x LE MIO0 MIO MIO MIO0 R M_M_XWE# MIO_XLE MIO_XLE MIO0_XE# uard N & dd R0 pin for damping. MIO0--> M ard etect MIO0--> Write Protect MIO0--> ard Power0 ontrol/ M Power ontrol RV MIO0 MIO00 MIO0 MIO0 MIO0 MIO0 MIO0 0 MIO0 T00 TPT WP_XR/# # M# /MLK_XRE# /MPWR MIO0--> External lock/ M External lock MIO0--> ommand/m us tate MIO0--> lock/m lock MIO0--> ata 0/M ata 0 MIO--> ata /M ata MIO--> ata /M ata MIO--> ata /M ata R_TQFP <Variant Name> UTeK OMPUTER IN RIOH R/PI_ ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

+V Q00 IRLML0PF To correct the problem when M uo adaptor is in use. R0 R00 0KOhm 00 0.0UF/V +M_V Place as close to card 0 reader socket as possible 0.UF/0V 0 0.0UF/V XR X_V Place as close to card reader 0 socket as 0.UF/0V XR possible /MPWR Q0 N00 remove ard Reader ocket for X0Z M# # WP_XR/# +M_V J0 NP_N _T /MT T M_M_XWE# /T M V M0 V M /MLK_XRE# V M /MT LK M Reserved M /MT IN M /MT0 Reserved M /MT IO M M_M_XWE# V M M V /MLK_XRE# V LK /MT0 V _T T0 T 0 NP_N 0.UF/V N _R_P # WP_XR/# M# +V X_V R0 0KOhm N X X_# X0 WP_XR/# R/- X /MLK_XRE# -RE X MIO0_XE# -E X MIO_XLE LE X MIO_XLE LE X M_M_XWE# -WE X MIO0_XWP# -WP X N X /MT0 0 X0 /MT X /MT X /MT X MIO_XT X MIO_XT X MIO_XT X X MIO_XT V X 0.UF/V N N Layout: HIEL N 0PF/0V c00 N /MLK_XRE# MIO0_XE# MIO_XLE MIO_XLE M_M_XWE# MIO0_XWP# /MT0 /MT /MT /MT MIO_XT MIO_XT MIO_XT MIO_XT +M_V /MT /MT # M# Q0 N00 0 T Q0 N00 X_# olve M uo daptor short problem _T _T Q N00 X_V 0PF/0V c00 0 0PF/0V c00 00PF/0V c00 +V R0 R0 0KOhm 0KOhm _ X_ 00000 N N # Q N00 X_# Q N00 0 FOR EMI +M_V +V H00 EMI_PRIN_P WWN N N No support X ard, don't need add this part. 0 0.0UF/V XR 0 0.0UF/V XR 0 0.0UF/V XR R0 0KOhm +V 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V H0 EMI_PRIN_P <Variant Name> UTeK OMPUTER IN ardreader ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

hange RIOH R as nd source and Winbond WLY (000000) put on st source. R0 U_PN UP- +VU +V +.V 0, VU_ON R0 0,, U_E#,,0,0,,,,0 UF_PLT_RT# 00 R0 00.0.0 R0 optionsl change to U0 UXIN.VIN N.VIN N 0 HN# TY# YRT# N N WLY UXOUT.VOUT N.VOUT N PERT# PPE# 0 PU# O# N RLKEN +V_PE +V_PE +.V_PE R00 KOhm PERT# PPE# PU# PERT# PPE#, U_O# U_PP R0!! Expressard tandard.0: hange Pin from REERVE to MLK hange Pin from MLK to MT hange Pin from MT to +.V L /00Mhz UP+ 0 0 J00 LP_FRME#_R M_LK_ M_T_ PIE_WKE#_ PERT# UP- UP+ PU# LP_FRME#_R M_LK_ M_T_ +.V_PE PIE_WKE#_ +V_PE +V_PE LKREQ#_ LKREQ#_ PPE#_ PPE#_ LK_PIE_NEWR# LK_PIE_NEWR PIE_RXN_NEWR PIE_RXP_NEWR PIE_TXN_NEWR PIE_TXP_NEWR 0 0 N U_- N U_+ NP_N PU# REERVE REERVE MLK MT +.V_ +.V_ WKE# +.VUX PERT# +.V_ +.V_ LKREQ# PPE# REFLK- REFLK+ N PERn0 PERp0 N PETn0 NP_N PETp0 N N 0 EXPRE_R_P J0 P_N P_N R_EJETOR_P +V.0V~.V ve= 000m Max= 00 m.0v~.v ve= 00m Max= m +VU.V~.V ve= 00 m Max= 0 m +.V 0.UF/0V 0 0.UF/0V 0.UF/.V 0 0.UF/0V 0.UF/.V 0 0.UF/0V <Variant Name> +V_PE 0.UF/0V 0 0UF/0V 0.0UF/V +V_PE.UF/0V 0.0UF/V +.V_PE.UF/0V 0.0UF/V UTeK OMPUTER IN ustom Z0Z/FTr Express ard Wednesday, March, 00 ate: heet of 0.

PERT# 00 00PF/0V R0 0KOhm +V 00 T R0 00KOhm R0 KOHM 0 R0 0.UF/0V KOHM PE_EUEN# Q00 PM0 E N U0 OE# V N Y LVV TPT T00 +V LP_FRME#_R LP_FRME# 0,0, LP_FRME#_R N N N N, PPE# PPE# lock RN00 RN00 RN00 RN00 R PIE_WKE#_ R0 KOhm +VU 0, LP_LKEU 0,0, LP_ 0,0, LP_0 0,0, LP_ 0,0, LP_ U0 0 0 0 0 PPE#_ LKREQ#_ PIE_WKE#_ M_LK_ M_T_ PPE#_ LKREQ#_ PIE_WKE#_ M_LK_ M_T_ LK_NEWR_REQ#,, PIE_WKE#,, M_LK_,, M_T_ 0 0 PE_EUEN# E# X V N +VU NTPWR 0 0.UF/0V N N N +V 0, PI_LK LP_0 LP_ LP_ LP_ LP_FRME# J0 IE 0 0 IE FP_ON_P <Variant Name> UTeK OMPUTER IN Express ard ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

E +V +VU +V +V,,,,,,0,,,,,,0,,,,,0,,,,,,,0,,,,,,,0,, +VU,0,,,,,0,,,,, +V,,,0,, LV_Y0P 0 LV_U0P LV_Y0N 0 LV_U0N LV_YP 0 LV_UP LV_YN +V 0 LV_UN 00 correct smbus LV_YP 0 LV_UP LV_YN 0 LV_UN LV_LKP change to 0000P 00 0 LV_ULKP LV_LKN 0 LV_ULKN LV_Y0P 0.UF/V 0 LV_L0P J0 LV_Y0N 0 LV_L0N LV_YP 0 LV_LP LV_YN +V IE +L_V 0 LV_LN +L_V 0 LV_YP 0 +L_V 0 LV_LP +V LV_YN EI_LK_PE EI_T_PE 0 LV_LN LV_LKP 0 LV_LLKP LV_LKN LV_Y0N LV_Y0N 0 LV_LLKN R0 R00 LV_Y0P 0 LV_Y0P 0 LV_YN 0KOhm 0KOhm LV_YN LV_YP LV_YP 0 EI_LK_PE LV_YN LV_YN 0 EI_T_PE 0 LV_YP 0 LV_YP 0 0 LV_LKN LV_LKN LV_LKP 00PF/0V 00PF/0V LV_LKP IE WTO_ON_0P LV_LKN PF/0V 0 PF/0V LV_LKN PF/0V PF/0V LV_LKP LV_LKP 0 PF/0V PF/0V 0 R 0 N/ N/ +V +V +V power suggest L00 /00Mhz _T_Y R R Q0 0 J0 00KOHM 0KOhm R +L_V L_L_ R 0.UF/V V 0 L_L_ V N PMNEN R L0 KOhm/00Mhz N 00KOHM 0 L_L_PWM L0 /00Mhz R0 00KOHM L0 KOhm/00Mhz VREF +L_V KEN Q00 0 RF 0 0 PWM UMKN LI_W# 0,, LI_W# WTO_ON_P 0.UF/V 0.UF/V 0 L_V_EN_PE 00PF/0V 0 L_KOFF# Q00 0.UF/V 0.UF/V 0UF/0V 0UF/0V UMKN R 0 RF 0KOhm 0,,0, PI_RT# 0 L_KEN_PE R0 MOhm Q0 F.ER N00 R Magnatic witch 0KOhm For LI_W# On/OFF 0 +V 0.0UF/V U0 V LIW# N <Variant Name> LIW# /F OUTPUT 0PF/0V only for FTR ELHLT 0.UF/0V UTeK OMPUTER IN LV & Inverter ustom INVERTOR NT Z0Z/FTr Wednesday, March, 00 ate: heet of 0. E

+V 0 RT_VYN +V U0 V 00 0.UF/V +V +V +V +V,,,,,,0,,,,,,0,,,,,0,,,,,,,0,,,,,,,0,,, +V,,,0,, +V,,,,,,0,,,,,, N Y LVV VYN_RT RT_RE RT_REEN L L 0.0UH 0.0UH L0 L0 0.0UH 0.0UH RE REEN +V RT_LUE L 0.0UH L0 0.0UH LUE 0 RT_HYN U0 V N Y LVV HYN_RT _ HYN_RT VYN_RT _ L0 /00Mhz R00 OHM R0 OHM L0 /00Mhz HYN VYN +V +V +V 00 hange option to N/ 00 +V_RT R0 R0.KOhm.KOhm R0 R0 R0 PF/0V PF/0V PF/0V 0 PF/0V 0 PF/0V 0 PF/0V PF/0V PF/0V 0 PF/0V 0 0 0 0 PF/0V 0PF/0V 0PF/0V PF/0V 0 _PE 0 _PE RN00.KOhm RN00.KOhm Q00 UMKN Q00 UMKN +V 0 V 0 V RE REEN LUE J0 0 HYN VYN 00.0.0 L0 L0 L0 from OHM/00M to NH add L L L NF add PF 0 from pf to pf and option change to R00 R0 from 0HM to OHM R0 from 0OHM to 0OHM for R0 0 0 0 from pf to pf _U_PR 0 RT_RE 0 RT_REEN 0 RT_LUE RT_RE RT_REEN RT_LUE RE LUE VYN HYN REEN 0 0 0 0 0 V V V V V +V +V <Variant Name> UTeK OMPUTER IN RT & TV-Out ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

<Variant Name> UTeK OMPUTER IN VI-***** Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

00 0.UF/.V 0.UF/.V +V_HMI VI_TX+_M VI_TX-_M VI_TX+_M VI_TX-_M VI_TX+_M VI_TX-_M +V_HMI VI_LK+_M VI_LK-_M lose to HMI ON(E Protection) IP0Z0 N TM_+ TM_V N TM_+ U0 IP0Z0 N TM_+ TM_V N TM_+ U0 TM_- N TM_- N TM_N TM_- N TM_- N TM_N 0 0 VI_TX+_M VI_TX-_M VI_TX+_M VI_TX-_M VI_TX+_M VI_TX-_M VI_LK+_M VI_LK-_M +V_HMI 00 add r0 R0 VI_TX+_M VI_TX-_M VI_TX+_M VI_TX-_M VI_TX+_M VI_TX-_M VI_LK+_M VI_LK-_M VI_LK_M VI_T_M HMI ON J0 P_N P_N 0 0 P_N P_N 0 +V 0 00 F0 0./V R0 +V_HMI HMI_ON_P 0.UF/.V 0 HMI_ETET 0 V R 00KOhm 0KOhm +V +V_HMI R0.KOhm R0.KOhm VI_T_M VI_LK_M P_TRLT trapping:(port ) Low = No HMI/P (default) High = HMI/P +V VI_T_M VI_LK_M +V 0 0 VI_T VI_LK.KOhm RN0.KOhm RN0 VI_T VI_LK Q0 UMKN Q0 UMKN 0 V 0 V 0 VI_TX- 0 VI_TX+ 0 VI_TX- 0 VI_TX+ 0 VI_TX- 0 VI_TX+ VI_TX-_M VI_TX+_M VI_TX-_M VI_TX+_M VI_TX-_M VI_TX+_M VI_TX+_M VI_TX-_M +V 0 VI_LK- 0 VI_LK+ VI_LK-_M VI_LK+_M VI_TX+_M VI_TX-_M VI_TX+_M VI_TX-_M VI_LK+_M VI_LK-_M R0 R0 R0 R R R R R 00.0.0 R0, R0, R0, R, R, R, R, R change to 0OHM +V R 00KOhm r00 Q0 I0 only for Z and X0Z UTeK OMPUTER IN. N HMI Wing heng ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0.

UTeK OMPUTER IN. N Wing heng Z0Z/FTr ate: Wednesday, March, 00 heet of 0.

Thermal ensor +V R00 R00 0KOhm 0KOhm O#_O THEM_LERT# To E 0,0 M_LK 0,0 M_T THEM_LERT# PU U00 LK LERT# N Max: m V XP XN OVERT# +V_THM R00 PU_THRM_ PU_THRM_ O#_O +V PU_THRM_ PU_THRM_ O#_O 0 PU_THRM_ PU_THRM_ 00 000PF/V 00 00 00PF/0V 00PF/0V N N N MXM lose to Pin & of PU N Use TTM0 ddress H 00 0.UF/0V O#_O R0 00 00PF/0V NV_OVERT# 0,0 N 00.0. add 00 00 optional is 00.0.0 U00 PN to 0000 00 PN to 00 add 00 optonal is 00.0. add 00 optional is Route H_THERM and H_THERM on the same layer FN ontrol +V +V +V +V ------------------OTHER INL mils ===============N 0 mils =========H_THERM(0 mils) 0 mils =========H_THERM(0 mils) 0 mils =========N mils ---------------------OTHER INL void F,Power 0 FN0_PWM 0 FN0_TH 00 R0 R0 T.KOhm 00KOHM R0 FN0_PWM_R N/ 00 00 00 UF/.V NW 0.UF/0V N N N FNP Pin fan PN:00000 Wto_ON_P IE IE J00 +V R0 00KOHM N00 Q00 0 0 00PF/0V 00PF/0V N N N N FN0_PWM N00 Q00 N O#_O 00 F0JE N <Variant Name> THER ENOR & FN UTeK OMPUTER IN Richard_Lu ustom Z0Z/FTr Wednesday, March, 00 ate: heet of 0 0.

E T H ON +V R0 0KOhm R0 0KOhm T_TXP0 T_TXN0 T_RXN0 T_RXP0 X0 X0 X0 X0 0.0UF/V 0.0UF/V 0.0UF/V 0.0UF/V T_TXP0_H T_TXN0_H T_RXN0_H T_RXP0_H J0 N NP_N H_LE# +V T_LE# 0 0 Q0 Q0 UMKN UMKN +V H_ET 00.0.0 T0 change Q to Q0 +V +V 0 add R0 0 NP_N N 0 0 0 0 0 + E0 T_ON_P 0UF/0V c00 0.UF/V 0.UF/V 0.UF/V 0UF/0V 00U/.V 00 HNE TO T O ON J0 X T_TXP_O T_TXP 0.0UF/V NP_N X T_TXN_O T_TXN 0.0UF/V NP_N T_RXN X T_RXN_O 0.0UF/V T_RXP X 0.0UF/V T_RXP_O +V +V T0 T0 O_ET P P P P P P P P P P P P NP_N NP_N T_ON_P UF/.V 0.UF/V 0.UF/V 0UF/0V 0.UF/V c00 c00 H & O UTeK OMPUTER IN close to connector (+V) Wednesday, March, 00 ate: heet of E ustom Z0Z/FTr 0. +V +V +V +V,,,,,,0,,,,,,0,,,,,0,,,,,,,,0,,,,,,0,,,, +V,,,,,,,0,,,,, +V,,,0,,

E U_PN U_PP R 0 R L /00Mhz 0 E00V0 E00V0 J0 HEER_X0P +VU UP- 0 0 U- UP+ EXT_MI_JK INT_MI_JK TP0-_ OPTI_V_JK TP0+_ 0 0 PIF_O_JK JK_W# TP0+_ HP_JK_L TP0-_ HP_JK_R <Variant Name> MI_J_JK HP_J UP- UP+ +V +V R 00KOHM 0UF/0V 00U/.V 0.UF/V R0 00 0 Q0 0 PMNEN R R E00V0 0.UF/V E00V0 U_O#.KOhm.KOhm +V_U F0./V R.KOhm +VU_ U-P: U//MI/ERPHONE 0 0 FOR EMI L0 + E0 0.UF/V /EMI /00Mhz +VU 0 +V +V,,0,, UP- U_PN 0 L UP+ U_PP /00Mhz N N UP+ N +V +V_U0 J0 R 0 0 UP- 0P+ U-UP +V +VU0 0P- R F0 V 00KOHM./V /00Mhz R E00V0 +VU_0 +VU0 UP0+ N L0 E00V0 UP0- P+ + U_ON_XP 0 E0 0 0 +VU0 P- V 00U/.V U-OWN UP0- Q0 0UF/0V R 0.UF/V 0.UF/V N N U_PN0 0 PMNEN F.PR L UP0+.KOhm 0 U_PP0 /00Mhz 0.UF/V U_O0# R0 0 FOR EMI +VU_J0 E.PR 0 FOR EMI 0.UF/V U 0 commom UP- U_PN choke /EMI 0.UF/V J0 L UP+ R0 co-lay U_PP IE_ /00Mhz +VU +VU_J0 V IE_ UP- +V +V_U T0- UP+ +V T0+ U- R0 0 0 N R00 F00 IE_ EMI./V /00Mhz IE_ 00KOHM +VU_ L00 +VU U_ON_XP H0 R0 E00V0 E00V0 00 + 0 E00 EMI_PRIN_P Q00 0UF/0V 00U/.V 0.UF/V /00Mhz UP- E.ER 0 PMNEN U_PN L UP+ R0 J0 H00 U_PP 0.UF/V IE_.KOhm +VU V IE_ UP- T0- EMI_PRIN_P R0 UP+ U_O# T0+ 0 0 N IE_ U- R0 IE_.KOhm U_ON_XP E00V0 E00V0 R L0 /00Mhz UTeK OMPUTER IN U/U P Z0Z/FTr ustom Wednesday, March, 00 ate: heet of 0. E