lz3c b

P STK UP LYER : TOP LYER : GN LYER : IN LYER : GN LYER : SV LYER : IN LYER : GN LYER : OT X'TL MHz RealTek (0/00 and G LN) RTL0E-V-G/ RTLF-G Page Transformer RJ LVI Page Page PIEx GPP PIE Note :R.V support 0~ MHz R.V support 0~00 MHz R III SO-IMM 0 SO-IMM Memory size MX is G per channel Page, Mini ard H (ST) O (ST) US.0/US.0 OMO PIEx GPP PIE Wlan/WiFi Page0 Page Page Page US.0 ST0 ST ual hannel /00 MHz PI-Express Gen PI-Express Gen US.0 US.0.GT/s.GT/s LOK IGRM Gbit/s Gbit/s Note :P means isplay Port Interface R SYSTEM MEMORY M Support W/ W TP Socket FSr-Trinity PU ( PU GPU ) upg pin GPP PIEX GPP PIEX X UMI interface.gt/s ST Gen ST Gen ST Gen US.0 US.0 Page0,0,0,0,0 UMI UMI M FH Hudson-M P0/TXPN[0:] P/TXPN[0:] P/TXPN[0:] P P to VG RT P0 P PEGX VG X'TL.KHz FN /THERML EM0- Page NX P to LVS HMI Page Page Thames XT VG Page LVS Page~Page LVS Page ischarge harge (Q) R/0.V (TPS) V/V (TPSRGER) 0 Page Page Page0 Page.V_UL &.V (TPS) Page.V_VPR/. Page V/VN_ORE (ISLHRTZ-T) GPU (ISLHRTZ-T).V GPU Page Page Page Page US.0 X Page, US.0 zalia ( H bus ) US.0 H FG pin Page0,0,0,0, PI-E luetooth Page US.0 LP SPI LP Page ard Reader RTS-GR Page US.0 US.0 udio OE LQ-V-GR Page SPI ROM M Page0 X'TL.KHz (IT HX) Page -IN- S/MM/MS/X HP Jack MI Jack SPK MI SPI ROM Touch Pad Keyboard Page Page Page Page Page PROJET : LZ Quanta omputer Inc. ate: ocument Number System lock iagram Monday, January 0, 0

() PEG_RXP0 () PEG_RXN0 () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP0 () PEG_RXN0 () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN PEG_RXP0 PEG_RXN0 PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP0 PEG_RXN0 PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN U00F PI EXPRESS P_GFX_RXP0 P_GFX_TXP0 P_GFX_RXN0 P_GFX_TXN0 P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN Y P_GFX_RXP P_GFX_TXP Y P_GFX_RXN P_GFX_TXN W P_GFX_RXP P_GFX_TXP W P_GFX_RXN P_GFX_TXN W P_GFX_RXP P_GFX_TXP W P_GFX_RXN P_GFX_TXN V P_GFX_RXP P_GFX_TXP V P_GFX_RXN P_GFX_TXN U P_GFX_RXP P_GFX_TXP U P_GFX_RXN P_GFX_TXN U P_GFX_RXP P_GFX_TXP U P_GFX_RXN P_GFX_TXN T P_GFX_RXP P_GFX_TXP T P_GFX_RXN P_GFX_TXN R P_GFX_RXP0 P_GFX_TXP0 R P_GFX_RXN0 P_GFX_TXN0 R P_GFX_RXP P_GFX_TXP R P_GFX_RXN P_GFX_TXN P P_GFX_RXP P_GFX_TXP P P_GFX_RXN P_GFX_TXN N P_GFX_RXP P_GFX_TXP N P_GFX_RXN P_GFX_TXN N P_GFX_RXP P_GFX_TXP N P_GFX_RXN P_GFX_TXN M P_GFX_RXP P_GFX_TXP M P_GFX_RXN P_GFX_TXN GRPHIS Y Y Y Y W W V V V V U U T T T T R R P P P P N N M M M M PEG_TXP0_ PEG_TXN0_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP0_ PEG_TXN0_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ 0 0 IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X 0 IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X PEG_TXP0 IS@0.U/0V_X PEG_TXN0 PEG_TXP IS@0.U/0V_X PEG_TXN PEG_TXP IS@0.U/0V_X PEG_TXN PEG_TXP IS@0.U/0V_X PEG_TXN PEG_TXP IS@0.U/0V_X PEG_TXN PEG_TXP IS@0.U/0V_X PEG_TXN PEG_TXP IS@0.U/0V_X PEG_TXN PEG_TXP IS@0.U/0V_X PEG_TXN PEG_TXP IS@0.U/0V_X PEG_TXN PEG_TXP IS@0.U/0V_X PEG_TXN PEG_TXP0 IS@0.U/0V_X PEG_TXN0 PEG_TXP IS@0.U/0V_X PEG_TXN PEG_TXP IS@0.U/0V_X PEG_TXN PEG_TXP IS@0.U/0V_X PEG_TXN PEG_TXP IS@0.U/0V_X PEG_TXN PEG_TXP IS@0.U/0V_X PEG_TXN (,,,,,) PEG_TXP0 () PEG_TXN0 () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP0 () PEG_TXN0 () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN () PEG_TXP () PEG_TXN ().V_VPR 0 TO ON OR LN TO WLN E P_GPP_RXP0 P_GPP_TXP0 E P_GPP_RXN0 P_GPP_TXN0 P_GPP_RXP P_GPP_TXP PIE_RXP_LN P_GPP_RXN P_GPP_TXN PIE_TXP_LN_ () PIE_RXP_LN PIE_TXP_LN () PIE_RXN_LN P_GPP_RXP P_GPP_TXP 00 0.U/0V_ PIE_TXN_LN_ () PIE_RXN_LN PIE_TXN_LN () PIE_RXP P_GPP_RXN P_GPP_TXN 00 0.U/0V_ PIE_TXP_WLN_ (0) PIE_RXP PIE_TXP (0) PIE_RXN P_GPP_RXP P_GPP_TXP 00 0.U/0V_ PIE_TXN_WLN_ (0) PIE_RXN P_GPP_RXN P_GPP_TXN 00 0.U/0V_ PIE_TXN (0) () () () () () () () () UMI_RXP0 UMI_RXN0 UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN.V_VPR R00 G P_UMI_RXP0 G P_UMI_RXN0 G P_UMI_RXP G P_UMI_RXN F P_UMI_RXP F P_UMI_RXN E P_UMI_RXP E P_UMI_RXN /F_ P_ZVP G P_ZVP GPP UMI-LINK P_UMI_TXP0 G P_UMI_TXN0 G P_UMI_TXP F P_UMI_TXN F P_UMI_TXP F P_UMI_TXN F P_UMI_TXP E P_UMI_TXN E P_ZVSS H UMI_TXP0_ UMI_TXN0_ UMI_TXP_ UMI_TXN_ UMI_TXP_ UMI_TXN_ UMI_TXP_ UMI_TXN_ P_ZVSS R00 00 00 00 0 /F_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 00 00 00 0 UMI_TXP0 0.U/0V_ UMI_TXN0 UMI_TXP 0.U/0V_ UMI_TXN UMI_TXP 0.U/0V_ UMI_TXN UMI_TXP 0.U/0V_ UMI_TXN UMI_TXP0 () UMI_TXN0 () UMI_TXP () UMI_TXN () UMI_TXP () UMI_TXN () UMI_TXP () UMI_TXN () TO ON OR LN TO WLN Trinity PU PROJET : LZ Quanta omputer Inc. ate: ocument Number PU /(PIE/UMI/GPP) Monday, January 0, 0

M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M S#0 M S# M S# M M M M M M M M M M M M0 M M M M M M M M M M M 0 M M M M M 0 M M M M M S#0 M S# M S# M M M M M M M M M M M M0 M M M M M M M M M M M 0 M M M M M 0 M M M M M EVENT# M_ZVIO MEMVREF_PU MEMVREF_PU M QSP0 () M QSP () M QSP () M QSP () M QSP () M QSP () M QSP () M QSP () M QSN0 () M QSN () M QSN () M QSN () M QSN () M QSN () M QSN () M QSN () M KE0 () M KE () M OT0 () M OT () M S#0 () M S# () M RS# () M RST# () M S# () M WE# () M EVENT# () M LKP0 () M LKN0 () M LKP () M LKN () M QSP0 () M QSP () M QSP () M QSP () M QSP () M QSP () M QSP () M QSP () M QSN0 () M QSN () M QSN () M QSN () M QSN () M QSN () M QSN () M QSN () M LKP0 () M LKN0 () M LKP () M LKN () M RS# () M OT0 () M OT () M S# () M RST# () M WE# () M EVENT# () M KE0 () M KE () M S#0 () M S# () M Q[0..] () M Q[0..] () M M[..0] () M S#[..0] () M [:0] () M [:0] () M S#[..0] () M M[..0] ().V_SUS (,,,0,,,,0,,,) MEMVREF_PU.V_SUS.V_SUS.V_SUS.V_SUS PROJET : LZ Quanta omputer Inc. ate: ocument Number PU /(R MEM I/F) Monday, January 0, 0 PROJET : LZ Quanta omputer Inc. ate: ocument Number PU /(R MEM I/F) Monday, January 0, 0 PROJET : LZ Quanta omputer Inc. ate: ocument Number PU /(R MEM I/F) Monday, January 0, 0 Place close to PU within " 0 0 0pF/0V_ 0 0pF/0V_ 0.U/0V_ 0.U/0V_ R00 K/F_ R00 K/F_ MEMORY HNNEL Trinity PU U00 MEMORY HNNEL Trinity PU U00 M_ZVIO W M_VREF W0 M_EVENT_L T M_RESET_L H M_WE_L W M_S_L W M_RS_L V M_S_L M_S_L0 V M_OT M_OT0 Y M_KE H M_KE0 H M_LK_L R M_LK_H R M_LK_L0 T M_LK_H0 T M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H E M_QS_L E M_QS_H E M_QS_L H M_QS_H J M_QS_L H M_QS_H G M_QS_L0 H M_QS_H0 G M_M M_M M_M M_M M_M F M_M E M_M J M_M0 E M_NK L M_NK U M_NK0 U M_ L0 M_ L M_ M_ L M_ M M_0 U M_ M M_ N M_ N0 M_ N M_ N M_ P M_ P M_ R M_0 U0 M_T Y M_T M_T M_T0 Y M_T M_T M_T Y M_T M_T M_T M_T Y M_T 0 M_T M_T0 M_T M_T M_T M_T M_T M_T M_T 0 M_T Y M_T M_T0 Y M_T M_T M_T M_T E M_T M_T M_T M_T M_T F M_T0 E M_T H M_T F M_T G M_T G M_T E M_T G M_T H M_T G M_T E0 M_T0 G0 M_T H M_T J M_T F M_T H0 M_T F M_T H M_T H M_T G M_T J M_T0 E M_T F M_T H M_T E M_T F M_T F M_T H M_T J M_T H M_T J M_T0 E M_ R0 R00./F_ R00./F_ 0 000P/0V_ 0 000P/0V_ R00 K/F_ R00 K/F_ R00 K/F_ R00 K/F_ 0 0pF/0V_ 0 0pF/0V_ MEMORY HNNEL Trinity PU U00 MEMORY HNNEL Trinity PU U00 M_EVENT_L T M_RESET_L J M_WE_L V M_S_L V M_RS_L V M_S_L Y M_S_L0 V M_OT Y M_OT0 W M_KE J M_KE0 J M_LK_L P M_LK_H P M_LK_L0 R M_LK_H0 R M_QS_L G M_QS_H H M_QS_L G M_QS_H G M_QS_L F M_QS_H G M_QS_L G M_QS_H G M_QS_L M_QS_H M_QS_L M_QS_H E M_QS_L M_QS_H E M_QS_L0 M_QS_H0 M_M M_M H M_M G M_M F M_M M_M M_M M_M0 M_NK K M_NK T M_NK0 U M_ K M_ K M_ W M_ K M_ L M_0 U M_ L M_ M M_ M M_ M M_ M M_ N M_ N M_ P M_ P M_0 T M_T F M_T E M_T F M_T0 G M_T M_T G M_T M_T G M_T M_T F M_T G M_T G0 M_T H M_T0 E M_T E M_T F M_T 0 M_T M_T M_T M_T H0 M_T E0 M_T H M_T0 E M_T E M_T H M_T F M_T G M_T G M_T F M_T H M_T G M_T M_T0 M_T M_T M_T M_T M_T M_T E M_T M_T E M_T M_T0 0 M_T M_T M_T M_T M_T M_T M_T M_T E M_T 0 M_T0 0 M_T M_T M_T M_T M_T M_T M_T E M_T M_T M_T0 R00 K/F_ R00 K/F_

P0 output to ep to LVS converter () () () () INT_LVS_TXP0 INT_LVS_TXN0 INT_LVS_TXP INT_LVS_TXN isplay port power.v min.v max :.v 00 0 0 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ TP00 TP00 INT_EP_TXP0_ INT_EP_TXN0_ INT_EP_TXP_ INT_EP_TXN_ L L K K K K U00 P0_TXP0 P0_TXN0 P0_TXP P0_TXN P0_TXP P0_TXN NLOG/ISPLY/MIS P0_UXP P0_UXN P_UXP P_UXN P_UXP P_UXN E E INT_LVS_UXP_L INT_LVS_UXN_L PU_P_UXP_ PU_P_UXN_ INT_HMI_SL INT_HMI_S 0 0 0 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ INT_LVS_UXP () INT_LVS_UXN () PU_P_UXP () PU_P_UXN () INT_HMI_SL () INT_HMI_S () INT_LVS_UXP LVS 0 R00 *00K/F_ INT_LVS_UXN R0 *00K/F_ V VG HMI INT_LVS_UXP_L INT_LVS_UXN_L R0 R0.K/J_.K/J_ P output to Hudson-M for VG translator interface note --HMI P&N can not swap P output to HMI connector Note: LK_PU_HLKP/N is 00MHZ SS Note: LK_P_NSSP/N is 00MHZ non-ss E--0.V_SUS () () () R0 R0 R0 R0 R0 () () () () () () () () () () () () () () () () () () () () PU_P_TXP0 PU_P_TXN0 PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN LK_PU_HLKP LK_PU_HLKN LK_P_NSSP LK_P_NSSN () () () (,) HMI_TX HMI_TX- HMI_TX0 HMI_TX0- HMI_TX HMI_TX- HMI_LK HMI_LK- () PU_V_RUN_F_L PU_VN_RUN_F_H PU_V_RUN_F_H SV SV PU_SVT PU_RST# PU_PWROK K/F_ K/F_ K/F_ K/F_ K/F_.V.V.V.V_SUS PU_TI PU_TK PU_TMS PU_TRST# PU_REQ# TP0 TP0 0 0 0 00 0 0 0 0 0 0 0 0 00 0 0 0 R0 R0 R0 R0 R0 TP0 TP0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ *K/F_ *0 short 00/J_ 00/J_ K/F_ PU_P_TXP0_ PU_P_TXN0_ PU_P_TXP_ PU_P_TXN_ PU_P_TXP_ PU_P_TXN_ PU_P_TXP_ PU_P_TXN_ P_HMI_TXP P_HMI_TXN P_HMI_TXP P_HMI_TXN P_HMI_TXP0 P_HMI_TXN0 P_HMI_TXP P_HMI_TXN LK_PU_HLKP LK_PU_HLKN LK_P_NSSP LK_P_NSSN SV SV PU_SVT_R PU_SI PU_SI PU_RST# PU_PWROK PU_PROHOT# PU_THERMTRIP# PU_LERT PU_TI PU_TO PU_TK PU_TMS PU_TRST# PU_RY PU_REQ# PU_V_RUN_F_L_R PU_VN_RUN_F_H PU_V_RUN_F_H J J H H H H G G F F L L L L K K J J E G H F0 0 E F H0 J0 F0 G0 F G H E--0 P0_TXP P0_TXN P_TXP0 P_TXN0 P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN P_TXP0 P_TXN0 P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN LKIN_H LKIN_L ISP_LKIN_H ISP_LKIN_L SV SV SVT SI SI RESET_L PWROK PROHOT_L THERMTRIP_L LERT_L TI TO TK TMS TRST_L RY REQ_L VSS_SENSE VP_SENSE VN_SENSE VIO_SENSE V_SENSE VR_SENSE ISPLY PORT 0 ISPLY PORT ISPLY PORT JTG LK TRL SER. SENSE Trinity PU TEST ISPLY PORT MIS. RSV P_UXP P_UXN P_UXP P_UXN P_UXP P_UXN P0_HP P_HP P_HP P_HP P_HP P_HP P_LON P_IGON P_VRY_L P_UX_ZVSS TEST TEST TEST0 TEST TEST TEST TEST TEST TEST TEST0 TEST TEST_H TEST_L TEST_H TEST_L TEST0_H TEST0_L TEST TEST_H TEST_L TEST FSR MTIVE_L TEST TEST RSV_ RSV_ RSV_ RSV_ E E F F G G E E F G M N F G H J F G J H E0 0 L0 M0 P R K T N W0 P R Y0 0 Y K isplay port power.v min.v max :.v FH_LVS_HP VG_HP_Q INT_HMI_HP PU_LEN PU_IGON PU_VRY_L P_UX_ZVSS PU_TEST PU_TEST PU_TEST0_SNLK PU_TEST_SNLK PU_TEST_H PU_TEST_L M_TEST PU_TEST FSR R0 MTIVE_L E--0 R0 E--0 TP0 TP0 TP0 TP0 TP0 TP0 E--0 E--0 0K/F_ 0/F_ V_S R0 R0 FH_LVS_HP () VG_HP_Q () INT_HMI_HP () PU_LEN () PU_IGON () PU_VRY_L () MTIVE_L controls entry and exit from the sleep and power states *K/F_ K/F_ MTIVE_L ().V.V_SUS SI FSR signals is for detect PU TYPE and protect it. FSR PU this pin is N. FSR PU this pin is LOW can remove it at MP.V_SUS PU_P_UXP PU_P_UXN PU_P_UXP_ PU_P_UXN_ M_TEST M_TEST ONNETION T PU_TEST_L R0 R0 R0 R0 R0./F_ PU_TEST PU_TEST PU_TEST0_SNLK PU_TEST_SNLK PU_TEST_H R00.V_SUS 00K/F_ 00K/F_.K/J_.K/J_ PU_TEST R0 R0 R0 R00 R0 V 0/J_ K/F_ K/F_ K/F_ K/F_ 0/J_.V_SUS R0 00/J_ R0 *00/J_.V_VPR E--0.V R0 0K/F_ (,,,) M_LK M_LK Q00 METR0-G R0 K/F_ R0 K/F_ R0 K/F_ PU_SI R00 K/F_ R 0/J_ E--0 SM_LV_LK () Q00 METR0-G R00V-0 00 () PU_VR_HOT PU_PROHOT#.V SI (,,,) M_T M_T Q00 METR0-G PU_SI R 0/J_ SM_LV_T () Thermal () FH_THERMTRIP#.V_SUS R0 0K/F_ R0 K/F_ Q00 METR0-G PU_THERMTRIP# THERMTRIP# shutdown temperature 度 () () () FH_PROHOT# H_PROHOT# PU_PROHOT#_VIO PU_PROHOT# 可可可 input or output 可 Low 時 PU 會會 P - STTE R0 *0_ R0 0_ to E reserve only 0 0pF/0V_ PU_PROHOT#_VIO PU_PROHOT# PV change to short-pad R0 K/F_ PV inner document R0 for E request R00V-0 00 (,,0,,) (,,,0,,,,0,,,) (,,,,,) (,,,0,,,,,,,,,,,0,,,,,,0,,,,,,,).V.V_SUS.V_VPR V PROJET : LZ Quanta omputer Inc. ate: ocument Number PU /(isplay/misc) Monday, January 0, 0

PU POWER TLE PIN NME NET NME VOLTGE V V_ORE.V V_ORE SI EMI 0 VN VIO VN_ORE.VSUS??.V 0 *0P/0V_ 0 *0P/0V_ 0 *0P/0V_ VP.V_VP.V VR.V_VR.V V_ORE U00 V.V_V.V F V_ H V_ J V_ J V_ P VN_ORE V_ P0 V_ J V_ J V_ J V_ K V_0 K 0 0 00 V_ K U/.VS_ U/.VS_ U/.VS_ U/.VS_ 0U/.V_ V_ M V_ K V_ V0 V_ V V_ V V_ F V_ L 0 0 0 0 0 V_ V 0U/.VS_ 0.U/.V_ 0.U/.V_ 0P/0V_ 0P/0V_ 0P/0V_ V_0 W V_ T V_ Y V_ V_ V_ V_ R V_ P V_ K0 V_ H V_0 M VN_ORE V_ VN_P VN_ 0 VN_ VN_ VN_ 0 0 0 VN_ U/.VS_ U/.VS_ 0P/0V_ VN_ 0 VN_ VN_ VN_ E0 VN_0 E VN_ 0 VN_ E--.V_SUS Up to R- @.0V VIO H VIO_ K0 VIO_ J 0 0 0 0 0 0 VIO_ K 0.U/.V_ 0.U/.V_ 0.U/.V_ 0.U/.V_ 0.U/.V_ 0.U/.V_ VIO_ K VIO_ L VIO_ L VIO_ L VIO_ M0 VIO_ M VIO_0 M VIO_ N 0 VIO_ N 0P/0V_ VIO_ N VIO_ P0 VIO_ P VIO_ P VIO_ VIO_ VP_ VP_ =..V_VPR R0 *0 short.v_vpr_r H VP H VP H 0 0 0 0 VP H U/.VS_ 0U/.V_ 0U/.V_ 0U/.V_ VP H VP 0 V V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_0 VN_ VN_ VN_ VN_P VN_P VIO_ VIO_0 VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_0 VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VR VR VR VR R T0 H G U W W W W W E L Y M N N T T U U Y Y Y F F F L 0 E K K T T U U U Y T0 R R R V0 V V W W W Y G G0 H H H0 V_ORE 0 U/.VS_ 0 U/.VS_ 0 0.U/.V_ Maximum INspike. VN_ORE VN_P.V_SUS 0 U/.VS_.V_VR_ Maximum Ispike 0 00 U/.VS_ 0 U/.VS_ 0 0.U/.V_ EOUPLING between PROESSOR and IMMs cross VIO and VSS split 0 U/.VS_.V_SUS 0 0.U/.V_ 0 U/.VS_ 0 U/.VS_ 0 0P/0V_ 00 U/.VS_ If the VSS plane is cut to create a VIO plane, ceramic capacitors are connected across the VIO and VSS plane split as follows VR = ( Up to R- @.V ) 00 0U/.V_ 0 0U/.V_ 0 U/.VS_ 0 U/.VS_ 00 0P/0V_ 0 0U/.V_ R0 0 U/.VS_ *0 short 0 U/.VS_ 0 U/.VS_ 0 0.0U/V_ 0 0.U/.V_ PV 0pF on for EMI suggestion.v_vpr 0 0.0U/V_ 0 0P/0V_ 0 0.0U/V_ 00 0P/0V_ 0 0 0.U/.V_.U/.V_.U/.V_ 0P/0V_ 0.U/.V_ U00E J0 VSS_ VSS_ L VSS_ VSS_ R VSS_ VSS_ W VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ E VSS_ VSS_ F VSS_ VSS_ H VSS_0 VSS_ H VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ 0 VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_00 VSS_ VSS_0 E VSS_ VSS_0 E VSS_ VSS_0 F VSS_0 VSS_0 F VSS_ VSS_0 F VSS_ VSS_0 F0 VSS_ VSS_0 F VSS_ VSS_0 F VSS_ VSS_0 F VSS_ VSS_0 G VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ G VSS_0 VSS_ G VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_0 J VSS_ VSS_ J VSS_ VSS_ K VSS_ VSS_ K VSS_0 VSS_ K VSS_ VSS_ VSS_ VSS_ L VSS_ VSS_ L VSS_ VSS_ M VSS_ VSS_ F VSS_ VSS_0 V VSS_ VSS_ V VSS_ VSS_ W VSS_ VSS_ W VSS_0 VSS_ W VSS_ VSS_ Y VSS_ VSS_ Y0 VSS_ VSS_ Y VSS_ VSS_ Y VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ K VSS_ VSS_ F VSS_ VSS_ G VSS_0 VSS_ H VSS_ VSS_ J VSS_ Trinity PU 0 E E E M N0 N N R0 R T T U0 U U U V E E E E E E F F F F0 F F F F G G H H H H H P W P E K W 0 0.U/.V_ 0 0.U/.V_ 0 0P/0V_ 0 0P/0V_ Trinity PU 0 0.U/.V_ 0 0.U/.V_ 0 000P/0V_ 0 0P/0V_ 0P/0V_ (,) V_ORE () VN_ORE VN_P (,,,0,,,,0,,,).V_SUS (,,,,,).V_VPR (,).V_V.V_V L00 H0KF-T0(0,)_ V= 0..V_V_R.U/.V_ 0.U/.V_ 00P/0V_ PROJET : LZ Quanta omputer Inc. ate: ocument Number PU /(POWER/GN) Monday, January 0, 0

VI Override ircuit (,,0,,) (,,,0,,,,0,,,).V.V_SUS 0 OOT VOLTGE SV SV VFIX_V =V/GN VFIX_V =OPEN 0 0.. Note: To override VI,Remove Rd, Re, Rf, install Rc set VI via SV & SV option RES. 0 0.0. 0..0.V_SUS SI.V 0. 0. R0 K/F_ Rd () SV SV R00 *0 short PU_SV Re PU_SV () () SV SV R0 *0 short PU_SV Rf PU_SV () (,) PU_PWROK PU_PWROK R0 *0 short PU_PWRG_SVI_REG PU_PWRG_SVI_REG () PU_PWRG have pull up 00ohm to.v on page R0 K/F_ for normal operation open Ra, Rb,Rc R0 *K/J_ R0 *K/J_ R0 *.K/J_ R00 R0 R0 *0/J_ *0/J_ *0/J_ Ra Rb Rc E--0 PROJET : LZ Quanta omputer Inc. ate: ocument Number PU /(Other) Monday, January 0, 0

V_S R R R V N,no install by default R R R *SHORT_P *.K/J_ *.K/J_ *.K/J_.K/J_.K/J_ *K/J_ G FH_TEST0 FH_TEST FH_TEST SM_RUN_LK SM_RUN_T SYS_RST# () FH_THERMTRIP# () SLP_S# () SLP_S# () NSWON# () FH_PWRG () () () () (,0) T T E_0GTE E_KRST# E_EXT_SI# E_EXT_SMI# PIE_WKE# R V SLP_S# SLP_S# T0 T T *0 short R R T T0 T NSWON# FH_PWRG FH_TEST0 FH_TEST FH_TEST SYS_RST# *0 short FH_THERMTRIP#_R 0K/F_ W_PWRG R W T W J N T T0 V E G R T U K V R0 F U PIE_RST#/GEVENT# RI#/GEVENT# SPI_S#/GE_STT/GEVENT# SLP_S# SLP_S# PWR_TN# PWR_GOO HUSON-M Part TEST0 TEST/TMS TEST G0IN/GEVENT0# KRST#/GEVENT# PME#/GEVENT# LP_SMI#/GEVENT# LP_P#/GEVENT# SYS_RESET#/GEVENT# WKE#/GEVENT# IR_RX/GEVENT0# THRMTRIP#/SMLERT#/GEVENT# W_PWRG PI / WKE UP EVENTS USLK/M_M_M_OS US MIS US. US_ROMP US_FSP/GPIO US_FSN US_FS0P/GPIO US_FS0N US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HS0P US_HS0N G H H H H H0 G0 K0 J G F K K US_ROMP_S USP0 USP0- USP USP- R.K/F_ (,,0,,0,,) V_S (,,,0,,,,,,,,,,,0,,,,,,0,,,,,,,) V (0) FH_V SSUS_S Hudson-//M does not support US_HS[:0]P/N as stand alone US ports. These signals can only be routed to US connectors in signal groups mentioned above. USP () USP- () USP0 () USP0- () US.0 US.0 Note: US.0 : MP to US.0 PORT s elow: SSUS0US0 US.0 PORT 0 SSUSUS US.0 PORT SSUSUS N SSUSUS N 0 V_S V_S R R R R R R R R R R *0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ *0K/J_ *0K/J_ *.K/J_ 0K/J_ 0K/J_ VG_P SL S SL S SM_LV_LK SM_LV_T FH_THERMTRIP# US_O# US_O0# (,,) E-- dgpu_pwren (0) () () T_ON# PIE_LKREQ_LN# () _ON# () SPKR (,) SM_RUN_LK (,) SM_RUN_T PIE_LKREQ_WLN# () L_K_OFF# VG_P for power control (0) VG_P R 0_ () () _E_0 SPI_HOL# FH_PIE_PEG_LKREQ# E--0 T R RSMRST# R R *0 short SM_RUN_LK SM_RUN_T SL S R0 *0_ *0 short *IS@0/J_ GEVENT# U G E E F H G F T R G G J G V W Y V0 F RSMRST# LK_REQ#/ST_IS0#/GPIO LK_REQ#/ST_IS#/GPIO SMRTVOLT/ST_IS#/GPIO0 LK_REQ0#/ST_IS#/GPIO0 ST_IS#/FNOUT/GPIO ST_IS#/FNIN/GPIO SPKR/GPIO SL0/GPIO S0/GPIO SL/GPIO S/GPIO LK_REQ#/FNIN/GPIO LK_REQ#/FNOUT/GPIO IR_LE#/LL#/GPIO SMRTVOLT/SHUTOWN#/GPIO R_RST#/GEVENT#/VG_P GE_LE0/GPIO SPI_HOL#/GE_LE/GEVENT# GE_LE/GEVENT0# GE_STT0/GEVENT# LK_REQG#/GPIO/OSIN/ILEEXIT# GPIO US.0 US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN E0 F0 0 0 H G F E USP USP- USP USP- USP USP- USP USP- USP USP- USP USP- T T E-- USP () USP- () USP () USP- () USP () USP- () USP (0) USP- (0) USP () USP- () US# ard Reader lue Tooth WLN V V_S R R R0 R0 R R 0K/J_ 0K/J_ *0K/J_ *0K/J_ 0K/J_.K/J_ US_O# O_PRSNT# E_EXT_SI# E_EXT_SMI# PIE_WKE# NSWON# Note:LL#, WKE# and PWR_TN need pull up to.v_s only if S mode is supported () () (,) O_M# () O_PRSNT# () () US_O# _PRESENT US_O# US_O0# H audio interface is V_S voltage R R R R R R R R *0K/F_ *0K/F_ *0K/F_ *0 short *0 short *0 short *0 short *0 short Z_LK_R Z_SOUT_R Z_SIN0 Z_SIN Z_SYN_R Z_RST#_R M R T P F P J T Y Y Y E LINK/US_O#/GEVENT# US_O#/IR_TX/GEVENT# US_O#/IR_TX0/GEVENT# US_O#/IR_RX0/GEVENT# US_O#/_PRES/TO/GEVENT# US_O#/TK/GEVENT# US_O#/TI/GEVENT# US_O0#/SPI_TPM_S#/TRST#/GEVENT# Z_ITLK Z_SOUT Z_SIN0/GPIO Z_SIN/GPIO Z_SIN/GPIO Z_SIN/GPIO0 Z_SYN Z_RST# H UIO US O US_HSP US_HSN US_HS0P US_HS0N USSS_LRP USSS_LRN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN E E E F USP0 USP0- USSS_LRP USSS_LRN E-- USP0 () USP0- () R R US@K/F_ US@K/F_ US# aughter oard If US.0 not implemented, left unconected FH_V SSUS_S To zalia V_S R *K/J_ RSMRST# T T S SL K J J 0 PS_T/S/GPIO PS_LK/E/SL/GPIO SPI_S#/GE_STT/GPIO PSK_T/GPIO PSK_LK/GPIO0 PSM_T/GPIO PSM_LK/GPIO US.0 US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN US_SS_TX0P US_SS_TX0N US_SS_RX0P US_SS_RX0N F G H G J H J K US_TXP US_TXN US_RXP US_RXN US_TXP0 US_TXN0 US_RXP0 US_RXN0 US_TXP () US_TXN () US_RXP () US_RXN () US_TXP0 () US_TXN0 () US_RXP0 () US_RXN0 () US.0 US.0 Z_SOUT_R Z_SYN_R Z_LK_R R R R /J_ /J_ /J_ Z_SOUT () Z_SYN () Z_ITLK () () RSMRST#_E RSMRST_GTE# from E R *0 short R *0K/J_ RSMRST_GTE# 0 *.U/.V_X Q *ISR@N00E T T T T T T T T0 T T T T T0 T T T T T KSO_0 KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_0 KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ KSO_ Provided test points from checklist F E0 F0 E 0 J H G K KSO_0/GPIO0 KSO_/GPIO0 KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_0/GPIO KSO_/GPIO0 KSO_/GPIO KSO_/GPIO KSO_/X0/GPIO KSO_/X/GPIO KSO_/X/GPIO KSO_/X/GPIO EMEE TRL SL/GPIO S/GPIO SL_LV/GPIO S_LV/GPIO E_PWM0/E_TIMER0/GPIO E_PWM/E_TIMER/GPIO E_PWM/E_TIMER/WOL_EN/GPIO E_PWM/E_TIMER/GPIO00 KSI_0/GPIO0 KSI_/GPIO0 KSI_/GPIO0 KSI_/GPIO0 KSI_/GPIO0 KSI_/GPIO0 KSI_/GPIO0 KSI_/GPIO0 H G G G E H J H K K F F E F SL S SM_LV_LK SM_LV_T E_PWM US_US_SW US_US_SW T T SM_LV_LK () SM_LV_T () E_PWM () INTEL_T_OFF# (0) Z_RST#_R Z_SIN0 R0 0 /J_ *P/0V_N Z_RST# () Z_SIN0 () Hudson-M PROJET : LZ Quanta omputer Inc. ate: ocument Number FH /(GPIO/US/Z) Monday, January 0, 0

(,) PU_PIE_RST# PU_PIE_RST# is for PU PIE devices reset PU_PIE_RST# 0P/0V_N () () () () () () () () (0) (0) () () (,0) PLE 0,,,,0,0,0, LOSE TO U Note: LK_P_NSSP/N is 00MHZ non-ss Note: LK_PIE_TRVISP/N is 00MHZ non-ss Note: LK_PU_HLKP/N is 00MHZ SS Note: LK_PIE_VGP/N is 00MHZ SS Note: For external LK gen mode, depop RP0/RP/RP/RP/RP/RP/RP LK_P_NSSP LK_P_NSSN LK_PU_HLKP LK_PU_HLKN LK_PIE_LNP LK_PIE_LNN PLTRST# () () () () () () () () () () () () () () () () LK_PIE_TRVISP LK_PIE_TRVISN LK_PIE_VGP LK_PIE_VGN LK_PIE_WLNP LK_PIE_WLNN UMI_RXP0 UMI_RXN0 UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_TXP0 UMI_TXN0 UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN.V_PIE_VR UMI_RXP0 UMI_RXN0 UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN Note: LK_FH_SRP/N is 00MHZ SS ( Pop RP if use external LK gen ) Note: GPP_LK(0:)P/N is 00MHZ SS capable R0 /J_ 0P/0V_N.V_KV RP RP RP RP RP RP R 0 0 0 0 PIE_RST#_R R0 R0 /J_ 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X R0 TP TP 0X UM@0X 0X IS@0X 0X 0X _RST# 0/F_ K/F_ UMI_RXP0_ UMI_RXN0_ UMI_RXP_ UMI_RXN_ UMI_RXP_ UMI_RXN_ UMI_RXP_ UMI_RXN_ PIE_LRP_FH PIE_LRN_FH K/F_ INT_LK_FH_SRP INT_LK_FH_SRN INT_LK_P_NSSP INT_LK_P_NSSN INT_LK_PIE_TRVISP INT_LK_PIE_TRVISN INT_LK_PU_HLKP INT_LK_PU_HLKN INT_LK_PIE_VGP INT_LK_PIE_VGN INT_LK_PIE_WLNP INT_LK_PIE_WLNN INT_LK_PIE_LNP INT_LK_PIE_LNN RP~RP need close to connect node LL LOK TEST POINT PLE LOSE U E E0 E 0 Y Y Y Y F F V V W0 W W V V W W W F G0 G R T H H T T J0 K H H J K F F E E M M M M N N UE PIE_RST# _RST# UMI_TX0P UMI_TX0N UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_RX0P UMI_RX0N UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN PIE_LRP PIE_LRN GPP_TX0P GPP_TX0N GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_RX0P GPP_RX0N GPP_RXP GPP_RXN GPP_RXP GPP_RXN GPP_RXP GPP_RXN LK_LRN PIE_RLKP PIE_RLKN ISP_LKP ISP_LKN ISP_LKP ISP_LKN PU_LKP PU_LKN SLT_GFX_LKP SLT_GFX_LKN GPP_LK0P GPP_LK0N GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN HUSON-M PI EXPRESS INTERFES Part LOK GENERTOR PI LKS PILK0 PILK/GPO PILK/GPO PILK/GPO PILK/M_OS/GPO 0/GPIO0 /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO 0/GPIO0 /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO 0/GPIO0 /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO 0/GPIO0 /GPIO E0# E# E# E# FRME# EVSEL# IRY# TRY# PR STOP# PERR# SERR# REQ0# REQ#/GPIO0 REQ#/LK_REQ#/GPIO REQ#/LK_REQ#/GPIO GNT0# GNT#/GPO GNT#/S_LE/GPO GNT#/LK_REQ#/GPIO LKRUN# LOK# PI INTERFE LPLK0 LPLK L0 L L L LFRME# LRQ0# LRQ#/LK_REQ#/GPIO SERIRQ/GPIO LP PIRST# INTE#/GPIO INTF#/GPIO INTG#/GPIO INTH#/GPIO F F F G F J L G L H J L N N J L L M J K N G M J0 L K N G E E F H H E N J N0 G0 K L0 F0 E0 H M H G G F M K H F E E E PI_LK0 PI_LK_R PI_LK PI_LK_R PI_LK_R PI_ PI_ PI_ PI_ PI_ HUSON_MEMHOT#_R INTE# INTF# INTG# INTH# T0 T0 T T LP_LK0_R LP_LK_R LP_L0 LP_L LP_L LP_L LP_LFRME# LRQ#0 LRQ# IRQ_SERIRQ R00 R R E--0 E--0 R0 dgpu_pwren_r LKRUN# E--0 R0 R V T *0 short *0 short *0 short *0/J_ R0 IS@0K/J_ R0 R 0/J_ 0/J_ PI_LK PI_LK PI_LK *P/0V_ PI_ () PI_ () PI_ () PI_ () PI_ () dgpu_.v_pg () LKRUN# () LP_LK0 LP_LK T PI_LK () T PI_LK () PI_LK () PIE_RST#_TRVIS () dgpu_rst# () EUG@/J_ /J_ E--0 *P/0V_ dgpu_pwren_r E-- PLK_EUG LK_PI_ LP_LK0 () LP_LK () LP_L0 (0,) LP_L (0,) LP_L (0,) LP_L (0,) LP_LFRME# (0,) LP_RQ#0 (0) T IRQ_SERIRQ (0,) V_RT (0).V_PIE_VR (0).V_KV (,,,0,,,,,,,,,,,0,,,,,,0,,,,,,,) V () V_RT (0,,,,,,,,,,,) VPU RT ircuitry(rt) 0MIL U/0V_X R *0_ R PLK_EUG (0) LK_PI_ () 0/F_ VRT 0MIL dgpu_pwren (,,) For EMI PLK_EUG LK_PI_ SM0K--F_00M VPU_RT SM0K--F_00M G *SHORT_P E--0 P/0V_ 0P/0V_ 0MIL R K/F_ 0MIL 0mils R 0_ VRT_ T N VPU RT_T(RT SOKET-0) 0 P/0V_N Y MHZ_0 P/0V_N R0 M/F_ TP TP TP TP M_X M_X GPP_LKP GPP_LKN R R N R J GPP_LKP GPP_LKN GPP_LKP GPP_LKN M_M_M_OS M_X M_X Hudson-M PU S PLUS M_TIVE# PROHOT# PU_PG LT_STP# PU_RST# K_X K_X S_ORE_EN RTLK INTRUER_LERT# VT_RT_G G E E G F G G H F F E MTIVE_L PU_PROHOT#_VIO PU_PWROK PU_RST# K_X K_X S_ORE_EN RT_LK INTRUER_LERT# V_RT 0MIL E--0 T T G *SHORT_ P T test pad can trigger V_RT MTIVE_L () PU_PROHOT#_VIO () PU_PWROK (,) PU_RST# () S_ORE_EN is necessary to connect enable pin VPU/VPU regulator for S mode implementation 0.U/0V_X RT_LK () INTRUER_LERT# Left not connected (FH has 0-kohm internal pull-up to VT). K_X R 0M/J_ K_X Y.KHZ USE GROUN GUR FOR K_X N K_X P/0V_ P/0V_ PROJET : LZ Quanta omputer Inc. ocument Number FH /(PI/PI/LOK) ate: Monday, January 0, 0

ST H/SS ST O () () () () () () () () ST_TXP0 ST_TXN0 ST_RXN0 ST_RXP0 ST_TXP ST_TXN ST_RXN ST_RXP PLE ST_L RES VERY LOSE TO LL OF HUSON-M/M.V_V_ST ST PORTS ISTRIUTION: 0, ST H/SS, ST O -, NOT USE R R0 K/F_ /F_ ST_LRP ST_LRN K M L0 N0 N L H0 J0 J H M K H J N L L N J H N L K M L N L L H H J J F F U ST_TX0P ST_TX0N ST_RX0N ST_RX0P ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP N N N N N0 N N N ST_LRP ST_LRN HUSON-M SERIL T S R SPI ROM VG GE LN Part S_LK/SLK_0/GPIO S_M/SLO_0/GPIO S_#/GPIO S_WP/GPIO S_T0/STI_0/GPIO S_T/STO_0/GPIO S_T/GPIO S_T/GPIO0 GE_OL GE_RS GE_MK GE_MIO GE_RXLK GE_RX GE_RX GE_RX GE_RX0 GE_RXTL/RXV GE_RXERR GE_TXLK GE_TX GE_TX GE_TX GE_TX0 GE_TXTL/TXEN GE_PHY_P GE_PHY_RST# GE_PHY_INTR SPI_I/GPIO SPI_O/GPIO SPI_LK/GPIO SPI_S#/GPIO ROM_RST#/SPI_WP#/GPIO VG_RE VG_GREEN VG_LUE VG_HSYN/GPO VG_VSYN/GPO VG S/GPO0 VG SL/GPO VG RSET L N J H K M H J W0 H F E G F G E W V V V T V L0 L M M N0 M N K GE_OL GE_RS GE_MIO GE_RXERR GE_PHY_INTR FH_SPI_SI FH_SPI_SO FH_SPI_LK FH_SPI_S0# FH_SPI_WP_L FH_SPI_WP R 0_ INT_RT_RE INT_RT_GRE INT_RT_LU INT_T INT_LK R R R R R R *0K/J_ *0K/J_ *0K/J_ *0K/J_ 0K/J_ /F_ T V_S V_S FH_SPI_SI () FH_SPI_SO () FH_SPI_LK () FH_SPI_S0# () INT_RT_RE () INT_RT_GRE () INT_RT_LU () INT_RT_HSYN () INT_RT_VSYN () INT_T () INT_LK () FH_SPI_S0# FH_SPI_LK FH_SPI_SO FH_SPI_SI V_S R R R R WINON(M): KEEFP0N0 MX(M): KENFP0Z00 EON(M):KEEFN0Q00 Socket: FHS0FS0 /J_ /J_ /J_ 0K/J_ INT_RT_RE INT_RT_GRE INT_RT_LU FH_SPI_LK_R FH_SPI_SO_R FH_SPI_SI_R *P/0V_N FH_SPI_WP R place close to PH R R R U E# SK SI SO WP# UM@0/F_ UM@0/F_ V HOL# WQFVSSIG UM@0/F_ VSS V_S R 0K/J_ R *0/J_ 0.U/0V_X INT_T R0 INT_LK R LN_ISLE# R 0 SPI_HOL# () V UM@.K/J_ UM@.K/J_ V_S 0K/J_ () FH_PROHOT# R V R R R0 V_S R R Q *MMT0--F_00M FH_PROHOT# *0K/J_ *0K/J_ 0K/J_ 0K/J_ 0K/J_ *0K/J_ V OR_I OR_I OR_I OR_I OR_I OR_I R0 *0K/F_ R R0 R R R R0 V R *0K/F_ V (0) LN_ISLE# () O_PWR 0K/J_ 0K/J_ *0K/J_ *0K/J_ *0K/J_ 0K/J_ R 0K/F_ S_ST_LE# Integrated lock Mode: Leave unconnected. LN_ISLE# FH_PROHOT#_ OR_I OR_I OR_I OR_I OR_I OR_I TEMPIN F G H M J K N L K K K M ST_T#/GPIO ST_X ST_X FNOUT0/GPIO FNOUT/GPIO FNOUT/GPIO FNIN0/GPIO FNIN/GPIO FNIN/GPIO TEMPIN0/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/TLERT#/GPIO HW MONITOR VG MINLINK UX_VG_H_P UX_VG_H_N UXL ML_VG_L0P ML_VG_L0N ML_VG_LP ML_VG_LN ML_VG_LP ML_VG_LN ML_VG_LP ML_VG_LN ML_VG_HP/GPIO 0/GPIO /GPIO /STI_/GPIO /STO_/GPIO /SLO_/GPIO /SLK_/GPIO0 /GE_STT/GPIO /GE_LE/GPIO N N N N N V V U T T T T R R0 P P N M L N P P M M G H0 G L 0 R R R R R R R R R 00/F_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ PU_P_UXP () PU_P_UXN () FH_VN ML PU_P_TXP0 () PU_P_TXN0 () PU_P_TXP () PU_P_TXN () PU_P_TXP () PU_P_TXN () PU_P_TXP () PU_P_TXN () V R0 *0K/F_ FH_VG_HP RT Hot-plug () VG_HP_Q N00K_00M Q V R 0K/J_ N00K_00M Q V R 0K/J_ FH_VG_HP R 00K/J_ E--0 OR I SETTING oard I I I I Remark R 0K/J_ Hudson-M VG_HP_Q R *0/J_ FH_VG_HP SV SIV SIT SVT SOVP 0 0 0 0 0 0 0 0 0 0 Model I 0 I " " GPIO 0 I UM IS (,,,0,,,,,,,,,,,0,,,,,,0,,,,,,,) V (0).V_V_ST (,,0,,0,,) V_S (,,,,,,,,,) V (0) FH_VN ML PROJET : LZ Quanta omputer Inc. I reserve ate: ocument Number FH /(ST/HWM/SPI) Monday, January 0, 0

VXL_.V VR_.V FH_VPL PIE FH_VPL ST FH_VN US_S FH_VR US_S FH_VN SSUS_S_R FH_VR SSUS_S FH_VN VG_P VIO S FH_VN ML VPL VPL ML VG_P ().V_UL (,) FH_V SSUS_S ().V ().V_SUS (,,,,,,,0,,,) FH_VN ML () V_S (,,,,0,,) V (,,,,,,,,,,,,,,0,,,,,,0,,,,,,,) V (,,,,,,) VPU (,,,,,,,,,,,) VPL_.V FH_VN R FH_VPL SSUS_S FH_VPL SUS_S V V.V_V_FH_R.V.V.V_KV.V_PIE_VR.V.V.V_V_ST VPU VIO_Z VN_.V_HWM VPL_.V.V_UL V_S.V_SUS FH_VN ML V_S V_V_US.V_UL.V_UL.V_UL FH_V SSUS_S VPL_.V.V_UL VIO_Z V FH_VN R V.V FH_VN ML FH_VPL ML FH_VN R V_S FH_VPL SSUS_S V_V_US FH_VPL SUS_S VN_.V_HWM V_S FH_VN V_S VPL_.V V.V_FH_R V V_S FH_VPL ML PROJET : LZ Quanta omputer Inc. ate: ocument Number FH /(POWER/GN) Monday, January 0, 0 0 PROJET : LZ Quanta omputer Inc. ate: ocument Number FH /(POWER/GN) Monday, January 0, 0 0 PROJET : LZ Quanta omputer Inc. ate: ocument Number FH /(POWER/GN) Monday, January 0, 0 0 m 0m m m KV_.V-- Internal clock Generator I/O power 0m 00m V-- S/ ORE power 0m PIE_VR--PIE I/O power V_ST--ST phy power m m S_.--.v standby power m S_.V--.V standby power m 0m PLE LL THE EOUPLING PS ON THIS SHEET LOSE TO S S POSSILE. VG_P is generated from FH 0 m 0m TRE WITH >=mil m TRE WITH >=mil m 0m VQ--.V I/O power 0m m m m m m m m Max m Max 0m m S plus mode EMI hecklist request one uf capacitor E--0.U/.V_.U/.V_ L PY00T-Y-N(0,) L PY00T-Y-N(0,) L LMPGSN(0,.)_ L LMPGSN(0,.)_ 0.U/0V_X 0.U/0V_X U/0V_X U/0V_X 0 0.U/0V_X 0 0.U/0V_X.U/.V_X.U/.V_X R *0 short R *0 short 0.U/0V_X 0.U/0V_X Q IS@O0 Q IS@O0 L *P00T-Y-N(0,) L *P00T-Y-N(0,) U/0V_X U/0V_X *U/0V_X *U/0V_X 0.U/0V_X 0.U/0V_X U/0V_X U/0V_X R *0 short R *0 short 0 0.U/0V_X 0 0.U/0V_X *0.U/0V_X *0.U/0V_X U/0V_X U/0V_X R0 0_ R0 0_ 0.U/0V_X 0.U/0V_X.U/.V_X.U/.V_X R *0 short R *0 short R 0_ R 0_ L H0KF-T0(0,000M)_ L H0KF-T0(0,000M)_ U/0V_X U/0V_X Q *ISR@N00E Q *ISR@N00E.U/.V_X.U/.V_X 0U/.V_X 0U/.V_X U/0V_X U/0V_X 0.U/0V_X 0.U/0V_X R 00K/F_ R 00K/F_ U/0V_X U/0V_X 0.U/0V_X 0.U/0V_X U/0V_X U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X L PY00T-Y-N(0,) L PY00T-Y-N(0,) 0 U/0V_X 0 U/0V_X 0 U/0V_X 0 U/0V_X U/0V_X U/0V_X *.U/.V_X *.U/.V_X.U/.V_X.U/.V_X 0.U/0V_X 0.U/0V_X U/.V_X U/.V_X L PY00T-Y-N(0,) L PY00T-Y-N(0,) U/0V_X U/0V_X 0 U/0V_X 0 U/0V_X L H0KF-T0(0,000M)_ L H0KF-T0(0,000M)_ U/0V_X U/0V_X.U/.V_.U/.V_ U/0V_X U/0V_X U/0V_X U/0V_X U/0V_X U/0V_X R *0 short R *0 short U/0V_X U/0V_X L LMPGSN(0,.)_ L LMPGSN(0,.)_ 0 0.U/0V_X 0 0.U/0V_X.U/.V_.U/.V_ 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/.V_X 0.U/.V_X 0U/.V_X 0U/.V_X 00 0.U/0V_X 00 0.U/0V_X Q IS@O0 Q IS@O0.U/.V_X.U/.V_X L H0KF-T0(0,000M)_ L H0KF-T0(0,000M)_.U/.V_X.U/.V_X R M/J_ R M/J_.U/.V_X.U/.V_X US MIN LINK GE LN LKGEN I/O US SS SERIL T PI EXPRESS.V_S I/O ORE S0 PI/GPIO I/O POWER HUSON-M Part Hudson-M U US MIN LINK GE LN LKGEN I/O US SS SERIL T PI EXPRESS.V_S I/O ORE S0 PI/GPIO I/O POWER HUSON-M Part Hudson-M U VR SSUS_S_ M VR SSUS_S_ P VR SSUS_S_ N VR SSUS_S_ N VN SSUS_S_ P VN SSUS_S_ P VN SSUS_S_ N VN SSUS_S_ M VN SSUS_S_ P VR US_S_ T VR US_S_ T VN US_S_ U VN US_S_ U VN US_S_ M VN US_S_ N VN US_S_0 M VN US_S_ N0 VN US_S_ N VN US_S_ M0 VN US_S_ M VN US_S_ K VN US_S_ K VN US_S_ J VN US_S_ H VN US_S_ G VIO_GE_S_ 0 VIO_GE_S_ VR GE_S_ VR GE_S_ VIO GE_S 0 VN ML_ V VN ML_ V VN ML_ V VN ML_ Y VPL V LO_P M VPL ST G VPL PIE H VPL US_S VPL SSUS_S L VN T VPL ML U VPL V VPL SYS H VIO PIGP_0 VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ G VIO PIGP_ 0 VIO PIGP_ E VIO PIGP_ VIO PIGP_ VIO_Z_S VN HWM_S M VPL SYS_S J VR S_ M0 VR S_ N0 VXL S G VIO S_ W VIO S_ Y VIO S_ Y VIO S_ V VIO S_ V VIO S_ M VIO S_ L VIO S_ N VN ST_0 VN ST_ 0 VN ST_ VN ST_ 0 VN ST_ VN ST_ VN ST_ VN ST_ VN ST_ Y0 VN ST_ VN PIE_ G VN PIE_ F VN PIE_ VN PIE_ VN PIE_ VN PIE_ E VN PIE_ Y VN PIE_ VN LK_ P VN LK_ N VN LK_ N VN LK_ M VN LK_ L VN LK_ K VN LK_ J VN LK_ H VR Y VR V0 VR V VR V VR U VR U VR T0 VR T VR T U/0V_X U/0V_X L PY00T-Y-N(0,) L PY00T-Y-N(0,) 0 0.U/0V_X 0 0.U/0V_X R *.K/J_ R *.K/J_ R *0 short R *0 short U/0V_X U/0V_X 0.U/0V_X 0.U/0V_X Part GROUN HUSON-M Hudson-M U Part GROUN HUSON-M Hudson-M U VSSPL_SYS H VSSXL K VSSN_HWM N VSS_ T VSS_ T VSS_ T VSS_ R VSS_0 R VSS_ R VSS_ R VSS_ P VSS_ P VSS_ P VSS_ P0 VSS_ P VSS_ P VSS_ N VSS_0 N VSS_ N VSS_ N VSS_ N VSS_ M VSS_ M VSS_ M VSS_ M VSS_ L VSS_ L VSS_0 L VSS_ L VSS_ L VSS_ L VSS_ K VSS_ K VSS_ K VSS_ K VSS_ J VSS_ J VSS_0 J VSS_ J0 VSS_ J VSS_ J VSS_ H VSS_ H VSS_ H VSS_ G VSS_ G VSS_ G VSS_0 F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_0 E VSS_ E VSS_ E VSS_ E VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ EFUSE R VSSIO_ N VSSNQ_ K VSSN_ L VSSPL_ T VSS_ N VSS_ N VSS_ N VSS_ N VSS_ M VSS_ M VSS_ L VSS_ K VSS_0 K VSS_ J VSS_ J VSS_ J VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_0 H VSS_0 H VSS_0 G VSS_0 G0 VSS_0 F VSS_0 F VSS_0 F VSS_0 F VSS_0 E VSS_0 E VSS_00 E VSS_ E VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ 0 VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ Y VSS_ Y VSS_ Y VSS_0 W VSS_ W VSS_ W VSS_ W VSS_ V VSS_ V VSS_ V VSS_ U VSS_ U0 VSS_ U VSS_0 U0 VSS_ U VSS_ U VSS_ U VSS_ T VSS_ T *U/0V_X *U/0V_X 0 0.U/0V_X 0 0.U/0V_X U/0V_X U/0V_X.U/.V_X.U/.V_X L H0KF-T0(0,000M)_ L H0KF-T0(0,000M)_ 0.U/0V_X 0.U/0V_X.U/.V_X.U/.V_X U/0V_X U/0V_X 0.U/0V_X 0.U/0V_X U/0V_X U/0V_X.U/.V_X.U/.V_X U/0V_X U/0V_X U/.V_X U/.V_X R *0 short R *0 short 0.U/0V_X 0.U/0V_X 0 U/0V_X 0 U/0V_X U/.V_X U/.V_X L H0KF-T0(0,000M)_ L H0KF-T0(0,000M)_ *0.U/0V_X *0.U/0V_X R 0_ R 0_.U/.V_X.U/.V_X 0 U/.V_X 0 U/.V_X 0 0.U/0V_X 0 0.U/0V_X L H0KF-T0(0,000M)_ L H0KF-T0(0,000M)_ R *0 short R *0 short *0.U/0V_X *0.U/0V_X 0.U/0V_X 0.U/0V_X U/0V_X U/0V_X.U/.V_.U/.V_ U/0V_X U/0V_X.U/.V_X.U/.V_X U/0V_X U/0V_X 0 0.U/0V_X 0 0.U/0V_X U/0V_X U/0V_X L LMPGSN(0,.)_ L LMPGSN(0,.)_ R *0/J_ R *0/J_ 00 0U/.V_X 00 0U/.V_X L H0KF-T0(0,000M)_ L H0KF-T0(0,000M)_.U/.V_X.U/.V_X 0.U/0V_X 0.U/0V_X U/0V_X U/0V_X R *0/J_ R *0/J_ U/0V_X U/0V_X 0 *0.U/0V_X 0 *0.U/0V_X R *0 short R *0 short L H0KF-T0(0,000M)_ L H0KF-T0(0,000M)_ 0 0U/.V_X 0 0U/.V_X L PY00T-Y-N(0,) L PY00T-Y-N(0,) 0 0.U/0V_X 0 0.U/0V_X 0 0.U/0V_X 0 0.U/0V_X R *0 short R *0 short 0.U/0V_X 0.U/0V_X L H0KF-T0(0,000M)_ L H0KF-T0(0,000M)_ U/.V_X U/.V_X 0.U/.V_X 0.U/.V_X 0 0U/.V_X 0 0U/.V_X

OVERLP OMMON PS WHERE POSSILE FOR UL-OP RESISTORS. STRPS PINS V V V V_S V_S V_S V_S (,,,,0,,,,,,,,,,0,,,,,,0,,,,,,,) (,,,0,0,,) V V_S R 0K/J_ R *0K/J_ R *0K/J_ R *0K/J_ R 0K/J_ R *0K/J_ R 0K/J_ () () PI_LK PI_LK PI_LK PI_LK FH PWRG KT V V () () () () () PI_LK LP_LK0 LP_LK E_PWM RT_LK PI_LK LP_LK0 LP_LK E_PWM RT_LK R *0K/J_ R 0K/J_ R 0K/J_ R 0K/J_ R *0K/J_ R.K/J_ R *.K/J_ () VR_PWRG () E_PWROK T 0 R 0K/J_ *.U/.V_X R *UPGGW R 0 *0.U/0V_X U *0/J_ FH_PWRG () 0_ REQUIRE STRPS PULL HIGH -------- -------- PI_LK -------- LLOW PIE Gen EFULT -------- PI_LK USE EUG STRP PI_LK LP_LK0 non_fusion LOK MOE E ENLE LP_LK LKGEN ENLE EFULT E_PWM LP ROM RT_LK S PLUS MOE ISLE EFULT PULL LOW -------- FORE PIE Gen -------- IGNORE EUG STRP EFULT FUSION LOK MOE EFULT E ISLE EFULT LKGEN ISLE SPI ROM EFULT S PLUS MOE ENLE EUG STRPS FH HS K INTERNL PU FOR PI_[:] () PI_ PI_ () PI_ PI_ () PI_ PI_ PI_ PI_ PI_ PI_ PI_ () () PI_ PI_ PI_ PI_ PULL HIGH USE PI PLL ISLE IL UTORUN USE F PLL USE EFULT PIE STRPS ISLE PI MEM OOT R *.K/J_ R0 *.K/J_ R *.K/J_ R0 *.K/J_ R0 *.K/J_ PULL LOW EFULT YPSS PI PLL EFULT ENLE IL UTORUN EFULT YPSS F PLL EFULT USE EEPROM PIE STRPS EFULT ENLE PI MEM OOT PROJET : LZ Quanta omputer Inc. ate: ocument Number FH /(Strap & PWRG) Monday, January 0, 0

M 0 M M M M M M 0 M M M M M M M M M SM_RUN_LK SM_RUN_T M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q IMM0_S0 IMM0_S M [:0] () M S#0 () M S# () M LKP0 () M LKN0 () M LKP () M LKN () M KE0 () M KE () M S# () M RS# () M WE# () M QSP[:0] () M QSN[:0] () M OT0 () M OT () M Q[0..] () SM_RUN_LK (,) SM_RUN_T (,) M RST# () M EVENT# () M M0 () M M () M M () M M () M M () M M () M M () M M () M S#0 () M S# () M S# () V (,,,,0,,,,,,,,,,0,,,,,,0,,,,,,,).V_SUS (,,,,0,,,0,,,) 0.V_R_VTT (,,0) R_VTTREF (0) 0.V_VREF_Q () 0.V_VREF_ ().V_SUS V 0.V_R_VTT V.V_SUS 0.V_R_VTT 0.V_VREF_Q 0.V_VREF_.V_SUS 0.V_VREF_ 0.V_VREF_ 0.V_VREF_Q 0.V_VREF_Q.V_SUS PROJET : LZ Quanta omputer Inc. ate: ocument Number RIII SO-IMM-0 Monday, January 0, 0 PROJET : LZ Quanta omputer Inc. ate: ocument Number RIII SO-IMM-0 Monday, January 0, 0 PROJET : LZ Quanta omputer Inc. ate: ocument Number RIII SO-IMM-0 Monday, January 0, 0. R_ST(R) Place these aps near So-imm0. R0 0K/J_ R0 0K/J_ 0.u/0V_X 0.u/0V_X 0U/.V_X 0U/.V_X 0 U/.V_X 0 U/.V_X 0U/.V_X 0U/.V_X 000P/0V_X 000P/0V_X.P/0V/OG_.P/0V/OG_ 0 U/0V_X 0 U/0V_X R K/F_ R K/F_ 0.U/0V_X 0.U/0V_X R0 K/F_ R0 K/F_ 0U/.V_X 0U/.V_X 0P/0V_X 0P/0V_X 0U/.V_X 0U/.V_X U/0V_X U/0V_X P00 R SRM SO-IMM (0P) JIM R-IMM_H=_ST_SKT P00 R SRM SO-IMM (0P) JIM R-IMM_H=_ST_SKT 0 0 0/P 0 /# 0 0 0 0 S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q U/0V_X U/0V_X *0U/.V_X *0U/.V_X.U/.V_X.U/.V_X 0 U/.V_X 0 U/.V_X 0U/.V_X 0U/.V_X 0.u/0V_X 0.u/0V_X P00 R SRM SO-IMM (0P) JIM R-IMM_H=_ST_SKT P00 R SRM SO-IMM (0P) JIM R-IMM_H=_ST_SKT V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 GN 0 GN 0 *0U/V_P_Eb *0U/V_P_Eb 000P/0V_X 000P/0V_X U/0V_X U/0V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0P/0V_X 0P/0V_X U/.V_X U/.V_X 0U/.V_X 0U/.V_X R *0/J_ R *0/J_ *0U/.V_X *0U/.V_X R K/F_ R K/F_ 0U/.V_X 0U/.V_X R 0K/J_ R 0K/J_ R K/F_ R K/F_ U/.V_X U/.V_X

M 0 M M M M M M 0 M M M M M M M M M M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q IMM_S0 IMM_S M [:0] () M S#0 () M S# () M S# () M S#0 () M S# () M LKP0 () M LKN0 () M LKP () M LKN () M KE0 () M KE () M S# () M RS# () M WE# () M QSP[:0] () M QSN[:0] () M OT0 () M OT () M Q[0..] () M RST# () M EVENT# () SM_RUN_LK (,) SM_RUN_T (,) M M0 () M M () M M () M M () M M () M M () M M () M M () V (,,,,0,,,,,,,,,,0,,,,,,0,,,,,,,).V_SUS (,,,,0,,,0,,,) 0.V_R_VTT (,,0) 0.V_VREF_Q () 0.V_VREF_ ().V_SUS V 0.V_R_VTT 0.V_VREF_ V.V_SUS 0.V_R_VTT 0.V_VREF_Q V 0.V_VREF_ 0.V_VREF_Q PROJET : LZ Quanta omputer Inc. ate: ocument Number RIII SO-IMM- Monday, January 0, 0 PROJET : LZ Quanta omputer Inc. ate: ocument Number RIII SO-IMM- Monday, January 0, 0 PROJET : LZ Quanta omputer Inc. ate: ocument Number RIII SO-IMM- Monday, January 0, 0 Place these aps near So-imm.. R_ST(R) 0U/.V_X 0U/.V_X 0.u/0V_X 0.u/0V_X.U/.V_X.U/.V_X *0U/.V_X *0U/.V_X 0 U/0V_X 0 U/0V_X 0 0U/.V_X 0 0U/.V_X 0.U/0V_X 0.U/0V_X 000P/0V_X 000P/0V_X P00 R SRM SO-IMM (0P) JIM R-IMM0_H=_ST_SKT P00 R SRM SO-IMM (0P) JIM R-IMM0_H=_ST_SKT V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 GN 0 GN 0 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X R0 0K/J_ R0 0K/J_ 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X U/0V_X U/0V_X *0U/.V_X *0U/.V_X U/0V_X U/0V_X U/.V_X U/.V_X 0.u/0V_X 0.u/0V_X 0U/.V_X 0U/.V_X.P/0V/OG_.P/0V/OG_ U/.V_X U/.V_X 000P/0V_X 000P/0V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X P00 R SRM SO-IMM (0P) JIM R-IMM0_H=_ST_SKT P00 R SRM SO-IMM (0P) JIM R-IMM0_H=_ST_SKT 0 0 0/P 0 /# 0 0 0 0 S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q R 0K/J_ R 0K/J_ 0 U/0V_X 0 U/0V_X

U0 (,,,) (,,,,,) V_GPU V_GPU () () PEG_TXP0 PEG_TXN0 Y PIE_RX0P PIE_RX0N PIE_TX0P PIE_TX0N Y Y PEG_RXP0_ PEG_RXN0_ 00 00 IS@0.U/0V_X IS@0.U/0V_X PEG_RXP0 () PEG_RXN0 () () () PEG_TXP PEG_TXN Y W PIE_RXP PIE_RXN PIE_TXP PIE_TXN W W PEG_RXP_ PEG_RXN_ 0 0 IS@0.U/0V_X IS@0.U/0V_X PEG_RXP () PEG_RXN () () () PEG_TXP PEG_TXN W V PIE_RXP PIE_RXN PIE_TXP PIE_TXN U U PEG_RXP_ PEG_RXN_ 00 00 IS@0.U/0V_X IS@0.U/0V_X PEG_RXP () PEG_RXN () () () PEG_TXP PEG_TXN V U PIE_RXP PIE_RXN PIE_TXP PIE_TXN U0 U PEG_RXP_ PEG_RXN_ 0 00 IS@0.U/0V_X IS@0.U/0V_X PEG_RXP () PEG_RXN () () () () () () () () () () () () () () () () () () () PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP0 PEG_TXN0 PEG_TXP PEG_TXN PEG_TXP PEG_TXN U T T R R P P N N M M L L K K J J H PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RX0P PIE_RX0N PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_TXP PIE_TXN PI EXPRESS INTERFE PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TX0P PIE_TX0N PIE_TXP PIE_TXN PIE_TXP PIE_TXN T T T0 T P P P0 P N N N0 N L L L0 L K K PEG_RXP_ 00 PEG_RXN_ 00 PEG_RXP_ 00 PEG_RXN_ 000 PEG_RXP_ 0 PEG_RXN_ 0 PEG_RXP_ 0 PEG_RXN_ 0 PEG_RXP_ 00 PEG_RXN_ 0 PEG_RXP_ 0 PEG_RXN_ 0 PEG_RXP0_ 0 PEG_RXN0_ 00 PEG_RXP_ PEG_RXN_ 00 0 PEG_RXP_ 0 PEG_RXN_ 0 IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X IS@0.U/0V_X PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () PEG_RXP0 () PEG_RXN0 () PEG_RXP () PEG_RXN () PEG_RXP () PEG_RXN () () () PEG_TXP PEG_TXN H G PIE_RXP PIE_RXN PIE_TXP PIE_TXN J J PEG_RXP_ 0 PEG_RXN_ 00 IS@0.U/0V_X IS@0.U/0V_X PEG_RXP () PEG_RXN () () () PEG_TXP PEG_TXN G F PIE_RXP PIE_RXN PIE_TXP PIE_TXN K0 K PEG_RXP_ 0 PEG_RXN_ 0 IS@0.U/0V_X IS@0.U/0V_X PEG_RXP () PEG_RXN () () () PEG_TXP PEG_TXN F E PIE_RXP PIE_RXN PIE_TXP PIE_TXN H H PEG_RXP_ 0 PEG_RXN_ 0 IS@0.U/0V_X IS@0.U/0V_X PEG_RXP () PEG_RXN () () LK_PIE_VGP () LK_PIE_VGN For M only Madison and Park the PWRGOO ball is for test purposes and must be conneccted to ground R IS@0K/F_ J K H LOK PIE_REFLKP PIE_REFLKN N# N# PWRGOO LIRTION PIE_LRP PIE_LRN Y0 Y PIE_LRP PIE_LRN R R IS@.K/F_ IS@K/F_ V_GPU GPU_RST# 0 PERST IS@Seymour/Thames_M V_GPU R IS@0K_ (,) PU_PIE_RST# *IS@SS () dgpu_rst# 0 IS@SS GPU_RST# PROJET : LZ Quanta omputer Inc. ate: ocument Number Seymour/Thames-M PIE I/F Monday, January 0, 0

U0 TXP_PP TXM_PN U V (,,,) (,,,) (,0,,,,,,,,,,,) (,,,,,) V_GPU.V_GPU VPU V_GPU MUTI GFX P TX0P_PP TX0M_PN TXP_PP TXM_PN T R U V U0G.V_GPU L V_GPU (.V@m PLL_PV) (.V@m PLL_PV) 0 ohm/00m IS@LMSN_00M PLL_PV IS@0U/.V_X IS@U/.V_X R IS@K/F_ 0 R *IS@0K/F_ IS@0.U/0V_X V_GPU R IS@K/F_ () () () () () () () () () RM_STRP0 RM_STRP RM_STRP RM_STRP () () SL S () GPU_GPIO0 () GPU_GPIO () GPU_GPIO GPIO_SMT GPIO_SMLK () GPU_LON () SOUT_GPIO () SIN_GPIO () GPIO0_ROMSK () RM_FG0 () RM_FG () RM_FG GFX_ORE_NTRL0 () LT#_GPIO GFX_ORE_NTRL () SS#_GPIO FH_PIE_PEG_LKREQ# *IS@00K/F_ N on Robson apilano support N on Robson apilano support SL must be tied high if not used T V_GPU R R *IS@.K/F_ T T R *IS@.K/F_ R LK_VG_M_SS_R *IS@0K/F_ LT#_GPIO T0 IS@0K/F_ R T FH_PIE_PEG_LKREQ# T GPU_JTG_TRST T GPU_JTG_TI T0 GPU_JTG_TK T GPU_JTG_TMS T GPU_JTG_TO T T T T T EXT_HMI_HP R U P W R R U U W P W U R W U T V N V T R0 W0 U0 P0 V T R W U P K J H0 H N H J H J K J H J K L M M M K G0 N M L J K N M N K L M J K J0 K0 J H H K VPNTL_MVP_0 VPNTL_MVP_ VPNTL_0 VPNTL_ VPNTL_ VPLK VPT_0 VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_0 VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_0 VPT_ VPT_ VPT_ I SL S GENERL PURPOSE I/O GPIO_0 GPIO_ GPIO_ GPIO SMT GPIO SMLK GPIO TT GPIO_ GPIO LON GPIO ROMSO GPIO ROMSI GPIO_0_ROMSK GPIO_ GPIO_ GPIO_ GPIO HP GPIO PWRNTL_0 GPIO SSIN GPIO THERML_INT GPIO HP GPIO TF GPIO_0_PWRNTL_ GPIO EN GPIO ROMS GPIO LKREQ JTG_TRST JTG_TI JTG_TK JTG_TMS JTG_TO GENERI GENERI GENERI GENERI GENERIE_HP GENERIF GENERIG HP P P P TXP_P0P TXM_P0N TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_P0P TXM_P0N TXP_PP TXM_PN TX0P_PP TX0M_PN TXP_PP TXM_PN TXP_P0P TXM_P0N TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_P0P TXM_P0N R R G G HSYN VSYN RSET V VSSQ VI VSSI R R G G Y OMP HSYN VSYN VI VSSI T R R0 T V U0 R T T U U V T R U V T R U0 T T R0 U V T R E F E E 0 0 F0 F F G G R0 V VI Park hannel -->No support M hannel &-->No support T T IS@/F_ HSYN () VSYN () V VI (.V@0m V) (.V@0m V) IS@0.U/0V_X IS@U/.V_X (.V@m VI) (.V@m VI) *IS@0.U/0V_X LVS ONTROL LVTMP IS@Seymour/Thames_M 0 *IS@U/.V_X VRY_L IGON TXLK_UP_PFP TXLK_UN_PFN TXOUT_U0P_PFP TXOUT_U0N_PFN TXOUT_UP_PFP TXOUT_UN_PFN TXOUT_UP_PF0P TXOUT_UN_PF0N TXOUT_UP TXOUT_UN TXLK_LP_PEP TXLK_LN_PEN TXOUT_L0P_PEP TXOUT_L0N_PEN TXOUT_LP_PEP TXOUT_LN_PEN TXOUT_LP_PE0P TXOUT_LN_PE0N TXOUT_LP TXOUT_LN K J K L J K H J G H F G P R W U R U P R N P T0 T0 0 ohm/00m L IS@LMSN_00M IS@0U/.V_X T0 T0 T0 T0 T0 T0 0 ohm/00m L *IS@LMSN_00M *IS@0U/.V_X.V_GPU V_GPU (V@m PLL_V) (V@m PLL_V) 0 ohm/00m L IS@LMSN_00M IS@0U/.V_X IS@U/.V_X PLL_V IS@0.U/0V_X.V_GPU Place close to hip R IS@/F_ VREFG H VREFG V VQ VSSQ RSET G V VQ F T T0.V_GPU (.V@m TS_V) (.V@m TS_V) 0 ohm/00m L0 IS@LMSN_00M TS_V IS@0U/.V_X IS@U/.V_X IS@0.U/0V_X IS@P/0V_ R IS@/F_ IS@0.U/0V_X PLL_PV PLL_V VG_XTLIN VG_XTLOUT R IS@M/F_ IS@MHZ_0 (,) VG_THERMP Y (,) VG_THERMN IS@P/0V_ T TS_V M N N V U F G K J J PLL/LOK PLL_PV PLL_PVSS PLL_V XTLIN XTLOUT PLUS THERML MINUS TS_FO TSV TSVSS /UX LK T UXP UXN LK T UXP UXN LK_UXP T_UXN LK_UXP T_UXN LK_UXP T_UXN LK T M N M L M L N0 M0 L0 M0 L M N M J0 J T T T T T T T T0 IS@Seymour/Thames_M N_LK_UXP N_T_UXN K0 K T T ate: PROJET : LZ Quanta omputer Inc. ocument Number Seymour/Thames-M HOST I/F Monday, January 0, 0

Thames XT use Memory Group (,,,,,) (,0,,,) V_GPU.V_GPU (0) VM_Q[..0] VM_Q[..0] () VM_Q[..0] VM_Q[..0] VM_M[..0] (0) VM_M[..0] VM_RQS[..0] (0) VM_RQS[..0] VM_WQS[..0] (0) VM_WQS[..0] VM_M[..0] (0) VM_M[..0] VM_0 (0) VM_0 VM_ (0) VM_ VM_ (0) VM_.V_GPU R Ra IS@0./F_ Place close to hip Rb R00 00 IS@00/F_ IS@0.U/0V_X.V_GPU.V_GPU R R0 R R R R VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q MVREF MVREFS IS@0/F_ IS@0/F_ IS@0/F_ IS@0/F_ IS@0/F_ IS@0/F_ E G F E F0 0 0 F E F F E F 0 F0 E F F E F F F0 0 0 G H J H G0 G K K0 G E E L L0 L N G M M H L U0 R GR/GR R Q0_0/Q_0 Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_0/Q_0 Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_0/Q_0 Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_0/Q_0 Q0_/Q_ Q_0/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_0 Q_/Q_ Q_0/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_0 Q_/Q_ Q_0/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_0 Q_/Q_ Q_0/Q_ Q_/Q_ MVREF MVREFS MEM_LRN0 MEM_LRN MEM_LRN MEM_LRP MEM_LRP0 MEM_LRP RSV MEMORY INTERFE R GR/GR R M0_0/M_0 M0_/M_ M0_/M_ M0_/M_ M0_/M_ M0_/M_ M0_/M_ M0_/M_ M_0/M_ M_/M_ M_/M_0 M_/M_ M_/M_ M_/M M_/M 0 M_/M WK0_0/QM_0 WK0_0/QM_ WK0_/QM_ WK0_/QM_ WK_0/QM_ WK_0/QM_ WK_/QM_ WK_/QM_ GR/R/GR E0_0/QS_0/RQS_0 E0_/QS_/RQS_ E0_/QS_/RQS_ E0_/QS_/RQS_ E_0/QS_/RQS_ E_/QS_/RQS_ E_/QS_/RQS_ E_/QS_/RQS_ I0_0/QS_0/WQS_0 I0_/QS_/WQS_ I0_/QS_/WQS_ I0_/QS_/WQS_ I_0/QS_/WQS_ I_/QS_/WQS_ I_/QS_/WQS_ I_/QS_/WQS_ I0/OT0 I/OT GR LK0 LK0 LK LK RS0 RS S0 S S0_0 S0_ S_0 S_ KE0 KE WE0 WE M0_ M_ G J H J H J H G H H0 L G J H J H E E0 E0 E E J0 E0 E 0 J F J G H G J H K K K0 K K K M K K J0 K L H J VM_M0 VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M0 VM_M VM_M VM_ VM_0 VM_ VM_M0 VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_RQS0 VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_WQS0 VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_LK0 VM_LK0# VM_LK VM_LK# VM_RS0# VM_RS# VM_S0# VM_S# VM_S0# VM_S# VM_KE0 VM_KE VM_WE0# VM_WE# VM_M QS[..0] QS#[..0] VM_OT0 (0) VM_OT (0) VM_LK0 (0) VM_LK0# (0) VM_LK (0) VM_LK# (0) VM_RS0# (0) VM_RS# (0) VM_S0# (0) VM_S# (0) VM_S0# (0) VM_S# (0) VM_KE0 (0) VM_KE (0) VM_WE0# (0) VM_WE# (0) only for apilano x support [M x x ] = 0Mits () () Ra Rb () () VM_M[..0] VM_RQS[..0] VM_WQS[..0] () () ().V_GPU.V_GPU VM_M[..0] VM_0 VM_ VM_ R IS@0./F_ R IS@00/F_ VM_M[..0] VM_RQS[..0] VM_WQS[..0] VM_M[..0] VM_0 VM_ VM_ Place close to hip IS@0.U/0V_X VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q MVREF MVREFS GPU_TESTEN LKTEST LKTEST E E F F F G H H J K K L M M M M N P P R T T U V V V Y Y Y Y F F F G H H J K F F G G K L M M K L M M N P P P Y K0 L0 U0 R GR/GR R Q0_0/Q_0 Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_0/Q_0 Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_0/Q_0 Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_/Q_ Q0_0/Q_0 Q0_/Q_ Q_0/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_0 Q_/Q_ Q_0/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_0 Q_/Q_ Q_0/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_ Q_/Q_0 Q_/Q_ Q_0/Q_ Q_/Q_ MVREF MVREFS TESTEN LKTEST LKTEST MEMORY INTERFE R GR/GR R M0_0/M_0 M0_/M_ M0_/M_ M0_/M_ M0_/M_ M0_/M_ M0_/M_ M0_/M_ M_0/M_ M_/M_ M_/M_0 M_/M_ M_/M_ M_/ M_/0 M_/ WK0_0/QM_0 WK0_0/QM_ WK0_/QM_ WK0_/QM_ WK_0/QM_ WK_0/QM_ WK_/QM_ WK_/QM_ GR/R/GR E0_0/QS_0/RQS_0 E0_/QS_/RQS_ E0_/QS_/RQS_ E0_/QS_/RQS_ E_0/QS_/RQS_ E_/QS_/RQS_ E_/QS_/RQS_ E_/QS_/RQS_ I0_0/QS_0/WQS_0 I0_/QS_/WQS_ I0_/QS_/WQS_ I0_/QS_/WQS_ I_0/QS_/WQS_ I_/QS_/WQS_ I_/QS_/WQS_ I_/QS_/WQS_ I0/OT0 I/OT LK0 LK0 LK LK RS0 RS S0 S S0_0 S0_ S_0 S_ KE0 KE WE0 WE GR M0_ M_ RM_RST P T P N N N U U Y W Y H H T T E F K K F K P V H J M G K P W H J M T W L L T0 Y0 W0 0 P0 L0 0 0 U0 N0 T W H VM_M0 VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M0 VM_M VM_M VM_ VM_0 VM_ VM_M0 VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_RQS0 VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_WQS0 VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_LK0 VM_LK0# VM_LK VM_LK# VM_RS0# VM_RS# VM_S0# VM_S# VM_S0# VM_S# VM_KE0 VM_KE VM_WE0# VM_WE# VM_M R QS[..0] QS#[..0] VM_OT0 () VM_OT () VM_LK0 () VM_LK0# () VM_LK () VM_LK# () VM_RS0# () VM_RS# () VM_S0# () VM_S# () VM_S0# () VM_S# () VM_KE0 () VM_KE () VM_WE0# () VM_WE# () for apilano x support [M x x ] = 0Mits IS@0 R IS@ MEM_RST# (0,) Ra Rb R0 IS@0./F_ R0 IS@00/F_ IS@0.U/0V_X IS@Seymour/Thames_M all Name Seymour M Thames M MVREF N V Ra Rb R IS@0./F_ R IS@00/F_ IS@0.U/0V_X *IS@0.U/0V_X R0 *IS@./F_ IS@Seymour/Thames_M *IS@0.U/0V_X LKTEST/LKTEST R ifferemtial only *IS@./F_ Single 0 ohm iff 00 ohm R IS@.K/F IS@0P R/GR Memory Stuff Option Robson/apilano R MVQ.V Ra 0.R Rb 00R MVREFS MVREF MVREFS MEM_LRN0 MEM_LRN MEM_LRN MEM_LRP0 N V V N V N N V V V V V V V V_GPU R00 *IS@0K/J_ GPU_TESTEN R IS@0K/J_ TESTEN 0 e-pop for normal operation escription Internal ebug use only JTG signals enable MEM_LRP MEM_LRP V N V V PROJET : LZ Quanta omputer Inc. ate: ocument Number Seymour/Thames-M MEM I/F Monday, January 0, 0