⊙内容：常用逻辑电路设计

内容 : 常用逻辑电路设计一般组合逻辑电路设计 例 2: 全加器设计 一般时序逻辑电路设计 一 一般组合逻辑电路设计 1 概念 : 组合逻辑电路输出只与当前的输入有关, 而与历史状态无关 即组合逻辑电路是无记忆功能电路 2 常见电路 : (1) 基本门电路 ( 与 非 或等 ) (2) 选择电路 (N 选 1 电路等 ) (3) 编码与解码电路 (3-8 电路 7 段显示 ) (4) 加法电路 ( 半加器 全加器 ) (5) 求补码电路 (6) 三态门电路 3 电路应用举例例 1: 半加器设计 输入 输出 x y cin s co 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 ENTITY plus2 IS PORT(x,y,cin: IN std_logic; S,co: out std_logic); 输入 输出 x y s co 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 S= xy+x y=x+y=x or y; Co=xy=x and y. ENTITY plus1 IS PORT(x,y: IN std_logic; S,co: out std_logic); ARCHITECTURE aaa OF plus1 IS S= xy+x y=x+y=x or y; Co=xy=x and y; End; ARCHITECTURE aaa OF plus2 IS Begin Process(a,b,cin) Variable temp: std_logic_vector(2 downto 0) Temp:=x&y&cin; Case temp is When 000 =>s<= 0 ; co<= 0 ; When 001 010 100 =>s<= 1 ; co<= 0 ; When 011 101 110 =>s<= 0 ; co<= 1 ; When 111 =>s<= 1 ; co<= 1 ; When others=>s<= X ; co<= X ; End case; End;

例 3: 求补码电路正数的补码与原码相同, 即最高位为符号位, 用 0 表示正数, 其余位为数值位 负数的补码为它的反码, 且在最底位加 1 形成 如 :[+4] 原 [00000100]b; [+4] 补 [00000100]b; [-4] 原 [10000100]b; [+4] 反 [11111011]b; [+4] 补 [+4] 反 + 1 11111011+00000001 11111100 ENTITY qiubu IS PORT(a: IN std_logic_vector(7 downto 0); b: OUT std_logic_vector(7 downto 0)); ARCHITECTURE aaa OF qiubu IS process(a) if a(7)='0'then b<= a; b<=not a + '1'; 例 4: 三态门电路 三态门电路用途 :1 双向口 2 多路数据竞争 或多路选择电路 输入 DIN, 输出 DOUT 当 EN=1 时,DOUT=DIN; 当 EN=0 时,DOUT=Z; 输入 输入使能 输出 DIN EN DOUT X 0 z 0 1 0 1 1 1 ENTITY TRI_GATE IS PORT(din,en: IN std_logic; dout: OUT std_logic); ARCHITECTURE aaa OF TRI_GATE IS process(din,en) if en='1'then dout<= din; dout<= 'Z';

4 2 线优先编码器 entity encoder is port(in0,in1,in2,in3:in std_logic; out0,out1:out std_logic); end; architecture behave of encoder is signal ou:std_logic_vector (1 downto 0); ou<="11" when in3='1' "10" when in2='1' "01" when in1='1' "00" when in0='1' "00"; out1<=ou(1); out0<=ou(0); end behave; 一位十进制编码器 entity decode is port(in0,in1,in2,in3,in4,in5,in6,in7,in8,in9 : in std_logic; decode:out std_logic_vector(3 downto 0)); end decode; architecture behave of decode is signal s_vec : std_logic_vector(9 downto 0) ; s_vec<=(in9, in8, in7, in6, in5, in4, in3, in2, in1, in0); with s_vec select out_decode<= "1001" when "1000000000", -- 数字 9 "1000" when "0100000000", -- 数字 8 "0111" when "0010000000", -- 数字 7 "0110" when "0001000000", -- 数字 6 "0101" when "0000100000", -- 数字 5 "0100" when "0000010000", -- 数字 4 "0011" when "0000001000", -- 数字 3 "0010" when "0000000100", -- 数字 2 "0001" when "0000000010", -- 数字 1 "0000"when others; -- 数字 0 end behave;

一般组时序辑电路设计 1 概念: 时序逻辑电路输出不仅与当前的输入有关, 与历史状态也有关 即时序逻辑电路是有记忆功能电路 2 常见电路: (1) 触发电路 (D T RS JK 等 ) (2) 寄存器电路 (3) 计数器电路 (4) (5) (6) 2 电路应用举例例 1:T 触发设计 CLK Q X Qn-1 Qn-1 ENTITY tff1 IS PORT(clk: IN std_logic; q: OUT std_logic); ARCHITECTURE aaa OF tff1 IS signal q_n:std_logic; process(clk) if clk='1'and clk' event then q_n<=not q_n ; q<=q_n; 例 2:RS 触发设计 真值表 Qn R S Qn+1 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 X 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 X 卡诺图 RS 00 01 11 10 QN 0 0 1 X 0 1 1 1 X 0 Q N+1 =S+ RQ N RS=0 约束条件 ENTITY rs_ff IS PORT(r,s,qn: IN std_logic; qn1: OUT std_logic); ARCHITECTURE aaa OF rs_ff IS --signal qn:std_logic; process(r,s,qn) qn1<=s or (not r and qn) ;

例 3:JK 触发设计 例 4:8 位积存器 74ls374 的设计 j k Qn Qn+1 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 1 Qn+1=J Qn+ K Qn ENTITY jk_ff IS PORT(j,k,qn,clk: IN std_logic; qn1: OUT std_logic); ARCHITECTURE aaa OF jk_ff IS --signal qn:std_logic; process(j,k,qn,clk) if clk'event and clk='1' then qn1<=(not qn and j ) or (not k and qn) ; oe cp d Q 0 0 0 0 1 1 0 0 x 保持 1 x x 高阻 ENTITY register1 IS PORT(d: in std_logic_vector(7 downto 0); oe,clk: in std_logic; q: OUT std_logic_vector(7 downto 0)); ARCHITECTURE aaa OF register1 IS signal q_temp: std_logic_vector(7 downto 0); process(clk,oe) if (oe='1')then q_temp<="00000000"; elsif clk='1' and clk'event then q_temp<=d; q<= q_temp;

例 5: 用 D 触发器器设计 4 位串入 / 并出移位寄存器 例 6: 设计 4 位二进制串入 / 并出同步计数器 计数器 能够记忆时钟信号的时序逻辑电路 还可以进行分频 定时 产生脉冲等信号 ENTITY move_reg IS PORT(a,clk: in std_logic; -- b: out std_logic; q: OUT std_logic_vector(1 to 4)); ARCHITECTURE aaa OF move_reg IS component dff1 port(d,clk:in std_logic; q:out std_logic); end component; signal x: std_logic_vector(0 to 4); x(0)<=a; aa:for i in 0 to 3 generate u: dff1 port map(x(i),clk, x(i+1)); end generate; q<=x(1 to 4); --b<=x(4); -------------------------------------------------------------- R S EN CLK Q3 Q2 Q1 Q0 1 X X X 0 0 0 0 0 1 X 预置值 0 0 1 计数值加 1 0 0 0 X 不变 ENTITY counter4bit IS PORT( reset,clk,set,en: in std_logic; count: out std_logic; q: buffer std_logic_vector(3 downto 0)); ARCHITECTURE aaa OF counter4bit IS process(clk,reset) if (reset='1')then q<=(others=>'0'); elsif clk='1' and clk'event then if (set='1')then q<="1010"; elsif(en='1')then q<=q+1; q<=q; count<='1'when (q="1111"and en='1') '0';

例 7: 用 D 触发器器设计 4 位异步并行输出计数器 低层 D 触发器器设计 ENTITY async_counter4bit IS PORT( clk,reset: in std_logic; count: out std_logic_vector(1 to 4)); ARCHITECTURE aaa OF async_counter4bit IS component async_dff PORT( d,clk,reset: in std_logic; q,qb: out std_logic); end component; signal x :std_logic_vector(0 to 4); x(0)<=clk; shen:for i in 0 to 3 generate aa: async_dff port map (d=>x(i+1),clk=>x(i),reset,q=>count(i+1),qb =>x(i+1)); end generate ; ENTITY async_dff IS PORT( d,clk,reset: in std_logic; q,qb: out std_logic); ARCHITECTURE aaa OF async_dff IS process(clk,reset) if (reset='1')then q<='0'; qb<='1'; elsif clk='1' and clk'event then q<=d; qb<=not d;

四位双向移位寄存器 entity shift is port(clk,rst,load,left_right : in std_logic; -- 时钟 复位 置数 移位控制信号 din : in std_logic_vector(3 downto 0); -- 预置数输入信号 dout : inout std_logic_vector(3 downto 0)); -- 输出信号 end shift; architecture behave of shift is constant len: integer:=3; process (clk,rst,load,left_right,din) if rst= 1 then dout<= 0000 ; -- 异步复位 elsif rising_edge(clk) then if (load='1') then dout<=din; -- 同步置数 elsif (left_right='0') then -- 循环右移 dout<=dout(0)&dout(len downto 1); elsif(left_right='1')then -- 循环左移 dout<=dout(len-1 downto 0)&dout(3); end behave; 同步十进制可逆计数器 entity count is port(clk,rst,load,plus_sub : in std_logic; din: in std_logic_vector(3 downto 0); dout: buffer std_logic_vector(3 downto 0)); end count; architecture behave of count is process(clk,rst,load,plus_sub,din) if (clk'event and clk='1') then if (rst='1') then dout<=(others=>'0'); -- 同步复位 elsif (load='1') then dout<=din; -- 同步置数 elsif (plus_sub='1') then -- 加法计数 if (dout=9) then dout<="0000"; dout<=dout+1; elsif (plus_sub='0') then -- 减法计数 if (dout=0) then dout<="1001"; dout<=dout-1; end behave;

例 8: 设计异步清零的使能的 10 进制计数器 例 9: 计异步清零的使能的 60 进制计数器 ENTITY counter10 IS PORT( reset,clk,en: in std_logic; cout: out std_logic; outy: out std_logic_vector(3 downto 0)); ARCHITECTURE aaa OF counter10 IS signal cnt :std_logic_vector(3 downto 0); process(clk,reset) if (reset='1')then cnt<=(others=>'0'); elsif if (en='1')then if cnt="1001"then cnt<="0000"; cout<='1'; cnt<=cnt+1; cout<='0'; outy<=cnt; clk='1' and clk'event then ENTITY counter60 IS PORT( clr,clk,en: in std_logic; cout: out std_logic; qh: buffer std_logic_vector(3 downto 0); ql: buffer std_logic_vector(3 downto 0)); ARCHITECTURE aaa OF counter60 IS cout<='1'when(qh="0101"and ql="1001"and en='1')'0'; process(clk,clr) if (clr='0')then qh<="0000"; ql<="0000"; elsif clk='1' and clk'event then if (en='1')then if ql=9 then ql<="0000"; if qh=5 then qh<="0000"; qh<=qh+1; ql<=ql+1; --end if (en) --end if (clr)

内容 : 一般实际电路设计 例题 1 如图所示 用 VHDL 语言设计一个 6 分频电路, 要求输出信号的占空比 1:1 例题 2 如图所示 用 VHDL 语言设计一个 16 分频电路, 要求输出信号的占空比 1:1 --p187 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY clk_div6 IS PORT(clk: IN std_logic; clk_out:out std_logic); ----------------------------- ARCHITECTURE beh OF clk_div6 IS signal clk_temp: std_logic; PROCESS(clk) variable counter:integer range 0 to 15;--10; constant md:integer:=2; if (clk'event and clk='1')then if counter=md then counter:=0; clk_temp<=not clk_temp; counter:=counter+1; clk_out<=clk_temp; end beh; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY clk_div16 IS PORT(clk: IN std_logic; clk_out:out std_logic); ----------------------------- ARCHITECTURE beh OF clk_div16 IS signal clk_temp: std_logic; PROCESS(clk) variable counter:integer range 0 to 15;--10; constant md:integer:=7; if (clk'event and clk='1')then if counter=md then counter:=0; clk_temp<=not clk_temp; counter:=counter+1; clk_out<=clk_temp; end beh;

例题 3 如图所示 用 VHDL 语言设计一个 16 分频电路, 要求输出信号的占空比 1:15 例题 4 如图所示 用 VHDL 语言设计同步 24 进制计数器 ---p188 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY clk_div_16 IS PORT(clk: IN std_logic; clk_out:out std_logic); ----------------------------- ARCHITECTURE beh OF clk_div_16 IS signal counter: std_logic_vector(3 downto 0); p1: PROCESS(clk) if (clk'event and clk='1')then if counter="1111" then counter<=(others=>'0'); counter<=counter+1; p2: PROCESS(clk) if (clk'event and clk='1')then if counter="1111" then clk_out<='1'; clk_out<='0'; end beh; library altera; use altera.maxplus2.all; library lpm; use lpm.lpm_components.all; library std; use std.textio.all; --************************************** entity count24 is port( clk,clr,en:in std_logic; --cy:out std_logic; qh,ql:out std_logic_vector(3 downto 0) ); end count24; --****************************************** architecture a of count24 is signal qh_tmp,ql_tmp:std_logic_vector(3 downto 0); process(clk,clr,en) if clr='0'then qh_tmp<="0000"; ql_tmp<="0000"; elsif clk'event and clk='1'then if en='1' then if ql_tmp=3 then if qh_tmp=2 then ql_tmp<="0000"; qh_tmp<="0000"; ql_tmp<=ql_tmp+1; elsif ql_tmp=9 then ql_tmp<="0000"; qh_tmp<=qh_tmp+1; ql_tmp<=ql_tmp+1; qh<=qh_tmp; ql<=ql_tmp;

end a; 例题 5 如图所示 用 VHDL 语言设计同步 60 进制计数器 library altera; use altera.maxplus2.all; library lpm; use lpm.lpm_components.all; ql_tmp<=ql_tmp+1; --END IF (EN) --END IF(clr) end behavior; library std; use std.textio.all; --library vital; --use vital.vital_timing.all; --use vital.vital_primitive.all; --************************************** entity count60 is port( clk,clr,en:in std_logic; cy:out std_logic; qh,ql:out std_logic_vector(3 downto 0) ); end count60; --****************************************** * architecture behavior of count60 is signal qh_tmp,ql_tmp:std_logic_vector(3 downto 0); qh<=qh_tmp;ql<=ql_tmp; cy<='1'when(ql_tmp="1001"and qh_tmp="0101") '0';--² ÐÐÓï¾äÃèÊö½øλ process(clr,clk,en) if clr='0'then qh_tmp<=(others=>'0');--µè¼ûóëqh_tmp<="0000"; ql_tmp<=(others=>'0'); elsif (clk'event and clk='1')then if en='1'then if (ql_tmp=9)then ql_tmp<="0000"; if(qh_tmp=5)then qh_tmp<="0000"; qh_tmp<=qh_tmp+1;

例题 5 如图所示 用 VHDL 语言设计 9999 计数器, 用动态扫描方式, 其中 CLK1,CLKS( 25Hz) 分别是计数时钟和扫描时钟,SEG[6..0] 和 SEL[3..0] 分别是七段数码管的段码和位选信号 seg<="1000000"when in47=0 "1111001"when in47=1 "0100100"when in47=2 "0110000"when in47=3 "0011001"when in47=4 "0010010"when in47=5 "0000010"when in47=6 "1111000"when in47=7 "0000000"when in47=8 "0010000"; library std; use std.textio.all; library vital; use vital.vital_timing.all; use vital.primitive.all; library altera; use altera.maxplus2.all; use altera.megacore.all; library lpm; use lpm.lpm_components.all; --************************************ ******* entity count99991 is port( clr:in std_logic; clk1,clks:in std_logic; seg:out std_logic_vector(6 downto 0); sel:out std_logic_vector(3 downto 0) ); end count99991; --************************************ ********** architecture a of count99991 is signal in47:integer range 9 downto 0; signal q0_tmp,q1_tmp,q2_tmp,q3_tmp:integer range 9 downto 0; --signal q:integer range 0 to 3; process(clr,clk1,in47) if clr='1'then q0_tmp<=0; q1_tmp<=0; q2_tmp<=0; q3_tmp<=0; elsif clk1'event and clk1='1'then q0_tmp<=q0_tmp-1; if q0_tmp=0 then q1_tmp<=q1_tmp-1; if q1_tmp=0 then q2_tmp<=q2_tmp-1; if q2_tmp=0 then q3_tmp<=q3_tmp-1; process(clks) variable q:integer range 0 to 3; if clks'event and clks='1'then q:=q+1; case q is when 0 => in47<=q0_tmp;sel<="0001"; when 1 => in47<=q1_tmp;sel<="0010"; when 2 => in47<=q2_tmp;sel<="0100"; when others => in47<=q3_tmp;sel<="1000"; end case; end a;