lx89-dis-0928

P STK UP LYER : TOP LYER :GN LYER : IN LYER : IN LYER : V LYER : OT R-SOIMM LX SYSTEM IGRM PGE, R-SOIMM PGE, R channel R channel M hamplain mm X mm SG Processor P (PG)W/W PGE,, HT PU THERML SENSOR PGE PU_LK NGFX_LK NGPP_LK SLINK_LK.MHz LOK GEN ISLPRSKLFT-->HP SLGSPVTR-->HP RTMN- -->HP PGE SYSTEM HRGER(ISL) PGE SYSTEM POWER ISL PGE R II SMR_VTERM.V/.VSUS(RT) PGE VP.V N.V(RT) PGE VGORE(.V~.V)Oz PGE PU ORE ISLHRTZ-T PGE X LN Realtek PIE-LN RTL (//) PGE RJ PGE ST - H PGE ST - -ROM PGE ST - H PGE E-ST PGE ccelerometer STM HPL PGE X Mini PI-E ard (Wireless LN) ST M ST M I PI-E PGE ST M ST M LINK X ENE K RS K x NORTH RIGE mm X mm, pin G PGE,,, SOUTH RIGE S mm X mm, pin G LP.W(Ext).W(Int) PGE,... PGE zalia IT H PGE PI-Express X Side port RT LVS R RM UM Only PGE US. US.,, T softbreeze PGE US. Ports X PGE TI PRK-PRO bit Madison bit mm X mm PGE,,, R MHz VRM MXX, bit MXX, bit PGE, UIO mplifier PGE FP VFM PGE E-ST&US ombo HMI RT LVS Webcam X PGE Sub Woofer PGE MUXs (S.G) PGE Touch Screen PGE Flash Media RTS PGE HMI PGE RT PGE LVS PGE PI-E WLN ard x PGE S--SL/S SMUS TLE lock gen/robson/tv tuner /R/R thermal/ccelerometer V Keyboard Touch Pad PGE PGE E --SL/S epress card Wlan ard attery charge/discharge VS VPU FN PGE SPI PGE igital MI UIO ONN (Phone/ MI) PGE PGE Speaker PGE E--SL/S VG thermal/system thermal V

.V ohm,. L LMPGSN(,.)_ U/.V_.U/V_.U/V_.V_LKVIO.U/V_.U/V_.U/V_.U/V_ ohm,. V_LKV V L LMPGSN(,.)_ U/.V_.U/.V_.U/V_.U/V_.U/V_ V_LKV.U/V_.U/V_.U/V_.U/V_.U/V_ V_LKV For EMI L LMPGSN(,.)_ P/V_ P/V_ Y.MHZ Place very close to /G G_XIN G_XOUT V_LK_V.U/.V_,,,, PLK_SM,,,, PT_SM V.U/V_ V_LKV.V_LKVIO G_XIN G_XOUT PLK_SM PT_SM LK_P# LKREQ# LKREQ# LKREQ# LKREQ# LKREQ# U VOT VSR VTIG VS V_ST VPU VHTT VREF V VSR_IO VSR_IO VTIG_IO VS_IO VPU_IO GN GNOT GNSR GNSR GNTIG GNS GNST GNPU GNHTT GNREF X X SMLK SMT P# *LKREQ# *LKREQ# *LKREQ# *LKREQ# *LKREQ# QFN PUK_T PUK_ TIGT TIG TIGT TIG S_SRT S_SR S_SRT S_SR SRT SR SRT SR SRT SR SRT SR SRT SR SRT/M_SS SR/M SRT/STT SR/ST HTTT/M HTT/M MHz_ REF/SEL_HTT REF/SEL_ST REF/SEL_ R PULKP_EXT PULKN_EXT EXT_GFX_LKP_EXT EXT_GFX_LKN_EXT SLINK_LKP_EXT SLINK_LKN_EXT PIE_MINI_LKP_EXT PIE_MINI_LKN_EXT PIE_LN_LKP_EXT PIE_LN_LKN_EXT LK_VG_M_SS LK_VG_M_NSS NHTREFLKP_EXT NHTREFLKN_EXT LKMUS SEL_HT SEL_ST SEL_ *_ T R R R Place within." of LKGEN R EXT *_ R EXT *_ R R R R R R R R R R EXT EXT EXT EXT EXT EXT EXT EXT EXT EXT EXT EXT EXT R EXT R *_ *_ *_ *_ *_ *_ *_ *_ *_ *_ *_ */F_ */F_ PULKP PULKN NGFX_LKP_EXT NGFX_LKN_EXT EXT_GFX_LKP EXT_GFX_LKN lock for is only SLINK_LKP SLINK_LKN SSR_LKP SSR_LKN PIE_LN_LKP PIE_LN_LKN NHT_REFLKP NHT_REFLKN *_ LK_M_US EXT PIE_MINI_LKP PIE_MINI_LKN *_ T T Mhz for is only PULKP, PULKN, NGFX_LKP_EXT NGFX_LKN_EXT EXT_GFX_LKP, EXT_GFX_LKN, SLINK_LKP, SLINK_LKN, SSR_LKP SSR_LKN PIE_LN_LKP, PIE_LN_LKN, NHT_REFLKP, NHT_REFLKN, LK_M_US EXT_S_OS to N for external Graphics reference clock to PRK -RS only to N for -LINK reference clock to S PIE_MINI_LKP, PIE_MINI_LKN, to WLN R R to LN /F_./F_ EXT_N_OS *P/V_ *P/V_ EXT_N_OS LK_M_US R R *.K_.K_ LKREQ# LK_P# RTMN-_QFN TGN V R R R R *.K_ LKREQ# *.K_ LKREQ# *.K_ LKREQ# *.K_ LKREQ# if use clock request pin, need to pull Hi for default setting SLG RTL SLGSPVTR--LSP RTMN--- L * default MHz.V single ended HTT clock SEL_HTT * MHz differential HTT clock MHz non-spreading differential SR clock SEL_ST * MHz spreading differential SR clock SEL_ * MHz non-spreading singled clock MHz spreading differential SR clock R *.K_ R.K_ V_LKV R.K_ R *.K_ SEL_ SEL_ST SEL_HT RSM/RXM not need to stuff, R have pull LOW lock chip has internal serial terminations for differencial pairs, external resistors are reserved for debug purpose. PROJET : LX Quanta omputer Inc. N/R Size ocument Number Rev ustom lock Generator ate: Monday, September, Sheet of

.V,,,,,,.V,,,,,,,,.VSUS,,,.V,,,,,,,,,,,, V.V.V VLT use. Max current R R *_/S *_/S HT_N_PU H[..] HT_N_PU L[..] HT_N_PU_LK_H[..] HT_N_PU_LK_L[..] HT_N_PU_TL_H[..] HT_N_PU_TL_L[..] HT_PU_N H[..] HT_PU_N L[..] HT_PU_N_LK_H[..] HT_PU_N_LK_L[..] HT_PU_N_TL_H[..] HT_PU_N_TL_L[..].V_VLT_R.V_VLT hange.v_vlt to.v_vlt_r for layout concern HT_N_PU H[..] HT_N_PU L[..] HT_N_PU_LK_H[..] HT_N_PU_LK_L[..] HT_N_PU_TL_H[..] HT_N_PU_TL_L[..] HT_PU_N H[..] HT_PU_N L[..] HT_PU_N_LK_H[..] HT_PU_N_LK_L[..] HT_PU_N_TL_H[..] HT_PU_N_TL_L[..] U/.V_ U/.V_.U/.V_ P/V_ FOX PZ-R-F G^ I SOKET SM P S(P.,H.) MLX - G^ I SOKET SM P S(P.,H.) TY -- G^ I SOKET SM P S(P.,H.).V HT_N_PU_LK_H HT_N_PU_LK_L HT_N_PU_LK_H HT_N_PU_LK_L HT_N_PU_TL_H HT_N_PU_TL_L HT_N_PU_TL_H HT_N_PU_TL_L LMPGSN(,M,)_ W/S= mil/mil PUV L LS-M-N.U/.V_.V_VLT.V_VLT VLT_.V_VLT VLT_.V_VLT VLT_ VLT_ HT_N_PU H E HT_N_PU L E HT_N_PU H E HT_N_PU L F HT_N_PU H G HT_N_PU L G HT_N_PU H G HT_N_PU L H HT_N_PU H J HT_N_PU L K HT_N_PU H L HT_N_PU L L HT_N_PU H L HT_N_PU L HT_N_PU H M N HT_N_PU L N HT_N_PU H E HT_N_PU L HT_N_PU H F F HT_N_PU L F HT_N_PU H G HT_N_PU L H HT_N_PU H H HT_N_PU L H HT_N_PU H K HT_N_PU L K HT_N_PU H L HT_N_PU L M HT_N_PU H M HT_N_PU L M HT_N_PU H N HT_N_PU L P U L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L J L_LKIN_H J L_LKIN_L J L_LKIN_H K L_LKIN_L N L_TLIN_H P L_TLIN_L P L_TLIN_H P L_TLIN_L SOKET PIN HT LINK.U/.V_.U/.V_ VLT_ E VLT_ E VLT_ E VLT_ E L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H W L_OUT_L W L_OUT_H V L_OUT_L U L_OUT_H U L_OUT_L U L_OUT_H T L_OUT_L R L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H Y L_OUT_L W L_OUT_H V L_OUT_L V L_OUT_H V L_OUT_L U L_OUT_H T L_OUT_L T L_LKOUT_H Y L_LKOUT_L W L_LKOUT_H Y L_LKOUT_L Y L_TLOUT_H R L_TLOUT_L R L_TLOUT_H T L_TLOUT_L R P/V_.V_VLT_R U/.V_.V_VLT_R.U/.V_.V_VLT_R P/V_.V_VLT_R HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N_LK_H HT_PU_N_LK_L HT_PU_N_LK_H HT_PU_N_LK_L HT_PU_N_TL_H HT_PU_N_TL_L HT_PU_N_TL_H HT_PU_N_TL_L hange.v_vlt to.v_vlt_r for layout concern.vsus PU LK.VSUS, PULKP, PULKN PULKIN PULKP PULKN PUTESTH PUTESTL /F_ PU_REQ# PUTEST PULKP PULKN Keep trace from resisor to PU within." keep trace from caps to PU within." PULKIN# PU_LT_RST# PU_PWRG, PU_LT_STOP# PU_ Sideand Temp sense I PU_ PU_LERT R /F_ R /F_ R R R K/F_ */F_ R /F_.V_VLT P/V_ P/V_ R R PU_V_RUN_F_H PU_V_RUN_F_L PU_V_RUN_F_H PU_V_RUN_F_L PU_RY PU_TMS PU_TK PU_TRST# PU_TI PUV m W/S= mil/mil PUV PUV PULKIN PULKIN# PU_THERM PU_THERM./F_ PU_HTREF./F_ PU_HTREF place them to PU within." R T T T T PU_PWRG PU_LT_RST# PU_LT_STOP# PU_LT_REQ#_PU PUTEST PUTEST PUTEST *_/S PUTEST F V F V LKIN_H LKIN_L PU_LT_RST# PU_PWRG RESET_L PU_LT_STOP# PWROK F PU_LT_REQ#_PU LTSTOP_L THERMTRIP_L F LTREQ_L PROHOT_L PU_ MEMHOT_L F PU_ F PU_LERT E LERT_L THERM W THERM W R HT_REF P HT_REF F V_F_H E V_F_L Y V_F_H V_F_L G RY TMS TK TRST_L F TI U TEST H TEST G TEST PUTESTH E PUTESTL TEST_H E place them to PU within." TEST_L PUTEST PUTEST TEST T F PUTEST TEST E PUTEST TEST T E PUTEST TEST T PUTEST TEST F TEST TEST TEST RSV RSV RSV RSV RSV SOKET PIN _ R _ R _ R */F_ R VSS M RSV W SV SV VIO_F_H W VIO_F_L Y VN_F_H H VN_F_L G RSV H RSV H RSV RSV RSV PU_THERM PU_THERM.V PU_SV_R PU_SV_R PU_THERMTRIP_L# PU_PROHOT_L# PU_THERM PU_THERM VIO_F_H VIO_F_L PU_REQ# REQ_L E TO E TEST_H J TEST_L H TEST TEST E TEST F TEST TEST TEST TEST TEST_H TEST_L PU_TO PUTESTH PUTESTL PUTEST PUTEST PUTEST PUTEST PUTEST K R */F_ PUTEST PUTESTH PUTESTL T VIO_F_H VIO_F_L PU_VN_RUN_F_H PU_VN_RUN_F_L R T T T T T T./F_ T.V_VLT T T T Route as ohm, diff.vsus R PU_LT_RST# K/F_ NTR_VREF Q MMT PU_LT_RST_HTP# an remove on MP V R K/F_ Serial VI.VSUS R *K/F_ PU_SV_R PU_SV_R PU_PWRG.V R *K/F_ R _ R _ R _ R R R *_ *_ *_ R K/F_ R K/F_ PU_SV PU_SV PU_PWRG_SVI_REG.VSUS.V PU_SV PU_SV PU_PWRG_SVI_REG VFIX MOE PUTEST PUTEST PUTEST PUTEST VI Override table (V) SV SV Output Voltage.V.V.V.V R R R R K/F_ K/F_ K/F_ K/F_ HT onnector.vsus.vsus PU_PROHOT_L# E_PROHOT# E new option R R R _ K/F_ R _ *_ Q PU_THERMTRIP_L# PU_PROHOT_R# MMT.VSUS.VSUS R R _ PU_THERMTRIP_L# PU_PROHOT_R# K/F_ Q MMT PU_THERMTRIP# PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO.VSUS *.U/V_ KEY N *HT ONN PU_LT_RST_HTP# N/R PUTEST PUTEST PUTEST R R R K/F_ K/F_ K/F_ PROJET : LX Quanta omputer Inc. Size ocument Number Rev ustom SG HT,TL I/F / ate: Monday, September, Sheet of

E.VSUS W->.V.V U.V W->.V PLE THEM LOSE TO PU WITHIN " VTT VTT W R MEM:M/TRL/LK VTT VTT R_VTTREF,, VTT VTT _ VTT VTT MEM_M_T[..] Processor Memory Interface M_ZP VTT R R./F_ F M_ZN MEMZP *_ R./F_ PU_VTT_SENSE U E MEMZN VTT_SENSE Y PU_VTT_SENSE MEM:T MEM_M_T[..] MEM_M_RESET# MEMVREF_PU MEM_M_T MEM_M_T MEM_M_RESET# H MEMVREF W MEM_M_T M_T M_T G RSV_M MEM_M_T MEM_M_RESET# MEM_M_T M_T M_T F U/.V_ MEM_M_T MEM_M_OT T M_OT RSV_M MEM_M_RESET# MEM_M_T M_T M_T H MEM_M_T MEM_M_OT V M_OT MEM_M_T M_T M_T G MEM_M_T T U M_OT M_OT W MEM_M_OT G MEM_M_T M_T M_T H V MEM_M_T M_OT M_OT W.U/V/XR_ T MEM_M_OT E MEM_M_T M_T M_T H MEM_M_T M_OT Y P/V_ T MEM_M_T M_T M_T MEM_M_T MEM_M_S# T M_S_L MEM_M_T M_T M_T E MEM_M_T MEM_M_S# U M_S_L M_S_L V MEM_M_S# MEM_M_T M_T M_T H MEM_M_T T U M_S_L M_S_L W MEM_M_S# MEM_M_T M_T M_T E MEM_M_T T V M_S_L M_S_L U T MEM_M_T M_T M_T E MEM_M_T MEM_M_T M_T M_T H MEM_M_T MEM_M_KE J M_KE M_KE J MEM_M_KE MEM_M_T M_T M_T E MEM_M_T MEM_M_KE J M_KE M_KE H MEM_M_KE MEM_M_T M_T M_T F MEM_M_T MEM_M_T M_T M_T MEM_M_T MEM_M_LK_P N M_LK_H M_LK_H P MEM_M_LK_P MEM_M_T M_T M_T G MEM_M_T MEM_M_LK_N N M_LK_L M_LK_L R MEM_M_LK_N MEM_M_T M_T M_T G MEM_M_T T E M_LK_H M_LK_H T MEM_M_T M_T M_T MEM_M_T T F M_LK_L M_LK_L T MEM_M_T M_T M_T MEM_M_T T Y M_LK_H M_LK_H F T MEM_M_T M_T M_T E MEM_M_T T M_LK_L M_LK_L F T MEM_M_T M_T M_T E MEM_M_T MEM_M_LK_P P M_LK_H M_LK_H R MEM_M_LK_P MEM_M_T M_T M_T F MEM_M_T MEM_M_LK_N P M_LK_L M_LK_L R MEM_M_LK_N MEM_M_T M_T M_T MEM_M_T MEM_M_[..] MEM_M_ MEM_M_ MEM_M_[..] MEM_M_T M_T M_T N E MEM_M_T MEM_M_ M_ M_ P MEM_M_ MEM_M_T M_T M_T F M E MEM_M_T MEM_M_ M_ M_ N MEM_M_ MEM_M_T M_T M_T F N G MEM_M_T MEM_M_ M_ M_ P MEM_M_ MEM_M_T M_T M_T H M G MEM_M_T MEM_M_ M_ M_ N MEM_M_ MEM_M_T M_T M_T J M MEM_M_T MEM_M_ M_ M_ N MEM_M_ MEM_M_T M_T M_T E L MEM_M_T MEM_M_ M_ M_ L MEM_M_ MEM_M_T M_T M_T E M G MEM_M_T MEM_M_ M_ M_ N MEM_M_ MEM_M_T M_T M_T H L G MEM_M_T MEM_M_ M_ M_ L MEM_M_ MEM_M_T M_T M_T H L MEM_M_T MEM_M_ M_ M_ M MEM_M_ MEM_M_T M_T M_T Y K MEM_M_T MEM_M_ M_ M_ K MEM_M_ MEM_M_T M_T M_T R MEM_M_T MEM_M_ M_ M_ T MEM_M_ MEM_M_T M_T M_T L E MEM_M_T MEM_M_ M_ M_ L MEM_M_ MEM_M_T M_T M_T K MEM_M_T MEM_M_ M_ M_ L MEM_M_ MEM_M_T M_T M_T W V MEM_M_T MEM_M_ M_ M_ W MEM_M_ MEM_M_T M_T M_T W K MEM_M_T MEM_M_ M_ M_ J MEM_M_ MEM_M_T M_T M_T Y K E MEM_M_T M_ M_ J MEM_M_T M_T M_T MEM_M_T MEM_M_T M_T M_T Y MEM_M_T MEM_M_NK R M_NK M_NK R MEM_M_NK MEM_M_T M_T M_T MEM_M_T MEM_M_NK R M_NK M_NK U MEM_M_NK E MEM_M_T M_T M_T MEM_M_T MEM_M_NK J M_NK M_NK J MEM_M_NK F MEM_M_T M_T M_T F MEM_M_T MEM_M_T M_T M_T MEM_M_T MEM_M_RS# R M_RS_L M_RS_L U MEM_M_RS# F MEM_M_T M_T M_T MEM_M_T MEM_M_S# T M_S_L M_S_L U MEM_M_S# MEM_M_T M_T M_T MEM_M_T MEM_M_WE# T M_WE_L M_WE_L U MEM_M_WE# MEM_M_T M_T M_T Y MEM_M_T MEM_M_T M_T M_T E MEM_M_T MEM_M_T M_T M_T W SOKET PIN MEM_M_T MEM_M_T M_T M_T W MEM_M_T MEM_M_T M_T M_T Y F MEM_M_T MEM_M_T M_T M_T Y MEM_M_T MEM_M_T M_T M_T F MEM_M_T.V Place close to socket MEM_M_T M_T M_T F MEM_M_T MEM_M_T M_T M_T F MEM_M_T MEM_M_T M_T M_T MEM_M_T MEM_M_T M_T M_T MEM_M_T MEM_M_T M_T M_T Y Y MEM_M_T.U/.V_ MEM_M_T M_T M_T W.U/.V_.U/.V_.U/.V_.U/.V_.U/.V_.U/.V_ E MEM_M_T MEM_M_T M_T M_T F MEM_M_T MEM_M_T M_T M_T F MEM_M_T MEM_M_T M_T M_T MEM_M_T M_T M_T MEM_M_M[..] MEM_M_M[..] MEM_M_M MEM_M_M.V MEM_M_M M_M M_M E MEM_M_M MEM_M_M M_M M_M MEM_M_M MEM_M_M M_M M_M E E MEM_M_M MEM_M_M M_M M_M F MEM_M_M MEM_M_M M_M M_M E MEM_M_M P/V_ MEM_M_M M_M M_M Y P/V_ P/V_ P/V_ P/V_ P/V_ P/V_ MEM_M_M MEM_M_M M_M M_M MEM_M_M M_M M_M Y MEM_M_QS_P M_QS_H M_QS_H G MEM_M_QS_P MEM_M_QS_N.VSUS M_QS_L M_QS_L H MEM_M_QS_N MEM_M_QS_P for M suggest M_QS_H M_QS_H G MEM_M_QS_P MEM_M_QS_N M_QS_L M_QS_L G MEM_M_QS_N MEM_M_QS_P M_QS_H M_QS_H MEM_M_QS_P MEM_M_QS_N M_QS_L M_QS_L MEM_M_QS_N R _ MEM_M_QS_P F M_QS_H M_QS_H G MEM_M_QS_P MEM_M_QS_N E VPU M_QS_L M_QS_L G MEM_M_QS_N MEM_M_QS_P M_QS_H M_QS_H MEM_M_QS_P MEM_M_QS_N M_QS_L M_QS_L MEM_M_QS_N R MEM_M_QS_P F M_QS_H M_QS_H MEM_M_QS_P MEM_M_QS_N F M_QS_L M_QS_L MEM_M_QS_N K/F_ MEM_M_QS_P E M_QS_H M_QS_H Y MEM_M_QS_P *.U/V_ MEM_M_QS_N M_QS_L M_QS_L W MEM_M_QS_N U MEM_M_QS_P F M_QS_H M_QS_H W MEM_M_QS_P R *_ MEM_M_QS_N E MEM_M_QS_N MEMVREF_PU M_QS_L M_QS_L W R - *OPN/K SOKET PIN K/F_ *.U/V_ R.V *K/F_,,,,,,,,.VSUS R *_ R *_ PROJET : LX Quanta omputer Inc. N/R Size ocument Number Rev ustom SG RII MEMORY I/F / ate: Monday, September, Sheet of E

,, MLK,, MT VORE PUVN.VSUS,,,,,,,, VS,,,,, V,,,,,,,,,.V,,,,, VORE Q *MMT MLK MT *RV- PUVN.VSUS.VSUS R K/F_ R K/F_ Q *MMT UE G V_ H V_ J V_ J V_ J V_ J V_ K V_ K V_ K V_ K V_ L V_ L V_ L V_ L V_ L V_ L V_ M V_ M V_ M V_ M V_ N V_ N V_ N V_ K VN_ M VN_ P VN_ T VN_ V VN_ H VIO J VIO K VIO K VIO K VIO K VIO L VIO M VIO M VIO M VIO M VIO N VIO SOKET PIN R K/F_ PU_ PU_ V_ P V_ P V_ R V_ R V_ R V_ R V_ T V_ T V_ T V_ T V_ T V_ T V_ U V_ U V_ U V_ U V_ U V_ V V_ V V_ V V_ V V_ V V_ W V_ Y V_ V_ VIO Y VIO V VIO V VIO V VIO V VIO U VIO T VIO T VIO T VIO T VIO R VIO P VIO P VIO P VIO P R _.VSUS VORE R _ R K/F_.VSUS PU_ PU_ UF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E VSS E VSS E VSS E VSS E VSS E VSS E VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS H VSS H VSS H VSS H VSS J VSS SOKET PIN VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J J J J J J J K K K K K K K L L L L L L L M M M N N N N N P P P P P R R R R T T T T T T U U U U U U U U V V V V V V V W Y Y N VORE U/.V_ VORE PUVN U/.V_.VSUS.VSUS U/.V_ OTTOM E EOUPLING U/.V_ U/.V_.VSUS U/.V_ U/.V_.U/.V_ U/.V_.U/.V_.U/.V_ P/V_ EOUPLING ETWEEN PROESSOR N IMMs PLE LOSE TO PROESSOR S POSLE.U/.V_ U/.V_ U/.V_.U/.V_ U/.V_ U/.V_ U/.V_.U/.V_.U/.V_.U/.V_.U/V_.U/V_.U/.V_.U/.V_ P/V_.U/V_.U/.V_.U/V_ P/V_ P/V_ P/V_.U/.V_.U/V_ SMLERT# *RV- Q *MMT PU_LERT V PU_LERT PROESSOR POWER N GROUN V R R K/F_ R K/F_ R K/F_ U /F_.U/V_ R *_ reserve for power shutdown ( if can ) SYS_SHN# *HH SYS_SHN# Need heck,, MLK,, MT PM_THERM# SLK V S LERT# OVERT# MSOP GP XP XN GN PU_THERM R *_/S _RST# _RST# Q P/V_ MMT EPWROK PU_THERM EPWROK, HH-PT SMLERT# R K/F_ V For fix HyperTransport nets across plane splits.vsus PU_THERMTRIP_L# R *K/F_ Q *MMT PU_THERMTRIP_L# SMLERT# PQ *NE-G R *K/F_ TEMP_FIL VG TEMP_ FIL function M is active Hi VS E *.U/V_ VS E *.U/V_ V.V E E *.U/V_ *.U/V_ N/R PROJET : LX Quanta omputer Inc. Size ocument Number Rev ustom SG PWR & GN / ate: Monday, September, Sheet of

.VSUS,,,,,,,, V,,,,,,,,,,,,,,,,,,,,,,,,.V_R_VTT,.VSUS MEM_M_[..] MEM_M_NK[..] MEM_M_S# MEM_M_S# MEM_M_LK_P MEM_M_LK_N MEM_M_LK_P MEM_M_LK_N MEM_M_KE MEM_M_KE MEM_M_S# MEM_M_RS# MEM_M_WE#,,,, PLK_SM,,,, PT_SM MEM_M_OT MEM_M_OT MEM_M_M[..] MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_NK MEM_M_NK MEM_M_NK PLK_SM PT_SM MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M N /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# P R SRM SO-IMM (P) Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T[..] VREF_Q VREF T MEM_M_EVENT# MEM_M_RESET# P/V_.VSUS V P/V_ R K/F_ MEM_M_EVENT# MEM_M_RESET# VREF_Q V V V V V V V V V V V V V V V V V V N VSP N MEM_M_TEST N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS R-IMM H=. footprint: "ddr-c--p" GMK VPU P R SRM SO-IMM (P) R VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT *_.V_R_VTT Place close to IMMs.U/V_ SO-IMM YPSS PLEMENT : Place these aps near So-imm. R-IMM H=. footprint: "ddr-c--p" GMK R K/F_ P/V_ U.U/V_ - OPN/K R _ R VREF_Q No Vias etween the Trace of PIN to P. R _ K/F_.U/V/XR_.VSUS E-OUPLING FOR IMM(ONE P PER POWER PIN) R *_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_.VSUS E-OUPLING FOR IMM VREF R *K/F_ V.V_R_VTT.V_R_VTT.VSUS,, R_VTTREF R _ VREF U/.V_ *.U/V_.U/.V_ *.U/V_.U/V_.VSUS U/.V_ U/.V_ *U/.V_ *u_.v_ R *K/F_ PROJET : LX Quanta omputer Inc. N/R Size ocument Number Rev ustom R SOIMMS: / HNNEL ate: Monday, September, Sheet of

.VSUS,,,,,,,, V,,,,,,,,,,,,,,,,,,,,,,,,.V_R_VTT, V R.K_ IM_S IM_S MEM_M_[..] MEM_M_NK[..] MEM_M_S# MEM_M_S# MEM_M_LK_P MEM_M_LK_N MEM_M_LK_P MEM_M_LK_N MEM_M_KE MEM_M_KE MEM_M_S# MEM_M_RS# MEM_M_WE#,,,, PLK_SM,,,, PT_SM MEM_M_OT MEM_M_OT MEM_M_M[..] MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_NK MEM_M_NK MEM_M_NK IM_S IM_S PLK_SM PT_SM MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M N /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# P R SRM SO-IMM (P) Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T[..] VREF_Q VREF MEM_M_EVENT# MEM_M_RESET# P/V_ T V P/V_.VSUS VREF_Q V V V V V V V V V V V V V V V V V V H=. footprint: "ddr-c--p-" GMK.V_R_VTT SO-IMM YPSS PLEMENT : R-IMM H=. footprint: "ddr-c--p-" GMK Place these aps near So-imm. No Vias etween the Trace of PIN to P..VSUS E-OUPLING FOR IMM(ONE P PER POWER PIN).U/V_.U/V_.U/V_.U/V_.VSUS E-OUPLING FOR IMM VREF V.V_R_VTT.V_R_VTT.VSUS N VSP N MEM_M_TEST N NTEST MEM_M_EVENT# MEM_M_RESET# EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS R-IMM P R SRM SO-IMM (P) VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT.U/V_.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ R *K/F_,, R_VTTREF R _ VREF U/.V_ *.U/V_.U/.V_ *.U/V_.U/V_.VSUS U/.V_ U/.V_ *U/.V_ *u_.v_ R *K/F_ PROJET : LX Quanta omputer Inc. N/R Size ocument Number Rev ustom R SOIMMS TERMINTIONS ate: Monday, September, Sheet of

R *_.V_MEM_VQ SP_R_RST#.V,,,.V,,,,,.V,,,,,, R SPM_VREF SPM_VREF SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_LKN SPM_LKP SPM_KE SPM_OT SPM_S# SPM_RS# SPM_S# SPM_WE# SPM_QSP SPM_QSP SPM_M SPM_M SPM_QSN SPM_QSN K/F_ VM_ZQ R /F_ HT_PU_N H[..] HT_PU_N L[..] HT_PU_N_LK_H[..] HT_PU_N_LK_L[..] HT_PU_N_TL_H[..] HT_PU_N_TL_L[..] HT_N_PU H[..] HT_N_PU L[..] HT_N_PU_LK_H[..] HT_N_PU_LK_L[..] HT_N_PU_TL_H[..] HT_N_PU_TL_L[..] N P P N P P R R T R L /P R N / T T M M N M J K K K K KE K OT L S J RS K S L WE G QSL QSU T L U M VREF H VREFQ F QSL QSU E ML MU RESET ZQ J N#J L N#L J N#J L N#L QL QL QL QL QL QL QL QL V# V# V#G V#K V#K V#N V#N V#R V#R VQ# VQ# VQ# VQ# VQ# VQ#E VQ#F VQ#H VQ#H VSS# VSS# VSS#E VSS#G VSS#J VSS#J VSS#M VSS#M VSS#P VSS#P VSS#T VSS#T VSSQ# VSSQ# VSSQ# VSSQ# VSSQ#E VSSQ#E VSSQ#F VSSQ#G VSSQ#G -LL SRM R HTQGFR- QU QU QU QU QU QU QU QU E F F F H H G H G K K N N R R E F H H E G J J M M P P T T E E F G G HT_PU_N H[..] HT_PU_N L[..] HT_PU_N_LK_H[..] HT_PU_N_LK_L[..] HT_PU_N_TL_H[..] HT_PU_N_TL_L[..] HT_N_PU H[..] HT_N_PU L[..] HT_N_PU_LK_H[..] HT_N_PU_LK_L[..] HT_N_PU_TL_H[..] HT_N_PU_TL_L[..] SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q.V_MEM_VQ.V_MEM_VQ R K/F_.U/V_.V_MEM_VQ SPM_VREF R R T HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N_LK_H HT_PU_N_LK_L HT_PU_N_LK_H HT_PU_N_LK_L HT_PU_N_TL_H HT_PU_N_TL_L HT_PU_N_TL_H HT_PU_N_TL_L Rb /F_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_RS# SPM_S# SPM_WE# SPM_S# SPM_KE SPM_OT SPM_LKP SPM_LKN HT_RXLP HT_RXLN./F_ SPM_OMPP./F_ SPM_OMPN.V_MEM_VQ SPM_VREF HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU_LK_H HT_N_PU_LK_L HT_N_PU_LK_H HT_N_PU_LK_L HT_N_PU_TL_H HT_N_PU_TL_L HT_N_PU_TL_H HT_N_PU_TL_L HT_TXLP HT_TXLN This block is for UM only, IS can remove all component R R K/F_.U/V_ U Y HT_RXP HT_TXP Y HT_RXN PRT OF HT_TXN V HT_RXP HT_TXP E V HT_RXN HT_TXN E V HT_RXP HT_TXP F V HT_RXN HT_TXN F U HT_RXP HT_TXP F U HT_RXN HT_TXN F T HT_RXP HT_TXP H T HT_RXN HT_TXN H P HT_RXP HT_TXP J P HT_RXN HT_TXN J P HT_RXP HT_TXP K P HT_RXN HT_TXN K N HT_RXP HT_TXP K N HT_RXN HT_TXN K HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN Y HT_RXP Y HT_RXN W HT_RXP W HT_RXN V HT_RXP V HT_RXN U HT_RXP U HT_RXN U HT_RXP U HT_RXN T HT_RXLKP T HT_RXLKN HT_RXLKP HT_RXLKN M HT_RXTLP M HT_RXTLN R HT_RXTLP R HT_RXTLN HT_RXLP HT_RXLN RSM U PR OF SPM_Q MEM_(N) MEM_Q/VO_VSYN(N) E SPM_Q MEM_(N) MEM_Q/VO_HSYN(N) V SPM_Q MEM_(N) MEM_Q/VO_E(N) E SPM_Q MEM_(N) MEM_Q/VO_(N) Y SPM_Q MEM_(N) MEM_Q(N) V SPM_Q MEM_(N) MEM_Q/VO_(N) SPM_Q MEM_(N) MEM_Q/VO_(N) SPM_Q MEM_(N) MEM_Q/VO_(N) Y SPM_Q MEM_(N) MEM_Q/VO_(N) SPM_Q MEM_(N) MEM_Q/VO_(N) SPM_Q MEM_(N) MEM_Q/VO_(N) E E SPM_Q MEM_(N) MEM_Q/VO_(N) SPM_Q MEM_(N) MEM_Q(N) Y SPM_Q MEM_(N) MEM_Q/VO_(N) SPM_Q MEM_Q/VO_(N) SPM_Q MEM_(N) MEM_Q/VO_(N) E MEM_(N) SPM_QSP MEM_(N) MEM_QSP/VO_IKP(N) Y SPM_QSN MEM_QSN/VO_IKN(N) W W SPM_QSP MEM_RSb(N) MEM_QSP(N) Y SPM_QSN MEM_Sb(N) MEM_QSN(N) E MEM_WEb(N) SPM_M MEM_Sb(N) MEM_M(N) W SPM_M MEM_KE(N) MEM_M/VO_(N) E V MEM_OT(N).V_IOPLLV IOPLLV(N) E LMPGSN(,.)_ V.V_IOPLLV MEM_KP(N) IOPLLV(N) E LMPGSN(,.)_ W MEM_KN(N) IOPLLVSS(N) E MEM_OMPP(N) SPM_VREF MEM_OMPN(N) MEM_VREF(N) E.U/.V_.U/.V_ RSM R S_MEM/VO_I/F K/F_ HYPER TRNSPORT PU I/F.U/V_ R HT_TXP F HT_TXN G HT_TXP G HT_TXN H HT_TXP J HT_TXN J HT_TXP J HT_TXN K HT_TXP L HT_TXN J HT_TXP M HT_TXN L HT_TXP M HT_TXN P HT_TXP P HT_TXN M HT_TXLKP H HT_TXLKN H HT_TXLKP L HT_TXLKN L HT_TXTLP M HT_TXTLN M HT_TXTLP P HT_TXTLN R HT_TXLP HT_TXLN K/F_.U/V_ R R K/F_.U/V_.V_MEM_VQ Ra /F_ R K/F_.U/V_ L L.V.V.V_MEM_VQ signals RS RX HT_TXLP HT_TXLN HT_RXLP HT_RXLN Ra ohm % Rb ohm %.V_MEM_VQ mils wdith or more U/V_.U/V_ U/.V_.U/V_ Ra.k ohm % Rb.k ohm % IS only U/.V_ U/V_ R _.V PROJET : LX Quanta omputer Inc. N/R Size ocument Number Rev ustom RS-HT LINK I/F / ate: Monday, September, Sheet of

UM Remove ll ap Swap pin for Layout PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# U GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN E GFX_RXP F GFX_RXN G GFX_RXP G GFX_RXN H GFX_RXP H GFX_RXN J GFX_RXP J GFX_RXN J GFX_RXP J GFX_RXN L GFX_RXP L GFX_RXN M GFX_RXP L GFX_RXN P GFX_RXP M GFX_RXN P GFX_RXP M GFX_RXN R GFX_RXP P GFX_RXN R GFX_RXP R GFX_RXN P GFX_RXP P GFX_RXN T GFX_RXP T GFX_RXN PRT OF PIE I/F GFX GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# E _PEG_TX# E _PEG_TX F _PEG_TX F _PEG_TX# F _PEG_TX# F _PEG_TX H _PEG_TX H _PEG_TX# H _PEG_TX# H _PEG_TX J _PEG_TX# J _PEG_TX K _PEG_TX# K _PEG_TX K _PEG_TX# K _PEG_TX M _PEG_TX M _PEG_TX# M _PEG_TX# M _PEG_TX N _PEG_TX _PEG_TX# P _PEG_TX P _PEG_TX#.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_ PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX# PEG_TX PEG_TX PEG_TX# PEG_TX# PEG_TX PEG_TX PEG_TX# PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX PEG_TX# PEG_TX# PEG_TX PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_RX#[:] PEG_RX[:] _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# PEG_RX#[:] PEG_RX[:] To HMI ONN lose to North ridge _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# PEG_TX#[:] PEG_TX[:] PEG_TX#[:] PEG_TX[:] PIE_RXP_WLN PIE_RXN_WLN PIE_RXP_LN PIE_RXN_LN PIE_S_N_RXP PIE_S_N_RXN PIE_S_N_RXP PIE_S_N_RXN PIE_S_N_RXP PIE_S_N_RXN PIE_S_N_RXP PIE_S_N_RXN PIE_RXP_WLN PIE_RXN_WLN PIE_RXP_LN PIE_RXN_LN E GPP_RXP GPP_RXN E GPP_RXP GPP_RXN GPP_RXP GPP_RXN V GPP_RXP W GPP_RXN U GPP_RXP U GPP_RXN U GPP_RXP U GPP_RXN S_RXP Y S_RXN S_RXP Y S_RXN S_RXP S_RXN W S_RXP Y S_RXN RSM GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP PIE I/F GPP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN PIE I/F S S_TXP S_TXN S_TXP S_TXN S_TXP S_TXN S_TXP S_TXN PE_LRP(PE_LRP) PE_LRN(PE_LRN) Y Y Y Y V V E E E PIE_TXP_WLN_ PIE_TXN_WLN_ PIE_TXP_LN_ PIE_TXN_LN TXP TXN TXP TXN TXP TXN TXP TXN_ N_PIELRP N_PIELRN R R.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.K/F_ K/F_ PIE_TXP_WLN PIE_TXN_WLN PIE_TXP_LN PIE_TXN_LN PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN.V TO WLN TO LN RS isplay Port Support (muxed on GFX).V,,,,,, P GFX_TX,TX,TX and TX UX and HP P GFX_TX,TX,TX and TX UX and HP PROJET : LX Quanta omputer Inc. N/R Size ocument Number Rev ustom RS-PIE I/F / ate: Monday, September, Sheet of

V,,,,,,,,,,,,,,,,,,,,,,,,.V,,,,,.V,,,,,,.V,,,, R for UM use ohm for ISPowerExpress use ohm (M) ohm SF ohm SF INT_RT_R INT_RT_G INT_RT_ R R R R R R *_/S /F_ *_/S /F_ *_/S /F_ V_V_N.V_VI_N.V_VQ_N RT_R_ RT_G_ RT T T T F E F G H H E F F G G E F E F U V(N) V(N) VI(N) VS(N) VQ(N) VSSQ(N) _Pr(FT_GPIO) Y(FT_GPIO) OMP_Pb(FT_GPIO) RE(FT_GPIO) REb(N) GREEN(FT_GPIO) GREENb(N) LUE(FT_GPIO) LUEb(N) PRT OF RT/TVOUT TXOUT_LP(N) TXOUT_LN(N) TXOUT_LP(N) TXOUT_LN(N) TXOUT_LP(N) TXOUT_LN(G_GPIO) TXOUT_LP(N) TXOUT_LN(G_GPIO) TXOUT_UP(N) TXOUT_UN(N) TXOUT_UP(PIE_RESET_GPIO) TXOUT_UN(PIE_RESET_GPIO) TXOUT_UP(N) TXOUT_UN(N) TXOUT_UP(PIE_RESET_GPIO) TXOUT_UN(N) L_TP L_TN L_TP L_TN L_TP L_TN L_TP L_TN L_TP L_TN L_TP L_TN L_TP L_TN L_TP L_TN T T T T L_TP L_TN L_TP L_TN L_TP L_TN L_TP L_TN L_TP L_TN L_TP L_TN N_REFLK_P N_REFLK_N.V N_REFLK_P N_REFLK_N EXT R.K_ V R K/F_ RS R INT.K_ RS NGFX_LKP NGFX_LKN R INT.K_ EXT R.K_,, INT_HSYN_OM INT_VSYN_OM,, INT_T INT_LK N_PLTRST# N_PWRG_IN NHT_REFLKP NHT_REFLKN EXT_N_OS NGFX_LKN_EXT NGFX_LKP_EXT SLINK_LKP SLINK_LKN T T R /F_ R EXT R EXT R EXT R EXT *_ *_ *_ *_ INT_HSYN_OM INT_VSYN_OM INT_T INT_LK _RSET_N.V_PLLV.V_PLLV.V_VHTPLL.V_VPIEPLL N_RST#_IN N_PWRG_IN N_LT_STOP# N_LLOW_LTSTOP NHT_REFLKP NHT_REFLKN N_REFLK_P N_REFLK_N NGFX_LKP NGFX_LKN SLINK_LKP SLINK_LKN E F G H E E F T T U U V V _HSYN(PWM_GPIO) _VSYN(PWM_GPIO) _S(PE_TLRN) _SL(PE_RLRN) _RSET(PWM_GPIO) PLLV(N) PLLV(N) PLLVSS(N) VHTPLL VPIEPLL VPIEPLL SYSRESETb POWERGOO LTSTOPb LLOW_LTSTOP HT_REFLKP HT_REFLKN REFLK_P/ON(ON) REFLK_N(PWM_GPIO) GFX_REFLKP GFX_REFLKN GPP_REFLKP GPP_REFLKN I I/O I/O GPPS_REFLKP(S_REFLKP) GPPS_REFLKN(S_REFLKN) I LOKs PM PLL PWR LVTM TXLK_LP(G_GPIO) TXLK_LN(G_GPIO) TXLK_UP(PIE_RESET_GPIO) TXLK_UN(PIE_RESET_GPIO) VLTP(N) VSSLTP(N) VLT_(N) VLT_(N) VLT_(N) VLT_(N) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) LVS_IGON(PE_TLRP) LVS_LON(PE_RLRP) LVS_EN_L(PWM_GPIO) E E F G L_LK L_LK# L_LK L_LK#.V_VLTP_N.V_VLT N INT_ISP_ON INT_PST_PWM INT_LVS_LON L_LK L_LK# L_LK L_LK# hange from M request INT_ISP_ON INT_PST_PWM INT_LVS_LON PE_GPIO PE_GPIO RV- *RV- VG_SWON INT_EIT INT_EILK HMI LK HMI T YN_PWR_EN hange HMI LK/T PIN for M recommand INT_EIT INT_EILK HMI T_L HMI LK HMI T YN_PWR_EN T G I_T I_LK _T/UXN(N) _LK/UXP(N) _LK/UXP(N) _T/UXN(N) STRP_T RSV UX_L(N) RSM MIS. TMS_HP(N) HP(N) SUS_STT#(PWM_GPIO) THERMLIOE_P THERMLIOE_N TESTMOE E TMS_HP SUS_STT#_N TEST_EN R.K_ R _ T INT_TMS_HP SUS_STT# STRP_EUG_US_GPIO_ENLEb Enables the Test ebug us using GPIO. RSM isable Enable INT_VSYN_OM R K_ V RSM --- V L LMPGSN(,.)_ V- nalog not applicable to RS.V L LMPGSN(,.)_ U/.V_ PLLV - Graphics PLL not applicable to RS V_V_N.U/.V_.V_PLLV.U/.V_.V.V LMPGSN(,.)_ L R _.U/V_.V_PLLV.U/.V_.V_VI_N LMPGSN(,.)_.V_VQ_N L PLLV - Graphics PLL not applicable to RS VI- igital not applicable to RS VQ- andgap Reference not applicable to RS.V L L LMPGSN(,.)_.U/.V_ LMPGSN(,M,)_.U/.V_.V_VLTP_N.V_VLT N VLT - LVS or VI/HMI digital not applicable to.u/v_ RS VLTP - LVS or VI/HMI PLL not applicable to RS RSM: Enables Side port memory.u/.v_ RSM:INT_HSYN_OM Selects if Memory E PORT is available or not = Memory Side port Not available = Memory Side port available Register Readback of strap: N_LKFG:LK_TOP_SPRE_[] For extrnal EEPROM ebug only INT_HSYN_OM YN_PWR_EN R R R *K_ K_ RS K/F_ V.V VPIEPLL -PIE PLL mils width L.V_VPIEPLL LMPGSN(,.)_.U/.V_ VHTPLL -HT LINK PLL mils width L.V_VHTPLL LMPGSN(,.)_.U/.V_, PU_LT_STOP# U N V IN GN OUT LVGGW.V R.U/V_ K/F_ LLOW_LTSTOP N_LT_STOP#.V R K/F_ R *_/S N_LLOW_LTSTOP PROJET : LX Quanta omputer Inc. N/R Size ocument Number Rev ustom RS-SYSTEM I/F / Monday, September, ate: Sheet of

E G G G H J R L L L L M N P R R R V U V V W W W W W Y E E UF E G E E J J K M L RSM POWER TLE PIN NME RSM PIN NME RSM VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE PRT / GROUN VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VHT VHTRX VHTTX VPIE VG V_MEM.V.V.V.V.V.V IOPLLV V VI VQ PLLV PLLV.V.V.V.V.V.V.V_YN V,,,,,,,,,,,,,,,,,,,,,,,,.V,,,,,,.V,,,.V,,,,, VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VPIE V V_MEM.V.V.V/.V VPIEPLL.V VHTPLL.V VLTP.V E G G G H J L L L L M N P R R R R H U V W W W Y L M N P P R R T U U U V W W Y E K VG IOPLLV.V.V VLT VLT.V N VHTTX - HT LINK TX I/O for RS RSM.V VHT - HT LINK digital I/O for RS VHTRX - HT LINK RX I/O for RS L *_/S.V..V for RSMS m.v L LMPGSN(,M,)_ VPIE - PIE TX stage I/O for RS V - RS I/O transform.v for RSM.. L *_/S L *_/S.V for RSM.U/.V_.V.U/V_ R.U/.V_ U/.V_.U/.V_.U/.V_.U/V_ *_/S.U/V_.U/V_.U/V_ m U/V_ m.v R *_/S V_MEM For UM RS only Not applicable to RX U/V_ memory I/O transform.v_vht.u/v_.u/v_.u/v_.v_vhtrx.u/v_.v_vhttx.u/v_.u/v_.u/v_.v_vpie.u/v_.u/v_.v_vg_n.v_v_mem J K L M P R T H G F E E Y W V U T R P M J P K M L W H T R Y E U F G E UE VHT_ VHT_ PRT / VHT_ VHT_ VHT_ VHT_ VHT_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ POWER VG_(V_) VG_(V_) V_MEM(N) V_MEM(N) RSM VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) VG_(N) VG_(N) E F G H J K M L P R T V U K J U J K M L L M M N N P P P R R T T U T J E Y H H.V_V_PIE.U/V_.U/V_ U/V_.U/V_.U/V_.V_V_MEM.U/V_ V_VG.U/V_.U/V_.U/V_.U/V_. U/V_.U/V_.U/.V_.U/V_.U/V_.U/V_.U/.V_ Ra R RS.V(.) *_/S V.U/V_.U/V_ R V -.V I/O Not applicable to RX VPIE - PIE-E Main power.v V - ore Logic power.v_yn U/.V_ U/.V_ *_/S L _ V_MEM For UM RS only Not applicable to RX memory I/O transform.v IS remove L, add Ra as ohm to GN PROJET : LX Quanta omputer Inc. N/R Size ocument Number Rev ustom RS-POWER/ ate: Monday, September, Sheet of

LN_PLTRST# MINI_PLTRST# PIE_RST#.V_PIE_VR V_VG, VS,,,,, VPU,,,,,,,,,,,, PLE THESE PIE OUPLING PS LOSE TO U, SLINK_LKP, SLINK_LKN SSR_LKP SSR_LKN N_REFLK_P N_REFLK_N, NHT_REFLKP, NHT_REFLKN, PULKP, PULKN, EXT_GFX_LKP, EXT_GFX_LKN, PIE_MINI_LKP, PIE_MINI_LKN, PIE_LN_LKP, PIE_LN_LKN V_VG To RS R _ R _ PIE_S_N_RXP PIE_S_N_RXN PIE_S_N_RXP PIE_S_N_RXN PIE_S_N_RXP PIE_S_N_RXN PIE_S_N_RXP PIE_S_N_RXN PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN _RST#_R dd N gate for the reset input of PIE devices for M recommand R K/F RST#_R SLINK_LKP SLINK_LKN SSR_LKP SSR_LKN N_REFLK_P N_REFLK_N NHT_REFLKP NHT_REFLKN PULKP PULKN N_PLTRST# R R.V_PIE_VR V RV- RV- U TSHFU EXT_GFX_LKP EXT_GFX_LKN PIE_MINI_LKP PIE_MINI_LKN PIE_LN_LKP PIE_LN_LKN R RST#_R R _ VG_RST R INT _ R INT RST#.U/V RXP_.U/V RXN_.U/V RXP_.U/V RXN_.U/V RXP_.U/V RXN_.U/V RXP_.U/V RXN_ PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN _RST# hange from VG_RST to _RST#_R P/V_ R _ /F_.K/F_.U/V_ T R _ R M/F_ P PIE_RST# L _RST# _TXP _TXN _TXP _TXN _TXP _TXN _TXP _TXN E _RXP E _RXN _RXP _RXN _RXP _RXN _RXP _RXN PIE_LRP_S PIE_LRN_S PIE_LRP PIE_LRN GPP_TXP GPP_TXN Y GPP_TXP Y GPP_TXN Y GPP_TXP Y GPP_TXN W GPP_TXP W GPP_TXN GPP_RXP Y GPP_RXN GPP_RXP GPP_RXN W GPP_RXP V GPP_RXN W GPP_RXP W GPP_RXN R EXT *_ NLKP M R EXT *_ NLKN PIE_RLKP/N_LNK_LKP P PIE_RLKN/N_LNK_LKN R INT _ N_REFLK_P_INT U R INT _ N_REFLK_N_INT N_ISP_LKP U N_ISP_LKN R INT _ NHT_REFLKP_INT T R INT _ NHT_REFLKN_INT N_HT_LKP T N_HT_LKN R INT _ PULKP_INT V R INT _ PULKN_INT PU_HT_LKP T PU_HT_LKN R INT _ EXT_GFX_LKP_INT V R INT _ EXT_GFX_LKN_INT SLT_GFX_LKP T SLT_GFX_LKN R INT _PIE_MINI_LKP_INT L R INT _PIE_MINI_LKN_INT GPP_LKP L GPP_LKN N GPP_LKP N GPP_LKN M GPP_LKP M GPP_LKN R INT _PIE_LN_LKP_INT T R INT _PIE_LN_LKN_INT GPP_LKP V GPP_LKN Y MHZ L GPP_LKP L GPP_LKN P GPP_LKP M GPP_LKN P GPP_LKP P GPP_LKN N GPP_LKP N GPP_LKN T GPP_LKP T GPP_LKN L U M_X L M_X M_X L M_X M_M_M_OS S PI EXPRESS INTERFES LOK GENERTOR PI LKS Part of PILK PILK/GPO PILK/GPO PILK/GPO PILK/M_OS/GPO PIRST# /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO E# E# E# E# FRME# EVSEL# IRY# TRY# PR STOP# PERR# SERR# REQ# REQ#/GPIO REQ#/LK_REQ#/GPIO REQ#/LK_REQ#/GPIO GNT# GNT#/GPO GNT#/GPO GNT#/LK_REQ#/GPIO LKRUN# LOK# PI INTERFE INTE#/GPIO INTF#/GPIO INTG#/GPIO INTH#/GPIO LPLK LPLK L L L L LFRME# LRQ# LRQ#/LK_REQ#/GPIO SERIRQ/GPIO LP LLOW_LTSTP/M_TIVE# PROHOT# LT_PG LT_STP# LT_RST# PU RT K_X K_X RTLK INTRUER_LERT# VT_RT_G W PI_LK W PI_LK_TPM W W PI_LK PI_LK Y PI_LK V E E F E F G F E F F F H G H E J E F E E E H H J H J G G J H H J J H H G J G H K G J PIRST#_L INT_VG_EN# S_MEMHOT# SERR# PX_EN# VG_ON_S LKRUN# INTG# VG_RST LP_LK LP_LK L L L L LFRME# LRQ#_S SERIRQ RT_X RT_X R _ INTG# LLOW_LTSTOP PU_PROHOT_R# PU_PWRG PU_LT_STOP# PU_LT_RST# PIRST# T PI_LK_TPM PI_LK PI_LK PI_LK ll the PI bus has build-in Pull-UP/own resistors R T T T R _ R _ T K/F_ RT_LK INTRUER_LERT# R VT T T SERR# T LKRUN# L, L, L, L, LFRME#, SERIRQ VS RT_LK R _ P/V_ LLOW_LTSTOP PU_PROHOT_R# PU_PWRG PU_LT_STOP#, PU_LT_RST# *M/F_ PIRST# LP_LK LP_LK VT VR_._EN VT VG_ON_S.P/V_ MIL U/V_ R P/V_ /F_ VRT_ PLK_LP_EUG PLK_LP_K VT MIL R *M_ R _ VRT MIL MIL RT_X RT_X MIL MIL H=. footprint: "T-_-_" footprint check ok R Y.KHZ P/V_ M_ RV- P/V_ G *SHORT_ P RV- R K/F_ T T_ONN T VRT_ VT.U/V_ VPU P/V_ S INTRUER_LERT# Left not connected (Southbridge has -kohm internal pull-up to VT). N/R PROJET : LX Quanta omputer Inc. Size ocument Number Rev ustom S-PIE/PI/PU/LP / ate: Monday, September, Sheet of

VS VS VS V S_TEST S_TEST S_TEST V SL/ST is V tolerance M datasheet define it VS R R R R R N,no install by default.k_ PLK_SM.K_ PT_SM SL/ST is V/S tolerance M datasheet define it R R.K_ S_SMLK.K_ S_SMT remove pull hi ( chip internal have pull hi ) SL/ST is V/S tolerance M datasheet define it R R R R *.K_ *.K_ *.K_.K_.K_.K_.K_ S_SLK S_ST NSWON# SUS_STT# lock gen/robson/tv tuner /R/R thermal/ccelerometer, PIE_WKE# MEM_GEVEN# T T SUS# SUS# NSWON# S_PWRG_IN SUS_STT# GTE RIN# T KSMI# # T PU_THERMTRIP# P/V_ T T, LN_ISLE# T LE_EN T Z_SPKR,,,, PLK_SM,,,, PT_SM T T T T SP_R_RST# T T T T EXT_S_OS PM_THERM# VS R *_ R K/F_ S_JTG_TO S_JTG_TK S_JTG_TI S_JTG_RST# MEM_GEVEN# RI# SPI_S# SUS# SUS# NSWON# S_PWRG_IN SUS_STT# S_TEST S_TEST S_TEST GTE RIN# KSMI# # SYS_RST# PU_THERMTRIP# W_PWRG W_PWRG RSMRST# RSMRST# SMLERT#_ U J PI_PME#/GEVENT# K RI#/GEVENT# SPI_S#/GE_STT/GEVENT# F SLP_S# H SLP_S# F PWR_TN# H PWR_GOO S G SUS_STT# TEST Part of TEST/TMS F TEST GIN/GEVENT# E KRST#/GEVENT# K LP_PME#/GEVENT# J LP_SMI#/GEVENT# H GEVENT# J SYS_RESET#/GEVENT# H WKE#/GEVENT# F IR_RX/GEVENT# J THRMTRIP#/SMLERT#/GEVENT# N_PWRG G RSMRST# LK_REQ#/ST_IS#/GPIO R *_ LN_ISLE#_S LK_REQ#/ST_IS#/GPIO SMRTVOLT/ST_IS#/GPIO LK_REQ#/ST_IS#/GPIO F ST_IS#/FNOUT/GPIO E Z_SPKR ST_IS#/FNIN/GPIO F PLK_SM SPKR/GPIO PT_SM SL/GPIO E S_SMLK S/GPIO F S_SMT SL/GPIO F S/GPIO H LK_REQ#/FNIN/GPIO LK_REQ#/FNOUT/GPIO E IR_LE#/LL#/GPIO J SMRTVOLT/SHUTOWN#/GPIO H R_RST#/GEVENT# GE_LE/GPIO GE_LE/GEVENT# G GE_LE/GEVENT# K EXT_S_OS GE_STT/GEVENT# LK_REQG#/GPIO/ON H LINK/US_O#/GEVENT# US_O#/IR_TX/GEVENT# E US_O#/IR_TX/GEVENT# US_O#/IR_RX/GEVENT# E US_O#/_PRES/TO/GEVENT# F US_O#/TK/GEVENT# E US_O#/TI/GEVENT# F US_O#/TRST#/GEVENT# PI / WKE UP EVENTS GPIO US O USLK/M_M_M_OS US. US MIS US. US_FSP/GPIO US_FSN US_FSP/GPIO US_FSN US_ROMP US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN G J H H J F E E E J J G G G G E E J J LK_M_US US_ROMP_S R USP USP- USP USP- T T USP USP- USP USP- USP USP- T T USP USP- USP USP- USP USP- T T USP USP- USP USP- USP USP- LK_M_US.K/F_ LUETOOTH Finger Print US onnector." ard reader WLN Min-ard US onnector US onnector." amera US igitizer onnector LK_M_US *.P/V_ for EMI US & EST ombo onnector US onnector." and " co-layout Z_SOUT Z_SYN Z_LK Z_RST# Z_N To zalia R _ R _ R _ R _ *P/V_ *P/V_ P/V_ Z_SOUT_UIO Z_SYN_UIO IT_LK_UIO Z_RST#_UIO Z_N VSUS,,,,, V,,,,,,,,,,,,,,,,,,,,,,,, VS,,,,, S JTG N VSUS Z_SOUT H audio interface is.s voltage S_JTG_TK S_JTG_TO S_JTG_TI S_TEST S_JTG_RST# R *K/F_ R R R R P/V_ *K/F_ *K/F_ *K/F_ *K/F_ Z_LK Z_SOUT Z_N Z_N Z_N_R Z_N_R Z_SYN Z_RST# T T T M Z_ITLK N Z_SOUT L Z_N/GPIO M Z_N/GPIO M Z_N/GPIO M Z_N/GPIO N Z_SYN P Z_RST# T GE_OL T GE_RS L GE_MK L GE_MIO T GE_RXLK U GE_RX U GE_RX T GE_RX U GE_RX T GE_RXTL/RXV V GE_RXERR P GE_TXLK M GE_TX P GE_TX T GE_TX P GE_TX M GE_TXTL/TXEN P GE_PHY_P M GE_PHY_RST# V GE_PHY_INTR GE LN H UIO E PS_T/S/GPIO E PS_LK/SL/GPIO F SPI_S#/GE_STT/GPIO G F_RST#/GPO PSK_T/GPIO F PSK_LK/GPIO F PSM_T/GPIO E PSM_LK/GPIO S EMEE TRL SL/GPIO S/GPIO SL_LV/GPIO S_LV/GPIO E_PWM/E_TIMER/GPIO E_PWM/E_TIMER/GPIO E_PWM/E_TIMER/GPIO E_PWM/E_TIMER/GPIO EMEE TRL K_/GPIO K_/GPIO K_/GPIO K_/GPIO K_/GPIO K_/GPIO K_/GPIO K_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO KSO_/GPIO F E F E F E G G E E S_SLK S_ST S_SLK _RST_R# S_GPIO S_GPIO T _RST_R# S_GPIO S_GPIO SPI/LP define PROJET : LX Quanta omputer Inc. *S/W JTG EUG N/R Size ocument Number Rev ustom S-PI/GPIO/US / ate: Monday, September, Sheet of

ST H ST O E-ST ST PORT,,, can support HI mode ST H ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP PLE ST_L RES VERY LOSE TO LL OF S NOTE: R IS K % FOR MHz XTL,.K % FOR MHz INTERNL LOK.V_V_ST PLE ST OUPLING PS LOSE TO S XTLV_ST-- ST crystal power PLV_ST-- ST PLL POWER.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_ R R V R P/V_ S_ST_LE# ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_RXN_ ST_RXP_ K/F_ ST_LRP /F_ ST_LRN K/F_ ST_X Remove Y for M recommand H ST_TXP J ST_TXN J ST_RXN H ST_RXP H ST_TXP J ST_TXN G ST_RXN F ST_RXP G ST_TXP F ST_TXN J ST_RXN H ST_RXP H ST_TXP J ST_TXN G ST_RXN F ST_RXP G ST_TXP F ST_TXN U J ST_RXN H ST_RXP J ST_TXP H ST_TXN H ST_RXN J ST_RXP ST_LRP ST_LRN ST_T#/GPIO ST_X Y R *MHZ M/F_ P/V_ ST_X ST_X SERIL T S F_LK Part of F_FLKOUT F_FLKIN F_OE#/GPIO F_V#/GPIO F_WE#/GPIO F_E#/GPIO F_E#/GPIO F_INT/GPIO F_INT/GPIO F_Q/GPIO F_Q/GPIO F_Q/GPIO F_Q/GPIO F_Q/GPIO F_Q/GPIO F_Q/GPIO F_Q/GPIO F_Q/GPIO F_Q/GPIO F_Q/GPIO F_Q/GPIO F_Q/GPIO F_Q/GPIO F_Q/GPIO F_Q/GPIO FNOUT/GPIO FNOUT/GPIO FNOUT/GPIO FNIN/GPIO FNIN/GPIO FNIN/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/TLERT#/GPIO TEMP_OMM HW MONITOR FLSH VIN/GPIO VIN/GPIO VIN/GPIO VIN/GPIO VIN/GPIO VIN/GPIO VIN/GE_STT/GPIO VIN/GE_LE/GPIO H G F F G G F E F H J J H H G H J G F H J F J J G H W W Y W V W IF THERE IS NO IE, TEST POINTS FOR EUG US IS MNTORY TEMPIN R RF_OFF# T_OFF# R _ K/F_ E_PORT_I E_PORT_I E_PORT_I OR_I OR_I OR_I OR_I OR_I T T T T T T T T T T T T T T T T T T T T T T T T T T T VS IF USE,power need ready E_PORT_I RF_OFF# T_OFF# T_OMO_EN# GT_STOP# GT_RESET L_K.V_V_ST V,,,,,,,,,,,,,,,,,,,,,,,, VS,,,,, E_PORT_I VS VS VS VS E_PORT_I R R R R R *K/F_ *K/F_ *K/F_ *K/F_ *K/F_ E_PORT_I R E_PORT_I R E_PORT_I R OR_I OR_I Samsung Hynix N no supprot side port R R *K/F_ *K/F_ *K/F_ *K/F_ *K/F_ T ROM_RST# J SPI_I/GPIO E SPI_O/GPIO K SPI_LK/GPIO K SPI_S#/GPIO G ROM_RST#/GPIO S SPI ROM N N G Y R R R *K/F_ *K/F_ *K/F_ OR_I OR_I OR_I R R R *K/F_ *K/F_ *K/F_ V I I I I I LX UM.U/V_ LX UM ST_LE# U TSHFU S_ST_LE# LX Madison LX Park LX Park.VSUS R.K_ Q MMT R.K_.VSUS MEM_M_EVENT# MEM_GEVEN# R.K_ Q MMT R.K_ MEM_M_EVENT# PROJET : LX Quanta omputer Inc. N/R Size ocument Number Rev ustom S-PI/GPIO/US / ate: Monday, September, Sheet of

V.V V.V VS.VS V.V_S_R.V : FLSH MEMORY MOE(EFULT) V_--.V IE I/O power.v: IE MOE.V flash memory I/O power R _ L LMPGSN(,.)_ L LMPGSN(,.)_ L LMPGSN(,.)_ L LMPGSN(,.)_ For support US wakeup-->v_s L LMPGSN(,.)_ L R _ VQ--.V I/O power M recommand remove.v.u/.v_.u/.v_ LMPGSN(,.)_ VPL_.V_PIE PIE_VR--PIE I/O power U/.V_ *.U/V_ *.U/V_ V_ST--ST phy power U/.V_ VTX--US Phy nalog I/O power.u/.v_ U/.V_.U/V_ VPL_.V_ST.U/V_ VN_.V_US.U/V_ m VIO F.V_PIE_VR.V_V_ST m.u/v_.u/v_.u/v_ U/V_ U/.V_ U/.V_ U/V_ m m U/.V_ U/V_.U/V_.U/V_ m m U/V_ V_V_US m U/V_ Tm PLE LL THE EOUPLING PS ON THIS SHEET LOSE TO S S POSLE. H VIO PIGP_ V VIO PIGP_ Y VIO PIGP_ E VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ F VIO PIGP_ VIO PIGP_ F VIO F_ E VIO F_ F VIO F_ VIO F_ E VPL PIE U VN PIE_ V VN PIE_ V VN PIE_ V VN PIE_ V VN PIE_ V VN PIE_ W VN PIE_ W VN PIE_ U POWER VPL ST S J VN ST_ F VN ST_ H VN ST_ G VN ST_ E VN ST_ VN ST_ E VN ST_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ VN US_S_ E VN US_S_ VN US_S_ VN US_S_ S PI/GPIO I/O FLSH I/O SERIL T PI EXPRESS US I/O PLL GE LN LKGEN I/O ORE S Part of VR N VR R VR N VR U VR U VR V VR V VR W VR W ORE S VN LK_ K VN LK_ K VN LK_ J VN LK_ K VN LK_ J VN LK_ J VN LK_ K VN LK_ J VRF_GE_S VIO GE_S VR GE_S_ L VR GE_S_ L VIO_GE_S_ M VIO_GE_S_ P M m Tm VXL_.V KV_.V-- Internal clock Generator I/O power U/V_ m.u/v_ *.U/V_ V-- S/ ORE power U/V_.V_V_S_R.V_KV U/V_ LMPGSN(,.)_ L V R _ U/.V_ VLW_R S_.--.v standby power m R _ VIO S_ VS VIO S_ VIO S_ VIO S_ K *.U/V_ VIO S_ L.U/.V_.U/.V_ VIO S_ J VIO S_ T VIO S_ T S_.V--.V standby power m VR_.V VR S_ F R _.VS VR S_ G Tm VIO_Z VIO_Z_S M U/V_ U/V_ VR_.V_US VR US_S_ VR US_S_ m LMPGSN(,.)_ VPL SYS M VPL_.V m L.VS VPL SYS_S L VPL_.V m VPL US_S F VPL_.V_US m U/.V_.U/V_.U/V_ VN HWM_S VN_.VHWM m.v_s I/O VXL S V L.U/V_ U/V_.U/V_.U/.V_.V LMPGSN(,.)_ L.V.U/V_ U/.V_ UE Y VSO_ST_ Y VSO_ST_ VSO_ST_ VSO_ST_ E VSO_ST_ E VSO_ST_ F VSO_ST_ F VSO_ST_ F VSO_ST_ F VSO_ST_ G VSO_ST_ H VSO_ST_ H VSO_ST_ H VSO_ST_ H VSO_ST_ J VSO_ST_ J VSO_ST_ J VSO_ST_ J VSO_ST_ VSO_US_ VSO_US_ K VSO_US_ VSO_US_ VSO_US_ VSO_US_ VSO_US_ VSO_US_ E VSO_US_ F VSO_US_ F VSO_US_ F VSO_US_ F VSO_US_ VSO_US_ G VSO_US_ F VSO_US_ VSO_US_ H VSO_US_ H VSO_US_ H VSO_US_ H VSO_US_ J VSO_US_ J VSO_US_ K VSO_US_ K VSO_US_ K VSO_US_ K VSO_US_ H VSO_US_ Y EFUSE VSSN_HWM M VSSXL S GROUN VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSSPL_SYS P VSO_PIELK_ VSO_PIELK_ P VSO_PIELK_ VSO_PIELK_ M VSO_PIELK_ VSO_PIELK_ M VSO_PIELK_ VSO_PIELK_ M VSO_PIELK_ VSO_PIELK_ P VSO_PIELK_ VSO_PIELK_ P VSO_PIELK_ VSO_PIELK_ P VSO_PIELK_ VSO_PIELK_ T VSO_PIELK_ VSO_PIELK_ T VSO_PIELK_ VSO_PIELK_ T VSO_PIELK_ VSO_PIELK_ V VSO_PIELK_ VSO_PIELK_ J VSO_PIELK_ VSO_PIELK_ VSO_PIELK_ Part of J E E E F N R R T P V U M V M L L J P V V W W J U Y Y Y Y G J G G M F H H V P N L L M H H Y W W E L K S V VPL_.V.V VPL_.V VS R _ VIO_Z L LMPGSN(,.)_.U/.V_ *.U/V_ L LMPGSN(,.)_.U/.V_ *.U/V_.V,,,,,, V,,,,,,,,,,,,,,,,,,,,,,,,.V,,,,,, VS,,,,,.VS.U/.V_ VS VN_.VHWM VS VPL_.V_US L *_/S.U/V_ el L for M recommand.u/.v_.u/v_ PROJET : LX Quanta omputer Inc. N/R Size ocument Number Rev ustom S-PWR/EOUPLING / ate: Monday, September, Sheet of

OVERLP OMMON PS WHERE POSLE FOR UL-OP RESTORS. REQUIRE STRPS intermal have pull Hi K, confirm M ward this pull Hi not need VIO_Z V,,,,,,,,,,,,,,,,,,,,,,,, VS,,,,,.V,,,,, It must ready refore RSMRST# VS VIO_Z V VS VS INT LK GEN R Z_SOUT R *K/F_ PI_LK_TPM PI_LK R K/F_ PI_LK PI_LK LP_LK LP_LK RT_LK R K/F_ R *K/F_ S_GPIO S_GPIO K/F_ R K/F_ R *K/F_ R K/F_ R K/F_ R K/F_ R *K/F_ GPIO R *.K_ R.K_ GPIO EXT LK GEN TYPE GPIO GPIO REQUIRE STRPS PULL HIGH Z_SOUT LOW POWER MOE PI_LK LLOW PIE Gen EFULT PI_LK Watchdog Timer Enabled PI_LK USE EUG STRP PI_LK non_fusion LOK MOE EFULT LP_LK E ENLE LP_LK LKGEN ENLE EFULT GPIO GPIO H,H = H,L = SPI ROM FWH LP SPI L :.K pull down N L :.K pull down L :.K pull down L :.K pull down N PULL LOW PERFORMNE MOE EFULT FORE PIE Gen Watchdog Timer isabled EFULT IGNORE EUG STRP EFULT FUON LOK MOE E ISLE EFULT LKGEN ISLE L,H = LP ROM (efault) L,L = FWH ROM RSV N N EUG STRPS S HS K INTERNL PU FOR PI_[:] N_PWRG_IN: RS/RX =.V; RS =.V o NOT share it with S_PWRG when use Internal lk Gen (Need S PLL initialize firstly) VS R K/F_ R *_/S S_PWRG_IN S_PWRG_IN R *.K_ R *.K_ R *.K_ R *.K_ R *.K_ Use.K P. VRM_PWRG, EPWROK *.U/.V_ T.V U N V GN Y *NLSZFTG SOT- *.U/V_ R *_ N/S POWER GOO IRUIT.V R _ RX,RS N_PWRG_IN N_PWRG_IN R *_/S W_PWRG PI_ PI_ PI_ PI_ PI_ PULL HIGH USE PI PLL ISLE IL UTORUN USE F PLL USE EFULT PIE STRPS ISLE PI MEM OOT LSZ LUG I(P) NLSZFTG(SOT-) I OTHER(P) SNUGVR(SOT-) SOT- SOT- EFULT EFULT EFULT EFULT EFULT PULL LOW YPSS PI PLL ENLE IL UTORUN YPSS F PLL USE EEPROM PIE STRPS ENLE PI MEM OOT PROJET : LX Quanta omputer Inc. N/R Size ocument Number Rev ustom S-STRPS ate: Monday, September, Sheet of

PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX#.GT/s bit rate PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# Y Y W W V V U U T T R R P P N N M M L L K K J J H H G G F F E U PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PI EXPRESS INTERFE PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN Y Y W W U U U U T T T T P P P P N N N N L L L L K K J J K K H H _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_ PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# R PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX#.V_P_V.V_P_V.V_P_V.V_P_V /F_P_LR.V_PE_V.V_PE_V.V_PE_V P P P T N P P W W P P P P N P P W W W H J L M N P R U F G UH P / POWER P_V# P_V# P_V# P_V# P_VSSR# P_VSSR# P_VSSR# P_VSSR# P_VSSR# P_V# P_V# P_V# P_V# P_VSSR# P_VSSR# P_VSSR# P_VSSR# P_VSSR# P_LR P E/F POWER PE_V# PE_V# PE_V# PE_V# PE_VSSR# PE_VSSR# PE_VSSR# PE_VSSR# PF_V# PF_V# P / POWER P_V# P_V# P_V# P_V# P_VSSR# P_VSSR# P_VSSR# P_VSSR# P_VSSR# P_V# P_V# P_V# P_V# P_VSSR# P_VSSR# P_VSSR# P_VSSR# P_VSSR# P_LR P PLL POWER P_PV P_PVSS P_PV P_PVSS P_PV P_PVSS P_PV P_PVSS PE_PV PE_PVSS N P P P N P P W W P P N P N P P W W W U V V R U V V R M N.V_P_V.V_VG.V_P_V ( P/_V :.V@m).V_VG L.V_P_V HKF-T_ U/.V_ U/.V_.U/V_ R P_LR /F_ ( P/_PV :.V@mm).V_VG L.V_P_PV HKF-T_ U/.V_ U/.V_.U/V_ ( P/_PV:.V@mm).V_VG.V_P_PV, EXT_GFX_LKP, EXT_GFX_LKN K/F_ EXT_GFX_LKP EXT_GFX_LKN R J K H LOK PIE_REFLKP PIE_REFLKN N# N# PWRGOO LIRTION PIE_LRP PIE_LRN Y Y M_PIE_LRP R M_PIE_LRN R.K/F_ K/F_.V_VG.V_PE_V K K F H K L M PF_V# PF_V# PF_VSSR# PF_VSSR# PF_VSSR# PF_VSSR# PF_VSSR# N_PF_PV N_PF_PVSS L M U/.V_ ( PE/F_PV.V@mm).V_VG L.V_PE_PV HKF-T_.U/V_.U/V_ PIE_RST# PERST R /F_ PEF_LR M PEF_LR MHz (/-ppm) input frequency, -.V single-ended swing M_m M_m ( V M.V) ( PE/F_V :.V@mm ).V_VG L.V_PE_V ( PE/F_V :.V@mm).V_VG L.V_PE_V HKF-T_ U/.V_ U/.V_.U/V_ U/.V_ U/.V_.U/V_ HKF-T_.V_P_V ( P_V :.V@m) L.V_VG ( P/_V :.V@mm).V_P_V.V_VG HKF-T_ U/.V_ U/.V_.U/V_.V_VG ( P/_V :.V@mm).V_P_V,,.V_VG,,.V_VG PROJET : LX Quanta omputer Inc. N/R Size ocument Number Rev ustom TI Park/Madison (PIE I/F) / ate: Monday, September, Sheet of