Behavior Model
DES PCI DES PCI
DES DES(Data Encryption Standard) IBM DES DES DES DES DES DES / DES DES P. - (Round) / - k,k,,k k,k,,k P. - (Initial Permutation) L R R k f L (XOR)
R R L Ri = Li- XOR f(ri-,ki) Li = Ri-i = R L P. - P. - A(P. -) C D ( P. -) C D B( P. -) k k k F P. - f f R K R E(P. -) K (XOR) SS S *= P(P. -) f
P. - - S ( ) S ( ) = ( ) = = ( )
PCI PCI BUS P. -Intel PCI VESA VL VL burst. PCI BUS PCI Peripheral Component Interconnect PCI PCI burst Burst burst master( ) target target master target. PCI PCI. PCI PCI PCI PCI. PCI PCI.
PCI. burst PCI Mbytes PCI Mbytes MHz PCI Mbytes.. PCI MHz. MHz.. ns PCI initiator PCI target MHz. PCI. bus master bus master peer-to-peerpci PCI-to-PCI PCI master PCI target. bus master PCI PCI. PCI target initiator.
. I/O. bit-level Configuration Register. PCI. PCI. PCI bus. burst ( P. - ) bus master target Target PCI,target(bus master ) master burst Target burst burst - Initiator Target Agent PCI burst initiator target
Initiator bus master PCI Target initiator PCI initiator target PCI-Compliant Agent.PCI : initiator target Target PCI / Initiator PCI / Command or Byte Enable Bus Initiator FRAME# initiator PCI PCI target / target / / initiator target / target PCI target target DEVSEL# (Device Select ) initiator DEVSEL# initiator target initiator
/ PCI initiator target PCI PCI initiatorirdy#targettrdy# Ready FRAME# initiator IRDY# target IRDY# FRAME# target TRDY# initiator IRDY# PCI -PCI PCI master target target target target inactive target. PCI CLK PCI CLK PCI CLK..
.. LOCK Reset Signal, RST# PCI master target PCI P. -.PCI : IRDY TRDY initiator IRDY TRDY IRDY FRAMEtarget TRDY STOP TRDY STOP DEVSEL Read
CLK FRAME# CycleAD bus C/BE# Cycle I/O Read Memory Read CLK C/BE# BytesDEVSEL# IRDY# CLK TRDY# bus IRDY#TRDY# AD bus CLK TRDY# CLK TRDY# bus IRDY#TRDY# AD bus CLK TRDY# bus IRDY#High. CLK TRDY# bus IRDY#TRDY# Low AD bus FRAME# High Cycle CLK Cycle CLK Cycle.PCI
Write CLK FRAME# CycleAD bus C/BE# Cycle I/O Write Memory Write CLK C/BE# BytesDEVSEL# IRDY# AD bus TRDY# IRDY#TRDY# CLK IRDY# AD bus TRDY# IRDY#TRDY# CLK IRDY# TRDY# CLK IRDY# AD bus TRDY#
FRAME# Cycle CLK TRDY# CLK TRDY# IRDY#TRDY# CLK Cycle CLK. Cycle.PCI PCI bus master PCI PCI master REQ bus PCI master GNT bus master master master master agent FRAME REQ bus master bus master bus master
PCI BUS CLK A REQ#-a. bus CLK A GNT#-a B REQ#-b. CLK A FRAME# A CLK A B GNT#-b. GNT#-a. CLK B B FRAME# CLK B FRAME# B B REQ#-b CLK A REQ#-a A GNT#-a GNT#-b B
.PCI.PCI
.PCI
VHDL VHDL Very high speed integrated circuit Hardware Description Language IEEE IEEE ASIC VHDL VHDL IEEE IEEE VHDL IEEE. VHDL VHDL VHDL ASIC PCB VHDL VHDL
VHDL VHDL
VHDL VHDL.. Flexibility VHDL. Portability Behavior Model Signal Assignment VHDL a <= b ; a b a gets the value of b VHDL VHDL Inertia delay Transport Delay
VHDL VHDL VHDL TRANSPORT
WinDriver WinDriver
DES DES Key DES Key Key Key DES Key DES Key DES Key Key Key Key Plaintext- DES DES DES DES DES DES Ciphertext- Key Key Key P.S. : - Mode ( )
DES.vhd
- Key_sel.vhd K( ) ABDEFC K BEFE K CEFAB K BA K EECFDA K FEDE K EABC K FCFAA K EFADACA K : DBF K BBCCA K AEE K BFB K DEDD K DDD K DBEAAB K EBAA
- : - DES Key ACEFEBFAC Key EDFAFFEC Key ABEFDD CFCF
VHDL
; DES by PCI DESPCIAMCC S Paper VHDL PCIAMCC SDES VHDL MaxPlus work WinDriver
( ) - DES
- A C D C D Cn Dn C D
- f(r,k)
- -
- A - B
- - E - F
- (S-Boxes) S S S S S S S S
- PCI - BURST - PCI Master Target Cycle Frame initiator Master bus PCI CLK FRAME# / FRAME#IRDY GNT initiator
FRAME Target Ready target target PCI CLK TRDY# IRDY# STOP# DEVSEL# LOCK# GNT# PERR# TRDY#IRDY# TRDY target TRDY target master Initiator ready bus master IRDY initiator / target IRDY initiator Target STOP initiator Device Select master CLK DEVSEL# atomic / / / initiator lock target Grant PCI master master GNT master (GNT# ) Parity Error PCI / PCI target
target PERR# STOP burst initiator PERR target PCI initiator initiator PERR System Error PCI SERR# /