10384 200024024 UDC 2003 5 2003 6 2003 2003 5 i
Abstract / / B-ISDN ATM Crossbar Batcher banyan N DPA Modelsim Verilog Synopsys Design Analyzer Modelsim FPGA ISE FPGA ATM ii
System On-Chip Design and Performance Analysis of Cell-based Switches Abstract Nowadays the great progress in information technology presents high requirements on the data communications and switching in the network. Data communications consist of data transfer and data switching. Optical fiber networks are usually used in high-speed services, which are characterized with high Bit Rate and low Bit Error Rate, and thus can meet the speeding requirements of data transfer. However, the electrical switching technique domains in data switching. This optical-electrical-optical process in switching greatly slows down the network speed and the switch nodes become the choke point of the whole network. This article is to design and realize two kinds of switch systems with high performance, which meet the requirement of high speed data switching. A switch node includes switch fabric, input/output modules & buffer memory strategy and switch control module. Several kinds of switch fabrics, buffer strategies and cell schedule algorithms are studied in this article. One high speed ATM switch system with VOQ as input buffer strategy, DPA schedule algorithm and Crossbar switch fabric, and another high speed ATM switch system with VOQ as input buffer strategy, DPA schedule algorithm and Batcher-Banyan switch fabric are chosen in this article. First, each module of the switch system is built using Verilog language and simulated in Modelsim software until the simulation result is consistent with the aim of the design for each module. Then all modules are combined into one integral system by using one main module. The whole system is also simulated by Modelsim and further modifications/adjustments are need for this system. After achieving a good performance in Modelsim, these two switch systems are synthesized by use of Design Analyzer tool in Synopsys software and they turn out to maintain good performance in later End-Simulation, which verify the reliability of the design of these two ATM switch systems. Moreover, The synthesis result by ISE tool verifies that the design can be integrated on one chip. The author also analyze the performance of these two systems theoretically. Key words: ATM Switch System Cell Switch Verilog iii
Abstract 1.1 1.2 1.3 1.4....1 B-ISDN ATM.1.2.3 2.1 2.2 2.3 2.4......4.....5 B-ISDN.. 6 ATM....7 3.1...8 3.2... 8 3.2.1.. 8 3.2.2......9 3.2.2.1.... 9 3.2.2.2....9 3.2.3. 10 3.2.3.1 crossbar...11 3.2.3.2 RTL......12 3.2.3.3 crossbar.... 12 3.2.3.4 banyan.14 3.2.3.5 Batcher banyan...18 4.1... 26 4.2... 26 4.2.1...26 4.2.2....27 4.3...28 4.3.1.. 28 4.3.1.1.....29 iv
4.3.1.2. 29 4.3.2...31 4.3.2.1..... 33 4.3.2.2...... 34 4.3.2.3 N.. 35 4.4..... 38 4.4.1 38 4.4.1 N. 39 5.1. 44 5.2 DPA. 45 5.2.1 DPA... 45 5.5.2 DPA.... 46 5.3 LDPA.. 49 6.1..50 6.2. 51 6.2.1 crossbar...51 6.2.2 Batcher banyan.53 6.3... 56 6.3.1 RTL..56 6.2.1..58 FPGA 7.1 7.2 FPGA 63...65 8.1.68 8.2.68..70..72 v
Abstract 1.1 60 ISDN(Integrated Service Digital Network) ISDN [1] ISDN ISDN ISDN 80 B-ISDN 1.2 B-ISDN ATM B-ISDN B-ISDN 1988 ATM(Asynchronous Transfer Mode)[2] B-ISDN 1990 ATM [26] ATM 1 ATM 53 5 ; 48 ATM 1-1 2. ATM UNI User--Network Internet 1-2 vi
1 1 1 2 UNI 3. ATM ATM ATM 4 ATM 1.3 40Gb/s[3] 1Gbps[4], [5] 16 16 FPGA ATM Crossbar Batcher banyan N vii
Abstract DPA FPGA 1.4 1 3 1 3 1 2 HDL 3 4 5 6 FPGA ASIC viii
B-ISDN B-ISDN 2.1 B-ISDN / / B-ISDN ATM [6] 1 ATM ATM CE Circuit Emulation) ATM 2 ATM 3 ATM ATM 4 ATM ATM 5 ATM VP(Virtual Path) VC(Virtual Channel) 5 ix
Abstract 2.2 VPI(Virtual Path Identifier) VCI(Virtual Channel Identifier) 2 1 / / [7] 2 1 2 2 SDH Synchronous Digital Hierarchy OAM(Operation And Maintenance) OAM SDH 2 3 UPC(Usage Parameter Control) 2 2 x
2 3 SDH HEC(Header Error Control) ATM VPI VCI B-ISDN / VP/VC 2.3 B-ISDN 1 2 3 xi
Abstract 4 [8] 5 ATM 2.4 ATM ATM LAN(Local Area Network) WAN(Wide Area Network) [9][37] ATM ATM ATM ATM ATM ATM ATM ATM ATM LAN/WAN ATM LAN WAN xii
ATM ATM 3.1 ATM ATM [6] VPI/VCI VPI/VCI VPI/VCI ATM VPI/VCI VPI/VCI ATM 3.2 3.2.1 ATM 3 1 xiii
Abstract 3 1 3.2.2 3.2.2.1 3 2 3 2 / N V NV W W / 2NV W / NV 3.2.2.2 3 3 xiv
3 3 FIFO First In First Out FIFO N N 3.2.3 Crossbar 2 Banyan Crossbar N Banyan Banyan CLOS Benes Crossbar ATM xv
Abstract Crossbar Banyan 3.2.3.1 Crossbar Crossbar (1) Crossbar N N Crossbar N 2 3 4 4 2 2 3 4 i j ( i, j) i j 3 4 4 4 Crossbar xvi
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