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1 RTI - FOR FREE VT ETERNL LOK ENERTOR LPR RTL PIE ETHERNET PIE I/F U Express R PIE I/F MINI-PIE U PIE I/F U0 MINI-PIE PIE I/F M PROEOR HT 00Mhz.T/s x -Pin ufp PU REV,,, TI N - R0 R0 HyperTransport LINK PU I/F 0 IP OUT LV/TVOUT/TM PIE F I/F -Link II-E I/F WITH PIE PP I/F IN,,,, RII 00MT/ RII 00MT/ PEIE I/F RT LV TM V ON UNUFFERE R NER OIMM,0 00-PIN R OIMM UNUFFERE R FR OIMM,0 00-PIN R OIMM TI V - M RT 0,,,,,, LV LV ON 0 HMI TM M M RIII RIII Option Orange for M Option reen for M -LINK II PIE. Lanes.bps/L TI - 00 U FINER PRINT U UONN LUETOOTH in ONNETOR 0 U MER U UONN U UONN U U RT R REER 0 U.0 ( PORT) T II ( PORT) T /00/ Mus.0 PI I/F LP I/F PI.0 INT RT HW MONITOR PI/PI E,,, 0, T././bps UP TO TII T././bps H UIO I/F L H OE FM00 P T H... ONN. T O... ONN. ERPHONE JK MIROPHONE JK PU&R0 HT VLT POWER R0 ORE POWER PU ORE POWER 00 & PIE POWER YTEM MIN POWER LP U RRY MIROPHONE PU MEMORY POWER TTERY HER 0 ENE K ENE IR (NI) IHRE IRUIT P K MOUE PI ROM PI I/F LOK IRM ize ocument Number Rev ustom 0 M- MIRO-TR INT'L O.,LT. ate: Monday, ugust 0, 00 heet of

2 TTERY.V WHr PTOR -V 0W TTERY HRER M +VIN PU core PWM M00 PU core PWM M R PWM LO VTT M PU_V0_RUN PU_V_RUN PU_VN_RUN PU_VIO_U PU_VTT_U +.V M PU_V_RUN V.V PU_V0_RUN V0 ORE V PU_V_RUN V ORE.-.00V PU_VN_RUN VN ORE.-.00V TP E VLT.V TP PU_VIO_U V MEM TP PU_VTT_U VTT_MEM TP PU_VIO_U PU_VTT_U +.V E +.V E +.V E +.V E +V E RII OIMM--YTEM V MEM VTT_MEM 0. RII IE PORT MEMORY V MEM LOK EN.V 0..V 0. H OE.V ORE 0. V NLO 0. UIO OP +VUL +.VUL +.VUL +.V_ +.V PU_VIO_U +.V +.VUL +.VUL +.V W +V~+.V W M +.V W +.V W M +.V W M W OZ +V W +V W +V LO +V LO M WITH WITH WITH WITH LO WITH.V LO.V LO R0 +V_N +.V +.V E VHTT.V 0. +.V Jumper N_V_MU +.V E VHTR.V 0. R0/R0 N_V_MU E VHT.V 0. N_V_MU E VPIE.V 0. +.V +.V E V.V 0. +.V +V_N V.0V-.V +.V V.V V E V.V V +.VUL E V_MEM.V V E V_MEM.V 0. +.V E V.V 0. +.V E VLT V V_LE_L_RUN E VLT 0. +.V E PLLs.V 0. N_V_MU E PLLs./.V 0. +.VLW +VLW 00 +.V E PIE IO 0. +.VUL +.V E PIE PV 0m +VUL +.V E T I/O 0. +.V E T PLL 0.0 V_.V OR.v I/O 0. +V +.V ORE 0. +.VUL.V PW 0. +.VUL +.V.V PW VUL E U I/O 0. +.VUL E U ORE 0. +.V V_ +.V_ MM_EN MM HE +.V +.VUL W MM_V_.V +.V W MM_V_.V +.V W MM_V_.V +.V +V W MM_V_V +VIN W MM_V_MIN PU_V_RUN +.VUL IT ENTHENET +.VUL E.V 0. +.VUL E.V 0. +.VUL E.V 0. +.VUL M00--E Jumper +.VLW.V 0. R0/R0 L PNEL +.V W.V. +V E V 0. K LIHT +V +V V_LE_L_RUN LE_L +VIN +V_MIN U FR +VUL Vual U FR +VUL Vual EPRE R +.V.V (0, ) 0. +.V.V (0, ). +.VUL.V (, ) 0. MINI PIE LOT +.V.V (0, ) 0. +.V IM.V (0, ). +.VUL.V (, ) 0. MINI PIE LOT +.V.V (0, ) 0. +.V.V (0, ). +.VUL.V (, ) 0. MINI PIE LOT +.V.V (0, ) 0. +.V.V (0, ). +.VUL.V (, ) 0. MIRO-TR INT'L O.,LT. POWER ELIVERY HRT ize ocument Number Rev ustom 0 M- ate: Monday, ugust 0, 00 heet of

3 RTI - FOR FREE > m Req. PU_LTTOP# PU_PWROK PU_REET# > m Req. > u Req. > m Req. PU_LKIN outhbridge PWR_OO Northbridge POWEROO m delay running m chipset delay If use Internal lk en N_PWR is asserted by 00 > m Req. ROUP PU_VLT_RUN PU_VN_RUN PU_V_RUN PU_V0_RUN PU_V_P PU_V_RUN V_N_ORE_RUN ROUP +.V +.V +V +.V LP L PU_VTT_U PU_VIO_U from to LP_# PWR_TN#_ RM_RT_L UL RIL V_UL_EN PWR_TN#_HW _OK power button locked out 0m delay VUL/.VUL/.VUL/.VUL Power button pressed not present scenario = LOW present= high stays active if present stays active if present stays active if present stays active if present waiting for power button +.VLW/+VLW +VIN attery inserted/ IN _VT MIRO-TR INT'L O.,LT. POWER EQUENE HRT ize ocument Number Rev ustom 0 M- ate: Monday, ugust 0, 00 heet of

4 PI LK0 MHZ PI LOT0 PI LK MHZ PI LOT NER O-IMM REV O-IMM HTREFLK MHZ N-O.MHZ TI N - R0 TI 00 PI LK MHZ PI LK MHZ UPER IO LK MHZ MINI PI LOT UPER IO ITF K_LK M_LK KEYOR MOUE PIR MEM LK PIR MEM LK THLON PU L PKE PIR PU LK 00MHZ ETERNL LK EN. N PIE LK 00MHZ PIE LK 00MHZ -OIN.MHZ PIE LK 00MHZ PIE LK 00MHZ PIE LK 00MHZ PIE LK 00MHZ TVLKIN TVLKIN -OIN.MHZ PIE F LOT - LNE PIE PP LOT - LNE PIE PP LOT - LNE PI EPRE R - LNE -OIN.MHZ ZLI_ITLK PI LK MHZ PI LK MHZ PI LK MHZ PI LK MHZ LP LOT LP IO EU POT PI LOT ZLI OE PIE LK 00MHZ IIT ETHERNET - LNE MHZ O INPUT PIE LK 00MHZ U LK MHZ M Hz UPER IO LK MHZ.K Hz.MHz MIRO-TR INT'L O.,LT. LOK ITRIUTION ize ocument Number Rev ustom 0 M- ate: Monday, ugust 0, 00 heet of

5 RTI - FOR FREE +VLT U +VLT VLT_0 VLT_ VLT_ VLT_ HT LINK VLT_0 VLT_ VLT_ VLT_ E E E E * If VLT is connected only on one side, one.uf cap should be added to the island side HT_N_PU H0 HT_N_PU L0 HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H0 HT_N_PU L0 HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L E E E F H J K L L L M N N E F F F H H H K K L M M M N P L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L W W V U U U T R Y W V V V U T T HT_PU_N H0 HT_PU_N L0 HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H0 HT_PU_N L0 HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L +VLT.U. 00.U U0 M check list -~- 0.U0 0P0N 0P0N LYOUT: Place bypass cap on topside of board NER HT POWER PIN THT RE NOT ONNETE IRETLY TO OWNTREM HT EVIE, UT ONNETE INTERNLLY TO OTHER HT POWER PIN PLE LOE TO VLT0 POWER PIN HT_N_PU_LK_H0 HT_N_PU_LK_L0 HT_N_PU_LK_H HT_N_PU_LK_L J J J K L0_LKIN_H0 L0_LKIN_L0 L0_LKIN_H L0_LKIN_L L0_LKOUT_H0 L0_LKOUT_L0 L0_LKOUT_H L0_LKOUT_L Y W Y Y HT_PU_N_LK_H0 HT_PU_N_LK_L0 HT_PU_N_LK_H HT_PU_N_LK_L HT_N_PU_TL_H0 HT_N_PU_TL_L0 HT_N_PU_TL_H HT_N_PU_TL_L N P P P L0_TLIN_H0 L0_TLIN_L0 L0_TLIN_H L0_TLIN_L L0_TLOUT_H0 L0_TLOUT_L0 L0_TLOUT_H L0_TLOUT_L R R T R HT_PU_N_TL_H0 HT_PU_N_TL_L0 HT_PU_N_TL_H HT_PU_N_TL_L OKET PIN P N-000-F0 NO TU Only for R0 OKET HT I/F ize ocument Number Rev ustom 0 M- MIRO-TR INT'L O.,LT. ate: Wednesday, ugust, 00 heet of

6 E E To reverse OIMM socket To normal OIMM socket Processor Memory Interface PLE THEM LOE TO PU WITHIN " V_VREF_U_PU LYOUT:PLE LOE TO PU M check list - PLE LOE TO PROEOR WITHIN. INH PLE LOE TO PROEOR WITHIN. INH M- 0 OKET R MEMORY I/F Wednesday, ugust, 00 ize ocument Number Rev ate: heet of MIRO-TR INT'L O.,LT. MEM_M_T MEM_M_T MEM_M_T MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T0 MEM_M_M MEM_M_T MEM_M_T MEM_M_T MEM_M_M0 MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_REET# MEM_M_ MEM_M_T MEM_M_T0 MEM_M_OT0 MEM_M_T MEM_M_ MEM_M_T0 MEM_M_M0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_M MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T0 MEM_M_T MEM_M_M MEM_M_T MEM_M_M MEM_M_ MEM_M_T MEM_M_M MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_OT0 MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_M MEM_M_T MEM_M_T MEM_M_M MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_M MEM_M_T MEM_M_ MEM_M_T MEM_M_T MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T0 MEM_M_M MEM_M_M MEM_M_ MEM_M_T M_ZP MEM_M_T0 MEM_M_T MEM_M_T MEM_M_M MEM_M_T MEM_M_T MEM_M_T MEM_M_M MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_M MEM_M_0 MEM_M_T MEM_M_T MEM_M_T MEM_M_REET# MEM_M_T MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_ MEM_M_T MEM_M_T M_ZN MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_M MEM_M_T MEM_M_T MEM_M_T MEM_M_OT MEM_M_T MEM_M_T MEM_M_T MEM_M_0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_ MEM_M_T MEM_M_ MEM_M_T MEM_M_T N_+0.VTT MEM_M_#0 MEM_M_# MEM_M_LK_P MEM_M_LK_N MEM_M_#0 MEM_M_LK_H MEM_M_LK_L MEM_M_LK_N MEM_M_LK_N MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_NK0,0 MEM_M_Q_P MEM_M_Q_N MEM_M_Q_N MEM_M0_#,0 MEM_M_Q_P MEM_M_T[0..] MEM_M_Q0_N MEM_M_Q_N MEM_M_Q_N MEM_M_NK,0 MEM_M_Q_P MEM_M_Q_N MEM_M_Q_P MEM_M0_OT0,0 MEM_M_Q_P MEM_M_Q0_N MEM_M_KE,0 MEM_M_KE0,0 MEM_M0_OT,0 MEM_M_NK,0 MEM_M_Q_P MEM_M_Q_N MEM_M_LK_P MEM_M_NK,0 MEM_M_WE#,0 MEM_M_Q_P MEM_M_Q0_P MEM_M_LK_P MEM_M_R#,0 MEM_M_Q_N MEM_M_KE,0 MEM_M_#,0 MEM_M_Q_P MEM_M_Q_N MEM_M0_#0,0 MEM_M_Q_N MEM_M_Q_P MEM_M_Q0_P MEM_M0_OT,0 MEM_M_LK_N MEM_M_[0..],0 MEM_M_R#,0 MEM_M_Q_P MEM_M_KE0,0 MEM_M_LK_N MEM_M_Q_N MEM_M_Q_P MEM_M0_OT0,0 MEM_M0_#0,0 MEM_M_LK_N MEM_M_Q_N MEM_M_Q_N MEM_M_LK_N MEM_M_LK_P MEM_M_NK,0 MEM_M_Q_N MEM_M_#,0 MEM_M_Q_P MEM_M_M[0..] MEM_M_WE#,0 MEM_M_LK_P MEM_M_T[0..] MEM_M_NK0,0 MEM_M0_#,0 MEM_M_Q_P MEM_M_Q_N MEM_M_M[0..] MEM_M_Q_P MEM_M_LK_N MEM_M_LK_P MEM_M_LK_P MEM_M_LK_N MEM_M_LK_P MEM_M_LK_P MEM_M_LK_N MEM_M_LK_N MEM_M_[0..],0 PU_VTT_U PU_M_VREF_U PU_VTT_U PU_VIO_U PU_M_VREF_U PU_VIO_U PU_VTT_U TP TP TP 0.P0N TP0 TP TP 000P0 R K_% TP R0.R_% R00.P0N.P0N TP TP TP 000P0 TP TP TP R0.R_% R00 TP 0.P0N TP0 R K_% MEM:T U OKET PIN P N-000-F0 F F E Y F F F F E 0 0 F F F0 E0 E E E E E W Y Y Y W W Y 0 Y0 Y W W Y H H0 E E J H F F0 F E E0 F E H E E H E H H H F E E F E E F F F E Y Y F E E W W Y W 0 H M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_M M_M M_M M_M M_M M_M M_M M_M0 M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H0 M_Q_L0 M_M M_M M_M M_M M_M M_M M_M M_M0 M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H0 M_Q_L0 MEM:M/TRL/LK U OKET PIN P N-000-F W V U V T Y W W U W V U V0 U0 T0 K K V K0 L R K L L M L0 M M N M0 N J R R0 R T T F0 E0 Y0 W P P0 Y E F N N0 R R F F P R J J0 J H J J W L L T K M L N L N N P N P J U R U U U H VTT VTT VTT VTT VTT VTT VTT VTT VTT M_OT M_OT0 M0_OT M0_OT0 M_OT0 M0_OT M0_OT0 RV_M M L0 M0 L M0 L0 M0 L M L M L0 M0 L0 M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_NK M_NK M_NK0 M_R_L M L M_WE_L MEMZP MEMZN VTT_ENE MEMVREF M_LK_H M_LK_L M_LK_H M_LK_L M_LK_H M_LK_L M_LK_H M_LK_L M_LK_H M_LK_L M_LK_H M_LK_L M_LK_H M_LK_L M_LK_H M_LK_L M_KE0 M_KE M_KE0 M_KE M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_NK M_NK M_NK0 M_R_L M L M_WE_L RV_M TP

7 RTI - FOR FREE +V PU_VIO_U maximun 0 ohm M check list - PU_PWR, PU_LT_TOP#, PU_LT_RT# +VU R0 0R L0L000m_0 L00.U. 00 R0 0R V.V ==> Max urrent 0m 00P0 PU_LT_REQ#_PU PU_LERT PU_I PU_I +.VRUN +.VRUN +.VRUN R 00R R K R0 00R R0 00R ap close to thermal sensor PU_THERM 00P0 PU_THERM T_RIT_PU# RN PR-0K RN00_MI T_RIT_PU# M_THRMPU_LK M_THRMPU_T PU_THRM_LERT- PU_LKP 0.U0 JN JN JN JN PU_V_._RUN PU_LKN PWR N_00_ LT_TOP# N_00_ LT_RT# N_00_ N_00_ 00 LYOUT: ROUTE V TRE PPRO. 0 mils WIE (UE x mil TRE TO EIT LL FIEL) N 00 mils LON. PU_LT_REQ# +VU 00P0 00 LMIMMNOP_MOP-RH MOP_T lose to PU socket PU_V_RUN Keep trace from resisor to PU within 0." keep trace from caps to PU within." PWM M_THRMPU_LK M_THRMPU_T PU_LKIN P PU_LKIN N R R_% LT_RT# 00P0 PWR 00 LT_TOP# PU_LT_REQ#_PU If unused, the LERT_L pin is left unconnected PU_I place them to PU within." PU_I PU_LERT TP R.R %R00 PU_HTREF0 +VLT R.R %R00 PU_HTREF U0 V + MLK MT - LERT# T_RIT_# N PU_V0_RUN_F_H PU_V0_RUN_F_L PU_V_RUN_F_H PU_V_RUN_F_L TP TP TP TP TP TP TP PU_RY PU_TM PU_TK PU_TRT# PU_TI PU_TET_TTUP PU_TET_PLLTET0 PU_TET_PLLTET PU_TET_H_YPLK_HE PU_TET_L_YPLK_L E M_THRMPU_LK M_THRMPU_T PU_THRM_LERT-, F F F0 R P F E Y 0 F H0 U V V LKIN_H LKIN_L REET_L PWROK LTTOP_L LTREQ_L F I F I E LERT_L HT_REF0 HT_REF V0_F_H V0_F_L V_F_H V_F_L RY TM TK TRT_L TI TET TET TET TET_H TET_L PU_TET_NEN PU_TET0_NLK TET F PU_TET_NLK TET0 E PU_TET_NHIFTEN TET E PU_TET_NHIFTEN TET PU_TET_INLEHIN TET F TET PU_TET_NLOIN PU_TET_IERKMON TET TET RV RV RV RV RV OKET PIN P N-000-F0 V V VIO_F_H VIO_F_L W W W Y H J H E F PU_V_R PU_V_R PU_THERMTRIP#_.V THERMTRIP_L F PU_PROHOT#_.V PROHOT_L PU_MEMHOT#_.V MEMHOT_L THERM THERM VN_F_H VN_F_L KEY M KEY W RV0 H RV H RV RV RV PU_THERM PU_THERM REQ_L E0 PU_REQ# TO E PU_TO TET_H TET_L TET TET TET TET PU_TET_H_PLLHRZ_P PU_TET_L_PLLHRZ_N PU_TET_P PU_TET_P PU_TET_P PU_TET_P0 PU_TET_H_FLKOUT_P PU_TET_L_FLKOUT_N VIO PU_VN_RUN_F_H PU_TET_NLO_T TET K PU_TET0_NLOOUT TET0 PU_TET_I_T TET TET_H TET_L PU_V_R JN0 PU_V_R JN PWR PU_VIO_U R 00R R0 00R R 00R JN E VR_PROHOT# PWM PU_VIO_U Q Q0 Q MT0 MT0 MT0 OTE_T OTE_T OTE_T E E PU_MEMHOT# 0, PU_PROHOT# PU_THERMTRIP# TP TP0 TP TP TP TP TP TP TP R 0K PU_VIO_U N_00_ PU_TET_H_YPLK_H R PU_TET_INLEHIN R0 PU_TET_NEN R0 PU_TET0_NLK R PU_TET_NLK R PU_TET_NHIFTEN R PU_TET_NHIFTEN R0 PU_TET_P R PU_TET_P0 R PU_TET_PLLTET R0 PU_TET_PLLTET0 R PU_TET_L_YPLK_L R PU_TET_NLOIN R R K PU_PWR_VI_RE PU_PWR Pull up to.vrun OKET TRL M- R 0K TP route as differential TP as short as possible testpoint under package R0 K N_00_ N_00_ R 0K JN R0.K ate: Wednesday, ugust, 00 heet of PU_V PU_V PU_PROHOT#_.V N_00_ PU_VIO_U 0R 00R 00R 00R 00R 00R 00R 00R 00R 00R 00R 0R 0R PWM MIRO-TR INT'L O.,LT. ize ocument Number Rev ustom 0

8 OTTOMIE EOUPLIN PROEOR POWER N ROUN EOUPLIN ETWEEN PROEOR N IMMs PLE LOE TO PROEOR POILE M heck list -~- M check list -~-,- M- 0 OKET PWR & N ustom Wednesday, ugust, 00 ize ocument Number Rev ate: heet of MIRO-TR INT'L O.,LT. PU_V_RUN PU_V0_RUN PU_V_RUN PU_VN_RUN PU_V0_RUN PU_VN_RUN PU_VIO_U PU_VIO_U PU_VIO_U PU_VIO_U PU_VTT_U 0.U N U. 00_ U. 00_.U. 00 0P0N.U. 00 U. 00_.U. 00 U. 00_ 0N U. 00_ 0.U0 000P0 000P0 U. 00_ 000P0 0.U0 0P0N 0.U0 0P0N 0 U. 00_ 0.U0 UF OKET PIN P N-000-F0 E E E E E E E E F F F F F F F F F H H H H J J J J0 J J J J K K K K K K K L L L0 L L L L M M M N N N0 N N P P P P P R R0 R R T T T T T T U U U U0 U U U U V V V V V V V W Y Y N V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V 0P0N 0.U0 0.U0 U. 00_ U. 00_ 0.U0 0.U0 0P0N 0.U0 0N 0P0N 0N 0.U0 0.U0 0.U0 0 0P0N.U. 00 0P0N U. 00_.U. 00 U. 00_ UE OKET PIN P N-000-F0 H J J J K K0 K K L L L L L M M M M0 N N N P P0 R R R R T T T T0 T T U U U U V V V0 V V W Y J K L M P T U V H J K K K K L M M M M N P P P P R T T T T U V V V V Y V_ V_ V0_ V0_ V0_ V0_ V0_ V0_ V0_ V0_ V0_0 V0_ V0_ V0_ V0_ V0_ V0_ V0_ V0_ V0_0 V0_ V0_ V0_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V0_ VN_ V0_ VN_ VN_ VN_ V_ VN_ VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO.U. 00 U. 00_ 000P0.U. 00

9 MEM_VREF_U LYOUT: PLE LOE TO IMMs M- 0 R OIMM / HNNEL ustom Wednesday, ugust, 00 ize ocument Number Rev ate: heet of MIRO-TR INT'L O.,LT. MEM_M_ MEM_M_ MEM_M_NK0 MEM_M_ MEM_M_NK MEM_M_NK MEM_M_M MEM_M_M MEM_M_M0 MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_VREF_U MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_ MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_M MEM_M_M MEM_M_NK0 MEM_M_ MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_NK MEM_M_VREF_U MEM_M_ MEM_M_T MEM_M_T MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_ MEM_M_NK MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_M MEM_M_M0 MEM_M_T MEM_M_T MEM_M_T MEM_M_0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_M MEM_M_ MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_M MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_ MEM_M_T0 MEM_M_M MEM_M_ MEM_M_0 MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_ MEM_M_M MEM_M_T MEM_M_T MEM_M_T MEMHOTIMM0# MEMHOTIMM# MEMHOT_OIMM# MEM_M_M[0..] MEM_M_M[0..] MEM_M_T[0..] MEM_M_T[0..] LK0 0,,, T0 0,,, MEM_M_Q0_N MEM_M_Q0_P MEM_M_Q_N MEM_M_Q_P MEM_M_Q_N MEM_M_Q_N MEM_M_Q_P MEM_M_Q_N MEM_M_Q_P MEM_M_Q_N MEM_M_Q_P MEM_M_Q_N MEM_M_Q_P MEM_M_Q_N MEM_M_Q_P MEM_M_Q_P MEM_M_NK[..0],0 MEM_M_NK[..0],0 MEM_M_WE#,0 MEM_M_#,0 MEM_M_KE0,0 MEM_M_R#,0 MEM_M0_#,0 MEM_M0_#0,0 MEM_M_KE,0 MEM_M0_OT0,0 MEM_M0_OT,0 MEM_M_[0..],0 MEM_M_[0..],0 MEM_M_Q_P T0 0,,, MEM_M_KE0,0 MEM_M_Q_P MEM_M0_OT0,0 MEM_M_Q_P MEM_M_Q_N MEM_M_Q0_P MEM_M_Q_N LK0 0,,, MEM_M_#,0 MEM_M_Q_N MEM_M_WE#,0 MEM_M_Q_P MEM_M_Q0_N MEM_M_R#,0 MEM_M_Q_P MEM_M_Q_P MEM_M0_OT,0 MEM_M_Q_P MEM_M0_#0,0 MEM_M_Q_N MEM_M_Q_N MEM_M_Q_N MEM_M_KE,0 MEM_M_Q_N MEM_M0_#,0 MEM_M_LK_N MEM_M_LK_P MEM_M_LK_P MEM_M_LK_N MEMHOT_OIMM# 0 MEM_M_LK_P MEM_M_LK_P MEM_M_LK_N MEM_M_LK_N +VRUN PU_VIO_U +VRUN PU_VIO_U MEM_M_VREF_U +VRUN PU_VIO_U 000P0 TP R K_% TP0 JN N_00_ O-IMM(RV) J R_OIMM_RV_H=.mm R_OIMM00P H Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q N N N N N/TET M0 M M M M M M M Q0 Q Q Q Q Q Q Q K0 K0 K K KE0 KE VREF R WE 0 0 L Vspd V0 V V V V V V V V V V0 V V0 V V V V V V V V V V0 V V V V V V V V V V V V V V0 V V V V V V V V V0 V V V V V0 V V V V V V V V V /N /N Q0 Q Q Q Q Q Q Q OT0 OT V V V V V V V V V0 V V R K_% R.K TP JN0 N_00_ O-IMM (RV) J R_OIMM_RV_H=.mm R_OIMM00P H Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q N N N N N/TET M0 M M M M M M M Q0 Q Q Q Q Q Q Q K0 K0 K K KE0 KE VREF R WE 0 0 L Vspd V0 V V V V V V V V V V0 V V0 V V V V V V V V V V0 V V V V V V V V V V V V V V0 V V V V V V V V V0 V V V V V0 V V V V V V V V V /N /N Q0 Q Q Q Q Q Q Q OT0 OT V V V V V V V V V0 V V TP hexainf@hotmail.com RTI - FOR FREE

10 Overtemperature Output ssertion efault etting 0 OVERTEMP ENOR O-IMM REION h -bit Overtemperature Output eassertion efault etting Mus ddress 0h -bit 0F-LM0-N0 M- 0 R OIMM TERMINTION ustom 0 Wednesday, ugust, 00 ize ocument Number Rev ate: heet of MIRO-TR INT'L O.,LT. MEM_M_KE0 MEM_M_NK[..0] MEM_M_R# MEM_M_ MEM_M_NK MEM_M_NK[..0] MEM_M_ MEM_M_# MEM_M_ MEM_M0_# MEM_M_NK MEM_M0_# MEM_M_0 MEM_M_ MEM_M0_OT0 MEM_M_NK0 MEM_M_ MEM_M_ MEM_M_WE# MEM_M_NK MEM_M_KE MEM_M_WE# MEM_M0_#0 MEM_M_KE MEM_M0_OT MEM_M0_OT MEM_M_[0..] MEM_M_# MEM_M_KE MEM_M_# MEM_M_NK MEM_M_R# MEM_M_# MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_NK MEM_M0_OT0 MEM_M_ MEM_M_NK0 MEM_M0_OT0 MEM_M0_OT MEM_M_ MEM_M_ MEM_M_ MEM_M0_#0 MEM_M_ MEM_M0_# MEM_M_ MEM_M_ MEM_M_ MEM_M_NK MEM_M_0 MEM_M_ MEM_M0_#0 MEM_M0_OT MEM_M_0 MEM_M_ MEM_M_KE0 MEM_M_ MEM_M_ MEM_M_WE# MEM_M_ MEM_M_ MEM_M_R# MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M0_# MEM_M_ MEM_M_KE0 MEM_M_ MEM_M_NK0 MEM_M_ MEM_M_ MEM_M_ MEM_M_KE MEM_M_NK MEM_M0_OT0 MEM_M_ MEM_M_ MEM_M_NK MEM_M_NK0 MEM_M_ MEM_M0_#0 MEM_M_0 MEM_M_KE0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_R# MEM_M_ MEM_M_ MEM_M_ MEM_M_[0..] MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_WE# MEM_M_ MEM_M_KE0, MEM_M_[0..], MEM_M_KE, MEM_M0_#, MEM_M_#, MEM_M_WE#, MEM_M0_#0, MEM_M_NK[..0], MEM_M_R#, MEM_M_KE0, MEM_M_R#, MEM_M0_OT, MEM_M0_OT0, MEM_M0_OT, MEM_M_#, MEM_M0_OT0, MEM_M_NK[..0], MEM_M_WE#, MEM_M0_#0, MEM_M_KE, MEM_M0_#, PU_MEMHOT#, MEMHOT_OIMM# T0,,, LK0,,, MEM_M_[0..], +VRUN +VRUN +VRUN +VRUN PU_VIO_U PU_VIO_U PU_VTT_U PU_VIO_U PU_VIO_U PU_VIO_U PU_VIO_U PU_VIO_U PU_VIO_U PU_VIO_U PU_VIO_U PU_VIO_U PU_VTT_U PU_VIO_U PU_VIO_U PU_VIO_U PU_VIO_U PU_VIO_U RN PR-R RN00_MI R00 0K RN0 PR-R RN00_MI 0 R 0K RN PR-R RN00_MI RN PR-R RN00_MI JN N_00_ RN PR-R RN00_MI Q MT0 OTE_T E U LM OI 0F-0000-N0 0 L N V O. RN PR-R RN00_MI R 0K RN PR-R RN00_MI RN PR-R RN00_MI RN PR-R RN00_MI RN PR-R RN00_MI R 0K RN PR-R RN00_MI 0 RN PR-R RN00_MI RN PR-R RN00_MI R0 0K R 0K RN PR-R RN00_MI RN PR-R RN00_MI 0 RN PR-R RN00_MI R 0K U.Y Q N-N00 OT_T 0 Q N-N00 OT_T R R <V

11 U HT_PU_N H0 Y HT_R0P HT_T0P HT_N_PU H0 HT_PU_N L0 Y HT_R0N PRT OF HT_T0N HT_N_PU L0 HT_PU_N H V HT_RP HT_TP E HT_N_PU H HT_PU_N L V HT_RN HT_TN E HT_N_PU L HT_PU_N H V HT_RP HT_TP F HT_N_PU H HT_PU_N L V HT_RN HT_TN F HT_N_PU L HT_PU_N H U HT_RP HT_TP F HT_N_PU H HT_PU_N L U HT_RN HT_TN F HT_N_PU L HT_PU_N H T HT_RP HT_TP H HT_N_PU H HT_PU_N L T HT_RN HT_TN H HT_N_PU L HT_PU_N H P HT_RP HT_TP J HT_N_PU H HT_PU_N L P HT_RN HT_TN J HT_N_PU L HT_PU_N H P HT_RP HT_TP K HT_N_PU H HT_PU_N L P HT_RN HT_TN K HT_N_PU L HT_PU_N H N HT_RP HT_TP K HT_N_PU H HT_PU_N L N HT_RN HT_TN K HT_N_PU L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H0 HT_PU_N L0 HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N_LK_H0 HT_PU_N_LK_L0 HT_PU_N_LK_H HT_PU_N_LK_L HT_PU_N_TL_H0 HT_PU_N_TL_L0 HT_PU_N_TL_H HT_PU_N_TL_L R.K_% HT_RLP HT_RLN Y Y W W0 V V0 U0 U U U T T M M R R0 HT_RP HT_RN HT_RP HT_RN HT_R0P HT_R0N HT_RP HT_RN HT_RP HT_RN HT_RP HT_RN HT_RP HT_RN HT_RP HT_RN HT_RLK0P HT_RLK0N HT_RLKP HT_RLKN HT_RTL0P HT_RTL0N HT_RTLP HT_RTLN HT_RLP HT_RLN HYPER TRNPORT PU I/F HT_TP HT_TN HT_TP HT_TN HT_T0P HT_T0N HT_TP HT_TN HT_TP HT_TN HT_TP HT_TN HT_TP HT_TN HT_TP HT_TN HT_TLK0P HT_TLK0N HT_TLKP HT_TLKN HT_TTL0P HT_TTL0N HT_TTLP HT_TTLN HT_TLP HT_TLN F 0 H J0 J J K L J M L M P P M H H L L0 M M P R M ( NKF ) F_MR_TET 0-R00-0 HT_TLP HT_TLN R R0M=0R R0=.K.K_% HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H0 HT_N_PU L0 HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU_LK_H0 HT_N_PU_LK_L0 HT_N_PU_LK_H HT_N_PU_LK_L HT_N_PU_TL_H0 HT_N_PU_TL_L0 HT_N_PU_TL_H HT_N_PU_TL_L hexainf@hotmail.com RTI - FOR FREE MIRO-TR INT'L O.,LT. R/R0 HT LINK I/F ize ocument Number Rev 0 M- ate: Wednesday, ugust, 00 heet of

12 lose M_HMI_TM_PP M_HMI_TP_PN M_HMI_TM_PP M_HMI_TP_PN M_HMI_T0M_PP M_HMI_T0P_PN M_HMI_TM_P0P M_HMI_TP_P0N R0 R 0R R 0R R 0R R 0R R 0R R 0R R 0R R 0R R0M lose to R0 HMI_TP HMI_TN HMI_TP HMI_TN HMI_T0P HMI_T0N HMI_LKP HMI_LKN PIE_N_R0P PIE_N_R0N PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_R0P PIE_N_R0N PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_EPR_N_RP PIE_EPR_N_RN PIE_PE_N_RP PIE_PE_N_RN PIE_PE_N_RP PIE_PE_N_RN PIE_LN_N_RP PIE_LN_N_RN PIE N_R0P PIE N_R0N PIE N_RP PIE N_RN PIE N_RP PIE N_RN PIE N_RP PIE N_RN E F H H J J J J L L M L P M P M R P R R P P T T E E V W U U U U Y Y W Y U F_R0P F_R0N F_RP F_RN F_RP F_RN F_RP F_RN F_RP F_RN F_RP F_RN F_RP F_RN F_RP F_RN F_RP F_RN F_RP F_RN F_R0P F_R0N F_RP F_RN F_RP F_RN F_RP F_RN F_RP F_RN F_RP F_RN PP_R0P PP_R0N PP_RP PP_RN PP_RP PP_RN PP_RP PP_RN PP_RP PP_RN PP_RP PP_RN _R0P _R0N _RP _RN _RP _RN _RP _RN PRT OF PIE I/F F PIE I/F PP PIE I/F M ( NKF ) F_MR_TET 0-R00-0 R R R R 0R 0R 0R 0R F_T0P_ F_T0P F_T0N_ F_T0N F_TP_ F_TP F_TN_ F_TN F_TP_ F_TP F_TN_ F_TN F_TP_ F_TP F_TN_ F_TN F_TP_ F_TP E F_TN_ F_TN E F F_TP_ F_TP F F_TN_ F_TN F F_TP_ F_TP F F_TN_ F_TN H F_TP_ F_TP H F_TN_ F_TN H F_TP_ F_TP H F_TN_ F_TN J F_TP_ F_TP J F_TN_ F_TN K F_T0P_ F_T0P K F_T0N_ F_T0N K F_TP_ F_TP K F_TN_ F_TN M F_TP_ F_TP M F_TN_ F_TN M F_TP_ F_TP M F_TN_ F_TN N F_TP_ F_TP N F_TN_ F_TN P F_TP_ F_TP P F_TN_ F_TN PP_T0P PP_T0N PP_TP PP_TN PP_TP PP_TN PP_TP PP_TN PP_TP PP_TN PP_TP PP_TN _T0P _T0N _TP _TN _TP _TN _TP _TN PE_LRP(PE_LRP) PE_LRN(PE_LRN) PP_T0P_ PP_T0N_ PP_TP_ PP_TN_ PP_TP_ PP_TN_ Y PP_TP_ Y PP_TN_ Y Y V V E E _T0P T0N TP TN TP TN TP_ E _TN_ PE_LRP R PE_LRN R R R R R 0R 0R 0R 0R K_% K_% +.VRUN R0 PIE_N_T0P PIE_N_T0N PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_T0P PIE_N_T0N PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_EPR_TP PIE_N_EPR_TN PIE_N_PE_TP PIE_N_PE_TN PIE_N_PE_TP PIE_N_PE_TN PIE_N_LN_TP PIE_N_LN_TN PIE_N T0P PIE_N T0N PIE_N TP PIE_N TN PIE_N TP PIE_N TN PIE_N TP PIE_N TN PIE Expressard MiniPIE LN -Link R/R0 PI-E LINK&PP ize ocument Number Rev 0 M- MIRO-TR INT'L O.,LT. ate: Wednesday, ugust, 00 heet of

13 RTI - FOR FREE,,,,,,, _RT# R0/R0/R0 difference table N_PWR IN LLOW_LTTOP OUT(default)/IN LT_TOP# IN(default)/IN R0.V IN O R0.V IN.V IN.V IN R0.V IN O/.V IN *.V IN/O * *, LM mode: N send LT_TOP#, LLOW_LTTOP will become input, PU_LT_TOP# V_N PU_LT_REQ# LLOW_LTTOP R0.K V_N R0M=.V, PU_LT_RT# R0 +.VRUN +.VRUN R P_R0.K N_I_LK N_I_T O 0R R0 R0.V,R0.V R0M L 00L00m L00 L 00L00m L00 R0M.U.Y 00 P_R0 PU = Optionally connected to TRP EPROM R0M N_TV_ TP TP 0R termination < inch trace TP R 0R % R0M R K_% R K_% for R0 P_R0 NI for R0M R0 R0M R0M R NHT_LKP Q.K NHT_LKN N-FV0N OT_T N_LT_TOP# N_REFLK_N N_O +.VRUN R0R % R0R % R 0R NF_LKP R0 Referenceesign=.K NF_LKN +.VRUN V_N R0M P_R0 page NPP_LKP R0M R0M NPP_LKN Q R N-FV0N.K LINK_LKP OT_T N_LLOW_LTTOP LINK_LKN R 0R 0 N_I_LK.V 0 N_I_T R 0R N_0LK R0.V N_0T R0=.V +VRUN V_N +.VRUN R 0R R00 0.U.Y 00 R 0R R00 R0M R 0R R0 +.VRUN V_N V_N R 0K TRP_T N_RT#_IN 0 N_R 0 N_ 0 N_ L 00L00m L00 L 00L00m L00 R.K,0 N_HYN#,0 N_VYN# 0 _L 0 _T.U.Y 00 +VRUN TRP_T R0.V Pull up Optionally connected to TRP EPROM L 00L00m L00 +.VRUN L 00L00m L00 +.VRUN +.VRUN L 00L00m L00.U.Y 00 R0.U.Y 00.V Pull up (onnected to TRP EPROM or PWM ckt) N_V.U.Y 00 VI.U.Y 00 VQ.U.Y 00 R 0R % R0 0R % N_PWR TP TP R0M RR_% _RET PLLV PLLV VHTPLL VPIEPLL N_RT#_IN N_LT_TOP# N_LLOW_LTTOP TRP_T TP TP U F V(N) E V(N) F VI(N) VI(N) H VQ(N) H VQ(N) E F F F E H E 0 0 T T U U V V 0 R0M FT_PIO[..0] _Pr(FT_PIO) Y(FT_PIO) OMP_Pb(FT_PIO) RE(FT_PIO0) REb(N) E REEN(FT_PIO) F REENb(N) E LUE(FT_PIO) F LUEb(N) _HYN(PWM_PIO) _VYN(PWM_PIO) _L(PE_RLRN) _(PE_TLRN) _RET(PWM_PIO) PLLV(N) PLLV(N) PLLV(N) VHTPLL VPIEPLL VPIEPLL YREETb POWEROO LTTOPb LLOW_LTTOP HT_REFLKP HT_REFLKN R0.V,R0.V E REFLK_P/OIN(OIN) F REFLK_N(PWM_PIO) F_REFLKP F_REFLKN PP_REFLKP PP_REFLKN M ( NKF ) F_MR_TET 0-R00-0 PRT OF RT/TVOUT LOKs PM PLL PWR PP_REFLKP(_REFLKP) PP_REFLKN(_REFLKN) I_LK I_T _LK0/U0P(N) _T0/U0N(N) _LK/UP(N) _T/UN(N) TRP_T RV U_L(N) LVTM MI. TOUT_L0P(N) TOUT_L0N(N) TOUT_LP(N) TOUT_LN(N) TOUT_LP(N) 0 TOUT_LN(_PIO0) 0 TOUT_LP(N) TOUT_LN(_PIO) TOUT_U0P(N) TOUT_U0N(N) TOUT_UP(PIE_REET_PIO) TOUT_UN(PIE_REET_PIO) TOUT_UP(N) 0 TOUT_UN(N) TOUT_UP(PIE_REET_PIO) TOUT_UN(N) TLK_LP(_PIO) TLK_LN(_PIO) TLK_UP(PIE_REET_PIO) TLK_UN(PIE_REET_PIO) VLTP(N) VLTP(N) VLT_(N) VLT_(N) VLT_(N) VLT_(N) VLT(V) VLT(V) VLT(V) VLT(V) VLT(V) 0 VLT(V) E0 VLT(V) LV_ION(PE_TLRP) LV_LON(PE_RLRP) LV_EN_L(PWM_PIO) E F TM_HP(N) HP(N) 0 U_TT#(PWM_PIO) THERMLIOE_P THERMLIOE_N E _PIO NI for R,R0 P_R0 R.K_% TET_EN TETMOE EU_OUT0 EU_OUT EU_OUT EU_OUT EU_OUT EU_OUT EU_OUT EU_OUT R.K_% P_R0 for R0 R0 R0M R0.K_% TP TP TP TP TP0 TP VLTP VLT R 0R.U.Y 00.U. 00 R0/R0/R0 EU PIN MPPIN R0 RE(FT_PIO0) REEN(FT_PIO) Y(FT_PIO) LUE(FT_PIO) TOUT_LN(_PIO0) TLK_LP(_PIO) TOUT_LN(_PIO) TLK_LN(_PIO) OM_Pb(FT_PIO) _Pr(FT_PIO) N_LV_T_L0P 0 N_LV_T_L0N 0 N_LV_T_LP 0 N_LV_T_LN 0 N_LV_T_LP 0 N_LV_T_LN 0 N_LV_T_LKLP 0 N_LV_T_LKLN 0 L 00L00m L00 L N_LV_ION 0 N_LV_LON 0 TP HP, U_TT# U_TT#_R LV_EN_L R0 LV_ION LV_LON TM_HP 0L L00_ +.VRUN +.VRUN R0M LV_EN_L LV_LON TM_HP UN UP HP R0 LV_ION U_L MIRO-TR INT'L O.,LT. R/R0 YTEM I/F ize ocument Number Rev ustom 0 M- ate: Wednesday, ugust, 00 heet of

14 +.V VPIE +.V N VQ IOPLLV N +.V VPIE R0 V +.V +.V PLLV N +.V.V(R0;R0) +.V V_MEM +.V PIN NME +.V V_MEM +.V R0 N +.V +.V +.V +.V +.V VI +.V PLLV VHTPLL +.V +.V R0 +.V +.V +.V +.V +.V VHT +.V +.V +.V +.V +.V N +.V +.V/.V VHTT N +.V +.V VLT V N PIN NME R0 +.V N +.V +.V N +.V +.V R0 +.V IOPLLV V N +.V V.V(R0;R0) N +.V N R0 N +.V.V VLT VHTR N +.V/.V N R0/R0/R0 POWER IFFERENE TLE VLTP N VPIEPLL N +.V +.V N +.V +.V +.V +.V.V power for side-port memory or VO interface Isolated power for side-port memory or VO interface R0 VN=.V N_V_MU=>+.VRUN R0 VN.V ERRT R0-00,FI.V(R0;R0) R0M heck the Orange in this page M whether NI or ommon M- 0 R/R0 POWER & N ustom Wednesday, ugust, 00 ize ocument Number Rev ate: heet of MIRO-TR INT'L O.,LT. V_MEM VHTT N_MEM VPIE VHT_ VHTR N_V +.VRUN +.VRUN +.VRUN +.VRUN +.VRUN +.VRUN +.VRUN +VRUN V_N 0 L 0LL00_ L 0LL00_.U. 00 L 0LL00_ L 0LL00_ L 0LL00_.U. 00.U. 00 0U. 00.U. 00.U PRT / ROUN UF M ( NKF ) F_MR_TET 0-R00-0 E H J L L L L M0 N P0 R R R R U V W W W Y E E J K M L L M N P P R R T U U U V W W Y E0 E H J R L L L L K M N P R R R V U V V W W W W W Y E E E H0 J VHT VHT VHT VHT VHT VHT VHT VHT VHT VHT0 VHT VHT VHT VHT VHT VHT VHT VHT VHT VHT VHT VHT VHT VHT VHT VHT V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V VPIE VPIE VPIE VPIE VPIE VPIE VPIE VPIE VPIE VPIE0 VPIE VPIE VPIE VPIE VPIE V VPIE VPIE VPIE VPIE VPIE0 VPIE VPIE VPIE VPIE VPIE VPIE VPIE VPIE VPIE VPIE0 VPIE VPIE VPIE VPIE VPIE VPIE VPIE VPIE VPIE VPIE0 V VHT0 V V U.Y R 0R U.Y U.Y PRT / POWER UE M ( NKF ) F_MR_TET 0-R00-0 J K L M P R T E Y0 W V H F0 E F E J0 P0 K0 Y E W H E F H J M0 L0 K J U M J K K M L L M M N N P P P R R T T U T H H E0 Y T0 J L R0 P R T V U U0 U T R P M VHT_ VHT_ VHT_ VHT_ VHT_ VHT_ VHT_ VHTT_ VHTT_ VHTT_ VHTT_ VHTT_ VHTT_ VHTT_ VHTT_ VHTR_ VHTR_ VHTR_ VHTR_ VHTR_ V_ V_ V_MEM(N) V_MEM(N) VPIE_ VPIE_ VPIE_ VPIE_0 VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ V_ V_ V_ VPIE_ V_ V_ VPIE_0 V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_(N) V_(N) V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) VPIE_ V_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VHTR_ VHTR_ VHTT_ VHTT_0 VHTT_ VHTT_ VHTT_ 0 U.Y 0 0U. 00.U. 00 R 0R

15 RTI - FOR FREE E V E E Y E W Y V V W E U MEM_0(N) MEM_(N) MEM_(N) MEM_(N) MEM_(N) MEM_(N) MEM_(N) MEM_(N) MEM_(N) MEM_(N) MEM_0(N) MEM_(N) MEM_(N) MEM_(N) MEM_0(N) MEM_(N) MEM_(N) _MEM/VO_I/F MEM_Rb(N) MEM_b(N) MEM_WEb(N) MEM_b(N) MEM_KE(N) MEM_OT(N) MEM_KP(N) MEM_KN(N) MEM_OMPP(N) MEM_OMPN(N) PR OF M ( NKF ) F_MR_TET 0-R00-0 MEM_Q0/VO_VYN(N) MEM_Q/VO_HYN(N) MEM_Q/VO_E(N) MEM_Q/VO_0(N) MEM_Q(N) MEM_Q/VO_(N) MEM_Q/VO_(N) MEM_Q/VO_(N) MEM_Q/VO_(N) MEM_Q/VO_(N) MEM_Q0/VO_(N) MEM_Q/VO_(N) MEM_Q(N) MEM_Q/VO_(N) MEM_Q/VO_0(N) MEM_Q/VO_(N) MEM_Q0P/VO_IKP(N) MEM_Q0N/VO_IKN(N) MEM_QP(N) MEM_QN(N) MEM_M0(N) MEM_M/VO_(N) 0 Y V Y 0 E 0 Y W 0 E W E IOPLLV IOPLLV(N) E IOPLLV IOPLLV(N) E IOPLLV(N) MEM_VREF(N) EMEN_VREF heck the Orange in this page M whether NI or ommon please make a provision for tying to their power rails R 0R R 0R R 0R +.VRUN +.VRUN +.VRUN R0M 0W IOE_O U_TT#_R _RT#,,,,,,, R0/R0/R0: LO_EEPROM_TRP elects Loading of TRP from EPROM : ypass the loading of EEPROM straps and use Hardware efault Values 0 : I Master can load strap values from EEPROM if connected, or use default values if not connected R0: pin FT_PIO R0: pin U_TT# R0/R0/R0: TRP_IE-PORT MEMORY ENLE Enables ide port memory : isable (R0/R0) 0 : Enable (R0/R0) R0: pin HYN R0: Not pplicable,0 N_VYN# N_TV_ R0M R0 R R0 K K P_R0 TRP_EU_U_PIO_ENLEb Enables the Test ebug us using PIO. : Enable (R0, R0) 0 : isable (R0, R0) PIN: R0-->N_TV_ (pin FT_PIO) ; R0--> VYN# (pin VYN),0 N_HYN# R0M R0 K R0 K +VRUN R0: FT_PIO[:]: TRP_PIE_PP_F[:0] These pin straps are used to configure PI-E PP mode. 000 : : : 00 0 : : : 000 : 00 FT_PIO0: TRP_EU_U_PIE_ENLEb R0: TRP_PIE_PP_F[:0] (Pins:R0_FT_PIO[:]) : Mode L default 0: Mode L 0: Mode 00: Mode K 0: Mode E 00: Mode L 00: Mode 000: Mode R0: TRP_PIE_PP_F[:0] (configurable thru register settings only) Mode L default Mode L Mode Mode K Mode E Mode L Mode Mode Enables Test debug bus over PIE bus (pplicable to R0 & R0 Only). isable (can be enabled thru nbcfg register) 0 : Enable R0: pin FT_PIO0 R0: configurable thru register setting only FT_PIO0: TRP_EU_U_PIE_ENLEb R0: Enables the Test ebug us using PIE bus : isable ( an still be enabled using nbcfg register access ) 0 : Enable R0/R0: Enables ide port memory ( R0 use HYN#). isable (R0) Enable (R0) 0 : Enable (R0) isable(r0) R/R0-VO ize ocument Number Rev ustom 0 M- MIRO-TR INT'L O.,LT. ate: Wednesday, ugust, 00 heet of

16 <V +VRUN L LK_V 00L00m L00 U. 00_ 0 U.Y - PLE LL ERIL TERMINTION REITOR LOE TO U - PUT EOUPLIN P LOE TO U POWER PIN +VRUN U Place within 0." of LKEN R R +VRUN L 00L00m L00 L 00L00m L00 L 00L00m L00 VREF V Parallel Resonance rystal P0N,,,,,,, _RT# U. 00_ Y.MHz T P0N LK_V,0,, LK0,0,, T0 R M LK_V LK_V R R.K 0W IOE_O LK_V VREF V I O.K RETORE# V N 0 VREF NREF V VTI VPU VHTT V_R VR VT VR N NTI NTI NPU NHTT NT N_R 0 NR NR P# MLK MT RETORE# N I ( ILPRKLFT ) QFN_ I-R00-I0 OVER LOK PUK0T_LPR 0 PUK0_LPR PUKT_LPR PUK_LPR TI0T_LPR TI0_LPR TIT_LPR TI_LPR TIT_LPR TI_LPR TIT_LPR 0 TI_LPR _R0T_LPR _R0_LPR _RT_LPR _R_LPR R0T_LPR R0_LPR 0 RT_LPR R_LPR RT_LPR R_LPR RT_LPR R_LPR RT_LPR R_LPR O_/RT_LPR O_0/R_LPR RT/TT_LPR R/T_LPR 0 HTT0T_LPR/M HTT0_LPR/M MHz_0 EL_O/MHz_ REF0/EL_HTT REF/EL_T REF PU_LKP_R PU_LKN_R NF_LKP_R NF_LKN_R F_LKP_R F_LKN_R PIE_PE_LKP_R PIE_PE_LKN_R R0 R0 R0 R0 0R R 0R R 0R R 0R JN N_00_ JN N_00_ NPP_LKP_R R 0R NPP_LKN_R R 0R PIE_EPR_LKP_R JN N_00_ PIE_EPR_LKN_R JN N_00_ PIE_PE_LKP_R PIE_PE_LKN_R NLINK_LKP_R JN JN JN N_00_ N_00_ N_00_ NLINK_LKN_R JN N_00_ PIE_LN_LKP_R JN0 N_00_ PIE_LN_LKN_R JN N_00_ FQ_L0 JN N_00_ FQ_L JN N_00_ R_LKP_R JN N_00_ R_LKN_R JN N_00_ NHTREF_LKP_R NHTREF_LKN_R M_U_R ELO EL_HT EL_T N_O_R R R R 0K R 0K R R O_M_N.V R/R R.R_%.V 00R/00R Pin, ynamic Over locking pin: real time frequency selection 0: Normal; : Frequency will transition to a preprogrammed value in the Ic. JN JN JN JN N_00_ N_00_ N_00_ N_00_ LK_V PU_LKP PU_LKN NF_LKP NF_LKN F_LKP F_LKN PIE_PE_LKP PIE_PE_LKN NPP_LKP NPP_LKN PIE_EPR_LKP PIE_EPR_LKN PIE_PE_LKP PIE_PE_LKN LINK_LKP LINK_LKN PIE_LN_LKP PIE_LN_LKN FREQ_L0 FREQ_L R_LKP R_LKN NHT_LKP NHT_LKN LK_M_U +VRUN N_O N LOK INPUT TLE N LOK HT_REFLKP HT_REFLKN REFLK_P REFLK_N F_REFLK PP_REFLK lock chip has internal serial terminations for differencial pairs, external resistors are reserved for debug purpose. M E(INLE EN) 00M IFF N 00M IFF M E (.V) N 00M IFF N R0 PP_REFLK 00M IFF R0 M E (.V) N 00M IFF 00M IFF 00M IFF * R0 can be used as clock buffer to output two PIE referecence clocks y deault, chip will configured as input mode, IO can program it to output mode. EMI 0/ E P0N PU_LKP E P0N PU_LKN E P0N LK_M_U E P0N PIE_LN_LKP_R E P0N PIE_LN_LKN_R EL_HTT 0* * EL_T 0 * default MHz.V single ended HTT clock 00 MHz differential HTT clock 00 MHz non-spreading differential R clock 00 MHz spreading differential R clock R0 00M IFF 00M IFF M E (.V) vref 00M IFF(IN/OUT)* N or 00M IFF OUTPUT 00M IFF when driven low _R clocks slow to reduced setpoint only supported with custom I EL_T EL_HT R.K R0.K R.K MIRO-TR INT'L O.,LT. LOK ENERTOR ize ocument Number Rev ustom 0 M- ate: Wednesday, ugust, 00 heet of

17 RTI - FOR FREE <V PLE THEE PIE OUPLIN P LOE TO U00 +.VRUN U which one need connect to LN_RT _.V RT#,,,,,,, _RT# R R N _RT# _R0P_ PIE N_R0P V 0 _R0N_ PIE_T0P PIE N_R0N V _RP_ PIE_T0N PIE N_RP V _RN_ PIE_TP PIE N_RN V _RP_ PIE_TN PIE N_RP U _RN_ PIE_TP PIE N_RN U _RP_ PIE_TN PIE N_RP T _RN_ PIE_TP PIE N_RN T PIE_TN PIE_N T0P PIE_N T0N PIE_N TP PIE_N TN PIE_N TP PIE_N TN PIE_N TP PIE_N TN 0 N 0 LOE TO U00 L 0L L00_ PIE_VR 0U. 00 R R U.Y R_LKP R_LKN U PIE_R0P U PIE_R0N U PIE_RP V PIE_RN R0 PIE_RP R PIE_RN R PIE_RP R _% PIE_RN _PE_P T _PE_N PIE_LRP T.0k_% PIE_LRN PIEPV P PIE_PV P N N L J J0 PIE_PV 00 Part of PI EPRE INTERFE PIE_RLKP/N_LNK_LKP PIE_RLKN/N_LNK_LKN K N_IP_LKP K N_IP_LKN M N_HT_LKP M N_HT_LKN P PU_HT_LKP M PU_HT_LKN M LT_F_LKP M LT_F_LKN J PP_LK0P J PP_LK0N L0 PP_LKP L PP_LKN M PP_LKP M0 PP_LKN N PP_LKP P PP_LKN M_M_M_O M_ M_ LOK ENERTOR PI LK PI INTERFE PILK0 P PILK P PILK P PILK P PILK T PILK/PIO T PIRT# E0# E# E# E# FRME# EVEL# IRY# TRY# PR TOP# PERR# ERR# REQ0# REQ# REQ# REQ#/PIO0 REQ#/PIO NT0# NT# NT# NT#/PIO NT#/PIO LKRUN# LOK# N 0 U P V T V U V V T W 0 T 0 0 INTE#/PIO INTF#/PIO INT#/PIO INTH#/PIO R R R U U Y W V Y Y Y Y W U Y W Y U W W V E PI_LK0_R R0 PI_LK_R R PI_LK_R R PI_RT# R PI_ PI_ PI_ PI_ PI_ PI_ PI_REQ#0 PI_REQ# PI_REQ# PI_REQ# PI_REQ# E E PILKRUN# R V E E R PI_LK0 R PI_LK PI_LK PI_LK R PI_LK PI_LK, PI_ PI_ PI_ PI_ PI_ PI_ 0R R TP TP TP TP TP TP0 PI_LK PI_LK PI_LK PI_LK PI_LK PI_LK0 E P0N PI_LKRUN# E P0N E P0N POWER EPRE UPPORT PE_PIO0 MM REET PI LK ==>rray Mic E P0N E P0N PE_PIO MM POWER ENLE PE_PIO MOE WITH(Y N) PI_REQ#0 R.K PI_REQ# R.K PI_REQ# R.K PI_REQ# R.K PI_REQ# R.K TM_HP0 MM HOT PLU RTV E0 P0N H: Enable H: Enable H:MM L:N +VRUN R0 0M R00 R Y.KHz xtalp_ma0 P0N 0M R00 PLE THEE OMPONENT LOE TO 00, N UE ROUN UR FOR K_ N K_ P0N LLOW_LTTOP PU_PROHOT# PU_PWR, PU_LT_TOP#, PU_LT_RT# R 0K K_ K_ +VRUN +.VRUN R 0K PU_PROHOT# PU.v EUE FOR FN ONTROL. OTHERWIE, PU TO VIO. RT TL F LLOW_LTTP F PROHOT# F LT_P LT_TP# LT_RT# PU M ( ELF ) F LP RT LPLK0 LPLK L0 L L L LFRME# LRQ0# E H H J J H H LRQ#/NT#/PIO MREQ#/REQ#/PIO ERIRQ V RTLK INTRUER_LERT# VT LP_K0 R0 LP_K R INTRUER_LERT# RTV U.Y R R LP_LK0 LP_LK L0 L L L LFRME# LRQ#0 ERIRQ RT_LK INTRUER_LERT# R M 0 -T P_T RTV +VLW R 0R U.Y RTV N H#_white-.pitch-RH _0 N MIRO-TR INT'L O.,LT. 00 PIE/PI/PU/LP ize ocument Number Rev ustom 0 M- ate: Wednesday, ugust, 00 heet of

18 <V U +VRUN R R R +VU R R.K.K.K.K.K U_TT# LK0 T0 LK T JT MPPIN: TK = PM TI = PM TO = PM TM = TET RT# = PM0 PIE_WKE#, LP_# LP_# _PWRON# _PWR U_TT# K0M#_ KRT#_ KI# LP_MI# PIE_LKEN, PIE_WKE_UP# PU_THERMTRIP# W_PWR RMRT# / Justin _EPOP# PKR,0,, LK0,0,, T0, LK, T, PU_THRM_LERT- JN N_00_ JN N_00_ LP# LP# _TET _TET _TET0 E E H F H H K H H H Y W K K F J H F J W 0W IOE_O PU_MEMHOT#_IN,0 PU_MEMHOT# U_O#/IR_T/EVENT# U_O#/IR_T0/PM# U_O#/IR_R0/PM# U_O#/IR_R/PM# E 0 U_O#/PM# F P0N R U_O#/PM# E 0R U_O0#/PM0#, Z_IT_LK M ZTOUT Z_ITLK, Z_T_OUT M Z_T_IN0 R Z_OUT J Z_T_IN R Z_IN0/PIO J R Z_IN/PIO L R Z_IN/PIO M ZYN, Z_YN Z_IN/PIO L ZRT# Z_YN,,, Z_RT# M R Z_RT# L R Z_OK_RT#/PM# H H0 H F E E PI_PME#/EVENT# RI#/ETEVNT0# LP_/PM# LP_# LP_# PWR_TN# PWR_OO U_TT# TET TET TET0 0IN/EVENT0# KRT#/EVENT# LP_PME#/EVENT# LP_MI#/ETEVNT# _TTE/EVENT# Y_REET#/PM# WKE#/EVENT# LINK/PM# MLERT#/THRMTRIP#/EVENT# N_PWR RMRT# M ( ELF ) F H UIO U O INTERTE u 00 PI / WKE UP EVENT E T_I0#/PIO0 LK_REQ#/T_I#/PIO MRTVOLT/T_I#/PIO W LK_REQ0#/T_I#/PIO0 V LK_REQ#/T_I#/FNOUT/PIO W0 LK_REQ#/T_I#/FNIN/PIO0 W PKR/PIO L0/PO0# W 0/PO# K L/PO# K /PO# 0 _L/PIO Y _/PIO LL#/PIO Y HUTOWN#/PIO R_RT#/EVENT# IM_PIO0 IM_PIO PI_#/IM_PIO IE_RT#/F_RT#/IM_PO IM_PIO IM_PIO IM_PIO IM_PIO INTERTE u U MI PIO U. U.0 Part of ULK/M_M_M_O LK_M_U U_ROMP U_ROMP R.K_% U_FP U_FN U_FP U_FN U_HP U_HN U_H0P U_H0N U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_H0P U_H0N E E F E H J0 E F 0 0 H E E H H IM_PIO IM_PIO IM_PWM0/IM_PIO0 F L/IM_PIO /IM_PIO F L_LV/IM_PIO E0 _LV/IM_PIO E IM_PWM/IM_PIO E IM_PWM/IM_PO IM_PWM/IM_PO E IM_PIO IM_PIO IM_PIO0 IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO0 IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO0 IM_PIO UP 0 UN 0 UP UN UP UN UP UN UP UN UP UN UP UN UP UN UP UN UP0 UN0 P P TRP pin to define use LP or PI ROM ardreader luetooth Expressard onnector onnector onnector FingerPrint Webamera MiniPIE MiniPIE _TET _TET0 _TET TET Pins TET0 TET control data input TET TET control mode TET Reserve TET input TET TET TET0 TET Mode escription None Normal operation 0 0 Reserved Reserved for I debug 0 x Test Mode Enalbe Test Mode x x Reserved Reserved for I debug 00 _TET0,_TET,_TET has internal 0K P. R.K R 0K +VU R.K R 0K R0.K R 0K MIRO-TR INT'L O.,LT. 00 PI/PIO/U/UIO ize ocument Number Rev ustom 0 M- ate: Wednesday, ugust, 00 heet of

19 RTI - FOR FREE PLE T OUPLIN P LOE TO 00 U T_T0+_ T_T0-_ T_R0-_ T_R0+_ T_T+_ T_T-_ T_R-_ T_R+_ O H +.VRUN +VRUN T_T0+_ T_T0-_ T_R0-_ T_R0+_ T_T+_ T_T-_ T_R-_ T_R+_ R 0M_% Y MHz O 0P0N L 0R_00m 0N T_T0+ 0N T_T0-0N T_R0-0 0N T_R0+ 0N T_T+ 0N T_T- 0N T_R- 0N T_R+ R 0P0N PLLV_T L00 U.Y K_% TLV_T NOTE: T_L T_ T_ T_T# PLLV_T TLV_T E 0 0 E0 0 E E E E E E V Y W W PLE T_L RE VERY LOE TO LL OF U00 T_T0P T_T0N T_R0N T_R0P T_TP T_TN T_RN T_RP T_TP T_TN T_RN T_RP T_TP T_TN T_RN T_RP T_TP T_TN T_RN T_RP T_TP T_TN T_RN T_RP T_L T_ T_ T_T#/PIO PLLV_T TLV_T M ( ELF ) F T PWR ERIL T 00 Part of HW MONITOR PI ROM T /00/ IE_IORY IE_IRQ IE_0 IE_ IE_ IE_K# IE_RQ IE_IOR# IE_IOW# IE_# IE_# IE_0/PIO IE_/PIO IE_/PIO IE_/PIO IE_/PIO IE_/PIO0 IE_/PIO IE_/PIO IE_/PIO IE_/PIO IE_0/PIO IE_/PIO IE_/PIO IE_/PIO IE_/PIO IE_/PIO0 PI_I/PIO PI_O/PIO PI_LK/PIO PI_HOL#/PIO PI_#/PIO LN_RT#/PIO ROM_RT#/PIO FNOUT0/PIO FNOUT/PIO FNOUT/PIO FNIN0/PIO0 FNIN/PIO FNIN/PIO TEMP_OMM TEMPIN0/PIO TEMPIN/PIO TEMPIN/PIO TEMPIN/TLERT#/PIO VIN0/PIO VIN/PIO VIN/PIO VIN/PIO VIN/PIO VIN/PIO VIN/PIO VIN/PIO0 V V Y Y Y Y E E0 0 E 0 0 E E F F U J M M M P P R F LN_RT 0 TP TP TP TP TP TP TP0 TP TP TP TP0 TP TP TP TP TP _V HWM_N L0 L00.U.Y 00 JN N_00_ 0R_00m +VU L 0R_00m L00 0 U.Y LN_RT,,,,,,, _RT# R 0R R0 0R R0 PIE_RT 00 T/IE/HWM/PI ize ocument Number Rev 0 M- MIRO-TR INT'L O.,LT. ate: Wednesday, ugust, 00 heet of

20 PLE LL THE EOUPLIN P ON THI HEET LOE TO POILE. ERRT P_00 +.VRUN +.VU +VRUN +.VRUN +.VRUN +VU L U. 00_ U.Y L 0L L00_ L U.Y U. U.Y 00_ 0LL00_ 0LL00_ 0 U. 00_ U.Y 0 U.Y +VRUN U.Y U.Y V_ Y0 +.V : FLH MEMORY MOE(EFULT) +.V : IE MOE E Please make a provision for tying to +.V_0 U.Y 0 U.Y 0 U.Y U.Y VK_.V L 00L00m L00 0.U.Y 00 V_T 0 U.Y U.Y 0U. 00 PIE_VR 0U. 00 V_U E U L VQ_ M VQ_ T VQ_ U VQ_ U VQ_ U VQ_ V VQ_ W VQ_ Y VQ_ VQ_0 VQ_ VQ_ V V V V P PIE_VR_ P PIE_VR_ P0 PIE_VR_ P PIE_VR_ R PIE_VR_ R PIE_VR_ R PIE_VR_ V_T_ V_T_ V_T_ V_T_ V_T_ V_T_ V_T_ VT_0 VT_ VT_ VT_ VT_ E VT_ F VR_0 F VR_ F VR_ VR_ VR_ VR_ 00 Part of PI/PIO I/O IE/FLH I/O -LINK I/O T I/O PLL LKEN I/O ORE.V_ I/O ORE 0 POWER U I/O M ( ELF ) F V_ V_ V_ V_ V_ V_ V_ L M M N P P R V_ R V_ T KV_.V_ KV_.V_ L L KV_.V_ L KV_.V_ L _.V.V.V.V_ J _.V_ J _.V_ L _.V_ L _.V.V_ U_PHY_.V_ U_PHY_.V_ V_VREF VK_.V VK_.V V 0 0 E J K E 0 U.Y +.V_KV +.VU +.VU UY 00 U.Y R 0R R00 0 U. U.Y 00_ V_VREF U.Y VK_.V VK_.V +.V_V _V U.Y 0 U.Y +.V_V +VU 0 U. 00_ R K 0W IOE_O R 0R R00 +VU +VRUN +VRUN H J J K M M M P UE T0 V_T_ U0 V_T_ U V_T_ U V_T_ V V_T_ V V_T_ W V_T_ Y V_T_ Y V_T_ Y V_T_0 Y V_T_ V_T_ V_T_ V_T_ V_T_ V_T_ V_T_ V_T_ V_T_ E V_T_0 V_U_ V_U_ V_U_ V_U_ V_U_ V_U_ V_U_ V_U_ V_U_ E V_U_0 F V_U_ F V_U_ V_U_ H V_U_ H V_U_ J V_U_ J V_U_ J V_U_ J V_U_ J V_U_0 K0 V_U_ K V_U_ K V_U_ K V_U_ 00 ROUN M ( ELF ) F V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 F0 H K K K L L L0 L L L L M M0 M M M N N N P P P0 P P V_ P V_ R V_ R V_ R V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 PIE_K_V_ PIE_K_V_ PIE_K_V_ PIE_K_V_ R R0 R R T T T U U V Y E E PIE_K_V_ P PIE_K_V_0 R PIE_K_V_ R T U U0 V PIE_K_V_ PIE_K_V_ PIE_K_V_ PIE_K_V_ V0 PIE_K_V_ PIE_K_V_ V PIE_K_V_ PIE_K_V_ W PIE_K_V_ PIE_K_V_ W PIE_K_V_ PIE_K_V_0 W PIE_K_V_ PIE_K_V_ W F V VK L Part of +.VRUN L 0L L00_ +.V_KV.U.Y 00 L 00L00m L00 U.Y U.Y 0 0U VU L 00L00mL00 VK_.V U. 00_ 0 U.Y U.Y 0.U.Y POWER & N ize ocument Number Rev ustom 0 M- MIRO-TR INT'L O.,LT. ate: Wednesday, ugust, 00 heet 0 of

21 RTI - FOR FREE <V NOTE: 00 H INTERNL K PULL UP REITOR FOR RT_LK +VRUN +VRUN +VRUN +VRUN +VU +VU +VU +VU +VU +VU R 0K R 0K R 0K R 0K R 0K R 0K R 0K R 0K R0.K R.K PI_LK PI_LK PI_LK, PI_LK LP_LK0 LP_LK RT_LK,,, Z_RT# P P REQUIRE TRP R 0K R 0K R.K R 0K R 0K R 0K R.K R 0K R.K R.K PI_LK PI_LK PI_LK PI_LK LP_LK0 LP_LK RT_LK Z_RT P P PULL HIH PULL LOW OOTFIL TIMER ENLE OOTFIL TIMER ILE EFULT UE EU TRP INORE EU TRP EFULT REERVE REERVE ENLE PI MEM OOT ILE PI MEM OOT EFULT LKEN ENLE LKEN ILE EFULT INTERNL RT EFULT ET. RT (P on, apply KHz to RT_LK) E ENLE E ILE EFULT H,H = Reserved L,H = LP ROM (EFULT) H,L = PI ROM L,L = FWH ROM EU TRP 00 H K INTERNL PU FOR PI_[:] +VRUN +VRUN +VRUN +VRUN +VRUN +VRUN R0 0K R0 0K R00 0K R0 0K R 0K R 0K PI_ PI_ PI_ PI_ PI_ PI_ R.K R.K R.K R.K R.K R.K Use.K P. PI_ PI_ PI_ PI_ PI_ PI_ PULL HIH UE LON REET EFULT UE PI PLL EFULT UE PI LK EFULT UE IE PLL EFULT UE EFULT PIE TRP EFULT REERVE PULL LOW UE HORT REET YP PI PLL YP PI LK YP IE PLL UE EEPROM PIE TRP 00 TRP ize ocument Number Rev ustom 0 M- MIRO-TR INT'L O.,LT. ate: Wednesday, ugust, 00 heet of

22 R0 U PIE_N_T0P PIE_N_T0N 0 PIE_R0P PIE_R0N PRT OF PIE_T0P PIE_T0N PIE_TP0 PIE_TN0 PIE_N_R0P PIE_N_R0N PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN PIE_N_TP PIE_N_TN 0 0 W0 W W V V V0 U U0 P0 P P N PIE_RP PIE_RN PIE_RP PIE_RN PIE_RP PIE_RN PIE_RP PIE_RN PIE_RP PIE_RN PIE_RP PIE_RN PIE_RP PIE_RN PIE_RP PIE_RN PIE_RP PIE_RN P I - E P R E I N T E R F E PIE_TP PIE_TN PIE_TP PIE_TN PIE_TP PIE_TN PIE_TP PIE_TN PIE_TP PIE_TN PIE_TP PIE_TN PIE_TP PIE_TN PIE_TP PIE_TN PIE_TP PIE_TN Y Y Y Y V V V V T T T T P P P P PIE_TP PIE_TN PIE_TP PIE_TN PIE_TP PIE_TN PIE_TP PIE_TN PIE_TP PIE_TN PIE_TP PIE_TN PIE_TP PIE_TN PIE_TP PIE_TN PIE_TP PIE_TN 0 0 PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_RP PIE_N_RN PIE_N_T0P PIE_N_T0N N N0 PIE_R0P PIE_R0N PIE_T0P PIE_T0N M M PIE_TP0 PIE_TN0 0 PIE_N_R0P PIE_N_R0N PIE_N_TP PIE_N_TN M M0 PIE_RP PIE_RN PIE_TP PIE_TN M M PIE_TP PIE_TN 0 0 PIE_N_RP PIE_N_RN PIE_N_TP PIE_N_TN K0 K PIE_RP PIE_RN PIE_TP PIE_TN L L PIE_TP PIE_TN 0 PIE_N_RP PIE_N_RN PIE_N_TP PIE_N_TN K J PIE_RP PIE_RN PIE_TP PIE_TN L L PIE_TP PIE_TN PIE_N_RP PIE_N_RN PIE_N_TP PIE_N_TN J J0 PIE_RP PIE_RN PIE_TP PIE_TN J J PIE_TP PIE_TN PIE_N_RP PIE_N_RN PIE_N_TP PIE_N_TN H H0 PIE_RP PIE_RN PIE_TP PIE_TN PIE_TP PIE_TN PIE_N_RP PIE_N_RN F_LKP F_LKN PIE_RT 0 lock PIE_REFLKP PIE_REFLKN M U N_MLK N_MT PERT M- 0-00M0-0 alibration PIE_LRN PIE_LRP N_ N_ F E E H0 V_PE_N V_PE_P R0 K_% R0.K_% PIE_V M PI-E LINK ize ocument Number Rev 0 M- MIRO-TR INT'L O.,LT. ate: Wednesday, ugust, 00 heet of

23 RTI - FOR FREE R0 PIO THERML_INT Thermal monitor interrupt. PIO THERML_INT is used for I temperature control. It is connected to the LERTb signal of the thermal monitor which measures the temperature of the I. If the I temperature falls outside a defined range, the LERTb signal is asserted. Low level on PIO THERML_INT causes M/M to generate an interrupt (the polarity of this interrupt is programmable the default is active low). oftware can then activate the implemented temperature control scheme. ack ias () control: When PIO EN = 0V then back bias is disabled on the P (ie PP=V and N=V). When IO EN =.V then back bias is enabled on the P. an function as a PIO if not required for control. PIO ROM IO_ROM_EN Enable external IO ROM device 0 - isable external IO ROM device - Enable external IO ROM device VLI.)Transport stream data valid input or general purpose I/O Note: an be left unconnected if not used..)this signals is also used for video capture and as an initialization pin strap..)internal use only. Other logic must not affect this signal during REET. PYN V_I(Internal pulldown) V isable determines whether or not the card will be recognized as the system's V controller (via the UL field in the PI configuration space). 0 V ontroller capacity enabled The device will not be recognized as the system s V controller Power ontrol signals control the core voltage regulator.,0 M_LV_LON t Reset, these signals will be inputs with weak internal pull-down resistors. VIO can define these signals to be either.v outputs or open drain outputs. The output state (high/low) of these signals is programmable for each PowerPlay state..v PIO LKREQ RIVE LOW URIN REET VREF VOLTE IVIER I R0 (VREF = VR,(.V) / =.V) R_% R R_% THE PIN WITH TET POINT RE REQUIRE TO E EILE FOR EU N OUNRY N PURPOE UIN TET POINT VI IF UNUE OR OMPONENT P ENURE EU_E TRP I LO EILE EE ONFI TRPPIN PE E TO TI EU PORT I MNTORY ON INITIL PROTOTYPE EIN PIO0_PW EN R 0K PIO R K PLE VREF IVIER N P LOE TO I VPT0 VPT VPT VPT TP TP R 0R R R M Y MHz O P0N M_VREF VLI PYN TP TP TP TP TP TP0 TP0 TP0 TP0 TP0 TP0 TP0 TP0 TP0 TP0 TP TP00 TP TP TP TP TP PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 00K PIO PIO0_PW_0 TP TP TP TP TP TP TP PLL_PV PIE_PV MPV PLL_V M_TLIN M_TETEN M_LON R 00K P0N M_TLOUT R K L K VPT0 Y VPT Y VPT Y VPT VPT VPT VPT VPT VPT VPT VPT0 VPT VPT VPT F VPT VPT H VPT VPT H VPT H VPT U J TM_P0P J TP_P0N L T0M_PP K T0P_PN K L E K L V V W W J J J K K Y V V V U U T T T T R R R P P N N P P P P V N Y M M H E J J0 H TM_PP TP_PN TM_PP TP_PN VLI PYN_NEW VPNTL_MVP_0 VPNTL_MVP_ VPNTL_0 VPNTL_ VPNTL_ VPLK VPT_0 VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_0 VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_0 VPT_ VPT_ VPT_ PIO_0 PIO_ PIO_ PIO_ PIO_ PIO_ PIO_ PIO LON M- 0-00M0-0 PRT OF INTERTE TM/P PORT ET TM VO ENERL PURPOE I/O PIO ROMO PIO ROMI PIO_0_ROMK PIO_ PIO_ PIO_ PIO HP PIO PWRNTL0 PIO IN PIO THERML_INT PIO HP PIO TF PIO_0_PWRNTL PIO EN PIO ROM PIO LKREQ PIO JMOE PIO TI M PIO TK M PIO TM L PIO TO Y EN_ Y EN_ V EN_ H EN HP EN_E VREF H PLL_PV PLL_PV PIE_PV MPV MPV PLL_V TLIN TLOUT TETEN PLLTET PLL & TL TET / RT (TV/RT) ERIL UE T_P_UN F LK_P_UP THERML TM_P0P TP_P0N T0M_PP T0P_PN TM_PP TP_PN TM_PP TP_PN P_PV P_PV P_PV P_PV P_VR_ P_VR_ K L J J0 L0 K0 L K L K E F J J P_VR_ K P_VR_ L P_VR_ P_VR_ P_VR_ P_VR_ P_VR_ L K J H H P_VR_ J P_VR_ F P_VR_ P_VR_ J P_VR_ H P_LR HP L K K K0 J L H J J L K J J J E F H H F J H F H M_HMI_TM_P0P M_HMI_TP_P0N M_HMI_T0M_PP M_HMI_T0P_PN M_HMI_TM_PP M_HMI_TP_PN M_HMI_TM_PP M_HMI_TP_PN TPV P_VR P_VR JN0 R 0R % JN JN JN M_HYN#,0 M_VYN#,0 M_RET M_V VI M_HYN# M_VYN# V VQ VI VI E RET M_RET R R_% L T LK T LK R L R K L K HYN VYN RET V VQ VI VI R L R K L K Y OMP VYN HYN V VQ VQ VI T_P_UN LK_P_UP T_FO E E M_THERM PLU E M_THERM MINU N_00_ N_00_ N_00_ N_00_ M_T 0 M_LK 0 M_T 0 M_LK 0 M_T M_LK R R_% HMI WITH Mx I Mx INTLL Mx TRP REITOR TRPPIN N O NOT INTLL Mx TRP REITOR PLE OR REITOR LOE TO I RT LV HMI HP,.V.V V M_R 0 M_ 0 M_ 0 OPTIONL 0 OHM TRP TO ROUN FOR R,, N R,, EE _R N _R HEET IF HOT PLU ETET I NOT REQUIRE REMOVE LL THI LOI EEPT FOR 00K PULL OWN RT ap close to thermal sensor +VU M_THERM U V MLK 00P0 + MT M_THERM - LERT# T_RIT_M# T_RIT_# N +VU LMIMMNOP_MOP-RH MOP_T RN PR-0K RN00_MI lose to M.V TO V LEVEL HIFT LOI REQUIRE IF, UE ON Mx OR,, UE ON Mx, RE V TOLERNT ON Mx M I/O M- ate: Wednesday, ugust, 00 heet of M_THRMM_LK M M_THRMM_T M_THRM_LERT- M_THRM_LERT- T_RIT_M# M_THRM_LERT- M_THRMM_T M_THRMM_LK MIRO-TR INT'L O.,LT. ize ocument Number Rev ustom 0