W79E825_824_823A_822A_SC6.PDF

Transcription

1 8- W79E825/824/823A/822A (RoHS) Flash EPROM I/O (UART) CPU ALU (ACC) B (PSW) RAM MANAGEMENT SC6

2 (POR) / / 0& NVM (UART) (KBI) I/O

3 RC CPU (PWM) ADC I2C SIO I2C : , I2ADDR , I2DAT , I2CON I2C, I2CLK , I2STATUS I2C GC ICP( ) FLASH CONFIG CONFIG DC/ADC / DC ADC DC AC SC6

4 32. AC pin SOP pin DIP pin SOP

5 1. W79E82X 51 (ICP) Flash EPROM W79E82X K/8K/4K/2K Flash EPROM 256/128 NVM Flash EPROM 256/128 RAM I/O / 4 10 AD 4 10 PWM 2 1 I2C W79E82X FLASH EPROM W79E82X (ICE) JTAG 2.? 8 CMOS 51 20MHZ VDD=4.5V~5.5V 20MHZ VDD=2.7V~ 5.5V 12MHz? 16K/8K/4K/2K (ICP) Flash EPROM (AP Flash EPROM)? 256/128 RAM? 256/128 NVM FLASH EPROM? MCS-51? JTAG? I/O? /? 13 4?? 4 I/O TTL/?? 4 10 PWM? 4 10 ADC? 1 I2C ( / )? 8??? LED (20mA)?? : JTAG ICE( ) ICP ( )? Lead Free (RoHS) DIP 20: W79E825ADG Lead Free (RoHS) SOP 20: W79E825ASG Lead Free (RoHS) DIP 20: W79E824ADG SC6

6 Lead Free (RoHS) SOP 20: W79E824ASG Lead Free (RoHS) DIP 20: W79E823ADG Lead Free (RoHS) SOP 20: W79E823ASG Lead Free (RoHS) DIP 20: W79E822ADG Lead Free (RoHS) SOP 20: W79E822ASG (RoHS) PART NO. EPROM FLASH SIZE RAM NVM FLASH EPROM ADC PWM PACKAGE REMARK W79E825ADG 16KB 256B 256B 4x10Bit 4x10Bit DIP-20 Pin W79E825ASG 16KB 256B 256B 4x10Bit 4x10Bit SOP-20 Pin W79E824ADG 8KB 256B 256B 4x10Bit 4x10Bit DIP-20 Pin W79E824ASG 8KB 256B 256B 4x10Bit 4x10Bit SOP-20 Pin W79E823ADG 4KB 128B 128B 4x10Bit 4x10Bit DIP-20 Pin W79E823ASG 4KB 128B 128B 4x10Bit 4x10Bit SOP-20 Pin W79E822ADG 2KB 128B 128B 4x10Bit 4x10Bit DIP-20 Pin W79E822ASG 2KB 128B 128B 4x10Bit 4x10Bit SOP-20 Pin - 6 -

7 4. 20 PIN DIP PWM3/CMP2/P P0.1/CIN2B/PWM0 PWM2/P P0.2/CIN2A/BRAKE PWM1/P P0.3/CIN1B/AD0 RST/P P0.4/CIN1A/AD1 VSS 5 16 P0.5/CMPREF/AD2 XTAL1/P VDD XTAL2/CLKOUT/P P0.6/CMP1/AD3 INT1/P P0.7/T1 SDA/INT0/P P1.0/TXD SCL/T0/P P1.1/RXD 20 PIN SOP PWM3/CMP2/P P0.1/CIN2B/PWM0 PWM2/P P0.2/CIN2A/BRAKE PWM1/P P0.3/CIN1B/AD0 RST/P P0.4/CIN1A/AD1 VSS 5 16 P0.5/CMPREF/AD2 XTAL1/P VDD XTAL2/CLKOUT/P P0.6/CMP1/AD3 INT1/P P0.7/T1 SDA/INT0/P P1.0/TXD SCL/T0/P P1.1/RXD SC6

8 5. R ST (P1.5) XTAL1(P2.1) XTAL2(P2.0) VSS P I 2 I/O 1: I/O I/O 2: XTAL1 I/O VDD P P0.0?P0.7 P1.0?P1.7 I/O P0.3~P0.6 ADC I/O P1.2(SCL) P1.3(SDA) P1.5 P: I O I/O - 8 -

9 6. W79E82X K/8K/4K/2K Flash EPROM, 256/128 RAM, 256/128 NVM FLASH EPROM I/O / 4 10 AD 4 10 PWM 1 I2C 1 FLASH EPROM ICP 6.1 Flash EPROM W79E82X 16K/8K/4K/2K ICP 16K/8K/4K/2K Flash EPROM ICP / IC 6.2 I/O W79E82X I/O I/O 18 I/O PxM1.y PxM I/O I/O I/O 6.3 (UART) W79E82X 8052 W79E82X 6.4 W79E82X W79E82X SC6

10 W79E82X MCU 16 (DPTR) AUXR1 DPS W79E82X CPU 6.8 CPU W79E82X ALU W79E82X ALU ALU W79E82X MCU ALU ALU ACC B ALU (PSW) (ACC) W79E82X MCU (ACC) CPU B B 8 / B

11 6.8.4 (PSW) PSW 8 ALU RAM W79E82X 256/128 RAM W79E82X 8- RAM RAM SC6

12 7. W79E82X W79E82X 16K/8K/4K/2K MOVC 7.2 W79E82X 256/128 NVM MOVC A,@A+DPTR NVMADDR, NVMDAT NVMCON FFFFH FCFFH FC00H FBFFH Unused Code Memory 256 Bytes NVM Data Memory Unused Code Memory Page 3 64 bytes Page 2 64 bytes Page 1 64 bytes Page 0 64 bytes FCFFH FCC0H FCBFH FC80H FC7FH FC40H FC3FH FC00H NVM Data Memory Area Unused Data Memory FFFFH 4000H 3FFFH 0000H 16K/8K Bytes On-Chip Code Memory On-Chip Code Memory Space CONFIG 2 CONFIG H External Data Memory Space W79E825/W79E824 Memory Map

13 FFFFH FFFFH Unused Code Memory FC7FH FC00H 128 Bytes NVM Data Memory Unused Code Memory Page 1 64 bytes Page 0 64 bytes FC7FH FC40H FC3FH FC00H NVM Data Memory area Unused Data Memory 1000H 0FFFH 0000H 4K/2K/1K Bytes On-Chip Code Memory On-Chip Code Memory Space CONFIG 2 CONFIG H External Data Memory Space W79E823/W79E822/W79E821 Memory Map 7.3 W79E82X 256/128 RAM ( ) SFR RAM SC6

14 W79E825/W79E824 RAM and SFR Memory Map FFH 80H 7FH 00H Unused Indirect RAM Direct & Indirect RAM Addressing SFR Direct Addressing Only RAM and SFR Data Memory Space W79E823/W79E822 RAM and SFR Memory Map RAM 256/

15 FFH 80H 7FH Indirect RAM Direct RAM 30H 2FH 7F 7E 7D 7C 7B 7A EH DH 6F 6E 6D 6C 6B 6A CH BH 5F 5E 5D 5C 5B 5A AH H 4F 4E 4D 4C 4B 4A H H 3F 3E 3D 3C 3B 3A H H 2F 2E 2D 2C 2B 2A H H 1F 1E 1D 1C 1B 1A H H 0F 0E 0D 0C 0B 0A H 1FH 18H 17H 10H 0FH 08H 07H 00H Bank 3 Bank 2 Bank 1 Bank SC6

16 R0 R1 R2 R3 R4 R5 R6 R7 PSW RS0 RS1 R0 R1 7.5 RAM 20h 2Fh RAM (SP) RAM 07h SP SP 1 SP

17 8. W79E82X MCU ( ) 80H-FFH 0 8 W79E82X W79E82X 1 F8 IP1 F0 B P0IDS IP1H E8 IE1 E0 ACC ADCCON ADCH D8 WDCON PWMPL PWM0L PWM1L PWMCON1 PWM2L PWM3L PWMCON2 D0 PSW PWMPH PWM0H PWM1H PWM2H PWM3H PWMCON3 C8 NVMCON NVMDAT C0 I2CON I2ADDR NVMADDR TA B8 IP0 SADEN I2DATA I2STATUS I2CLK I2TIMER B0 P0M1 P0M2 P1M1 P1M2 P2M1 P2M2 IP0H A8 IE SADDR CMP1 CMP2 A0 P2 KBI AUXR1 98 SCON SBUF 90 P1 DIVM 88 TCON TMOD TL0 TL1 TH0 TH1 CKCON 80 P0 SP DPL DPH PCON 1 2 W79E82X SC6

18 0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 0 I/O : P0 : 80h SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 : SP : 81h RAM DPL.7 DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 16 : DPL : 82h DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 16 : DPH : 83h SMOD SMOD0 BOF POR GF1 GF0 PD IDL : PCON : 87h

19 7 SMOD SMOD0 5 BOF 4 POR 0: SCON.7 FE 1: SCON SCON.7. 0: 1: 0: 1: 3 GF1 2 GF0 1 PD 1 0 IDL 1 CPU TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 : TCON : 88h TF1 0 6 TR1 1 5 TF TR0 0 3 IE1 1 int 1 1 IE IT IE0 0 INT0 1 IE0 0 0 IT SC6

20 GATE C/ T M1 M0 GATE C/ T M1 M0 : TMOD : 89h 7 GATE 1, / TRx int n TRx int n 1 / 0 TRx 6 C/ T / 0 1 TX 5 M1 4 M0 3 GATE 1, / TRx int n TRx int n 1 / 0 TRx 2 C/ T / 0 1 TX 1 M1 0 M0 M1, M0: : M1 M : : : 8 THx 1 1 3: T0 TL0 0 8 / TH0 1 8 / 1 0 TL0.7-0: 0 TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0 : TL0 : 8Ah

21 1 TL1.7-0: 1 TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0 : TL1 : 8Bh 0 TH0.7-0: 0 TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 : TH0 : 8Ch 1 TH1.7-0: 1 TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 : TH1 : 8Dh T1M T0M : CKCON : 8Eh 7~5 4 T1M 3 T0M 2~0 1 0: 1 1/12 1: 1 1/4 0 : 0: 0 1/12 1: 0 1/ SC6

22 1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 : P1 : 90h P1.7?0 / P1.7 PWM2 6 P1.6 PWM 1 5 P1.5 RST 4 P1.4 INT1 3 P1.3 INT0 I 2 C SDA 2 P1.2 0 I 2 C SCL 1 P1.1 RXD 0 P1.0 TXD DIVM.7 DIVM.6 DIVM.5 DIVM.4 DIVM.3 DIVM.2 DIVM.1 DIVM.0 : DIVM : 95h DIVM uc SM0/FE SM1 SM2 REN TB8 RB8 TI RI : SCON : 98h

23 7 SM0/FE 6 SM1 5 SM2 0 0 PCON SMOD0 SM0 1 SM0 SM SM2 1 RB8 0 RI 1 SM2 1 RI 0 SM REN 1 3 TB RB8 1 TI 0 RI SM2=0 RB SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0 : SBUF : 99h 7~0 SBUF P2.1 P2.0 : P2 : A0h SC6

24 7~2-1 P2.1 XTAL2 CLK 0 P2.0 XTAL1. KBI.7 KBI.6 KBI.5 KBI.4 KBI.3 KBI.2 KBI.1 KBI.0 : KBI : A1h 7 KBI.7 1: P KBI.6 1: P KBI.5 1: P KBI.4 1: P KBI.3 1: P KBI.2 1: P KBI.1 1: P KBI.0 1: P KBF BOD BOI LPBOV SRST ADCEN 0 DPS : AUXR1 : A2h

25 7 KBF 6 BOD 5 BOI 4 LPBOV 3 SRST 2 ADCEN DPS : 1: 0. : 0:. 1:. : 0:. 1:. : 0: BOD 1: BOD MCU BOD RC (2MHz~0.5MHZ) 1/16 : 1: 0: ADC. 1: ADC. Dual 0: 8051 DPTR. 1: DPTR1 EA EADC EBO ES ET1 EX1 ET0 EX0 : IE : A8h SC6

26 7 EA. /. 6 EADC ADC. 5 EBO. 4 ES. 3 ET EX ET EX0 0. SADDR.7 SADDR.6 SADDR.5 SADDR.4 SADDR.3 SADDR.2 SADDR.1 SADDR.0 : SADDR : A9h 7 SADDR SADDR CE1 CP1 CN1 OE1 CO1 CMF1 : CMP1 : Ach

27 CE1 4 CP1 3 CN1 2 OE1 1 CO1 0 CMF1 : 0: 1: CE1 1 10uS : 0: CIN1A 1: CIN1B : 0: CMPREF 1: Vref : 1: (CE1 = 1) CMP1 CPU : CPU (CE1 = 0) : CO1 MCU (CE1 = 0) CE2 CP2 CN2 OE2 CO2 CMF2 : CMP2 : ADh SC6

28 CE2 4 CP2 3 CN2 2 OE2 1 CO2 0 CMF2 : 0: 1: CE2 1 10uS : 0: CIN2A 1: CIN2B : 0: CMPREF 1: Vref : 1: (CE2 = 1) CMP2 CPU : CPU (CE2 = 0) : CO2 MCU (CE2 = 0) P0M1.7 P0M1.6 P0M1.5 P0M1.4 P0M1.3 P0M1.2 P0M1.1 P0M1.0 : P0M1 : B1h 1 1 P0M2.7 P0M2.6 P0M2.5 P0M2.4 P0M2.3 P0M2.2 P0M2.1 P0M2.0 : P0M2 : B2h P1M1.7 P1M1.6 - P1M P1M1.1 P1M1.0 : P1M1 : B3h

29 P1M2.7 P1M2.6 - P1M P1M2.1 P1M2.0 : P1M2 : B4h 2 2 P2S P1S P0S ENCLK T1OE T0OE P2M1.1 P2M1.0 : P2M1 : B5h P2M2.1 P2M2.0 : P2M2 : B6h 7 P2S =1: 2 6 P1S =1: 1 5 P0S =1: 0 4 ENCLK =1: RC XTAL2 (P2.0) 3 T1OE =1: 1 P0.7 P T0OE =1: 0 P1.2 P P2M1.1 P2.1 0 P2M1.0 P2.0 PXM1.Y PXM2.Y ( ) SC6

30 - PADCH PBOH PSH PT1H PX1H PT0H PX0H : IP0H : B7h 7-6 PADCH 1: ADC 5 PBOH 1: 4 PSH 1: 0 3 PT1H 1: 1 2 PX1H 1: 1 1 PT0H 1: 0 0 PX0H 1: PADC PBO PS PT1 PX1 PT0 PX0 : IP0 : B8h PADC 1: ADC. 5 PBO 1:. 4 PS 1:. 3 PT1 1: 1. 2 PX1 1: 1. 1 PT0 1: 0. 0 PX0 1:

31 : SADEN : B9h 0 SADEN 1 SADDR 7~0 SADEN SADEN.n 0 SADEN 0 I2C I2DAT.7 I2DAT.6 I2DAT.5 I2DAT.4 I2DAT.3 I2DAT.2 I2DAT.1 I2DAT.0 : I2DAT : BCh 0~7 I2DAT I2C I2C : I2STATUS : BDh I2C I2STATUS F8H I2STATUS I2C 0~7 I2STATUS (SI=1) SI 1 I2STATUS SI 0 I2STATUS 00H SC6

32 I2C I2CLK.7 I2CLK.6 I2CLK.5 I2CLK.4 I2CLK.3 I2CLK.2 I2CLK.1 I2CLK.0 : I2CLK : BEh 7~ 0 I2CLK I2C I2C / ENTI DIV4 TIF : I2TIMER : BFh 7~ ENTI 1 DIV4 0 TIF I2C14- / : 0: 14- /. 1: 14- / 14-0 I2C SI 1 I2C / 0: 14- / Fosc 1: 14- / Fosc/4 I2C / : 0: 14- /. 1: 14- / I2C (ENTI) SI 0 I2C 0 I2C - ENS1 STA STO SI AA - - : I2CON : C0h

33 ENS1 I2C 5 STA I2C START 4 STO I2C STOP 3 SI I2C 2 AA I2C I2C I2ADDR. 7 I2ADDR. 6 I2ADDR. 5 I2ADDR. 4 I2ADDR. 3 I2ADDR. 2 : I2ADDR : C1h 7~1 I2ADDR.7 ~ I2ADDR1 0 GC NVM I2C : I2ADDR. 1 I2ADDR uc 8- / 7 MCU. 0:. 1:. NVMAD DR.7 NVMAD DR.6 NVMAD DR.5 NVMAD DR.4 NVMAD DR.3 NVMAD DR.2 NVMAD DR.1 : NVMADDR : C6h 7~0 NVMADDR.7 ~ NVMADDR.0 NVM : NVMAD DR.0 NVM SC6

34 TA.7 TA.6 TA.5 TA.4 TA.3 TA.2 TA.1 TA.0 : TA : C7h 7~0 TA : TA AAH 55H 3 NVM 7 EER 6 EWR 5~0 - EER EWR : NVMCON : CEh NVM 0: NVM 1: 1 NVM FFH NVM 4 64 NVMADDR NVM NVM 0: NVM. 1: 1 NVM NVM 0 00H 3FH 1 40H 7FH 2 80H BFH 3 C0H FFH W79E823 W79E822 W79E

35 NVM NVMDA T.7 NVMDA T.6 NVMDA T.5 NVMDA T.4 NVMDA T.3 NVMDA T.2 NVMDA T.1 : NVM : CFh NVMDA T.0 7~0 NVMDAT.7 ~ NVMDAT.0 NVM NVM MOVC. CY AC F0 RS1 RS0 OV F1 P : PSW : D0h 7 CY ALU 6 AC 5 F0 0 4 RS1 3 RS0 2 OV : 1 F1 1: 0 P 1 RS.1-0: : RS1 RS h Fh h Fh SC6

36 PWM PWMP.9 PWMP.8 : PWMPH : D1h 7~2-1~0 PWMP.9 ~PWMP.8 PWM 9~8. PWM PWM0.9 PWM0.8 : PWM0H : D2h 7~2-1~0 PWM0.9 ~PWM0.8 PWM 0 9~8. PWM PWM1.9 PWM1.8 : PWM1H : D3h 7~2-1~0 PWM1.9 ~PWM1.8 PWM1 9~8. PWM PWM2.9 PWM2.8 : PWM2H : D5h 7~2-1~0 PWM2.9 ~PWM2.8 PWM2 9~

37 PWM PWM3.9 PWM3.8 : PWM3H : D6h 7~2-1~0 PWM3.9 ~PWM3.8 PWM3 9~8. PWM BKF : PWMCON3 : D7h 7~1-0 BKF. 0: PWM. 1: WM 0 WDRUN - WD1 WD0 WDIF WTRF EWRST WDCLR : WDCON : D8h 7 WDRUN 6-0: 1:. 5 WDI. 4 WD0. 3 WDIF SC6

38 2 WTRF 1 EWRST 0 WDCLR EWT 0 0:. 1:. 0 WDCON WDCON 0x0000x0B WTRF (WDCON.2) 1 0 WDIF (WDCON.3) POR 1 EWRST (WDCON.1) 0 WDCON EWRST, WDIF WDCLR TA TA TA REG C7H WDCON REG D8H CKCON REG 8EH MOV TA, #AAH MOV TA, #55H SETB WDCON.0 ; ORL CKCON, # B ; 26 MOV TA, #AAH MOV TA, #55H ORL WDCON, # B ; PWM PWMP.7 PWMP.6 PWMP.5 PWMP.4 PWMP.3 PWMP.2 PWMP.1 PWMP.0 : PWMPL : D9h 7~0 PWMP.7 ~PWMP.0 PWM

39 PWM0 PWM0.7 PWM0.6 PWM0.5 PWM0.4 PWM0.3 PWM0.2 PWM0.1 PWM0.0 : PWM0L : DAh 7~0 PWM0.7 ~PWM0.0 PWM0. PWM1 PWM1.7 PWM1.6 PWM1.5 PWM1.4 PWM1.3 PWM1.2 PWM1.1 PWM1.0 : PWM1l : DBh 7~0 PWM1.7 ~PWM1.0 PWM 1. PWM 1 PWMRUN Load CF CLRPWM PWM3I PWM2I PWM1I PWM0I : PWMCON1 : DCh 7 PWMRUN 6 Load 5 CF 0: PWM. 1: PWM. 0: PWMP 1: PWMP 0 0: : CLRPWM 1: 10- PWM 000H. 3 PWM3I 2 PWM2I 0: PWM3 1: PWM3 0: PWM2 1: PWM SC6

40 1 PWM1I 0: PWM1 1: PWM1 0 PWM0I 0: PWM0 1: PWM0 PWM2 PWM2.7 PWM2.6 PWM2.5 PWM2.4 PWM2.3 PWM2.2 PWM2.1 PWM2.0 : PWM2L : DDh 7~0 PWM2.7 ~PWM2.0 PWM2. PWM3 PWM3.7 PWM3.6 PWM3.5 PWM3.4 PWM3.3 PWM3.2 PWM3.1 PWM3.0 : PWM3L : DEh 7~0 PWM3.7 ~PWM3.0 PWM 3 PWM 2 BKCH BKPS BPEN BKEN PWM3B PWM2B PWM1B PWM0B : PWMCON2 : DFh

41 7 BKCH 6 BKPS 0: P0.2=0 PWM 1: P0.2=1 PWM 5 BPEN 4 BKEN 3 PWM3B 0:. 1: 0: PWM3 1: PWM3 2 PWM2B 1 PWM1B 0 PWM0B 0: PWM2 1: PWM2 0: PWM1 1: PWM1 0: PWM0 1: PWM0 BPEN BKCH 0 0 BKEN PWM (PWMRUN=0) PWMnB PWM PWM (PWMRUN=1) PWM PWMRUN BKF 0. ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 : ACC : E0h ACC.7-0: The A ( ACC) SC6

42 ADC ADC.1 ADC.0 ADCEX ADCI ADCS RCCLK AADR1 AADR0 : ADCCON : E1h 7 ADC.1 ADC 1 6 ADC.0 ADC 0 5 ADCEX 4 ADCI 3 ADCS 2 RCCLK = 0 ADCS 1 ADC = 1 ADCS 1 STADC 1.4 ADC ADC ADCI 1 ADC ADC ADC ADC ADCS 1 ADC STADC 1 ADC ADCS= 1 ADCI ADCS= 0 ADCS= 1 ADCI = 1 ADC ADCI ADCS ADC ADC ADC ADCI=0 ADCI=0 ADCI=0 ADCS=1 A/D ADCI=0 ADCS=1 0: CPU ADC. 1: RC ADC. 1 AADR1 0 AADR0 AADR1, AADR0: ADC : ADC ADCI=0 ADCS=0 AADR1 AADR0 0 0 AD0 (P0.3) 0 1 AD1 (P0.4) 1 0 AD2 (P0.5) 1 1 AD3 (P0.6)

43 ADC ADC.9 ADC.8 ADC.7 ADC.6 ADC.5 ADC.4 ADC.3 ADC.2 : ADCH : E2h 7~0 ADC.9 ~ADC.2 ADC EPWM EWDI EC2 EC1 EKB EI2 : IE1 : E8h EPWM 4 EWDI 3 EC2 2 EC1 1 EKB 0 EI2 0: PWM 1: PWM 0:. 1:. 0: 2. 1: 2. 0: 1. 1: 1. 0:. 1:. 0: I2C. 1: I2C. B B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 : B : F0h B.7-0: B SC6

44 0 P0ID.7 P0ID.6 P0ID.5 P0ID.4 P0ID.3 P0ID.2 P0ID.1 P0ID.0 : P0ID : F6h 7~0 P0ID.7 ~P0ID.0 / 0. 0: 0 1: PPWMH PWDIH PC2H PC1H PKBH PI2H : IP1H : F7h PPWMH 1: PWM 4 PWDIH 1: 3 PC2H 1: 2 2 PC1H 1: 1 1 PKBH 1: 0 PI2H 1: I2C

45 1 - - PPWM PWDI PC2 PC1 PKB PI2 : IP1 : F8h PPWM 1: PWM 4 PWDI 1: 3 PC2 1: 2 2 PC1 1: 1 1 PKB 1: 0 PI2 1: I2C SC6

46 9. W79E82X W79E82X W79E82X W79E82X W79E82X CARRY AUXILIARY CARRY : ADD X X X CLR C 0 ADDC X X X CPL C X SUBB X X X ANL C, X MUL 0 X ANL C, X DIV 0 X ORL C, X DA A X ORL C, X RRC A X MOV C, X RLC A X CJNE X SETB C 1 "X" CARRY AUXILIARY CARRY 9.1 W79E82X W79E82X 8032 W79E82X 4 4 C1 C2 C3 C4 2 50% W79E82X W79E82X MOVX W79E82X 2-9 RD WR W79E82X W79E82X W79E82X

47 Single Cycle C1 C2 C3 C4 CPU CLK ALE PSEN AD<7:0> Address <15:0> A7-0 Data_ in D7-0 Address A15-8 Instruction Fetch Operand Fetch CPU CLK C1 C2 C3 C4 C1 C2 C3 C4 ALE PSEN AD<7:0> PC OP-CODE PC+1 OPERAND Address<15:0> Address A15-8 Address A SC6

48 Instruction Fetch Operand Fetch Operand Fetch C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 CPU CLK ALE PSEN AD<7:0> A7-0 OP-CODE A7-0 OPERAND A7-0 OPERAND Address<15:0> Address A15-8 Address A15-8 Address A Instruction Fetch Operand Fetch Operand Fetch Operand Fetch C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 CPU CLK ALE PSEN AD<7:0> A7-0 OP-CODE A7-0 OPERAND A7-0 OPERAND A7-0 OPERAND Address<15:0> Address A15-8 Address A15-8 Address A15-8 Address A

49 Instruction Fetch Operand Fetch Operand Fetch Operand Fetch Operand Fetch C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 CPU CLK ALE PSEN AD<7:0> A7-0 OP-CODE A7-0 OPERAND A7-0 OPERAND A7-0 OPERAND A7-0 OPERAND Address<15:0> Address A15-8 Address A15-8 Address A15-8 Address A15-8 Address A SC6

50 10. W79E82X PCON.0 CPU CPU ALE PSEN 2 RST H SFR 512 W79E82X PCON.1 SFR RST 0000H EA=1 ISR

51 11. W79E82X C4 RST 2 RST RST RST H (POR) POR VDD Vrst, POR H 11.4 SFR 0000H 0000H RAM RAM 07H VDD 2V RAM RAM RAM 2V RAM SFR FF P SC6

52 VALUE VALUE P B I2DAT xxxxxxxxb SP B I2STATUS 00000xxxB DPL B I B DPH B I2CLK B PCON 00xx0000B I2CON B TCON B I2ADDR xxxxxxxxb TMOD B TA B TL B PSW B TL B PWMP1 xxxxxx00b TH B PWM0H xxxxxx00b TH B PWM1H xxxxxx00b CKCON B PWM2H xxxxxx00b P1 1111xx11B PWM3H xxxxxx00b DIVM B WDCON 0x000000B SCON B PWMP B SBUF xxxxxxxxb PWM0L B P2 xxxxx11b PWM1L B KBI B PWMCON B AUXR B PWM2L B IE B PWM3L B SADDR B PWMCON B CMP B ACC B CMP B ADCCON xx000x00b P0M B ADCH xxxxxxxxb P0M B IE1 xx000000b P1M B B B P1M B P0IDS B P2M B IPH xx000000b P2M2 xxxxxx00b IP1 xx000000b IP0H IP0 SADEN x b x b B

53 WDCON / 0 WDCON 0x0x0xx0b 0x0x01x0b b POR WDCON.6 PFI WDCON WTRF WDCON.2 1, 0 EWT WDCON SC6

54 12. W79E82X INT0 INT1 IT0 IT1 TCON IE0 IE1 2 INTx IEx IEx IEx TF0 TF1 0 1 WDIF WDCON.3 EIE.4=1 SCON RI TI 1 0 / IE IE ADC ADC ADCCON ADCI 0 CMF1 CMF2 0 I2C SI SI 1 I2C I2C 0 PWM BKF

55 0 IE0 1( ) BOF 2 WDIF 3 0 TF0 4 I2C SI 5 ADC ADCI 6 1 IE1 7 KBI KBF 8 1 CMF1 9 1 TF CMF2 11 RI + TI 12 PWM BKF 13 ( ) LCALL LCALL IE IE1 IP0 IP0H IP1 IPH1 RETI. LCALL 1 LCALL TF0 TF1 INT0 INT1 WDIF PSW PC SC6

56 0 0003h 0 000Bh h 1 001Bh 0023h 002Bh I2C 0033h KBI 003Bh h - 004Bh 0053h ADC 005Bh h - 006Bh PWM 0073h - 007Bh IPXH IPX ( ) ( ) RETI RETI PC CPU PC W79E82X 4 W79E82X W79E82X 13. IEN0 IEN1 IEN0 EA 4 IP0, IP0H, IP1 IP1H

57 CPU 0 IE0 0003H EX0 (IE0.0) IP0H.0, IP0.0 1( ) BOF 002BH EBO (IE.5) IP0H.5, IP0.5 2 WDIF 0053H EWDI (IE1.4) IP1H.4, IP TF0 000BH ET0 (IE.1) IP0H.1, IP0.1 4 I2C SI 0033H EI2 (IE1.0) IP1H.0, IP1.0 5 ADC ADCI 005BH EAD (IE.6) IP0H.6, IP IE1 0013H EX1 (IE.2) IP0H.2, IP0.2 7 KBI KBF 003BH 1 CMF1 0063H EKB (IE1.1) EC1 (IE1.2) IP1H.1, IP1.1 8 IP1H.2, IP TF1 001BH ET1 (IE.3) IP0H.3, IP CMF2 0043H EC2 (IE1.3) IP1H.3, IP Tx Rx TI & RI 0023H ES (IE.4) IP0H.4, IP PWM BKF 0073H EPWM (IE1.5) IP1H.5, IP ( ) RC ADC 12.2 INT0 RI+TI C3 IEx 0 1 C ( ) W79E82X IE, IE1, IP0, IP0H, IP1 IP1H MUL DIV 12 1 IE, IE1, IP0, IP0H, IP1 IP1H 2 MUL DIV 5 LCALL SC6

58 % 12.3 W79E82X 13 IE0,IE1, BOF, KBF, WDT, ADC, CMF1 CMF2 IF0, IF1, RI+TI,SI BKF. 2 80C51 W79E82X CPU IE0 EX0 IE1 EX1 BOF EBO KBF EKB ADCI EADC WDT EWDI CM1 EC1 CM2 EC2 EA Wakeup (If in Power Down) Interrupt To CPU

59 TF0 ET0 TF1 ET1 RI+TI ES Interrupt To CPU SI EI2 EA BKF EPWM SC6

60 13. / W79E82X 2 16 / / 0&1 W79E82X 2 16 / TH0 8 TL0 8 1 TH1 TL T0 0 T1 1 T0 T1 C C3 T0 T1 1 TMOD C / T / TMOD 2 / 0 6 / 1 / 4 TMOD M0 M W79E82X / W79E82X 1/4 3 CKCON T0M T1M / 8 THx TLx 5 TLx 3 TLx TLx 1 0 THx THx FF 00 TCON TFx TRx GATE 0 INTx 1 C / T =0 / C / T =1 P1.2(T0) P0.7 T FFFH 0000H 1/12 1/4-60 -

61 Fcpu T0=P1.2 T1=(P0.7) TR0=TCON.4 TR1=TCON.6 GATE=TMOD.3 (GATE=TMOD.7) INT0=P1.3 (INT1=P1.4) 1/4 1/12 T0M=CKCON.3 (T1M=CKCON.4) 1 0 C/T=TMOD.2 (C/T=TMOD.6) 0 1 Timer 0/1 Mode 0 TL0 (TL1) TFx TH0 (TH1) TF0 (TF1) Interrupt T0OE (T1OE) P1.2 / / THx TLx 16 FFFFH 0000H Fcpu T0=P1.2 T1=(P0.7) TR0=TCON.4 TR1=TCON.6 GATE=TMOD.3 (GATE=TMOD.7) INT0=P1.3 (INT1=P1.4) 1/4 1/12 T0M=CKCON.3 (T1M= CKCON.4) 1 0 C/T=TMOD.2 (C/T=TMOD.6) 0 1 Timer 0/1 Mode 1 TL0 (TL1) TFx TH0 (TH1) TF0 (TF1) Interrupt T0OE (T1OE) P1.2 (P0.7) / SC6

62 / TLx 8 THx TLx FFH 00H TCON TFx THx TLx THx TRx GATE 0 INTx /12 1/4 Tn Fcpu T0=P1.2 T1=(P0.7) TR0=TCON.4 TR1=TCON.6 GATE=TMOD.3 (GATE=TMOD.7) INT0=P1.3 (INT1=P1.4) 1/4 1/12 T0M=CKCON.3 (T1M= CKCON.4) 1 0 C/T=TMOD.2 (C/T=TMOD.6) 0 1 TL0 (TL1) TH0 (TH1) TF0 (TF1) TFx Interrupt T0OE (T1OE) P1.2 (P0.7) Timer 0/1 Mode 2 : 8-bit Auto-reload Mode /

63 / 1 3 / 0 3 TL0 TH TL0 0 C / T, GATE, TR0, INT0 TF0 TL0 1/12 1/4 T0 1 0 TH0 / 1 TR1 TF TF1 TR1 1 GATE INT1 3 Fcpu 1/4 1/12 T0M=CKCON.3 (T1M=CKCON.4) 1 0 C/T=TMOD TL0 0 7 TF0 Interrupt T0=P1.2 TR0=TCON.4 T0OE P1.2 GATE=TMOD.3 INT0=P1.3 TH0 0 7 TR1=TCON.6 TF1 Interrupt Timer 0/1 Mode 3 : Two 8-bit Counters T1OE P0.7 / SC6

64 14. NVM W79E82X 256/128 NVM 256/128 NVM 4/ FC00h ~ FC3Fh 1 FC40h ~ FC7Fh 2 FC80h ~ FCBFh 3 FCC0h ~ FCFFh. NVM NVM MOVC A,@A+DPTR NVMADDR NVMDAT NVMCON NVMADDR NVMCON.7 EER ( ) PC 5ms. NVM NVMADDR NVMDA T EWR(NVMCON.6) uc 50us FFFFH FCFFH FC00H FBFFH Unused Code Memory 256 Bytes NVM Data Memory Unused Code Memory Page 3 64 bytes Page 2 64 bytes Page 1 64 bytes Page 0 64 bytes FCFFH FCC0H FCBFH FC80H FC7FH FC40H FC3FH FC00H NVM Data Memory Area Unused Data Memory FFFFH 4000H 3FFFH 0000H 16K/8K Bytes On-Chip Code Memory On-Chip Code Memory Space CONFIG 2 CONFIG H External Data Memory Space W79E825/W79E824 Memory Map

65 7~0 NVMADDR.7 ~ NVMADDR.0 NVM : NVM : NVMADDR : C6h 7 EER 6 EWR 5~0-0: NVM NVM 1: 1 NVM FFH NVM 4 64 NVMADDR NVM 0: NVM. NVM 1: 1 NVM : NVMCON : CEh NVM : PAGE 0 00H 3FH 1 40H 7FH 2 80H BFH 3 C0H FFH : W79E823, W79E822 W79E ~0 NVMDAT.7 ~NVMDAT.0 NVM NVM MOVC. : NVM : CFh SC6

66 15. 2 (Security Bit) WDTE uc clock 500KHz RC Oscillator /Enable WDRUN (WDCON.7) 0 Time-Out 26-bits Counter Selector (WDCON.3) WDIF Interrupt EWDI MUX (IE1.4) (WDCON.2) 11 WDRF WDCLR (Reset Watchdog) (WDCON.0) WD 1,WD0 (WDCON.5/4) 512 clock delay EWRST (WDCON.1) Reset WDCLR WDCLR RWT 1 WD1 WD0 WDCON.5 WDCON.4 WDIF(WDCON.3) 512 EWRST (WDCON.1) =1 WDCLR WTRF(WDCON.2) WDIF WDIF RWT EA=

67 WD1 WD0 INTERVAL NUMBER 10 MHZ ms ms ms ms 15.1 WDIF WDCON.3-1 (IE1.4)= 1 ( 1 ) 0 WDRF WDCON.2 1 EWDRST = 0 EWRST: WDCON WDCLR WDCON WD1, WD0: CKCON.5, CKCON EWT,WDIF RWT SC6

68 16. (UART) W79E82X W79E82X SBUF SBUF SBUF RXD TXD TXD W79E82X 8 1/12 1/4 SM2 SCON.5 SM2=0 1/12 SM2=1 1/ W79E82X 0 RXD TXD W79E82X / SBUF RXD 8 SM2=1 TXD RXD 1 TXD 2 TXD SM2=0 RXD TXD 3 TXD 6 TXD TXD Fcpu 1/12 Write to SBUF TX START Internal Data Bus TX SHIFT Transmit Shift Register PARIN LOAD CLOCK SOUT RXD P1.1 Alternate Output Function SM2 0 TX CLOCK TI Serial Interrupt RI REN RXD P1.1 Alternate Input Function RI RX CLOCK SHIFT CLOCK LOAD SBUF TX START RX SHIFT Serial Controllor CLOCK SIN PAROUT SBUF TXD P1.0 Alternate Output Function Read SBUF Internal Data Bus Serial Port Mode

69 TI C1 1 REN=1 RI=0 8 RI TXD 1 RI RXD TXD SCON RB8 1 1/16 1/32 1 SBUF 16 C1 TXD 16 C1 TXD 16 SBUF 9 TXD TI C1 SBUF REN=1 16 RXD REN= 1 RXD 1-0 RXD RXD 3 2 RXD RXD RB8 RI RI 1 RI=0 SM2=0 1 RB8 8 SBUF RI SC6

70 Timer 1 Overflow 1/2 Write to SBUF Internal Data Bus 1 0 Transmit Shift Register STOP PARIN START SOUT LOAD CLOCK TXD SMOD 0 1 TX START TX SHIFT 1/16 TX CLOCK 1/16 Serial Controllor TI Serial Interrupt SAMPLE 1-To-0 DETECTOR RX CLOCK TX START RI LOAD SBUF RX SHIFT Read SBUF RXD BIT DETECTOR CLOCK SIN PAROUT D8 Receive Shift Register SBUF RB8 Internal Data Bus Serial Port Mode TB8 (0) 9 RB8 1/32 1/64 PCON SMOD SBUF 16 C1 TXD 16 C1 TXD 16 SBUF 9 TXD TI C1 SBUF REN= 1 RXD 1-0 RXD RXD 3 2 RXD RXD

71 Transmit Shift Register Clock/2 1/2 Write to SBUF 1 TB8 Internal Data Bus 0 STOP D8 PARIN START LOAD CLOCK SOUT TXD SMOD 0 1 TX START TX SHIFT 1/16 TX CLOCK 1/16 Serial Controllor TI Serial Interrupt SAMPLE 1-To-0 DETECTOR RX CLOCK TX START RI LOAD SBUF RX SHIFT Read SBUF RXD BIT DETECTOR CLOCK PAROUT SIN D8 Receive Shift Register SBUF RB8 Internal Data Bus Serial Port Mode RB8 RI RI 1 RI=0 SM2=0 1 RB8 8 SBUF RI SFR SBUF 0 RI=0 REN=1 TXD RXD 8 REN= SC6

72 Transmit Shift Register Timer 1 Overflow 1/2 Write to SBUF 1 TB8 Internal Data Bus 0 STOP D8 PARIN START LOAD CLOCK SOUT TXD SMOD 0 1 TX START TX SHIFT 1/16 TX CLOCK 1/16 Serial Controllor TI Serial Interrupt SAMPLE 1-To-0 DETECTOR RX CLOCK TX START RI LOAD SBUF RX SHIFT Read SBUF RXD BIT DETECTOR CLOCK PAROUT SIN D8 Receive Shift Register SBUF RB8 Internal Data Bus Serial Port Mode 3 3 SM1 SM TCLKS TCLKS , , W79E82X SCON.7 FE FE_1) 8051 SM0 W79E82X SM0/FE FE SMOD0 PCON.6 SMOD0=1 FE SMOD0=0 SM0-72 -

73 FE 0 FE SMOD0 1 FE W79E82X RI 9 1 SM2 SM2 SM2=0 1 1 SM2=1 RI 1 SADDR SADEN SADDR 8 SADEN 0 SADDR SADEN 1 SADDR 1: SADDR SADEN Given x0x 2: SADDR SADEN Given xx =1 1=0 3 SADDR SADEN 0 FFH X SADDR SADEN A9h B9h SC6

74 17. W79E82X ROM / W79E82X 3 3 TA AAH 55H TA C7H TA REG 0C7h ; C7H TA MOV TA, #0AAh MOV TA, #055h TA AAh 3 55h; 3 55h, 3 1 MOV TA, #0AAh 3 M/C : M/C = MOV TA, #055h 3 M/C MOV WDCON, #00h 3 M/C 2 MOV TA, #0AAh 3 M/C MOV TA, #055h 3 M/C NOP 1M/C SETB EWT 2 M/C 3 MOV TA, #0Aah 3 M/C MOV TA, #055h 3 M/C ORL WDCON, # B 3M/C

75 4 MOV TA, #0AAh 3 M/C MOV TA, #055h 3 M/C NOP 1 M/C NOP 1 M/C CLR POR 2 M/C 5 MOV TA, #0AAh 3 M/C NOP 1 M/C MOV TA, #055h 3 M/C SETB EWT 2 M/C SC6

76 18. (KBI) W79E82X 8 W79E82X CPU P0 P0 KBI KBI0 ~ KBI7 KBI ( 1 ) AUXR1 (KBF) 1 KB 0 KBI P0 P0.7 KBI.7 P0.6 KBI.6 P0.5 KBI.5 P0.4 KBI.4 KBF (KBI Interrupt) P0.3 KBI.3 EKB (From IEN1 Register) P0.2 KBI.2 P0.1 KBI.1 P0.0 KBI

77 19. W79E82X MCU (CMP1 CMP2) CINnA, CINnB, CMPREF OEn 1 CMP1 CMP2 OEn 1 (Vref) 1.19V +/- 10%. (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF Enable CMP1 Vref CP1 CMP1 Analog Circuit Comparator 1 + CO1 - OE1 CMP1(P0.6) CE1 CE2 (P0.2) CIN2A (P0.1) CIN2B En Enable CMP2 Vref CN1 CP2 CMP2 Analog Circuit Comparator 2 + CO2 - Change Detect OE2 CMF1 Interrupt CMP2(P0.0) CN2 Change Detect CMF2 Interrupt SC6

78 20. I/O W79E82X MCU 3 I/O P0 P1 P2 I/O 4 P1.5 1 RPD=0 W79E82X MCU 15 I/O RC P1.5 W79E82X MCU 18 I/O I/O I/O PXM1.Y PXM2.Y ( ) 1 1 CONFIG1 PRHI P1.5 P2M1 ENT0 ENT W79E82X I/O P2M1 P(n)S TTL n P(n)S 1 RC P2.0(XTAL2) RC 1/ MCU CPU

79 VDD 2 CPU Clock Delay P P Very P Strong Weak Weak Port Pin Port Latch Data N Input Data Quasi-Bidirection Output 20.2 Port Pin Port Latch Data N Input Data Open Drain Output SC6

80 W79E82X MCU 3 P1.2, P1.3, P1.5 P1.2 P1.3 VDD P Port Pin Port Latch Data N Input Data Push-Pull Output 20.4 W79E82X PxM1.y PxM2.y TTL

81 21. W79E82X 3 CONFIG (CONFIG1) RC 4MHz 20MHz Crystal Oscillator 00H Internal RC Oscillator External Clock input 01H 11H 16 bits Ripple Counter FOSC1 FOSC0 Divide-By-M (DIVM Register ) CPU Clock Power Monitor Reset Power Down 21.1 RC RC 6MHz +/- 25% FOSC1 FOSC0 = 10H RC P2.0 (XTAL2) 21.2 FOSC1, FOSC0 = 11H (XTAL1) 0Hz 20MHz P2.0 (XTAL2) W79E82X MCU RC W79E82X P2M1 ENCLK XTAL2/CLK 1/4 CPU 21.3 CPU W79E82X CPU DIVM DIVM = 00H CPU 4CPU / (Fosc) DIVM N CPU 2(DVIM+1) CPU CPU CPU CPU (Fcpu) SC6

82 22. W79E82X POF (PCON.4) 1 POF 22.2 W79E82X 2 BOV ( 1.4) BOV =0 3.8V BOV = 1 2.5V VDD Brownout Detect Circuit BOF 0 1 To Reset To Brownout interrupt BOD (Enable Brownout Detect ) BOI Drownout Detect Block BOD (AUXR.6) BOF (PCON.5) BOF BOI (AUXR1.5) 1 EA (IE.7) EBO (IE.5) 1. VDD 50mV/us 2mV/us

83 23. (PWM) W79E82X 4 PWM PWM PWM0(P0.1) PWM1(P1.6) PWM2(P1.7) PWM3(P0.0) PRHI 1 PWM 1 PRHI 0 PWM 0 PWM 1 PWM 1 W79E82X 10- PWM PWM CPU F CPU = F OSC PWM f = FCPU / (PWMP+1), PWMP 10- PWMPH.1 PWMPH.0 PWMPL.7~PWMPL.0 PWMP PWMRUN CF 10- CF PWMP PWM PWMP CLRPWM H CF PWMRUN PWM PWM PWM0L PWM3L PWM0H PWM3H PWM 10- PWM PWMn 1 PWMn t HI = (PWMP PWMn+1) 000H PWMn 3FFH PWMn SC6

84 PWMP Register Counter Register load BKCH BPEN BKEN Brake Control Block Brake Flag BKF Enable External Brake Pin (BPEN,BKCH) = (1,0) 0 1 BKPS P0.2=0 P0.2=1 Brake Pin (P0.2) CF PWMRUN 10-bits Counter X + F Clear CPU Counter CLRPWM > Y -- Compare Register PWM0I PWM0B 0 1 P0.1 Bit PWM0 Pin P0.1 PWM0 register Compare Register X + > Y - PWM1I PWM1B 0 1 P1.6 Bit PWM1 Pin P1.6 PWM1 register Compare Register X + Y > - PWM2I PWM2B 0 1 P1.7 Bit PWM2 Pin P1.7 PWM2 register Compare Register X + Y > - PWM3I PWM3B 0 1 P0.0 Bit PWM3 Pin P0.0 PWM3 register

85 PWM PWMCON1, PWMCON2, PWMCON3 PWM PWMPL(D9H) 7~0 PWMP.7 ~PWMP.0 PWM 7~0 PWM PWMPH(D1H) 7~2-1~0 PWMP.9 ~PWMP.8 PWM 9~8 PWM 0 PWM0L(DAH) 7~0 PWM0.7 ~PWM0.0 PWM 0 7~0 PWM 1 PWM1L(DBH) 7~0 PWM1.7 ~PWM1.0 PWM 1 7~0 PWM 2 PWM2L(DDH) 7~0 PWM2.7 ~PWM2.0 PWM 2 7~0 PWM 3 PWM3L(DEH) 7~0 PWM3.7 ~PWM3.0 PWM3 7~0 PWM 0 PWM0H(D2H) 7~ SC6

86 1~0 PWM0.9 ~PWM0.8 PWM0 9~8 PWM1 PWM1H(D3H) 7~2-1~0 PWM1.9 ~PWM1.8 PWM 1 9~8 PWM2 PWM2H(D5H) 7~2-1~0 PWM2.9 ~PWM2.8 PWM 2 9~8 PWM3 PWM3H(D6H) 7~2-1~0 PWM3.9 ~PWM3.8 PWM3 9~8 PWM 1 PWMCON1(DCH) 7 PWMRUN 6 Load 5 CF 0: PWM. 1: PWM. 0: PWMP PWMn 1: PWMP PWMn PWMP PWMn 0 0: : CLRPWM 1: 10- PWM 000H. 3 PWM3I 2 PWM2I 0: PWM3 1: PWM3 0: PWM2 1: PWM2-86 -

87 1 PWM1I 0 PWM0I 0: PWM1 1: PWM1 0: PWM0 1: PWM0 PWM 2 PWMCON2(DFH) 7 BKCH 6 BKPS 0: P0.2=0 PWM 1: P0.2=1 PWM 5 BPEN 4 BKEN 3 PWM3B 2 PWM2B 1 PWM1B 0 PWM0B 0:. 1: 0: PWM3 1: PWM3 0: PWM2 1: PWM2 0: PWM1 1: PWM1 0: PWM0 1: PWM0 BPEN BKCH 0 0 BKEN 0 1 PWM (PWMRUN=0) PWMnB PWM PWM PWMRUN BKF SC6

88 PWM 3 PWMCON3 (D7H) 7~1-0 BKF. 0: PWM. 1: PWM

89 W79E82X (P0.2) PWMCON2 PWM PWMnB BKEN 1 BPEN BKCH (BPEN, BKCH) = (0,0) (BPEN, BKCH) = (0,1) PWM PWMRUN PWM PWMRUN=0 PWM PWMnB PWM PWMRUN = 1 PWM W79E82X (P0.2) PWM (BKF) PWM P0.2 BKPS = 0 BKF(PWMCON3.0) 1 PWNRUN PWM PWM PWMnB BKF(PWMCON3.0) 1 PWMCON1.7 PWM PWM PWM PWM PWM Start To change external pin to S/W Brake To set PWM Comparator output to High (1) or Low (0), The output high is 000H, output low is 3FFH or given output brake pattern To clear BKF flag, that will release PWMnB brake Polling external brake pin. If brake pin is not active Yes To decide PWM output frequency and width by PWMP and PWM[3:0] registers No Clear 10-bits Counter to 000H by CLRPWM bit Start PWM running, that set PWMRUN and load to 1. End SC6

90 24. W79E82X ADC DAC (VDAC) (Vin) (V DAC) ADCCON ADCS 1 ADCS ADC ADCCEX 1 ADCCON.5 (ADCEX) =0 ADCCON.3 (ADCS) 1 ADC ADCCON.5 =1 ADCCON.3 (ADCS) 1 STADC (P2.0) ADC STADC (P2.0) ADC STADC. ADCCON.4 (ADCI) ADCH ADCCON.7 (ADC.1) ADCCON.6 (ADC.0) ADCCON 8- ADC ( 8 ADCH ) 50 ADC ADCS ADCCON.0 ADCCON ADC ADCI = 1 ADC (ADCI = 1) DAC MSB Successive Approximation Register LSB Successive Approximation Control Logic Start Ready (Stop) VDAC Comparator - Vin + The Successive Approximation ADC ADC

91 24.1 ADC ADC (AVDD and AVSS ) (Vref+) DAC 1023 AVss 0.5XR Vref+ 0.5XR 1024XR DAC AVss [(Vref+ ) + ½ LSB] 10- ADC b = 000H [(Vref+) 3/2 LSB] Vref+ 10- ADC B = 3FFH AVref+ AVSS AVDD + 0.2V AVSS 0.2 V Avref+ AVSS (Vin) AVref+ AVSS Result = 1024? Vin Result = AVref? 1024? VDD VSS ADC SC6

92 25. I2C 2 (SDA SCL)I2C 2 ( ) I2C W79E82X I2C I2C ( ) I2C (I2STA) I2C CPU I2C 4 : I2CON (SIO1 ), I2STA (SIO1 ), I2DAT (SIO1 ), I2ADR (SIO1 ) SIO1 I2C P1 P1.2/SCL ( ) P1.3/SDA ( ) 25.1 SIO1 SIO1 I/O I2C SIO1 I2CON ENS1 '1' CPU SIO1 6 I2CON (I2C, C0H), I2STATUS (, BDH), I2DAT (, BCH), I2ADDR (, C1H), I2CLK ( BEH) I2 (, BFH). SIO1 I2C 2 SDA (P1.3, ) SCL (P1.2, ) SIO1 P1.2 P I2C : W79E82X I2C , I2ADDR SIO1 I2ADDR CPU 8-8- SIO1 SIO1 I2ADDR.7 I2ADDR.6 I2ADDR.5 I2ADDR.4 I2ADDR. 3 : I2ADDR : C1h I2ADDR.2 I2ADDR. 1 GC

93 25.2.2, I2DAT CPU 8- SIO1 (SI) 1 SI= 1 I2DAT I2DAT I2DAT I2DAT.7 I2DAT.6 I2DAT.5 I2DAT.4 I2DAT.3 I2DAT.2 I2DAT.1 I2DAT.0 : I2DAT : BCh I2DAT 9- SIO1 CPU I2DAT SCL I2DAT I2DAT (ACK NACK) 9 (SCL ) I2DAT (SCL ) I2DAT , I2CON CPU 8- SI SIO1 STO SI 1 ENS1 = "0" STO - ENS1 STA STO SI AA - - : I2CON : C ENS1 5 STA 0: I2C SDA SCL SDA SCL I2C I2CON STO 0 P1.0(SCL) P1.1(SDA) I/O 1: I2C P1.0 P :STA 1:STA 1 I2C I2C I2C I2C STOP I2C STA 1 I2C STA 1 STA I2C SC6

94 4 STO 3 SI 2 AA I2C STO 1 I2C STOP STOP I2C STO STO 1 STOP I2C I2C STOP STO I2C ( I2C STOP ) STA STO 1 STOP I2C I2C 0: SI SCL 1: SI 1 0 EA ES ( IE ) 1 SI 1 SCL SI 0: SCL (SDA ) 1) SIO1 2) SIO1 1: SCL (SDA ) 1) 2) SIO1 3) SIO I2C, I2CLK SIO1 I2C I2CLK SIO1 I2C 400 KHz I2C I2C = Fcpu / (I2CLK+1) Fcpu=Fosc/4 Fosc = 16MHz I2CLK = 40(28H) I2C I2C = 16MHz /(4X (40 +1)) = 97.56K / I2CLK.7 I2CLK.6 I2CLK.5 I2CLK.4 I2CLK.3 I2CLK.2 I2CLK.1 I2CLK.0 : I2CLK : BEh 7 ~ 0 I2CLK

95 Fosc 0 1/ bits Counter Clear Counter TIF To I2C Interrupt DIV4 ENTI SI SI I2C Timer Count Block Diagram , I2STATUS I2STATUS I2STATUS F8H I2STATUS SIO1 (SI = 1) SI 1 1 SI I2STATUS 00H START STOP 25.3 I2C 4 / / / I2CON STA STO AA SI SIO1 I2STATUS SI 1 ( SI ) Last state Last action is done Expected next action 08H A START has been transmitted. (STA,STO,SI,AA)=(0,0,0,X) SLA+W will be transmitted ; ACK bit will be received. (1) Data byte will be transmitted : Software should load the data byte (to be transmitted ) into S 1DAT before new S1CON setting is done. (2) SLA+W (R) will be transmitted : Software should load the SLA+W/R (to be transmitted ) into S 1DAT before new S1CON setting is done. (3) Data byte will be received: Software can read the received data byte from S 1DAT while a new state is entered. New state next action is done 18H SLA+W has been transmitted; ACK has been received SC6

96 Set STA to generate a START. From Slave Mode (C) 08H A START has been transmitted. ( STA,STO,SI,AA)=(0,0,0,X) SLA+W will be transmitted; ACK bit will be received. From Master/Receiver (B) 18 H SLA+W will be transmitted; ACK bit will be received. or 20 H SLA+W will be transmitted; NOT ACK bit will be received. ( STA,STO,SI,AA )=( 0,0,0,X ) Data byte will be transmitted; ACK will be received. (STA,STO,SI,AA)=(1,0,0,X) A repeated START will be transmitted ; (STA,STO,SI,AA )=(0,1,0,X ) A STOP will be transmitted; STO flag will be reset. (STA,STO,SI,AA )=(1,1,0,X) A STOP followed by a START will be transmitted; STO flag will be reset. 28 H Data byte in S1DAT has been transmitted; ACK has been received. or 10 H A repeated START has been transmitted. Send a STOP Send a STOP followed by a START 30 H Data byte in S1DAT has been transmitted; NOT ACK has been received. (STA,STO,SI,AA )=(0,0,0,X ) SLA+R will be transmitted; ACK bit will be transmitted; SIO 1 will be switched to MST/REC mode. 38 H Arbitration lost in SLA+R/W or Data byte. To Master/Receiver (A) ( STA,STO,SI,AA)=(0,0,0,X) I 2C bus will be release; Not address SLV mode will be entered. (STA,STO,SI,AA)=( 1,0,0,X ) A START will be transmitted when the bus becomes free. Enter NAslave Send a START when bus becomes free

97 Set STA to generate a START. From Slave Mode (C) 08H A START has been transmitted. From Master/Transmitter (A) ( STA, STO, SI, AA)=(0,0, 0, X) SLA+ R will be transmitted; ACK bit will be received. 48H SLA+ R has been transmitted; NOT ACK has been received. 40H SLA +R has been transmitted; ACK has been received. (STA,STO, SI,AA )=(0,0,0,0) Data byte will be received; NOT ACK will be returned. (STA, STO,SI, AA)=(0,0,0, 1) Data byte will be received; ACK will be returned. 58H Data byte has been received; NOT ACK has been returned. 50H Data byte has been received; ACK has been returned. (STA,STO,SI,AA )=(1,1,0,X ) A STOP followed by a START will be transmitted; STO flag will be reset. (STA, STO,SI, AA)=( 0, 1, 0, X) A STOP will be transmitted; STO flag will be reset. (STA, STO,SI, AA)=(1, 0, 0, X) A repeated START will be transmitted; Send a STOP followed by a START Send a STOP 10H A repeated START has been transmitted. 38H Arbitration lost in NOT ACK bit. (STA, STO,SI, AA)=(0,0, 0,X) SLA+ R will be transmitted; ACK bit will be transmitted; SIO1 will be switched to MST/REC mode. (STA,STO,SI, AA)=(1,0, 0,X) A START will be transmitted ; when the bus becomes free ( STA, STO, SI,AA )=(0,0, 0, X) I 2C bus will be release; Not address SLV mode will be entered. To Master/Transmitter (B) Send a START when bus becomes free Enter NAslave SC6

98 Set AA A8H Own SLA+R has been received; ACK has been return. or B0 H Arbitration lost SLA+R/W as master ; Own SLA+R has been received; ACK has been return. (STA,STO,SI,AA)=(0,0,0,0) Last data byte will be transmitted ; ACK will be received. (STA,STO,SI,AA)=(0,0,0,1) Data byte will be transmitted; ACK will be received. C8H Last data byte in S1DAT has been transmitted; ACK has been received. C0 H Data byte or Last data byte in 1SDAT has been transmitted; NOT ACK has been received. B8H Data byte in S1 DAT has been transmitted; ACK has been received. (STA,STO,SI,AA)=(0,0,0,0) Last data will be transmitted; ACK will be received. (STA,STO,SI,AA)=(0,0,0,1 ) Data byte will be transmitted; ACK will be received. A0 H A STOP or repeated START has been received while still addressed as SLV/REC. ( STA,STO,SI,AA)=( 1,0,0,1) Switch to not address SLV mode ; Own SLA will be recognized; A START will be transmitted when the bus becomes free. (STA,STO,SI,AA)=(1,0,0,0) Switch to not addressed SLV mode; No recognition of own SLA; A START will be transmitted when the becomes free. (STA,STO,SI,AA)=(0,0,0,1) Switch to not addressed SLV mode ; Own SLA will be recognized. (STA,STO,SI,AA)=(0,0,0,0 ) Switch to not addressed SLV mode ; No recognition of own SLA. Send a START when bus becomes free Enter NAslave To Master Mode (C)

99 Set AA 60 H Own SLA+W has been received; ACK has been return. or 68 H Arbitration lost SLA+R/W as master; Own SLA+W has been received; ACK has been return. (STA,STO,SI,AA)=(0,0,0,0) Data byte will be received; NOT ACK will be returned. (STA,STO,SI,AA)=(0,0,0,1) Data byte will be received; ACK will be returned. 88H Previously addressed with own SLA address ; NOT ACK has been returned. 80H Previously addressed with own SLA address ; Data has been received; ACK has been returned. A0H A STOP or repeated START has been received while still addressed as SLV/REC. ( STA,STO,SI,AA)=( 0,0,0,0) Data will be received; NOT ACK will be returned. ( STA,STO,SI,AA)=(0,0,0,1) Data will be received; ACK will be returned. (STA,STO,SI,AA)=(1,0,0,1) Switch to not address SLV mode ; Own SLA will be recognized; A START will be transmitted when the bus becomes free. (STA,STO,SI,AA)=( 1,0,0,0 ) Switch to not addressed SLV mode ; No recognition of own SLA; A START will be transmitted when the becomes free. ( STA,STO,SI,AA)=( 0,0,0,1) Switch to not addressed SLV mode ; Own SLA will be recognized. (STA,STO,SI,AA)=(0,0,0,0) Switch to not addressed SLV mode ; No recognition of own SLA. Send a START when bus becomes free Enter NAslave To Master Mode (C) SC6

100 GC Set AA 70 H Reception of the general call address and one or more data bytes; ACK has been return. or 78 H Arbitration lost SLA+R/W as master; and address as SLA by general call ; ACK has been return. ( STA,STO,SI,AA)=(X,0,0,0) Data byte will be received; NOT ACK will be returned. (STA,STO,SI,AA)=(X,0,0,1) Data byte will be received; ACK will be returned. 98H Previously addressed with General Call ; Data byte has been received; NOT ACK has been returned. 90H Previously addressed with General Call ; Data has been received; ACK has been returned. A0H A STOP or repeated START has been received while still addressed as SLV/REC. ( STA,STO,SI,AA)=(X,0,0,0) Data will be received; NOT ACK will be returned. (STA,STO,SI,AA)=(X,0,0,1 ) Data will be received; ACK will be returned. (STA,STO,SI,AA)=(1,0,0,1) Switch to not address SLV mode ; Own SLA will be recognized; A START will be transmitted when the bus becomes free. (STA,STO,SI,AA)=(1,0,0,0 ) Switch to not addressed SLV mode ; No recognition of own SLA; A START will be transmitted when the becomes free. ( STA,STO,SI,AA)=(0,0, 0,1) Switch to not addressed SLV mode ; Own SLA will be recognized. (STA,STO,SI,AA)=(0,0,0,0) Switch to not addressed SLV mode ; No recognition of own SLA. Send a START when bus becomes free Enter NAslave To Master Mode (C)

101 26. ICP( ) FLASH W79E82X ICP( ) ICP P1.5 P0.4 P0.5 ICP ICP ( ~10.5V) P1.5 ICP ICP 1 W79E82X Flash EPROM 16K/8K/4K/2K/1K AP Flash EPROM 256/128 NVM ICP AP Flash EPROM 256/128 NVM Vcc ICP Power Jumper Vdd ICP Connector Vdd Jumper Vpp Data Clock P1.5 P0.4 P0.5 To Reset or Input Pin To I/O pin To I/O pin Vss Vss Vss ICP Program Tool W79E82X Chip System Board : 1 P1.5, P0.4 P0.5 2 ICP ICP SC6

102 27. W79E82X 2 (CONFIG1 CONFIG2) 2 2 flash EPROM 2 flash EPROM 2 MOVC 27.1 CONFIG1 7 WDTE : 0: RC 1: CPU 6 RPD : 0: P1.5. 1: P1.5 5 PRHI : 0:. 1:. 4 BOV : 0: 3.8V. 1: 2.5V Fosc1 CPU 1 0 Fosc0 CPU

103 : FOSC1 FOSC MHz ~ 20MHz 0 1 RC CONFIG2 C7: 16K/8K/4K/2K Flash EPROM W79E82X 0 Flash EPROM C6: 256/128 Flash EPROM W79E82X 256/128 0 Flash EPROM K/8K/4K/2K 256/128 ICP K/8K/4K/2K ICP 256/ K/8K/4K/2K 256/128 ICP SC6

104 28. DC VDD?VSS V VIN VSS-0.3 VDD+0.3 V TA ?C Tst ?C

105 29. DC/ADC / 29.1 DC (TA = -40~85?C, unless otherwise specified.) MIN. TYP. MAX. UNIT V DD V I DD I IDLE I PWDN ma V DD =4.5V ~ 20MHz V DD =2.7V ~ 12MHz V DD = 20MHz, No load, RST = V ss 6 8 ma V DD = 12MHz, No load, RST = V ss ma V DD = 5.5V, 20 MHz, no load ma V DD = 3.0V, 12 MHz, no load 1 10?A 1 10?A V DD = 5.5V, no BOV V DD = 3.0V, no BOV P0, P1, P2 I IN ?A V DD = 5.5V, V IN = 0V<V IN<V DD P1.5(RST pin) [1] I IN ?A V DD = 5.5V, V IN = 0.45V P0, P1, P2 ( ) ILK ?A VDD = 5.5V, 0<VIN<VDD [*3] P0, P1, P2 1 0 I TL P0, P1, P2 (TTL ) V IL1 P0, P1, P2 (TTL ) V IH1 XTAL1 [*2] XTAL1 [*2] V IL3 VIH ?A V DD = 5.5V, V IN<2.0V V DD = 4.5V V V DD = 2.7V V DD +0.2 V DD = 5.5V V VDD +0.2 VDD =3.0V V DD = 4.5V V V DD = 3.0V V DD +0.2 V DD = 5.5V V V DD +0.2 V DD = 3.0V ( ) VILS VDD V ( ) V IHS 0.7V DD - V DD+0.5 V V HY 0.2V DD V P0, P1, P2 I SR ?A V DD = 4.5V, V S = 2.4V ( ) P0, P1, P2 I SK ma V DD = 4.5V, V S = 0.45V ( ) P0, P1, P2 ( ) V OL V V DD = 4.5V, I OL = 20 ma V V DD = 2.7V, I OL = 3.2 ma SC6

106 P0, P1, P2 ( ) V OH V V DD = 4.5V, I OH = -16mA V DD = 2.7V, I OH = -3.2mA BOV=1 V BO V BOV=0 V BO V Vref V : *1. RST. *2. XTAL1 CMOS. *3. P2 P3 VIN 2V 29.2 ADC DC (VDD?VSS = 3.0~5V, TA = -40~85?C, Fosc = 20MHz,.) MIN. TYP. MAX. UNIT AVin V SS -0.2 V DD +0.2 V ADC ADCCLK 200KHz - 5MHz Hz ADC t C 52t ADC 1 DNL LSB INL LSB Ofe LSB Ge % Ae LSB : 1. tadc: ADC us

107 29.3 (VDD?VSS = 3.0~5V, TA = -40~85?C, Fosc = 20MHz, ) MIN. TYP. MAX. UNIT V CR 0 VDD-0.3 V CMRR -50 db t RS ns t EN us IIL ua 0< VIN <VDD 30. AC tclcl tclch tclcx tchcl tchcx : 50%. 31. TYP. t CHCX ns t CLCX ns Rise t CLCH ns Fall tchcl ns SC6

108 32. AC 1/t CLCL 0 20 MHz 33. C1 C2 R 4MHz ~ 20 MHz C1 XTAL1 R C2 XTAL2 W79E825 W79E

109 pin SOP 20L SOP-300mil E 1 10 Control demensions are in milmeters. E? SC6

110 pin DIP 20L PDIP 300mil 20 D 11 1 E 1 10 S E A 2 A 1 A Base Plane c L Seating Plane B B 1 e 1 a ea Symbol A A A B c D E e L a e S 1 2 B 1 E1 1 A Dimension in inch Min Nom Max Min Nom Max Dimension in mm

111 pin SOP 24L SOP-300mil E 1 12 Control demensions are in milmeters. E? SC6

112 35. SC SC ,6 SC ~91 W79E823 W79E822 W79E821 4 SC SC ~ SC6 2007/2/ PWM 4. CLRPWM DC 6. JTAG 1. ROM ICP Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: FAX: Taipei Office 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: FAX: Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: FAX: Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, Shinyokohama Kohoku-ku, Yokohama, TEL: FAX: Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, China TEL: FAX: Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: FAX: Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners