C8051F330/1 ISP FLASH : (024) :
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- 蹄圭 贰
- 5 years ago
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1 C8051F330/1 ISP FLASH C8051F330/1 ISP FLASH Rev : (024) :
2 C8051F330/1 ISP FLASH : (024) :
3 ADC F330 70% 200ksps 16 25MIPS 25MHz VREF VREF VDD 768 RAM C 8KB FLASH DAC F I/O 5V 0 UART SMBus SPI <0.4µA 4 16 / 16 / PCA 3 / PCA / 24.5MHz 2% UART 2.7V - 3.6V 80/40/20/10 khz 25MHz RC C 32KHz 0.1µA -40 C C 20 MLP A M U X ksps AD C DAC DIGITAL I/O UART SMBus SPI PCA P MHz 8KB ISP FLASH 8051 CPU 768 B SRAM (25MIPS) POR WDT : (024) :
4 CIP-51 TM I/O / DAC ADC ADC0 C8051F DAC IDA0 C8051F IDA On-Demand CNVSTR IDAC : (024) :
5 CIP CPU MOVX MCU VDD PCA FLASH FLASH FLASH FLASH FLASH FLASH : (024) :
6 12 RAM H-F C8051F330/1 H-F L-F L-F RC / I/O I/O SMBUS SMBUS SMBUS SCL SCL SMBus SMBUS SMBus SMBus SMBUS SMBUS UART UART : (024) :
7 UART SPI MOSI MISO SCK NSS SPI SPI SPI SPI PCA / / PCA : (024) :
8 20. C C C : (024) :
9 1. C8051F330/1 MCU CIP-51 25MIPS ksps 16 / ADC 10 DAC 25MHz 8KB FLASH 768 RAM SMBus/ I 2 C UART SPI / PCA VDD 175 I/O 5V VDD C8051F330/1 FLASH 8051 Cygnal C2 MCU C2 C V-3.6V I/O /RST 5V C8051F330/1 20 MLP MIPS FLASH RAM 24.5MHz 80KHz 1.1 SMBus/1 2 C SPI UART (16 ) I/O ksps ADC 10 DAC C8051F K MLP-20 C8051F K MLP-20 : (024) :
10 1.1 C8051F330 VDD GND /RST/C2CK XTAL1 XTAL2 / C2D POR 24.5MHz (2%) KB FLASH 256 SRAM 512 XRAM SFR 0 UART 0, 1, 2, 3 3 PCA/WDT SMBus SPI 1 X B A R P 0 P 1 P0.0/VREF P0.1/IDA0 P0.2/ XTAL1 P0.3/ XTAL2 P0.4/TX P0.5/RX P0.6/CNVST P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 CP khz VREF VDD ksps ADC VREF Temp A M U X - 10 DAC AIN0-AIN15 2 C2D P2.0/C2D 1.2 C8051F331 VDD GND /RST/C2CK XTAL1 XTAL2 / C2D POR 24.5MHz (2%) KB FLASH 256 SRAM 512 XRAM SFR 0 UART 0, 1, 2, 3 3 PCA/WDT SMBus SPI 1 X B A R P 0 P 1 P0.0/VREF P0.1/IDA0 P0.2/ XTAL1 P0.3/ XTAL2 P0.4/TX P0.5/RX P0.6/CNVST P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 CP khz - 2 C2D P2.0/C2D 8 : (024) :
11 1.1 CIP-51 TM C8051F330/1 Cygnal CIP-51 CIP-51 MCS-51 TM 803x/805x CIP / UART SPI 768 RAM 128 SFR 17 I/O CIP MUL DIV MHz CIP-51 70% CIP /3 3 3/4 4 4/ CIP-51 25MHz 25MIPS MCU Cygnal CIP-51 (25MHz clk) Microchip PIC17C75x (33MHz clk) Philips 80C51 (33MHz clk) ADuC (16MHz clk) : (024) :
12 1.1.3 C8051F330/1 MCU CIP-51 CIP MCU MCU 8 POR VDD V RST 0 FLASH / POR FLASH MCU WDT C8051F330/1 24.5MHz ± 2% 0.5% RC MCU 25MHz 1.4 VDD Px.x Px.x C0RSEF + - '0 ' ( ) /RST EN PCA WDT ( ) SWRSF MCD EN WDT FLASH XTAL1 XTAL2 CIP : (024) :
13 1.2 CIP RAM 128 RAM SFR RAM KB FLASH MCU 1.5 0x1FFF 0x1E00 0x1DFF / (FLASH) 0xFF 0x80 0x7F (RAM) 128 RAM ( ) ( ) 8K FLASH 0x30 0x2F ( 0x x1F ) 0x00 ( ) 128 RAM ( ) 0x0000 0xFFFF 0x0000-0x01FF RAM 512 0x0200 0x01FF 0x0000 XRAM ( MOVX ) : (024) :
14 1.3 C8051F330/1 Cygnal 2 C2 Cygnal RAM MCU ADC SMBus C8051F330DK C8051F330/1 MCU 8051 RS-232 C2 MCU RS-232 C2 Windows 95/98/Me/2000 RS PC RS C2 VDD GND V 20 ma Cygnal IDE MCU MCU Cygnal 1.6 / WINDOWS 95/98/NT/ME/2000 CYGNAL Integrated Development Environment RS-232 Serial Adapter C2 (x2), VDD, GND VDD GND TARGET PCB C8051F : (024) :
15 1.4 I/O C8051F I/O 8 1C8051F330/ I/O I/O 8051 I/O 1.7 / I/O I/O 1.7 XBR0, XBR1, PnMDOUT, PnMDIN PnSKIP UART ( ) SPI SMBus CP0 SYSCLK 2 8 P0 I/O P1 I/O P0.0 P0.7 P1.0 P1.7 PCA 4 T0, T1 ( ) P0 P1 2 8 (P0.0-P0.7) 8 (P1.0-P1.7) 1.5 C8051F330/1 MCU SMBus/I 2 C UART SPI CIP-51 CPU : (024) :
16 / MCU / PCA PCA 16 / 5 / /12 /4 0 ECI /8 PCA / 8 16 / 4 WDT / 4 WDTPCA / I/O I/O 1.8 PCA SYSCLK/12 SYSCLK/4 0 ECI SYSCLK PCA 16 / /8 / 0 / 1 / 2 / WDT CEX2 CEX1 CEX0 ECI I/O 14 : (024) :
17 / C8051F330/1 10 SAR ADC 16 ADC 200ksps 10 INL DNL 1LSB ADC ADC 0~1 ADC VDD ADC A/D ADC ADC / ADC P0.0 P0.7 P1.0 P1.7 VDD 18-1 AMUX AD0BUSY (W) 0 2 P0.0 P0.7 P AMUX (+) (-) 10 SAR ADC 16 ADC P1.7 VREF GND : (024) :
18 SET CLR SET CLR C8051F330/1 ISP FLASH 1.8 C8051F330/1 / I/O / MCU MCU CPT0MX CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3 CMX0P2 CMX0P1 CMX0P0 P0.0 CPT0CN CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 VDD P0.2 P0.4 P0.6 P1.0 P1.2 P1.4 P1.6 CP GND D Q Q D Q Q CP0 CP0A P0.1 P0.3 P0.5 CP0RIF CP0FIF CP0EN 0 1 EA 0 1 CP0 P0.7 CP0 - P1.1 P1.3 P1.5 P1.7 CPT0MD CP0RIE CP0FIE CP0MD1 CP0MD0 16 : (024) :
19 DAC C8051F / IDA0 IDA0 0.5mA 1mA 2mA IDA0 IDA0 IDA0H 1.11 IDA0 IDA0CN IDA0EN IDA0CM2 IDA0CM1 IDA0CM0 IDA0H CNVSTR IDA0OMD1 IDA0OMD0 IDA0H IDA0L IDA0 IDA0 : (024) :
20 * I/O /RST GND V VDD DGND V VDD GND 500 ma /RST 100 ma * MHz V RST V VDD=2.7V, CLK=25MHz 6.4 ma CPU VDD=2.7V, CLK= 1MHz 0.36 ma VDD=2.7V, CLK=80kHz VDD=2.7V, CLK=32kHz 20 9 µa µa VDD=2.7V, CLK=25MHz 3.2 ma CPU VDD=2.7V, CLK= 1MHz 180 µa FLASH VDD=2.7V, CLK=80kHz VDD=2.7V, CLK=32kHz µa µa VDD <0.1 µa RAM 1.5 V SYSCLK 0 25 MHz TSYSH SYSCLK 18 ns TSYSH SYSCLK 18 ns SYSCLK 32kHz 18 : (024) :
21 C8051F330/1 VDD 3 GND 2 /RST 4 I/O C2CK I/O P2.0 5 I/O C2D I/O VDD 10µs C2 2.0 P0.0 1 I/O 0.0 VREF VREF P I/O 0.1 P I/O 0.2 C2 XTAL1 P I/O XTAL2 0.3 I/O CMOS RC P I/O 0.4 P I/O 0.5 P I/O 0.6 CNVSTR ADC0 IDA0 P I/O 0.7 P I/O 1.0 P I/O 1.1 P I/O 1.2 P I/O 1.3 P1.4 9 I/O 1.4 P1.5 8 I/O 1.5 P1.6 7 I/O 1.6 P1.7 6 I/O 1.7 : (024) :
22 4.1 MLP P0.0 GND P0.6 P0.7 VDD GND P1.0 /RST/C2CK P1.1 P2.0/C2D P1.2 P1.7 P1.6 P1.5 P1.4 P1.3 P0.1 P0.2 P0.3 P0.4 P : (024) :
23 4.2 MLP MLP-20 b e L D2 2 DETAIL D2 18 E2 2 4 x e D 9 4 x e E A1 A2 E2 A 17 e A R DETAIL 1 AA BB MM MIN TYP MAX A A A A b D D E E e L N ND NE R AA BB CC DD CC DD : (024) :
24 5. 10 ADC ADC0 C8051F330 C8051F330 ADC0 16 AMUX0 200ksps 10 ADC ADC AMUX0 5.1 ADC0 P0~P1 VDD P0~P1 GND ADC ADC0CN AD0EN 1 ADC0 AD0EN 0 ADC0 5.1 ADC0 P0.0 AMX0P ADC0CN P0.7 P AMUX AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 P1.7 VDD P0.0 P0.7 P AMUX (+) (-) VDD 10 SAR ADC 000 AD0BUSY (W) CNVSTR ADC0L ADC0H P1.7 VREF GND AMX0N AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0LJST ADC0CF REF SYSCLK ADC0LTH ADC0GTH ADC0LTL ADC0GTL 32 AD0WINT 22 : (024) :
25 5.1 AMUX0 ADC P0~P1 VDD P0~P1 VREF GND GND ADC0 ADC0 ADC0 AMX0P AMUX0N ADC0H ADC0L ADC ADC0H:ADC0L AD0LJST 10 0 VREF*1023/1024 ADC0H:ADC0L (AD0LJST = 0) ADC0H:ADC0L (AD0LJST = 1) VREF*1023/1024 0x03FF 0xFFC0 VREF*512/1024 0x0200 0x8000 VREF*256/1024 0x0100 0x x0000 0x VREF ~ VREF*511/512 ADC0H ADC0L 0 ADC0H:ADC0L (AD0LJST = 0) ADC0H:ADC0L (AD0LJST = 1) VREF*511/512 0x01FF 0x7FC0 VREF*256/512 0x0100 0x x0000 0x0000 -VREF*256/512 0xFF00 0xC000 -VREF 0xFC00 0x8000 ADC0 PnMDIN n=0,1 0 PnSKIP n=0,1 1 : (024) :
26 AMX0P AMX0P4-0 V TEMP ADC ( ) V TEMP = 2.86(TEMP C ) mv ( ) 24 : (024) :
27 5.3 ADC0 200ksps ADC0 ADC0CF AD0SC / AD0SC+1 0 AD0SC A/D ADC0CN ADC0 AD0CM ADC0CN AD0BUSY CNVSTR P AD0BUSY 1 ADC0 AD0BUSY 1 0 AD0BUSY ADC0CN AD0INT ADC0 AD0INT ADC AD0INT 1 ADC CNVSTR P0.6 CNVSTR P0.6 P0.6 P0SKIP 6 1 I/O 14. / : (024) :
28 5.3.2 ADC0CN AD0TM ADC0 ADC0 AD0TM 1 ADC0 3 SAR CNVSTR CNVSTR CNVSTR 5.3 AMUX ADC CNVSTR (AD0CM[2:0]=100) ADC A. ADC SAR AD0TM=1 AD0TM=0 B. ADC 0, 2 1, 3 (AD0CM[2:0]=000, 001, , 101) SAR AD0TM=1 SAR AD0TM=0 26 : (024) :
29 5.3.3 ADC AMUX0 AMUX0 ADC0 SAR SAR 5.4 ADC0 SA ADC0 5.1 VDD GND R TOTAL R MUX 5.1 ADC0 5.1 ADC0 SA t = ln R n TOTALCSAMPLE 2 SA LSB /4 LSB t R TOTAL AMUX0 n ADC ADC0 MUX MUX P0.x R MUX =5k P0.x R MUX =5k C SAMPLE = 5pF C SAMPLE = 5 pf RC Input =R MUX *C SAMPLE RC Input =R MUX *C SAMPLE C SAMPLE = 5pF P0.y R MUX = 5k MUX : (024) :
30 5.5 AMUX0P: AMUX0 R R R R/W R/W R/W R/W R/W AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P SFR 0xBB 7-5 =000b = 4-0 AMX0P4-0 AMUX0 AMX0P3-0 ADC P P P P P P P P P P P P P P P P VDD 10010~ : (024) :
31 5.6 AMUX0N: AMUX0 R R R R/W R/W R/W R/W R/W AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N SFR 0xBA 7-5 =000b = 4-0 AMX0N4-0 AMUX0 GND ADC0 ADC0 AMX0N4-0 ADC P P P P P P P P P P P P P P P P VREF GND ADC 10010~11111 : (024) :
32 5.7 ADC0CF: ADC0 R/W R/W R/W R/W R/W R/W R R AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0LJST SFR 0xBC 7-3 AD0SC4-0 ADC0 SAR SAR AD0SC AD0SC4-0 5 CLK SAR ADC0 SAR SYSCLK AD 0SC = 1 CLK SAR 2 AD0LJST ADC0 0 ADC0H:ADC0L 1 ADC0H:ADC0L 1-0 =00b = 5.8 ADC0H: ADC0 R/W R/W R/W R/W R/W R/W R/W R/W SFR 0xBE 7-0 ADC0 AD0LJST = 0 7~2 1 1~0 10 ADC0 2 AD0LJST = 1 7~0 10 ADC ADC0L: ADC0 R/W R/W R/W R/W R/W R/W R/W R/W SFR 0xBD 7-0 ADC0 AD0LJST = 0 7~0 10 ADC0 8 AD0LJST = 1 7~6 10 ADC0 2 5~ : (024) :
33 5.10 ADC0CN: ADC0 R/W R/W R/W R/W R/W R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM SFR ( ) 0xE8 7 AD0EN ADC0 0 ADC0 ADC0 1 ADC0 ADC0 6 AD0TM ADC0 0 ADC0 1 AD0CM2-0 5 AD0INT ADC0 0 0 ADC0 1 ADC0 4 AD0BUSY ADC0 0 ADC0 AD0INT AD0BUSY 1 1 ADC0 0 1 AD0CM b ADC0 3 AD0WINT ADC0 0 ADC0 1 ADC0 2-0 AD0CM2-0 ADC0 AD0TM = AD0BUSY 1 ADC ADC ADC ADC0 100 CNVSTR ADC ADC0 11x AD0TM = AD0BUSY 1 3 SAR SAR SAR SAR 100 ADC0 CNVSTR CNVSTR SAR 111 : (024) :
34 5.4 ADC ADC0 CPU ADC0CN AD0WINT ADC0 ADC0GT ADC0 ADC0LT ADC0GT ADC0LT 5.11 ADC0GTH: ADC0 R/W R/W R/W R/W R/W R/W R/W R/W SFR 0xC4 7-0 ADC ADC0GTL: ADC0 R/W R/W R/W R/W R/W R/W R/W R/W SFR 0xC3 7-0 ADC ADC0LTH: ADC0 R/W R/W R/W R/W R/W R/W R/W R/W SFR 0xC6 7-0 ADC ADC0LTL: ADC0 R/W R/W R/W R/W R/W R/W R/W R/W SFR 0xC5 7-0 ADC0 32 : (024) :
35 ADC0LTH:ADC0LTL = 0x0080 ADC0GTH:ADC0GTL = 0x0040 ADC0LTH:ADC0LTL = 0x0040 ADC0GTH:ADC0GTL = 0x ~ VREF*1023/1024 ADC0 ADC0GTH:ADC0GT ADC0LTH:ADC0LTL 0x0040 < ADC0H:ADC0L < 0x0080 AD0WINT ADC0 ADC0GT ADC0LT ADC0H:ADC0L < 0x0040 ADC0H:ADC0L > 0x0080 AD0WINT ADC (Px.x - GND) ADC0H:ADC0L (Px.x - GND) ADC0H:ADC0L VREF x (1023/1024) 0x03FF VREF x (1023/1024) 0x03FF AD0WINT AD0WINT=1 0x0081 0x0081 VREF x (128/1024) 0x0080 0x007F 0x0041 ADC0LTH:ADC0LTL AD0WINT=1 VREF x (128/1024) 0x0080 0x007F 0x0041 ADC0GTH:ADC0GTL AD0WINT VREF x (64/1024) 0x0040 ADC0GTH:ADC0GTL VREF x (64/1024) 0x0040 ADC0LTH:ADC0LTL 0x003F 0x003F AD0WINT AD0WINT=1 0 0x x ADC (Px.x - GND) ADC0H:ADC0L (Px.x - GND) ADC0H:ADC0L VREF x (1023/1024) 0xFFC0 VREF x (1023/1024) 0xFFC0 AD0WINT AD0WINT=1 0x2040 0x2040 VREF x (128/1024) 0x2000 0x1FC0 0x1040 ADC0LTH:ADC0LTL AD0WINT=1 VREF x (128/1024) 0x2000 0x1FC0 0x1040 ADC0GTH:ADC0GTL AD0WINT VREF x (64/1024) 0x1000 ADC0GTH:ADC0GTL VREF x (64/1024) 0x1000 ADC0LTH:ADC0LTL 0x0FC0 0x0FC0 AD0WINT AD0WINT=1 0 0x x0000 : (024) :
36 ADC0LTH:ADC0LTL = 0x d ADC0GTH:ADC0GTL = 0xFFFF -1d ADC0LTH:ADC0LTL = 0xFFFF -1d ADC0GTH:ADC0GTL = 0x d VREF ~ VREF*511/512 ADC0 ADC0H:ADC0L ADC0GTH:ADC0GT ADC0LTH:ADC0LTL 0xFFFF -1d < ADC0H:ADC0L< 0x d AD0WINT ADC0 ADC0H:ADC0L ADC0H:ADC0L < 0xFFFF -1d ADC0H:ADC0L > 0x d ADC0GT ADC0LT AD0WINT 5.17 ADC (Px.x - Px.x) ADC0H:ADC0L (Px.x - Px.x) ADC0H:ADC0L VREF x (511/512) 0x01FF VREF x (511/512) 0x01FF AD0WINT AD0WINT=1 0x0041 0x0041 VREF x (64/512) 0x0040 0x003F 0x0000 ADC0LTH:ADC0LTL AD0WINT=1 VREF x (64/512) 0x0040 0x003F 0x0000 ADC0GTH:ADC0GTL AD0WINT VREF x (-1/512) 0xFFFF ADC0GTH:ADC0GTL VREF x (-1/512) 0xFFFF ADC0LTH:ADC0LTL 0xFFFE 0xFFFE AD0WINT AD0WINT=1 -VREF 0x0200 -VREF 0x : (024) :
37 5.18 ADC (Px.x - Px.x) ADC0H:ADC0L (Px.x - Px.y) ADC0H:ADC0L VREF x (511/512) 0x7FC0 VREF x (511/512) 0x7FC0 AD0WINT AD0WINT=1 0x1040 0x1040 VREF x (64/512) 0x1000 0x0FC0 0x0000 ADC0LTH:ADC0LTL AD0WINT=1 VREF x (64/512) 0x1000 0x0FC0 0x0000 ADC0GTH:ADC0GTL AD0WINT VREF x (-1/512) 0xFFC0 ADC0GTH:ADC0GTL VREF x (-1/512) 0xFFC0 ADC0LTH:ADC0LTL 0xFF80 0xFF80 AD0WINT AD0WINT=1 -VREF 0x8000 -VREF 0x8000 : (024) :
38 5.1 ADC0 VDD=3.0V, VREF=2.40V(REFSL=0), -40 o C +85 o C LSB LSB 0 LSB -1 LSB 10 ppm/ 10kHz 0-1dB 200ksps db 5-67 db 78 db SAR 3 MHz SAR 10 / 300 ns 200 ksps AIN+-GND ADC AIN+-AIN- GND 0 -VREF VREF VREF 0 VDD V 5 pf mv/ 1 2 = mv VDD 200ksps µa ADC0 0.3 mv/v V V 1 2 ADC 36 : (024) :
39 6. 10 DAC IDA0 C8051F330 C8051F330 / IDAC IDAC 0.5mA 1mA 2mA IDA0 IDA0EN IDAC 6.3 IDA0EN 0 IDAC P0.1 GPIO IDA0EN 1 IDAC IDAC IDAC IDAC P0SKIP 1 1 IDAC 6.1 IDA0 IDA0 IDA0 IDA0H On-Demand IDA0 On-Demand IDA0 IDA0H IDA0L IDA0H IDA0 IDAC IDA0L IDA0H IDA0H IDA0 10 IDA0L IDA0H IDAC 8 IDA0L 0x00 IDA0H 6.1 IDA0 IDA0CN IDA0EN IDA0CM2 IDA0CM1 IDA0CM0 IDA0H CNVSTR IDA0OMD1 IDA0OMD0 IDA0H IDA0L IDA0 IDA0 : (024) :
40 6.1.2 ADC IDAC IDAC IDA0CM IDA0CN.[6:4] IDAC IDA0L IDA0H IDA0H:IDA0L IDAC IDAC CNVSTR IDAC CNVSTR IDA0CM IDA0CN.[6:4] IDA0L IDA0H IDAC CNVSTR IDA0CM IDAC CNVSTR IDA0H:IDA0L IDAC IDAC 6.2 IDAC IDAC IDA0H IDA0L 8 IDA0H IDAC IDAC 7-0 IDAC 2 IDA0L IDA0 IDA0H D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IDA0L D9 D0 IDA0OMD[1:0]= 1x IDA0OMD[1:0]= 01 IDA0OMD[1:0]= 00 0x000 0 ma 0 ma 0 ma 0x001 1/1024 x 2 ma 1/1024 x 1 ma 1/1024 x 0.5 ma 0x /1024 x 2 ma 512/1024 x 1 ma 512/1024 x 0.5 ma 0x3FF 1023/1024 x 2 ma 1023/1024 x 1 ma 1023/1024 x 0.5 ma 38 : (024) :
41 6.3 IDA0CN: IDA0 R/W R/W R/W R/W R R R/W R/W IDA0EN IDA0CM - - IDA0OMD SFR 0xB9 7 IDA0EN IDA0 0 IDA0 1 IDA0 6-4 IDA0CM[2:0] IDA IDA IDA IDA IDA0 100 CNVSTR IDA0 101 CNVSTR IDA0 110 CNVSTR IDA0 111 IDA0H IDA0 3-2 = 00b = 0 ADC0 1 ADC0 1-0 IDA0OMD[1:0] IDA ma ma 1x 1.0 ma 6.4 IDA0H: IDA0 R/W R/W R/W R/W R/W R/W R/W R/W SFR 0x IDA0 7~0 10 IDA0 8 : (024) :
42 6.5 IDA0L: IDA0 R/W R/W R/W R/W R/W R/W R/W R/W SFR 0x ADC = 00000b = 40 : (024) :
43 VDD=3.0V 6.1 ADC0 2 ma -40 o C +85 o C LSB LSB VDD-1.2 V I OUT = TBD R LOAD =TBD TBD PA/rtHz 0 LSB 2 ma 0 LSB 30 ppm/ VDD 52 db TBD kω TBD pf 10kHz 0-1dB 200ksps TBD ma/µs 1/2LSB 5 µs 5 µs VDD IDAC 1 ma 0.5 ma 2 ma 1 ma 0.5 ma % % µa µa µa : (024) :
44 7. C8051F330/1 MUX VDD 7.1 REF0CN REFSL REFSL 0 VDD REFSL 1 REF0CN BIASE ADC DAC BIASE 1 REF0CN BIASE REF0CN V VREF REF0CN REFBE VREF GND 0.1 µf 4.7 µf REFBE P0.0 VREF VREF P0.0 P0.0 P0MDIN 0 0 P0.0 P0SKIP 0 1 I/O 14 /REF0CN TEMPE / 42 : (024) :
45 7.1 REF0CN REFSL TEMPE BIASE REFBE EN ADC, IDAC, VDD R1 VREF 0 IOSCEN EN Mux GND VDD 1 VREF ( ADC) REFBE EN : (024) :
46 7.2 REF0CN: R R R R R/W R/W R/W R/W REFSL TEMPE BIASE REFBE SFR 0xD1 7-4 = 0000b = 3 REFSL 0 VREF 1 VDD 2 TEMPE BIASE REFBE 0 1 VREF 6.1 VDD=3.0V REFBE V VREF 10 ma VREF 15 ppm/ = 0-200µA AGND 0.5 ppm/µa VREF 1 4.7µF 0.1µF 2 VREF 2 0.1µF 20 µs VREF 3 10 µs 140 ppm/v REFBE 0 0 VDD V = 200ksps VREF=3.0V 12 µa ADC BIASE = µa 40 µa ms 44 : (024) :
47 SET CLR SET CLR C8051F330/1 ISP FLASH 8. C8051F330/ CP0 CP0A CP0A CPT0MX CMX0P1 CMX0P0 CMX0N1 CMX0N I/O CPT0MX CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3 CMX0P2 CMX0P1 CMX0P0 P0.0 P0.2 P0.4 CPT0CN CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 VDD P0.6 P1.0 P1.2 P1.4 P1.6 CP GND D Q Q D Q Q CP0 CP0A P0.1 P0.3 P0.5 CP0RIF CP0FIF CP0EN 0 1 EA 0 1 CP0 P0.7 CP0 - P1.1 P1.3 P1.5 P1.7 CPT0MD CP0RIE CP0FIE CP0MD1 CP0MD0 : (024) :
48 I/O 100 na V (VDD) V 8.1 CPT0MD VIN+ CP0- VIN- CP0+ + CP0 _ OUT ( CP0HYP ) VIN- VIN+ ( CP0HYN ) VOL VOH CPT0CN CPT0CN CP0HYN mV 10mV 5mV CP0HYP 1 CP0FIF 1 CP0RIF 1 1 CP0RIE 1 CP0FIE 46 : (024) :
49 1 CP0OUT 1 CP0EN CPT0CN: 0 R/W R R/W R/W R/W R/W R/W R/W CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN SFR 0x9B 7 CP0EN CP0OUT 0 0 CP0+ < CP0-1 CP0+ > CP0-5 CP0RIF CP0FIF CP0HYP = 5mV 10 = 10mV 11 = 20mV 1-0 CP0HYN = 5mV 10 = 10mV 11 = 20mV : (024) :
50 8.4 CPT0MX: 0 MUX R/W R/W R/W R/W R/W R/W R/W R/W CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3 CMX0P2 CMX0P1 CMX0P SFR 0x9F 7-4 CMX0N3-0: 0 MUX 0 CMX0N3 CMX0N2 CMX0N1 CMX0N P P P P P P P P1.7 1 x x x 3-0 CMX0P3-0: 0 MUX 0 CMX0P1 CMX0P0 CMX0P1 CMX0P P P P P P P P P1.6 1 x x x 48 : (024) :
51 8.5 CPT0MD: R/W R/W R/W R/W R/W R/W R/W R/W - - CP0RIE CP0FIE - - CP0MD1 CP0MD SFR 0x9D 7-6 = 00b = 5 CP0RIE CP0FIE = 00b = 1-0 CP0MD CP0MD1 CP0MD0 CP ns ns ns ns : (024) :
52 8.1 VDD=3.0V, (CP0+) - (CP0-) = 100mV 100 ns 0 Vcm =1.5V (CP0+) - (CP0-) = -100mV 250 ns (CP0+) - (CP0-) = 100mV 175 ns 1 Vcm =1.5V (CP0+) - (CP0-) = -100mV 500 ns (CP0+) - (CP0-) = 100mV 320 ns 2 Vcm =1.5V (CP0+) - (CP0-) = -100mV 1100 ns (CP0+) - (CP0-) = 100mV 1050 ns 3 Vcm =1.5V (CP0+) - (CP0-) = -100mV 5200 ns mv/v 1 CP0HYP1-0 = mv 2 CP0HYP1-0 = mv 3 CP0HYP1-0 = mv 4 CP0HYP1-0 = mv 1 CP0HYN1-0 = mv 2 CP0HYN1-0 = mv 3 CP0HYN1-0 = mv 4 CP0HYN1-0 = mv VDD+0.25 V 4 pf na mv mv/v 10 µs DC µa µa µa µa Vcm CP0+ CP0-50 : (024) :
53 9. CIP-51 MCU CIP-51 CIP-51 MCS-51 TM 803x/805x MCU / 18 UART 16 SPI RAM 128 SFR 17 I/O 14 CIP MCU CIP CIP-51 MCS-51 25MHz 25MIPS 0 25MHz 256 RAM 17 I/O 9.1 CIP-51 B PSW TMP1 ALU TMP2 SRAM SRAM (256 X 8) D8 D8 D8 SFR SFR SFR SFR SFR PC D8 D8 A16 D8 D8 : (024) :
54 CIP MUL DIV MHz CIP-5170% CIP-51 25MHz 25MIPS CIP /3 3 3/4 4 4/ FLASH Cygnal 2 C2 MOVC MOVX FLASH / RAM C2 20. C2 CIP-51 Cygnal Cygnal IDE IDE CIP-51 C2 C 9.1 CIP-51 MCS-51 TM 8051 CIP-51 CIP-51 MCS-51 TM PSW CPU CIP-51 CIP CIP MOVX MOVX C8051F330/1 CIP-51 MOVX FLASH CIP FLASH 52 : (024) :
55 9.1 CIP-51 ADD A,Rn 1 1 ADD A,direct 2 2 ADD A,@Ri RAM 1 2 ADD A,#data 2 2 ADDC A,Rn ( ) 1 1 ADDC A,direct ( ) 2 2 ADDC A,@Ri RAM ( ) 1 2 ADDC A,#data ( ) 2 2 SUBB A,Rn ( ) 1 1 SUBB A,direct RAM( ) 2 2 SUBB A,@Ri RAM( ) 1 2 SUBB A,#data ( ) 2 2 INC A INC Rn INC direct RAM DEC A DEC Rn DEC direct RAM INC DPTR MUL AB B 1 4 DIV AB B 1 8 DA A 1 1 ANL A,Rn 1 1 ANL A,direct 2 2 ANL A,@Ri RAM 1 2 ANL A,#data 2 2 ANL direct,a 2 2 ANL direct,#data 3 3 ORL A,Rn 1 1 ORL A,direct 2 2 ORL A,@Ri RAM 1 2 ORL A,#data 2 2 ORL direct,a 2 2 ORL direct,#data 3 3 XRL A,Rn 1 1 XRL A,direct 2 2 XRL A,@Ri RAM 1 2 XRL A,#data 2 2 XRL direct,a 2 2 XRL direct,#data 3 3 CLR A 1 1 CPL A 1 1 RL A 1 1 RLC A 1 1 : (024) :
56 RR A 1 1 RRC A 1 1 SWAP A 1 1 MOV A,Rn A 1 1 MOV A,direct 2 2 MOV A,@Ri RAM 1 2 MOV A,#data 2 2 MOV Rn,A 1 1 MOV Rn,direct 2 2 MOV Rn,#data 2 2 MOV direct,a 2 2 MOV direct,rn 2 2 MOV direct,direct 3 3 MOV direct,@ri RAM 2 2 MOV direct,#data 3 3 RAM 1 2 RAM 2 2 RAM 2 2 MOV DPTR,#data MOVC A,@A+DPTR 1 3 MOVC A,@A+PC 1 3 MOVX A,@Ri RAM(8 ) A 1 3 RAM MOVX A,@DPTR RAM(16 ) A 1 3 RAM PUSH direct 2 2 POP direct 2 2 XCH A,Rn 1 1 XCH A,direct 2 2 XCH A,@Ri RAM 1 2 XCHD A,@Ri RAM 1 2 CLR C 1 1 CLR bit 2 2 SETB C SETB bit 2 2 CPL C 1 1 CPL bit 2 2 ANL C,bit 2 2 ANL C,/bit 2 2 ORL C,bit 2 2 ORL C,/bit 2 2 MOV C,bit 2 2 MOV bit,c 2 2 JC rel 1 2 2/3 JNC rel 2 2/3 JB bit,rel 1 3 3/4 JNB bit,rel 3 3/4 JBC bit,rel 1 3 3/4 54 : (024) :
57 ACALL addr LCALL addr RET 1 5 RETI 1 5 AJMP addr LJMP addr SJMP rel 2 3 DPTR 1 3 JZ rel 0 2 2/3 JNZ rel 0 2 2/3 CJNE A,direct,rel A 3 3/4 CJNE A,#data,rel A 3 3/4 CJNE Rn,#data,rel 3 3/4 RAM 3 4/5 DJNZ Rn,rel 1 2 2/3 DJNZ direct,rel 1 3 3/4 NOP 1 1 Rn R0-R1 RAM rel 8 2 SJMP direct 8 RAM 0x00-0x7F SFR 0x80-0xFF #data 8 #data16 16 bit RAM SFR addr11 ACALL AJMP 11 2K addr16 LCALL LJMP 16 64K 0xA5 NOP : (024) :
58 9.2 CIP CIP x1FFF 0x1E00 0x1DFF / (FLASH) 0xFF 0x80 0x7F (RAM) 128 RAM ( ) ( ) 8K FLASH 0x30 0x2F ( 0x x1F ) 0x00 ( ) 128 RAM ( ) 0x0000 0xFFFF 0x0000-0x01FF RAM 512 0x0200 0x01FF 0x0000 XRAM ( MOVX ) CIP-51 64KB C8051F330/1 8KB FLASH 0x0000 0x1DFF 0x1E00 CIP-51 PSCTL.0 MOVX CIP FLASH 56 : (024) :
59 9.2.2 CIP RAM 0x00 0xFF x00 0x1F x20 0x2F SFR SFR 0x7F CPU 128 SFR SFR 0x7F CIP x00 0x1F 8 R0 - R7 4 RS0 PSW.3 RS1 PSW PSW R0 R x20 0x2F x00 0x7F 0x20 0 0x00 0x20 7 0x07 0x2F 7 0x7F MCS-51 TM XX. B XX B MOV C 22h. 3 0x13 0x SP 0x81 SFR SP SP+1 SP 1 0x07 0x08 1 R0 SP 256 : (024) :
60 x80 0xFF SFR SFR CIP-51 CIP-51 CIP SFR SFR MCS-51 TM 9.2 CIP-51 SFR 0x80~0xFF SFR 0x0 0x8 SFR P0 TCON P1 SCON IE SFR SFR F8 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 VDM0CN F0 B P0MDIN P1MDIN EIP1 E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 RSTSRC E0 ACC XBR0 XBR1 OSCLCN IT01CF EIE1 D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 D0 PSW REF0CN P0SKIP P1SKIP C8 TMR2CN TMR2RLL TMR2RLH TMR2L TMR2H C0 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH B8 IP IDA0CN AMX0N AMX0P ADC0CF ADC0L ADC0H B0 OSCXCN OSCICN OSCICL FLSCL FLKEY A8 IE CLKSL EMI0CN A0 P2 SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT 98 SCON0 SBUF0 CPT0CN CPT0MD CPT0MX 90 P1 TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H IDA0L IDA0H 88 TCON TMOD TL0 TL1 TH0 TH1 CKCON PSCTL 80 P0 SP DPL DPH PCON 0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F) 58 : (024) :
61 9.3 SFR SFR ACC 0xE0 80 ADC0CF 0xBC ADC0 43 ADC0CN 0xE8 ADC0 45 ADC0GTH 0xC4 ADC0 46 ADC0GTL 0xC3 ADC0 46 ADC0H 0xBE ADC0 43 ADC0L 0xBD ADC0 44 ADC0LTH 0xC6 ADC0 47 ADC0LTL 0xC6 ADC0 47 AMX0N 0xBA AMUX0 42 AMX0P 0xBB AMUX0 41 B 0xF0 B 80 CKCON 0x8E 175 CLKSEL 0xA9 112 CPT0CN 0x9B 0 62 CPT0MD 0x9D 0 64 CPT0MX 0x9F 0 MUX 63 DPH 0x83 78 DPL 0x82 78 EIE1 0xE EIP1 0xF EMI0CN 0xAA 103 FLKEY 0xB7 FLASH 101 FLSCL 0xB6 FLASH 101 IDA0CN 0xB9 DAC0 53 IDA0H 0x97 DAC0 53 IDA0L 0x96 DAC0 54 IE 0xA8 84 IP 0xB8 85 IT01CF 0xE4 INT0/INT1 88 OSCICL 0xB3 107 OSCICN 0xB2 107 OSCLCN 0xE3 108 OSCXCN 0xB1 110 P0 0x P0MDIN 0xF P0MDOUT 0xA P0SKIP 0xD : (024) :
62 9.3 SFR SFR P1 0x P1MDIN 0xF P1MDOUT 0xA P1SKIP 0xD P2 0xA P2MDOUT 0xA PCA0CN 0xD8 PCA 196 PCA0CPH0 0xFC PCA PCA0CPH1 0xEA PCA PCA0CPH2 0xEC PCA PCA0CPL0 0xFB PCA PCA0CPL1 0xE9 PCA PCA0CPL2 0xEB PCA PCA0CPM0 0xDA PCA PCA0CPM1 0xDB PCA PCA0CPM2 0xDC PCA PCA0H 0xFA PCA 199 PCA0L 0xF9 PCA 199 PCA0MD 0xD9 PCA 197 PCON 0x87 90 PSCTL 0x8F 100 PSW 0xD0 79 REF0CN 0xD1 58 RSTSRC 0xEF 95 SBUF0 0x99 UART0 151 SCON0 0x98 UART0 150 SMB0CF 0xC1 SMBus 134 SMB0CN 0xC0 SMBus 136 SMB0DAT 0xC2 SMBus 138 SP 0x81 79 SPI0CFG 0xA1 SPI 162 SPI0CKR 0xA2 SPI 164 SPI0CN 0xF8 SPI 163 SPI0DAT 0xA3 SPI 165 TCON 0x88 / 173 TH0 0x8C / TH1 0x8D / TL0 0x8A / TL1 0x8B / TMOD 0x89 / : (024) :
63 9.3 SFR SFR TMR2CN 0xC8 / TMR2H 0xCD / TMR2L 0xCC / TMR2RLH 0xCB / TMR2RLL 0xCA / TMR3CN 0x91 / TMR3H 0x95 / TMR3L 0x94 / TMR3RLH 0x93 / TMR3RLL 0x92 / VDM0CN 0xFF VDD 93 XBR0 0xE1 I/O XBR1 0xE2 I/O CIP-51 SFR 1 0 SFR 9.3 DPL R/W R/W R/W R/W R/W R/W R/W R/W SFR 0x DPL DPL 16 DPTR DPTR FLASH XRAM 9.4 DPH R/W R/W R/W R/W R/W R/W R/W R/W SFR 0x DPH DPH 16 DPTR DPTR FLASH XRAM : (024) :
64 9.5 SP R/W R/W R/W R/W R/W R/W R/W R/W SFR 0x SP PUSH 1 SP 0x PSW R/W R/W R/W R/W R/W R/W R/W R/W CY AC F0 RS1 RS0 OV F1 PARITY SFR ( ) 0xD0 7 CY AC F RS1-RS0 RS1 RS x00-0x x08-0x0F x10-0x x18-0x1F 2 OV ( ) ( ) F1 1 0 PARITY : (024) :
65 9.7 ACC R/W R/W R/W R/W R/W R/W R/W R/W ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC SFR ( ) 0xE0 7-0 ACC 9.8 B B R/W R/W R/W R/W R/W R/W R/W R/W B.7 B.6 B.5 B.4 B.3 B.2 B.1 B SFR ( ) 0xF0 7-0 B B : (024) :
66 9.3 CIP SFR 1 CPU LCALL ISR ISR RETI 1 / SFR IE EIE1 EA IE EA CPU ISR ISR CPU RETI CPU ISR MCU MCU 13 1 CPU ISR 9.4 MCU /INT0 /INT1 IT01CF IN0PL /INT0 IN1PL /INT1 TCON IT0 IT1 IT0 IN0PL /INT0 IT1 IN1PL /INT /INT0 /INT1 IT01CF 9.13 /INT0 /INT0 /INT0 /INT1 /INT0 /INT1 XBR : (024) :
67 IE0 TCON.1 IE1 TCON.3 /INT0 /INT1 /INT0 /INT1 CPU ISR IN0PL IN1PL 1 0 ISR SFR IP EIP CPU 5 4 ISR LCALL CPU RETI CPU RETI DIV RETI 8 DIV 4 ISR LCALL CPU ISR ISR RETI : (024) :
68 9.4 0x0000 N/A N/A 0 (/INT0) 0x IE0 (TCON.1) Y Y EX0 (IE.0) PX0 (IP.0) 0 0x000B 1 TF0 (TCON.5) Y Y ET0 (IE.1) PT0 (IP.1) 1 (INT1) 0x IE1 (TCON.3) Y Y EX1 (IE.2) PX1 (IP.2) 1 0x001B 3 TF1 (TCON.7) Y Y ET1 (IE.3) PT1 (IP.3) UART0 0x x002B 5 SPI0 0x RI0 (SCON0.0) TI0 (SCON0.1) TF2H (TMR2CN.7) TF2L (TMR2CN.6) SPIF (SPI0CN.7) WCOL (SPI0CN.6) MODF (SPI0CN.5) RXOVRN (SPI0CN.4) SMB0 0x003B 7 SI (SMB0CN.0) Y N Y N ES0 (IE.4) PS0 (IP.4) Y N ET2 (IE.5) PT2 (IP.5) Y N ESPI0 (IE.6) ESMB0 (EIE1.0) 0x N/A N/A N/A N/A N/A ADC0 0x004B 9 ADC0 0x x005B x AD0WINT (ADC0CN.3) AD0INT (ADC0CN.5) CF (PCA0CN.7) CCFn (PCA0CN.n) CP0FIF (CPT0CN.4) CP0RIF (CPT0CN.5) Y Y Y N N N N N EWADC0 (EIE1.2) EADC0C (EIE1.3) EPCA0 (EIE1.4) ECP0 (EIE1.5) 0x N/A N/A N/A N/A N/A 3 0x TF3H (TMR3CN.7) TF3L (TMR3CN.6) N N ET3 (EIE1.7) PSPI0 (IP.6) PSMB0 (EIP1.0) PWADC0 (EIP1.2) PADC0C (EIP1.3) PPCA0 (EIP1.4) PCP0 (EIP1.5) PT3 (EIP1.7) 66 : (024) :
69 IE R/W R/W R/W R/W R/W R/W R/W R/W EA ESPI0 ET2 ES0 ET1 EX1 ET0 EX SFR ( ) 0xA8 7 EA ESPI0 SPI0 SPI0 0 SPI0 1 SPI0 5 ET TF2L TF2H 4 ES0 UART0 UART0 0 UART0 1 UART0 3 ET TF1 2 EX /INT1 1 ET TF0 0 EX /INT0 : (024) :
70 9.10 IP R/W R/W R/W R/W R/W R/W R/W R/W - PSPI0 PT2 PS0 PT1 PX1 PT0 PX SFR ( ) 0xB8 7 =1b = 6 PSPI0 SPI0 SPI0 0 SPI0 1 SPI0 5 PT PS0 UART0 UART0 0 UART0 1 UART1 3 PT PX PT PX : (024) :
71 9.11 EIE1 1 R/W R/W R/W R/W R/W R/W R/W R/W ET3 ECP0 EPCA0 EADC0 EWADC0 ESMB SFR 0xE6 7 ET TF3L TF3H 6 =0b 0 5 ECP0 0 CP0 CP0 0 CP0 1 CP0RIF CP0FIF 4 EPCA0 PCA0 PCA0 0 PCA0 1 PCA0 3 EADC0C ADC0 ADC0 0 ADC0 1 AD0INT 2 EWADC0 ADC0 ADC0 0 ADC0 1 ADC0 1 =0b 0 0 ESMB0 SMBus SMBus SMB0 0 SMB0 1 SMB0 : (024) :
72 9.12 EIP1 1 R/W R/W R/W R/W R/W R/W R/W R/W PT3 PCP0 PPCA0 PADC0 PWADC0 PSMB SFR 0xF6 7 PT =0b 0 5 PCP0 0 CP0 CP0 0 CP0 1 CP0 4 PPCA0 PCA0 0 PCA0 1 PCA0 3 PADC0 ADC0 ADC0 0 ADC0 1 ADC0 2 PWADC0 ADC0 ADC0 0 ADC0 1 ADC0 1 =0b 0 0 PSMB0 SMBus SMBus 0 SMBus 1 SMBus 70 : (024) :
73 9.13 INT01CF INT0/INT1 R/W R/W R/W R/W R/W R/W R/W R/W IN1PL IN1SL2 IN1SL1 IN1SL0 IN0PL IN0SL2 IN0SL1 IN0SL SFR 0xE4 7 IN1PL /INT1 0 /INT1 1 /INT1 6-4 IN1SL2-0 /INT1 /INT1 /INT1 P0SKIP 1 IN1SL2-0 /INT1 000 P P P P P P P P0.7 3 IN0PL /INT0 0 /INT0 1 /INT0 2-0 IN0SL2-0 /INT0 /INT0 /INT0 P0SKIP 1 IN0SL2-0 /INT0 000 P P P P P P P P0.7 : (024) :
74 9.4 CIP-51 CPU CPU 9.14 CIP-51 CIP MCU MCU PCON.0 1 CIP-51 CPU 1 MCU PCON.0 0 CPU RETI CIP-51 0x0000 WDT PCON WDT PCON.1 1 CIP-51 1 MCU CPU CIP-51 0x0000 CPU 100 MCD 72 : (024) :
75 9.14 PCON R/W R/W R/W R/W R/W R/W R/W R/W GF5 GF4 GF3 GF2 GF1 GF0 STOP IDLE SFR 0x GF5-GF STOP 1 CIP IDLE 1 CIP CPU : (024) :
76 10. CIP-51 SFR SFR SFR SFR SFR I/O 0xFF 1 VDD /RST PC MCU x0000 VDD 10.1 Px.x Px.x C0RSEF + - '0 ' ( ) /RST EN PCA WDT ( ) SWRSF MCD Enable EN WDT Enable FLASH CIP : (024) :
77 10.1 /RST VDD V RST VDD VDD VDD 0V V RST 10.2 VDD VDD 1ms VDD V RST 1ms 0.3ms PORSF RSTSRC.1 T PORDelay 1 PORSF RSTSRC PORSF 0 0x0000 PORSF VDD 10.2 VDD ( ) V RST VDD 1.0 /RST T PORDelay t VDD 10.2 VDD VDD V RST /RST CIP VDD V RST CIP-51 VDD PORSF RAM VDD / VDD VDD VDD VDD VDD : (024) :
78 VDD 1 VDD VDM0CN.7 = 1 2 VDD 10.1 VDD 3 VDD RSTSRC.1 = VDD VDD 10.1 VDD 10.3 VDM0CN VDD R/W R R R R R R R VDMEN VDDSTAT SFR 0xFF 7 VDMEN VDD VDD VDD VDD VDD VDD VDD 1 VDD 6 VDDSTAT VDD VDD 0 VDD VDD 1 VDD VDD 5-0 = 00000b = 10.3 /RST MCU /RST MCU / /RST PINRSF RSTSRC MSD 100 MCDRSF RSTSRC.2 1 MSD 0 MCDRSF 1 0 /RST 76 : (024) :
79 C0RSEF RSTSRC C0RSEF 0 0 CP0+ CP0- MCU 0 C0RSEF RSTSRC /RST 10.6 PCA PCA WDT PCA WDT WDT SYSCLK/12 WDT WDT WDTRSF RSTSRC.5 1 /RST 10.7 FLASH FLASH / / FLASH PSWE 1 MOVX 0x1DFF FLASH MOVC 0x1DFF 0x1DFF FLASH FLASH FERROR RSTSRC.6 /RST 10.8 SWRSF RSTSRC.4 1 SWRSF 1 /RST : (024) :
80 10.4 RSTSRC R R R/W R/W R R/W R/W R - FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF SFR 0xEF 7 = 0 = 6 FERROR FLASH 0 FLASH / / 1 FLASH / / 5 C0RSEF SWRSF SWRSF 1 SWRSF 3 WDTRSF 0 WDT 1 WDT 2 MCDRSF PORSF VDD VDD VDD 1 0 VDD 1 VDD 0 VDD 1 VDD 0 PINRSF 0 /RST 1 /RST 78 : (024) :
81 10.1 VDD = 2.7V ~ 3.6V /RST I OL = 8.5 ma,vdd= v 0.6 V /RST 0.7xVDD V /RST 0.3xVDD V /RST /RST=0.0V µa VDD (V RST ) V µs 0x µs /RST 15 µs VDD 100 µs VDD µa : (024) :
82 11. FLASH C8051F33x 8KB FLASH C2 MOVX FLASH FLASH 0 1 0xFF / FLASH / 11.1 FLASH 11.1 FLASH FLASH Cygnal C2 FLASH C2 20. C2 FLASH FLASH / VDD FLASH FLASH FLASH FLASH FLASH FLKEY 0xA5 0xF1 FLASH FLASH FLASH FLASH FLASH FLASH 11.3 FLKEY FLASH MOVX FLASH MOVX MOVX FLASH FLASH FLASH 1 PSWE PSCTL.0 1 MOVX FLASH 2 FLASH FLKEY FLASH PSWE FLASH 1 FLASH 1 FLASH 512 0xFF PSCTL PSEE 3 1 PSCTL PSWE 4 FLKEY 0xA5 5 FLKEY 0xF1 FLASH FLASH 6 MOVX 80 : (024) :
83 7 PSWE PSEE FLASH FLASH 1 2 FLASH 3 1 PSCTL PSWE 4 PSCTL PSEE 5 FLKEY 0xA5 6 FLKEY 0xF1 7 MOVX 8 PSWE 5-7 FLASH PSWE 0 MOVX 11.1 FLASH FLASH C8051F330/1 8192* 20k 100k / 25 MHz ms 25 MHz µs * 0x1E00 ~ 0x1FFF FLASH MOVX MOVC MOVX XRAM FLASH : (024) :
84 11.3 CIP-51 FLASH PSWE PSCTL.0 PSEE PSCTL.1 FLASH FLASH PSWE 1 FLASH PSWE PSEE 1 CIP-51 C2 FLASH FLASH C2 FLASH 0 0x0000 ~ 0x01FF n 512 FLASH n FLASH FLASH FLASH 3 0x0000-0x03FF 0x1C00-0x1DFF FLASH + FLASH FLASH 1 0 FLASH 0x00 2 C C2 7 FLASH FLASH 82 : (024) :
85 11.1 FLASH C8051F330/1 FLASH 0x1E00 0x1DFF 0x1DFE 0x1C00 FLASH FLASH 512 FLASH 0x PSCTL R/W R/W R/W R/W R/W R/W R/W R/W PSEE PSWE SFR 0x8F 7-2 = b = 1 PSEE 1 FLASH PSWE 1 1 MOVX MOVX FLASH 0 FLASH 1 FLASH 0 PSWE 1 MOVX FLASH 0 FLASH 1 FLASH MOVX FLASH : (024) :
86 11.3 FLKEY FLASH R/W R/W R/W R/W R/W R/W R/W R/W SFR 0xB7 7-0 FLKEY FLASH FLASH FLASH 0xA5 0xF1 FLASH FLKEY FLASH FLASH FLASH FLKEY 0xA5 FLASH 1-0 FLASH 00 FLASH / 01 0xA5 10 FLASH / 11 FLASH / 11.4 FLSCL FLASH R/W R/W R/W R/W R/W R/W R/W R/W FOSE SFR 0xB6 7 FOSE FLASH FLASH FLASH FLASH 10MHz FLASH 0 FLASH 1 FLASH 6-0 = : (024) :
87 12 RAM C8051F330/1 512 RAM MOVX DPTR MOVX MOVX 16 EMI0CN 11 PSTCL.0 = MOVX FLASH MOVX XRAM RAM 64KB 0x0000 XRAM 0x0200 0x0400 0x0600 0x0800 RAM 12.1 EMI0CN: R/W R/W R/W R/W R/W R/W R/W R/W PGSEL SFR 0xAA b = 0 PGSEL XRAM 8 MOVX XRAM RAM 0 PGSEL XRAM EMI0CN = 0x01 0x0100 0x01FF : (024) :
88 13. C8051F330/1 MCU OSCICN OSCICL / 13.1 OSCLCN / OSCICL OSCICN OSCLCN IOSCEN IFRDY IFCN1 IFCN0 3 XTAL2 4 XTAL2 EN n 2 VDD 1 XTAL1 SYSCLK XTAL2 10MΩ OSC XTAL2 XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 XFCN2 XFCN1 XFCN0 SEL1 SEL0 OSCLEN OSCLRDY OSCLF3 OSCLF2 OSCLF1 OSCLF0 OSCLD1 OSCLD0 OSCLF OSCLD OSCLF EN n OSCLD OSCXCN CLKSEL 86 : (024) :
89 13.1 H-F C8051F330/1 OSCICL 13.1 f BASE T OSCICL OSCICL 13.1 H-F OSCICL T f BASE OSCICL C8051F330/1 OSCICL f BASE 24.5MHz 13.1 OSCICN IFCN C8051F330/1 H-F OSCICL 24.5MHz ±2% OSCICL OSCICL MHz f BASE T BASE f DES T DES f BASE = Hz f DES = Hz 1 T BASE = s 1 T DES = s T DES 1 T 9 DES = 1 = s OSCICL = OSCICL f BASE OSCICL = 45 OSCICL 45 OSCICL f OSC = Hz OSCICL OSCICL : (024) :
90 13.2 OSCICL H-F R/W R/W R/W R/W R/W R/W R/W R/W SFR 0xB3 7 =0b = 6-0 OSCICL 13.1 OSCICL C8051F330/1 24.5MHz 13.3 OSCICN R/W R/W R/W R/W R/W R/W R/W R/W IOSCEN IFRDY IFCN1 IFCN SFR 0xB2 7 IOSCEN IFRDY = 0000b = 1-0 IFCN SYSCLK 8 01 SYSCLK 4 10 SYSCLK 2 11 SYSCLK 88 : (024) :
91 13.2 L-F C8051F330/1 80KHz OSCLCN OSCLD OSCLCN OSCLF L-F 2 3 L-F 2 3 L-F 2 3 TMRnH:TMRnL TMRnRLH:TMRnRLL OSCLF L-F 3% 13.2 f BASE OSCLF L-F T L-F OSCLF OSCLF 13.2 L-F OSCLF T f BASE OSCLF 13.4 OSCLCN L-F R/W R/W R/W R/W R/W R/W R/W R/W OSCLEN OSCLRDY OSCLF3 OSCLF2 OSCLF1 OSCLF0 OSCLD1 OSCLD0 00xxxx SFR 0xE3 7 OSCLEN L-F 0 L-F 1 L-F 6 OSCLRDY L-F 0 L-F 1 L-F 5-2 OSCLF[3:0] L-F L-F 0000b L-F 1111b L-F OSCLF L-F OSCLD[1:0] L-F : (024) :
92 13.3 RC CMOS / XTAL1 XTAL XTAL1 XTAL2 10MΩ RC CMOS XTAL OSCXCN XFCN 13.5 / P0.2 P0.3 XTAL1 XTAL2 RC CMOS P0.3 XTAL2 I/O / RC CMOS 14.2 I/O 90 : (024) :
93 13.5 OSCXCN R R/W R/W R/W R R/W R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 - XFCN2 XFCN1 XFCN SFR 0xB1 7 XTLVLD XOSCMD 11x XOSCMD2-0 00x 010 CMOS 011 CMOS 100 RC = 0 = 2-0 XFCN XFCN XOSCMD=11x RC(XOSCMD=10x) C(XOSCMD=10x) 000 F 32kHz F 25kHz K = kHz < f 84kHz 25kHz < f 50kHz K = kHz < f 225kHz 50kHz < f 100kHz K = kHz < f 590kHz 100kHz < f 200kHz K = kHz < f 1.5MHz 200kHz < f 400kHz K = MHz < f 4MHz 400kHz < f 800kHz K = MHz < f 10MHz 800kHz < f 1.6MHz K = MHz < f 30MHz 1.6MHz < f 3.2MHz K = XOSCMD=11x XFCN RC XOSCMD=10x XFCN f = 1.23(10 3 )/(R*C) f = MHz C = pf R = kω C XOSCMD=10x K KF f = KF/(C*VDD) f = MHz C = XTAL2 pf VDD = MCU : (024) :
94 MCU OSCXCN XFCN MHz XFCN 111b XTLVLD 1ms 1 2 1ms 3 XTLVLD => 1 4 PCB XTAL RC RC MCU pF PCB OSCXCN XFCN RC 100kHz R = 246kΩ C = 50pF f= 1.23*10 3 /RC = 1.23*10 3 /[246*50] = 0.1MHz = 100kHz 13.5 XFCN 010b MCU pF PCB OSCXCN XFCN VDD = 3.0V C = 50pF f = KF / (C * VDD) = KF / (50*3) MHz f = KF / 150 MHz 150kHz 13.5 K KF = 22 f = 22 / 150 = MHz 146 khz XFCN 011b 92 : (024) :
95 13.4 OSCICN CLKSL CLKSL 1 PCA OSCICN OSCXCN XTLVLD 1 XTLVLD XTLVLD 1ms RC C 13.6 CLKSEL R/W R/W R/W R/W R/W R/W R/W R/W SEL1 SEL SFR 0xA9 7-2 = b = 0 SEL[1:0] 00 OSCICN IFCN OSCLCN OSCLD 11 VDD = 2.7V~ IFCN = 11b MHz VDD 25 VDD = 3.0V OSCICN.7 = µa 0.3±0.1* %/V 50±10* ppm/ OSCLD = 11b KHz VDD 25 VDD = 3.0V OSCLCN.7 = µa -3±0.1* %/V 20±8* ppm/ * ±1 : (024) :
96 14. / 17 I/O 8 1 I/O GPIO P0.0 ~ P I/O I/O I/O XBR0 XBR I/O 5V I/O 14.2 I/O PnMDOUT n = 0, I/O XBR0, XBR1, PnMDOUT, PnMDIN PnSKIP 14.1 I/O UART ( ) SPI SMBus CP0 SYSCLK 2 8 P0 I/O P1 I/O P0.0 P0.7 P1.0 P1.7 PCA 4 T0, T1 ( ) P0 P1 2 8 (P0.0-P0.7) 8 (P1.0-P1.7) 94 : (024) :
97 / 14.2 I/O VDD VDD / (WEAK) GND I/O UART0 UART0 4 5 PnSKIP 1 PnSKIP GPIO PnSKIP 1 P0.0 VREF P0.3 / P0.2 P0.6 ADC CNVSTR ADC 14.3 P0SKIP, P1SKIP = 0x00 XTAL1(P0.2) XTAL2(P0.3) P0SKIP = 0x0C 14.4 : (024) :
98 14.3 SF Signals PIN I/O TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI T0 T1 P0 P1 P2 VREF IDA x1 x2 CNVSTR *NSS 4 SPI P0SKIP[7:0] P1SKIP[7:0] SF Signals 96 : (024) :
99 14.4 SF Signals PIN I/O TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI T0 T1 P0 P1 P2 VREF IDA x1 x2 CNVSTR P0SKIP[7:0] *NSS 4 SPI P1SKIP[7:0] SF Signals XBR0 XBR1 I/O I/O SMBus SDA SCL UART TX RX UART0 UART TX0 P0.4 UART RX0 P0.5 I/O SPI SPI0CN NSSMD1-NSSMD0 SPI NSS : (024) :
100 14.2 I/O I/O 1 PnMDIN 2 PnMDOUT 3 P0SKIP 4 5 ADC PnSKIP 1 PnMDIN 1 0 PnMDIN 14.8 I/O PnMDOUT SMBus SDA SCL PnMDOUT XBR1 WEAKPUD 0 I/O 0 XBR0 XBR1 I/O 1 XBAR1 XBARE XBRn XBRn I/O Cygnal IDE XBRn I/O 98 : (024) :
101 14.5 XBR0 I/O 0 R R R/W R/W R/W R/W R/W R/W - - CP0AE CP0E SYSCKE SMB0E SPI0E URT0E SFR 0xE1 7-6 = 00b = 5 CP0AE 0 0 CP0A 1 CP0A 4 CP0E 0 0 CP0 1 CP0 3 SYSCKE /SYSCLK 0 /SYSCLK 1 /SYSCLK 2 SMB0E SMBus I/O 0 SMBus I/O 1 SMBus I/O 1 SPI0E SPI I/O 0 SPI I/O 1 SPI I/O 0 URT0E UART I/O 0 UART I/O 1 UART TX0, RX0 P0.4 P0.5 : (024) :
102 14.6 XBR1 I/O 1 R/W R/W R/W R/W R/W R R/W R/W WEAKPUD XBARE T1E T0E ECIE - PCA0ME SFR 0xE2 7 WEAKPUD I/O XBARE T1E T1 0 T1 1 T1 4 T0E T0 0 T0 1 T0 3 ECIE PCA0 0 ECI 1 ECI 2 = 0b = 1-0 PCA0ME PCA I/O 00 PCA I/O 01 CEX0 10 CEX0 CEX1 11 CEX0 CEX1 CEX2 100 : (024) :
103 14.3 I/O I/O P2-0 XBRn I/O SFR - - ANL ORL XRL JBC CPL INC DEC DJNZ SFR MOV CLR SETB SFR 14.7 P0 0 R/W R/W R/W R/W R/W R/W R/W R/W P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P SFR ( ) 0x P0.[7:0] I/O 0 1 P0MDOUT.n = 0 P0MDIN 1 0 P0.n 1 P0.n 14.8 P0MDIN 0 R/W R/W R/W R/W R/W R/W R/W R/W SFR 0xF1 7-0 P0MDIN.[7:0] P0.7 P0.0 0 P0.n 1 P0.n : (024) :
104 14.9 P0MDOUT 0 R/W R/W R/W R/W R/W R/W R/W R/W SFR 0xA4 7-0 P0MDOUT.[7:0] P0.7 P0.0 P0MDIN 0 0 P0.n 1 P0.n SDA SCL P0MDOUT P0SKIP 0 R/W R/W R/W R/W R/W R/W R/W R/W SFR 0xD4 7-0 P0SKIP.[7:0] 0 ADC VREF CNVSTR 0 P0.n 1 P0.n 102 : (024) :
105 14.11 P1 1 R/W R/W R/W R/W R/W R/W R/W R/W P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P SFR ( ) 0x P1.[7:0] I/O 0 1 P1MDOUT.n = 0 P1MDIN 0 0 P1.n 1 P1.n P1MDIN 1 R/W R/W R/W R/W R/W R/W R/W R/W SFR 0xF2 7-0 P1MDIN.[7:0] P1.7 P1.0 0 P1.n 1 P1.n P1MDOUT 1 R/W R/W R/W R/W R/W R/W R/W R/W SFR 0xA5 7-0 P1MDOUT.[7:0] P1.7 P1.0 P1MDIN 0 0 P1.n 1 P1.n : (024) :
106 14.14 P1SKIP 1 R/W R/W R/W R/W R/W R/W R/W R/W SFR 0xD5 7-0 P1SKIP.[7:0] 1 ADC VREF CNVSTR 0 P1.n 1 P1.n P2 2 R/W R/W R/W R/W R/W R/W R/W R/W P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P SFR ( ) 0xA0 7-0 P2.[7:0] I/O 0 1 P2MDOUT.n = 0 P2MDIN 1 0 P2.n 1 P2.n P2MDOUT 2 R R R R R R R R/W SFR 0xA6 7-1 = b = 7-0 P2.0 0 P2.0 1 P : (024) :
107 14.1 I/O VDD = 2.7V 3.6V, I OH = -10µA I/O VDD-0.1 I OH = -3mA I/O VDD-0.7 V OH I OH = -10mA I/O VDD-0.8 V I OL = 10µA 0.1 I OL = 8.5mA 0.6 V OL I OL = 25mA 1.0 V V IH 2.0 V V IL V IN = 0 V V 1 50 µa : (024) :
108 15. SMBus SMBus I/O SMBus 1.1 I 2 C SMBus SMBus SMBus / SMBus SDA SCL / SMBus SMB0CF SMBus SMB0CN SMBus SMB0DAT SMBus 15.1 SMBus M A S T E R T X M O D E SMB0CN S S A T T C A O K R Q A R B L O S T A C K S I SMB0CF I B E S S S S N U X M M M M H S T B B B B Y H T F C C O O T S S L E E 1 0 D E N S M B T0 T1 TMR2H TMR2L SMBUS SCL SCL ( ) IRQ SCL SDA N SCL I/O SMB0DAT SDA N 106 : (024) :
109 I 2 C 2 I 2 C SBS 15.2 SMBus 15.2 SMBus SMBus 3.0V 5.0V SCL SDA SCL SDA 300ns 1000ns 15.2 SMBus VDD = 5V VDD = 3V VDD = 5V VDD = 3V 1 2 SDA SCL : (024) :
110 15.3 SMBus SMBus START SMBus START R/W STOP SCL SDA 15.3 ACK ACK NACK SCL SDA R/W 1 READ 0 WRITE 15.3 SMBus 15.3 SMBus SCL SDA SLA6 SLA5-0 R/W D7 D6-0 START +R/W ACK NACK STOP SCL SDA SDA 108 : (024) :
111 SMBus I 2 C SCL SCL SCL SCL SMBus 25ms 10ms SMB0CF SMBTOE 3 SCL 3 SCL SCL 3 25ms SMBTOE 1 SCL 3 SMBus SCL SMBus SMBus SCL SDA 50 SMB0CF SMBFTE 1 SCL SDA 10 SMBus SMBus 15.4 SMBus SMBus SMBus SCL SDA / SMB0CF START/STOP SMBus ACK ACK ACK ACK SMB0CN SMBus SMBus : (024) :
112 SMBus 1 SCL / 2 SDA 3 / 4 SMB0CF SMBus SMBus SMBus SMB0CF SMBus / SMBus SMBus ENSMB 1 SMBus INH 1 SMBus SCL SDA NACK INH START SMBCS1-0 SMBus 15.1 SMBus SCL 15.1 SMBus 1 SMBus UART 15.1 SMBus SMBCS1 SMBCS0 SMBus SCL T HighMin = T LowMin = f 1 ClockSourceOverflow T HighMin SCL T LowMin SCL f ClockSourceOverflow 15.1 SCL SCL SMBus SMBus = f ClockSourceOverflow : (024) :
113 SCL T HIGH T LOW SCL SCL SMBus SCL SCL T Low T High SCL EXTHOLD 1 SDA SDA SCL SDA SDA SCL SDA SMBus 250ns 300ns EXTHOLD 1 SMBus 15.2 EXTHOLD SYSCLK 10MHz 15.2 SDA EXTHOLD SDA SDA 0 T low ACK MSB SMB0DAT ACK SI ACK SI 0 SMBTOE ms SCL SMBus SCL 3 3 SCL 3 SMBus SMBus SMBFTE 1 SMBus 1 SCL SDA 10 SMBus 15.4 SMBus STO : (024) :
114 15.5 SMB0CF SMBus R R/W R/W R/W R/W R/W R/W R/W ENSMB INH BUSY EXTHOLD SMBTOE SMBFTE FTE TOE SFR ( ) 0xC1 7 ENSMB SMBus / SMBus SDA SCL 0 SMBus 1 SMBus 6 INH SMBus 1 SMBus SMBus 0 SMBus 1 SMBus 5 BUSY SMBus SMBus 1 SMBus 4 EXTHOLD SMBus SDA SDA 1 SDA 3 SMBTOE SMBus SCL / SCL 1 SMBus SCL 3 3 SCL 3 25ms 3 SMBus 2 SMBFTE SMBus 1 SCL SDA 10 SMBus 1-0 SMBCS1-SMBCS0 SMBus SMBus 15.1 SMBCS1 SMBCS0 SMBus : (024) :
115 SMBus SMBus SMB0CN SMBus 15.6 SMB0CN 4 MASTER TXMODE STA STO MASTER TXMODE / STA STO SMBus START / STOP SMBus STA STO STA 1 SMBus STA SMBus STO 1 ACK STA STO SMBus ACK ACK ACK ACK ACKRQ ACK ACKRQ SI ACK ACK SI ACK NACK ACK SDA ACK SCL SI ARBLOST SMBus SI ARBLOST SI SMBus SI 1 SMBus SCL SI SMB0CN SMBus 15.4 SMBus : (024) :
116 15.6 SMB0CN SMBus R R R/W R/W R R R/W R/W MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI SFR ( ) 0xC0 7 MASTER SMBus / SMBus 0 SMBus 1 SMBus 6 TXMODE SMBus SMBus 0 SMBus 1 SMBus 5 STA SMBus 0 1 STA 1 ACK STO SMBus 0 1 STO 1 ACK STO 0 STA STO ACKRQ SMBus SMBus ACK ACK 1 2 ARBLOST SMBus SMBus 1 1 ACK SMBus ACK ACK ACK ACKRQ = 1 ACK SI SMBus SI SI 1 SCL 114 : (024) :
117 MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI 15.3 SMB0CN 1 0 SMBus SMB0DAT SMBus SMB0DAT ACK ACK STA 0 SI SCL 1 SDA ACK ACK ACK ACK/NACK +R/W SMBus SMB0DAT SI 1 / SMBus SI 0 SMB0DAT SMB0DAT MSB SMB0DAT MSB SMB0DAT SMB0DAT 15.7 SMB0DAT SMBus R/W R/W R/W R/W R/W R/W R/W R/W SFR 0xC2 7-0 SMB0DAT SMBus SMB0DAT SMBus SMBus SI 1 CPU SI 1 SI 1 / CPU : (024) :
118 15.5 SMBus SMBus / 4 SMBus SMBus ACK ACK SDA SCL SMBus R/W 0 ACK 15.8 ACK 15.8 S SLA W A A A P SMBus SMBus S = START( ) P = STOP( ) A = ACK( ) W = WRITE( ) SLA = 116 : (024) :
119 SDA SCL SMBus R/W 1 SDA SCL ACKRQ 1 SMB0CN.1 NACK STO 1 ACK 1 ACK ACK 0 ACK 0 NACK 15.9 ACK 15.9 S SLA R A A N P SMBus SMBus S = START( ) P = STOP( ) A = ACK( ) N = NACK( ) R = READ( ) SLA = : (024) :
120 SDA SCL INH = 0 START SMBus ACKRQ 1 ACK NACK 0 ACK ACK NACK SMBus SMB0DAT ACK S SLA R A A A P SMBus SMBus S = START( ) P = STOP( ) A = ACK( ) R= READ( ) SLA = 118 : (024) :
121 SDA SCL INH = 0 START SMBus ACK NACK SMB0DAT SMBus ACK SMB0DAT NACK SMB0DAT SI SMB0DAT NACK SMBus SMB0DAT ACK S SLA W A A N P SMBus SMBus S = START( ) P = STOP( ) N = NACK( ) W = WRITE( ) SLA = : (024) :
122 15.6 SMBus SMB0CN SMBus 15.4 SMB0CN 4 MASTER TXMODE STA STO SMBus SMBus 15.4 SMBus ACKRQ ARBLOST ACK SMBus STA STO ACK X +R/W SMB0DAT 0 0 X STA 1 0 X NACK 0 1 X SMB0DAT 0 0 X 0 1 X X ACK 1 0 X SI 0 0 X SMB0DAT SMB0DAT NACK NACK ACK X NACK ACK SI SMB0DAT NACK SI SMB0DAT 120 : (024) :
DPJJX1.DOC
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W77E58中文手册
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1 Quick51...1 1.1 SmartSOPC Quick51...1 1.2 Quick51...1 1.3 Quick51...2 2 Keil C51 Quick51...4 2.1 Keil C51...4 2.2 Keil C51...4 2.3 1 Keil C51...4 2.4 Flash Magic...9 2.5 ISP...9 2.6...10 2.7 Keil C51...12
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Microchip MCP3221 12 I 2 C TM 12 1LSB DNL 2LSB INL 250 A 5nA 1 A I 2 C TM I 2 C 100kHz I 2 C 400kHz 2 8 I 2 C 22.3ksps 2.7V 5.5V 40 +85 40 +125 SOT-23 Microchip MCP3221 12 A/D SOT-23 CMOS MCP3221 250 A
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