The 888 and 886 Microprocessors and Their Memory and Input/output Interfaces TE 888 AND 886 MICROPROCESSORS AND TEIR MEMORY AND INPUT/OUTPUT INTERFACES 8. The 888 and 886 Microprocessors 8.2 Minimum-Mode and Maximum-Mode System 8.3 Minimum-Mode Interface 8.4 Maximum-Mode Interface 8.5 Electrical Characteristics 8.6 System Clock 8.7 Bus Cycle and Time States 8.8 ardware Organization of the Memory Address Space 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-2 The 888 and 886 Microprocessors and Their Memory and Input/output Interfaces 8.9 Memory Bus Status Codes 8. Memory Control Signals 8. Read and Write Bus Cycles 8.2 Memory Interface Circuits 8.3 Programmable ogic Arrays 8.4 Types of Input/Output 8.5 An Isolated Input/Output Interface 8.6 Input/Output Data Transfer 8.7 Input/Output Instructions 8.8 Input/Output Bus Cycles ๅ็ซๅฐ็ฃๅคงๅญธ 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-3 8. The 888 and 886 Microprocessors The 886, announced in 978, was the first 6-bit microprocessor introduced by Intel Corporation. 886 and 888 are internally 6-bit MPU. owever, externally the 886 has a 6-bit data bus and the 888 has an 8-bit data bus. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-4 The 888 microprocessor ็็ฉๆฉ้ป็ณป 8. The 888 and 886 Microprocessors 886 and 888 both have the ability to address up to Mbyte of memory and 64K of input/output port. The 888 and 886 are both manufactured using high-performance metal-oxide semiconductor (MOS) technology. The 888 and 886 are housed in a 4-pin dual inline package and many pins have multiple functions. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-5 Intel D886- Microprocessor Processor Speed:. Mz Bus Speed:. Mz FPU: no SOURCE:http://cpu-museum.de/ 8. The 888 and 886 Microprocessors CMOS, Complementary Metal-Oxide- Semiconductor, is a major class of integrated circuits used in chips such as microprocessors, microcontrollers, static RAM, digital logic circuits, and analog circuits such as image sensors. Two important characteristics of CMOS devices are high noise immunity and low static power supply drain. Significant power is only drawn when its transistors are switching between on and off states; consequently, CMOS devices do not produce as much heat as other forms of logic such as TT. CMOS also allows a high density of logic functions on a chip. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-6
8. The 888 and 886 Microprocessors Pin layout of the 886 and 888 microprocessor 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-7 888 CPU 8.2 Minimum-Mode and Maximum- Mode System The 886 and 888 microprocessors can be configured to work in either of two modes: The minimum mode - MN/ MX = The maximum mode - MN/ MX = The mode selection feature lets the 888 or 886 better meet the needs of a wide variety of system requirement. Minimum mode 888/886 systems are typically smaller and contain a single processor. Depending on the mode of operation selected, the assignment for a number of the pins on the microprocessor package are changed. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-8 8.2 Minimum-Mode and Maximum- Mode System 8.2 Minimum-Mode and Maximum- Mode System Signals common to both minimum and maximum mode 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-9 Unique minimum-mode signals 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-8.2 Minimum-Mode and Maximum- Mode System Unique maximum-mode signals 8.2 Minimum-Mode and Maximum- Mode System EXAMPE Which pins provide different signal functions in the minimum-mode 888 and minimum-mode 886? Solution: (a) Pins 2 through 8 on the 888 are address lines A 4 through A 8, but on the 886 they are address/data lines AD 4 through AD 8. (b) Pin 28 on the 888 is IO/M output and on the 886 it is the M/IO output. (c) Pin 34 of the 888 is the SSO output, and on the 886 this pin supplies the BE/S 7. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-2 2
8.3 Minimum-Mode Interface 8.3 Minimum-Mode Interface Block diagram of the minimum-mode 888 MPU Block diagram of the minimum-mode 886 MPU 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-3 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-4 8.3 Minimum-Mode Interface The minimum-mode signals can be divided into the following basic groups: Address/Data bus Status signals Control signals Interrupt signals DMA interface signals 8.3 Minimum-Mode Interface Address/Data bus The address bus is used to carry address information to the memory and I/O ports. The address bus is 2-bit long and consists of signal lines A through A 9. A 2-bit address gives the 888 a Mbyte memory address space. Only address line A through A 5 are used when addressing I/O. This give an I/O address space of 64 Kbytes. The 888 has 8 multiplexed address/data bus lines (A ~A 7 ) while 886 has 6 multiplexed address/data bus lines (A ~A 5 ). 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-5 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-6 8.3 Minimum-Mode Interface Status signals The four most significant address, A 9 through A 6 are multiplexed with status signal S 6 through S 3. Bits S 4 and S 3 together form a 2-bit binary code that identifies which of the internal segment registers was used to generate the physical address. S 5 is the logic level of the internal interrupt flag. S 6 is always at the logic level. S 4 S 3 Address Status Alternate (relative to the ES segment) Stack (relative to the SS segment) Code/None (relative to the CS segment or a default of zero Data (relative to the DS segment) 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-7 8.3 Minimum-Mode Interface Control signals The control signals are provided to support the memory and I/O interfaces of the 888 and 886. AE Address atch Enable IO/M IO/Memory (888) M/IO Memory/IO (886) DT/R Data Transmit/Receive (888/886) SSO System Status Output (888) BE Bank igh Enable (886) RD Read (888/886) WR Write (888/886) DEN Data Enable (888/886) READY Ready (888/886) 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-8 3
8.3 Minimum-Mode Interface Interrupt signals The interrupt signals can be used by an external device to signal that it needs to be serviced. INTR Interrupt Request INTA Interrupt Acknowledge TEST Test (can be use to synchronize MPU) NMI Nonmaskable Interrupt RESET Reset (hardware reset of the MPU) 8.3 Minimum-Mode Interface DMA interface signals When an external device wants to take control of the system bus, it signals this fact to the MPU by switching OD to the logic level. When in the hold state, signal lines AD through AD 7, A 8 through A 5, A 6 /S 3 through A 9 /S 6, SSO, IO/M, DT/R, RD, WR, DEN, and INTR are all put into high-z state. The 888 signals external devices that the signal lines are in the high-z state by switching its DA output to the logic level. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-9 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-2 8.4 Maximum-Mode Interface The maximum-mode configuration is mainly used for implementing a multiprocessor/coprocessor system environment. Global resources and local resources In the maximum-mode, facilities are provided for implementing allocation of global resources and passing bus control to other microprocessors sharing the system bus. 8.4 Maximum-Mode Interface 8288 bus controller 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-2 888 maximum-mode block diagram 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-22 8.4 Maximum-Mode Interface 8288 bus controller 8.4 Maximum-Mode Interface 8288 bus controller In the maximum-mode, 888/886 outputs a status code on three signal line, S, S, S 2, prior to the initialization of each bus cycle. The 3-bit bus status code identifies which type of bus cycle is to follow and are input to the external bus controller device, 8288. The 8288 produces one or two command signals for each bus cycle. 886 maximum-mode block diagram 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-23 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-24 4
8.4 Maximum-Mode Interface 8288 bus controller 8.4 Maximum-Mode Interface 8288 bus controller Status Inputs CPU Cycle 8288 Command S 2 S S Interrupt Acknowledge Read I/O Port Write I/O Port alt Instruction Fetch Read Memory Write Memory Passive Bus status code 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-25 INTR IORC IOWC, AIOWC None MRDC MRDC MWTC, AMWC None Block diagram and pin layout of 8288 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-26 8.4 Maximum-Mode Interface ock signal The lock signal (OCK) is meant to be output (logic ) whenever the processor wants to lock out the other processor from using the bus. ocal bus control signals The request/grant signals (RQ/GT, RQ/GT ) provide a prioritized bus access mechanism for accessing the local bus. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-27 8.4 Maximum-Mode Interface Queue status signals The 2-bit queue status code QS and QS tells the external circuitry what type of information was removed form the queue during the previous clock cycle. QS QS Queue Status (low) No Operation. During the last clock cycle, nothing was taken form the queue. First byte. The byte taken from the queue was the first byte of the instruction. (high) Queue Empty. The queue has been reinitialized as a result of the execution of a transfer of instruction. Subsequent Byte. The byte taken from the queue was a subsequent byte of the instruction. Queue status code ๅ็ซๅฐ็ฃๅคงๅญธ ็็ฉๆฉ้ป็ณป 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-28 8.4 Maximum-Mode Interface EXAMPE If the bus status code S 2 S S equals, what type of bus activity is taking place? Which command output is produced by the 8288? Solution: ooking at the bus status table, we see that bus status code identifies a read memory bus cycle and causes the MRDC output of the bus controller to switch to logic. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-29 8.5 Electrical Characteristics Power is applied between pin 4 (V cc ) and pins (GND) and 2 (GND). The nominal value of V cc is specified as +5V dc with a tolerance of ±%. Both 888 and 886 draw a maximum of 34mA from the supply. Symbol V I V I V O V O Meaning Input low voltage Input high voltage Output low voltage Output high voltage 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-3 Minimum -.5 V +2. V +2.4 V I/O voltage levels Maximum +.8 V V cc +.5 V +.45 V I O =2. ma I O =-4 μa Test condition 5
8.6 System Clock The time base for synchronization of the internal and external operations of the microprocessor in a microcomputer system is provided by the clock (CK) input signal. The standard 888 operates at 5 Mz and the 888-2 operates at 8 Mz. The 886 is manufactured in three speeds: 5-Mz 886, 8-Mz 886-2, and the -Mz 886-. The CK is externally generated by the 8284 clock generator and driver IC. 8.6 System Clock Block diagram of the 8284 clock generator 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-3 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-32 8.6 System Clock 8.6 System Clock Block diagram of the 8284 clock generator Connecting the 8284 to the 888 5- or 24Mz crystal Typical value of C when used with 5Mz crystal is 2pF The fundamental crystal frequency is divided by 3 within the 8284 to give either a 5- or 8-Mz clock signal 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-33 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-34 8.6 System Clock 8.6 System Clock CK waveform The signal is specified at Metal Oxide Semiconductor (MOS)-compatible voltage level. The period of the 5-Mz 888 can range from 2 ns to 5 ns, and the maximum rise and fall times of its edges equal ns. PCK and OSC signals The peripheral clock (PCK) and oscillator clock (OSC) signals are provided to drive peripheral ICs. The clock output at PCK is half the frequency of CK. The OSC output is at the crystal frequency which is three times of CK. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-35 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-36 6
8.6 System Clock EXAMPE If the CK input of an 886 MPU is to be driven by a 9-Mz signal, what speed version of the 886 must be used and what frequency crystal must be attached to the 8284 Solution: The 886- is the version of the 886 that can be run at 9-Mz. To create the 9-Mz clock, a 27-Mz crystal must be used on the 8284. 8.7 Bus Cycle and Time States A bus cycle defines the basic operation that a microprocessor performs to communicate with external devices. Examples of bus cycles are the memory read, memory write, input/output read, and input/output write. The bus cycle of the 888 and 886 microprocessors consists of at least four clock periods. If no bus cycles are required, the microprocessor performs what are known as idle states. When READY is held at the level, wait states are inserted between states T 3 and T 4 of the bus cycle. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-37 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-38 8.7 Bus Cycle and Time States 8.7 Bus Cycle and Time States EXAMPE What is the duration of the bus cycle in the 888-based microcomputer if the clock is 8 Mz and the two wait states are inserted. Solution: The duration of the bus cycle in an 8 Mz system is given by t cyc = 5 ns + N x 25 ns In this expression the N stands for the number of waits states. For a bus cycle with two wait states, we get t cyc = 5 ns + 2 x 25 ns = 5 ns + 25 ns = 75 ns Bus cycle clock periods, idle state, and wait state 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-39 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-4 8.8 ardware Organization of the Memory Address Space M BYTES FFFFF FFFFF 8.8 ardware Organization of the Memory Address Space 52K BYTES FFFFF FFFFD 52K BYTES FFFFE FFFFC 2 5 3 4 2 A 9 A D 5 D 8 BE D 7 D A A 9 A D 7 D 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-4 Mx8 memory bank of the 888 igh and low memory banks of the 886 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-42 7
8.8 ardware Organization of the Memory Address Space 8.8 ardware Organization of the Memory Address Space Transfer X First bus cycle Second bus cycle X+ (X) X+ (X) X+ (X) A 9 A D 7 D A 9 A D 7 D A 9 A D 7 D Byte transfer by the 888 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-43 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-44 Word transfer by the 888 8.8 ardware Organization of the Memory Address Space 8.8 ardware Organization of the Memory Address Space Transfer X Transfer X+ Y+ X+ Y (X) Y+ (X+) Y X A 9 A D 5 D 8 BE (IG) D 7 D A (OW) A 9 A D 5 D 8 BE (OW) D 7 D A (IG) Even address byte transfer by the 886 Odd address byte transfer by the 886 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-45 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-46 8.8 ardware Organization of the Memory Address Space 8.8 ardware Organization of the Memory Address Space Y+ (X+) Transfer X, X+ Y (X) X+3 (X+) First bus cycle X+2 (X) X+3 (X+) Second bus cycle X+2 (X) A 9 A D 5 D 8 BE (OW) D 7 D A (IG) A 9 A D 5 D 8 BE (IG) D 7 D A (OW) A 9 A D 5 D 8 BE (OW) D 7 D A (OW) Even address word transfer by the 886 Odd-address word transfer by the 886 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-47 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-48 8
8.8 ardware Organization of the Memory Address Space EXAMPE Is the word at memory address 23 6 of an 886-based microcomputer aligned or misaligned? ow many cycle are required to read it from memory? Solution: The first byte of the word is the second byte at the aligned-word address 23 6. Therefore, the word is misaligned and required two bus cycles to be read from memory. 8.9 Address Bus Status Codes Whenever a memory bus cycle is in progress, an address bus status code S 4 S 3 is output by the processor. S 4 S 3 identifies which one of the four segment register is used to generate the physical address in the current bus cycle: S 4 S 3 = identifies the extra segment register (ES) S 4 S 3 = identifies the stack segment register (SS) S 4 S 3 = identifies the code segment register (CS) S 4 S 3 = identifies the data segment register (DS) The memory address reach of the microprocessor can thus be expanded to 4 Mbytes. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-49 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-5 8. Memory Control Signals Minimum-mode memory control signals Minimum-mode 888 memory interface 8. Memory Control Signals Minimum-mode memory control signals (888) AE Address atch Enable used to latch the address in external memory. IO/M Input-Output/Memory signal external circuitry whether a memory of I/O bus cycle is in progress. DT/R Data Transmit/Receive signal external circuitry whether the 888 is transmitting or receiving data over the bus. RD Read identifies that a read bus cycle is in progress. WR Write identifies that a write bus cycle is in progress. DEN Data Enable used to enable the data bus. SSO Status ine identifies whether a code or data access is in progress. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-5 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-52 8. Memory Control Signals The control signals for the 886 s minimum-mode memory interface differs in three ways: IO/M signal is replaced by M/IO signal. The signal SSO is removed from the interface. BE (bank high enable) is added to the interface and is used to select input for the high bank of memory in the 886 s memory subsystem. 8. Memory Control Signals Maximum-mode memory control signals Maximum-mode 888 memory interface 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-53 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-54 9
8. Memory Control Signals Maximum-mode memory control signals MRDC Memory Read Command MWTC Memory Write Command AMWC Advanced Memory Write Command 8. Read and Write Bus Cycle Read cycle Status Inputs CPU Cycle 8288 Command S 2 S S Interrupt Acknowledge Read I/O Port Write I/O Port alt Instruction Fetch Read Memory Write Memory Passive 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-55 INTA IORC IOWC, AIOWC None MRDC MRDC MWTC, AMWC None Minimum-mode memory read bus cycle of the 888 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-56 8. Read and Write Bus Cycle Read cycle 8. Read and Write Bus Cycle Read cycle Minimum-mode memory read bus cycle of the 886 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-57 Maximum-mode memory read bus cycle of the 886 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-58 8. Read and Write Bus Cycle Write cycle 8. Read and Write Bus Cycle Write cycle Minimum-mode memory write bus cycle of the 888 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-59 Maximum-mode memory write bus cycle of the 886 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-6
8.2 Memory Interface Circuit 8.2 Memory Interface Circuit Address bus latches and buffers Bank write and bank read control logic Data bus transceivers/buffers Address decoders 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-6 Memory interface block diagram 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-62 8.2 Memory Interface Circuit Address bus latches and buffers 8.2 Memory Interface Circuit Address bus latches and buffers Operation of the 74F373 OC Inputs Enable C X D X X Output Q Q Z Block diagram of a D-type latch 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-63 Circuit diagram of the 74F373 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-64 8.2 Memory Interface Circuit A review of flip-flop/latch logic 8.2 Memory Interface Circuit A review of flip-flop/latch logic R Q Cross-NOR S-R flip-flop S 2 Q S Q Cross-NAND S-R flip-flop RESET SET 2 Q R 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-65 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-66 Cross-NOR S-R flip-flop
8.2 Memory Interface Circuit A review of flip-flop/latch logic The D latch is used to capture, or latch the logic level which is present on the data line when the clock input is high. 8.2 Memory Interface Circuit A review of flip-flop/latch logic S R Q t- S R Q Q Q t 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-67 Positive edge-triggered D flip-flop 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-68 8.2 Memory Interface Circuit A review of flip-flop/latch logic 8.2 Memory Interface Circuit A review of flip-flop/latch logic 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-69 Positive edge-triggered JK flip-flop 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-7 D-type latch 8.2 Memory Interface Circuit Address bus latches and buffers 8.2 Memory Interface Circuit Bank write and bank read control logic Bank write control logic Bank read control logic 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-7 Address latch circuit 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-72 2
8.2 Memory Interface Circuit Data bus transceivers 8.2 Memory Interface Circuit Data bus transceivers Block diagram and circuit diagram of the 74F245 octal bus transceiver 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-73 Data bus transceiver circuit 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-74 8.2 Memory Interface Circuit Address decoder 8.2 Memory Interface Circuit Address decoder INPUTS OUTPUTS ENABE G SEECT B A Y Y Y2 Y3 X X Address bus configuration with address decoding Block diagram and operation of the 74F39 decoder 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-75 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-76 8.2 Memory Interface Circuit Address decoder 8.2 Memory Interface Circuit Address decoder Circuit diagram of the 74F39 decoder 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-77 Address decoder circuit using 74F39 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-78 3
8.2 Memory Interface Circuit Address decoder 8.2 Memory Interface Circuit Address decoder Block diagram and operation of the 74F38 decoder 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-79 Circuit diagram of the 74F38 decoder 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-8 8.2 Memory Interface Circuit Address decoder 8.3 Programmable ogic Arrays Programmable logic array, PA, are generalpurpose logic devices that have the ability to perform a wide variety of specialized logic functions. A PA contains a general-purpose AND-OR-NOT array of logic gate circuits. The process used to connect or disconnect inputs of the AND gate array is known as programming, which leads to the name programmable logic array. Address decoder circuit using 74F38 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-8 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-82 8.3 Programmable ogic Arrays Major types of programmable logic architecture Simple Programmable ogic Devices (SPDs) PA, GA, PA, EPD Complex Programmable ogic Devices (CPDs) EPD, PEE, EEPD, MAX Field Programmable Gate Arrays (FPGAs) CA, pasic, FEX, APEX, ACT, ORCA, Virtex,pASIC Field Programmable InterConnect (FPICs) 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-83 8.3 Programmable ogic Arrays PAs, GAs, and EPDs Early PA devices were all manufactured with the bipolar semiconductor process. Bipolar devices are programmed with an interconnect pattern by burning out fuse links within the device. PAs made with bipolar technology are characterized by slower operating speeds and higher power consumption. Two kinds of newer PA, manufactured with the CMOS process, are in wide use today: the GA and EPD. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-84 4
8.3 Programmable ogic Arrays Block diagram of a PA The logic levels applied at inputs I through I 5 and the programming of the AND array determine what logic levels are produced at outputs F through F 5. The capacity of a PA is measured by three properties: the number of inputs, the number of outputs, and the number of product terms (P-terms) 8.3 Programmable ogic Arrays Architecture of a PA Block diagram of a PA 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-85 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-86 8.3 Programmable ogic Arrays Architecture of a PA (a) Typical PA architecture. (b) PA with output latch 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-87 8.3 Programmable ogic Arrays Standard PA TM device A PA, programmable array logic, is a PA in which the OR array is fixed; only the AND array is programmable. The 68 is a widely used PA IC. It is housed in a 2-pin package. It has dedicated input, 2 dedicated outputs, and 6 programmable I/O lines. The 68 is manufactured with bipolar technology. It operates from a +5V±% dc power supply and draw a maximum of 8mA. The 28 has 2 inputs, 8 outputs and 64 P-terms. The 2R8 is the register output version of 28. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-88 8.3 Programmable ogic Arrays Standard PA TM device 8.3 Programmable ogic Arrays Standard PA TM device 68 circuit diagram and pin layout 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-89 28 circuit diagram and pin layout 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-9 5
8.3 Programmable ogic Arrays Standard PA TM device 8.3 Programmable ogic Arrays Standard PA TM device 6R8 circuit diagram and pin layout 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-9 2R8 circuit diagram and pin layout 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-92 8.3 Programmable ogic Arrays Expanding PA capacity Expanding output word length Expanding input word length 8.4 Types of Input/Output Isolated input/output When using isolated I/O in a microcomputer system, the I/O device are treated separate from memory. The memory address space contains M consecutive byte address in the range 6 through FFFFF 6 ; and that the I/O address space contains 64K consecutive byte addresses in the range 6 through FFFF 6. All input and output data transfers must take place between the A or AX register and I/O port. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-93 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-94 8.4 Types of Input/Output Isolated input/output 8.4 Types of Input/Output Memory-mapped input/output In the case of memory-mapped I/O, MPU looks at the I/O port as though it is a storage location in memory. Some of the memory address space is dedicated to I/O ports. Instructions that affect data in memory are used instead of the special I/O instructions. The memory instructions tend to execute slower than those specifically designed for isolated I/O. 888/886 memory and I/O address spaces 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-95 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-96 6
8.4 Types of Input/Output Memory-mapped input/output 8.4 Types of Input/Output Memory-mapped input/output 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-97 Isolated I/O ports 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-98 Memory mapped I/O ports 8.5 Isolated Input/Output Interface I/O devices: Keyboard Printer Mouse 82C55A, etc. Functions of interface circuit: Select the I/O port atch output data Sample input data Synchronize data transfer Translate between TT voltage levels and those required to operate the I/O devices. 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-99 8.5 Isolated Input/Output Interface Minimum-mode interface Minimum-mode 888 system I/O interface 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-8.5 Isolated Input/Output Interface Minimum-mode interface 8.5 Isolated Input/Output Interface Maximum-mode interface Minimum-mode 886 system I/O interface 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8- Maximum-mode 888 system I/O interface 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-2 7
8.5 Isolated Input/Output Interface Maximum-mode interface 8.5 Isolated Input/Output Interface Maximum-mode interface Status Inputs CPU Cycle 8288 Command S 2 S S Interrupt Acknowledge INTA Read I/O Port IORC Write I/O Port IOWC, AIOWC alt None Instruction Fetch MRDC Read Memory MRDC Write Memory MWTC, AMWC Passive None Maximum-mode 886 system I/O interface 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-3 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-4 I/O bus cycle status codes 8.6 Input/Output Data Transfers 8.7 Input/Output Instructions Input/output data transfers in the 888 and 886 microcomputers can be either byte-wide or word-wide. I/O addresses are 6 bits in length and are output by the 888 to the I/O interface over bus lines AD through AD 7 and A 8 through A 5. In 888, the word transfers is performed as two consecutive byte-wide data transfer and takes two bus cycle. In 886, the word transfers can takes either one or two bus cycle. Word-wide I/O ports should be aligned at evenaddress boundaries. Mnemonic IN OUT Meaning Input direct Input indirect (variable) Output direct Output indirect (variable) Format IN Acc, Port IN Acc, DX OUT Port, Acc OUT DX, Acc Operation (Acc) (Port) Acc = A or AX (Acc) ((DX)) (Port) (Acc) ((DX)) (Acc) 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-5 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-6 8.7 Input/Output Instructions EXAMPE Write a sequence of instructions that will output the data FF 6 to a byte-wide output port at address AB 6 of the I/O address space. Solution: First, the A register is loaded with FF 6 as an immediate operand in the instruction MOV A, FF Now the data in A can be output to the byte-wide output port with the instruction OUT AB, A 8.7 Input/Output Instructions EXAMPE Write a series of instructions that will output FF 6 to an output port located at address B 6 of the I/O address space. Solution: The DX register must first be loaded with the address of the output port. This is done with the instruction MOV DX, B Next, the data that are to be output must be loaded into A with the instruction MOV A, FF Finally, the data are output with the instruction OUT DX, A 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-7 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-8 8
8.7 Input/Output Instructions EXAMPE Data are to be read in from two byte-wide input ports at addresses AA 6 and A9 6 and then output as a word-wide output port at address B 6. Write a sequence of instructions to perform this input/output operation. Solution: First read in the byte at address AA 6 into A and move it into A. IN A, AA MOV A, A Now the other byte can be read into A by the instruction IN A, 9A And to write out the word of data MOV DX, B OUT DX, AX 8.8 Input/Output Bus Cycle Input bus cycle of the 888 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-9 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-8.8 Input/Output Bus Cycle Output bus cycle of the 888 8.8 Input/Output Bus Cycle Input bus cycle of the 886 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-2 8.8 Input/Output Bus Cycle Output bus cycle of the 886 6 37 ๅพฎ่็ๆฉๅ็่ๆ็จ ecture 8-3 9