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邏念理 Performance You Can See 1

論 4 邏 ( LA ) 念理 4 (support package) 4 LA : TLA 7012 & TLA 7016 4 Q & A 2

3 邏念理

Basic concept of Logic analyzer 4 什 LA LA 4 LA 4 LA - (Probe) - (Synchronous) & (Asynchronous) - 狀 (Trigger state machine) - (Acquisition memory) 4

Driving Innovation Creates Digital Debugging Challenges Today s speeds are causing more signal integrity challenges than ever: 4 Faster synchronous bus architectures 0Faster clock & data rates 0Quicker rise & fall times 0Shorter setup & hold times 4 Electrical & physical challenges 0Smaller logic swings 0Differential signals 0More signals to measure 0Signal impedance & termination issues Digital Designers need to be able to correlate the analog characteristics of their digital signals! 5

& 參數 Emulator 邏 6

什 LA (Logic Analyzer)? ( vs. ) ( 率 vs. 率 ) ( 率 vs. ) 邏 ( 邏 vs. ) FFT ( 量 ) 邏 7

LA? 4 LA : 0 理數 0 路邏 0 0 0 (Embedded system) 0... 8

LA 4 ( ) 0, 路行 4 (,, ) 0 數不邏行理 4 (Trigger) (Qualification) 0,, 老金 4 ( 狀,,, ) 0, 不 9

LA 4 數 34CH for 8 CPU, 例 8031,6805 68CH for 16 CPU, 例 8086,68IIC11 102CH for 32 CPU, 例 80386,68360 136CH for?, 例 P6,Power PC,or System 4 度 : 64K : (Deep Mem.),4M~16M / : 度 4 度 4 力 4 數 (BW) Processor / Bus 靈, 易理 10

邏 Reference Memory DATA Clock Qualifier External Clock B U F F E R S Log-in Register DATA Acquisition Memory DATA Display Control (SYNC) (ASYNC) Sample Clock Generator Trigger Control Store Clock Memory Address Register 11

LA - 數來 (asynchronous) (synchronous) 狀 (Trigger state machine) (Acquisition memory) 12

數臨 4 LA Probe 1 率臨 LA LA 13

LA 數 4 4 41 度 ( 類 ) 4 ( ) 臨 0 (TTL/CMOS logic) 0 (+/- 5-10V) 4 降 0 路 / / 14

LA - 數來 (asynchronous) (synchronous) 狀 (Trigger state machine) (Acquisition memory) 15

(Asynchronous) vs. (Synchronous) 4 (Asynchronous) (Timing) 0 邏 0 4 (Synchronous) 狀 (State) 0 0 邏率 16

(Timing) 4 邏 4 - 度 (resolution) 4 = 度 LA 0 0 0 1 1 0 1 0 50 GHz = 20ps clock 17

(Timing) 4 5 10 LA LA 18

4 邏 1 A B 量 C 量 19

度 (Resolution) vs. 度 (Accuracy) 度不度 Delay 1 Delay 2 20

(Skew) 4 路不 Ch 1 Ch 2 邏 Ch 1 Ch 2 21

臨度 4 臨 0 臨度度臨臨臨料臨料 22

( ) 4 0T CLK min. ( ) 0T SKEW min. ( ) 0T DATA-WIDTH min. ( 料 ) 4T DATA-WIDTH min. = T CLK min. + T SKEW min. 0T GLITCH min. ( 料度 ) 4 0T R min. ( / - ) 0V THRESH-ACC ( 臨度 / ) 0V SWING min. ( ) 23

(Conventional) vs. (Transitional) 4 0 邏 0 率省 LA 0 0 1 1 0 1 0 0 1 0 1 0 Conventional = 8 locations Transitional = 4 locations Data 料 24

Benefits of Faster Edge Rates 4 Edge CYCLE TIME TRANSITION TIME 4 Edge 臨 25

Faster Edge Rates Challenges 4 Edge 易 Turn Lump Turn Lumped 4 Edge 流 0Increased ground bounce, especially on wide buses 0Increased crosstalk 26

Fast Digital Signal Edges Create Signal Integrity Problems Digital Signal Analog Signal Error 4 Signal integrity problems results from the complex interactions of 0Output drivers 0Signal path layout 0Signal path loads 0Signal path termination 0Ground and power distribution 27

Capture Elusive Hardware Problems 4 Glitches 4 Logic level violations 4 Setup/hold violations 4 Logic errors 4 Crosstalk 4 Reflections 4 Bus contention 4 Termination errors 4 Clock skew 4 Missing clocks 4 Missing data 4 Refresh problems 4 Power supply problems 4 Ground bounce problems 4 Propagation delay errors 4 Incorrect state 4 Timing margins & violations 4 Pulse width violations 4 Propagation delay errors 4 Critical races 4 Timing hazards 4 Metastability 4 Errors in bridge circuits 4 Thermal circuit errors 4 Handshake errors 4 Address decoding errors 4 Fan out errors 4 Tri-state errors 28

Glitches Capture Elusive Hardware Problems 4 Glitches cause errors in state machine logic 0Counter circuits, trigger circuits, etc. 4 Unexpected signals 4 Very short in duration 4 Hard to detect & trigger on 4 May occur infrequently 29

Logic Analyzer Timing Operation Logic Analyzer Acquires Data on a Clock Edge 4 Timing is clocking internal to the logic analyzer 0Store at fixed intervals - Asynchronous 0Precise time interval measurement for signal to signal edges or pulse/event widths 0Faster the sample rate, the finer the resolution 0Also, called general purpose timing 30

Logic Analyzer Timing Operation Clocking is Internal (From the Logic Analyzer) Target Probing Internal Clocking Analysis & Display Acquisition Memory Trigger Control Logic Analyzer 31

Glitch Errors Glitch Trigger & Display A3 is a 4 bit bus A2 is a 8 bit bus Glitches are occurring on A3 bus 32

Glitch Errors Expand A3 bus into its 4 signal lines A3(3) and A3(0) have glitches 33

Glitch Errors View A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing A3(3) glitches measured with 125 ps resolution 34

Breakthrough 50 GHz MagniVu iview BREAKTHROUGH TECHNOLOGY 50 GHz Timing Simultaneous with up to 2.8 MHz State with up to 3 GHz Analog Anytime on any channel on any model without reconnecting or reacquiring! 34 ch 34 ch 34 ch 34 ch 3 GHz Analog Mux 50 GHz Sample 50 GHz (20 ps) @ 128 Kb depth 4/2/1 GHz adjustable sample rate + - Real-Time Clocking State Machine Trigger State Machine 4 ch Trigger position variable from 0-65% pre-fill Independent MagniVu and Main triggers Always available in ALL clocking modes 50GHz MagniVu Timing 128 Kb 2.8 MHz State or 6.4 GHz Deep Timing 2M 256 Mb Internal DSO or TDS Scope (iview) 35

Glitch Errors Analog measurements time correlated with digital signals A3(3) glitches measured with external oscilloscope using the logic analyzer probes 36

Glitch Caused by PCB Reflection 臨 37

PCB Reflection error 2 ns Deep Timing & 20 ps MagniVu Timing 臨 38

Crosstalk Errors 39

Bus Delay Error 40

(Timing) / 0 0 更更力 ( 料 Level Actions.) 0 流 (Address, Data, Control...) 0 (race conditions),,... 0 41

( 狀 ) 4 / 4 LA 料, 料 4 (Setup) (Hold) 4 LA - 不料度 42

流度 vs. 理度 4 度不流度 33 MHz Clock = 11 MHz Bus Clock 68020 T1 T2 T3 One Bus Cycle R3000 33 MHz Clock = 66 MHz Bus Clock One Bus Cycle One Bus Cycle 43

Setup / Hold Time Requirement DATA D Q OUTPUT CLOCK CK DATA OUTPUT CLOCK 44

Setup-Time 料 DATA D Q OUTPUT CLOCK CK DATA OUTPUT CLOCK Setup Hold 45

DATA D Q OUTPUT CLOCK CK DATA OUTPUT CLOCK? Setup Hold 46

DATA D Q OUTPUT CLOCK CK DATA OUTPUT? CLOCK Setup Hold 47

Hold-Time 料 DATA D Q OUTPUT CLOCK CK DATA OUTPUT CLOCK Setup Hold 48

Setup/Hold Violation Error Caused Glitch 50 GHz (20 ps) MagniVu Timing Data-in(0) changed 1.5 ns before the clock edge Flip-flop setup specification is 2.5 ns Glitch 49

Glitches: Some Causes Violation of Device Input Setup/Hold Timing 4 Input setup timing requirements 0Input signal has to be stable before the clock edge t setup t hold D Input Data 4 Input hold timing requirements 0Input signal has to be stable after the clock edge Clock Clock Input 50

D Flip-Flop Electrical Characteristics 51

Need for 125 ps. Timing Typical Digital Devices Clock Rate Setup Hold Altera Max 7000 PLD 200 MHz 2.5 ns 0.5 ns Lattice GAL22V10-7 PAL 133 MHz 4.5 ns 0 ns TI TMS320C549-40 DSP 80 MHz 5 ns 0 ns Motorola MCM69D536 SRAM 66 MHz 3 ns 1 ns Motorola MPC 860 Comm Controller 50 MHz 4 ns 2 ns IDT 72420L20 Synchronous FIFO 50 MHz 5 ns 1 ns Motorola Coldfire MCF 5206 Microcontroller 33 MHz 3 ns 3 ns Motorola MC68332 Microcontroller 16 MHz 5 ns 0 ns AMD 29DL800B Flash Memory 16 MHz 35 ns 0 ns TI FN74LVC573A Octal Latch n/a 2 ns 1.5 ns 52

State Operation Logic Analyzer Acquires Data on a Clock Edge 4 State is clocking external from the circuit under test 0Store data when valid - Synchronous 0Setup & hold violations 0Use for processor buses & state machines 53

Logic Analyzer State Acquisition Clocking is External (From the Target) Target Probing External Clocking Analysis & Display Acquisition Memory Trigger Control Logic Analyzer 54

Setup/Hold Violation State Acquisition and 50 GHz (20 ps) MagniVu Timing 55

Setup/Hold Violation Data-In Changed 375 ps before Clock edge 56

AutoDeskew Deskew 4 Automate Deskew of logic analyzer sample position 0Per channel analysis 0Supports external, external 2X, external 4X, and custom clock modes 57

AutoDeskew Verify 4 Verify logic analyzer sample position placement 0Utilizes setup/hold violation detection to verify the TLA s ability to capture valid data 58

Timing & State Operation Logic Analyzer Acquires Data on a Clock Edge 4 Timing is clocking internal to the logic analyzer 0Store at fixed intervals - Asynchronous 0Precise time interval measurement for signal to signal edges or pulse/event widths 0Capture glitches 4 State is clocking external from the circuit under test 0Store data when valid - Synchronous 0Use for processor buses & state machines 0Setup/hold violations 59

( 狀 ) 4 0T PERIOD min. ( ) 0T CLOCK min. ( 度 high/low) 0T SU min. ( ) 0T H min. ( ) 4 0T SU min. + T H min. 4( ) 60

(Time stamp) 4 料 4 兩 4 料 61

料 4 狀 (State Analysis) 4 料連 Data A - 1 Data A - 2 Data A - 3 Data A - 4 Data A - 5 Data B - 1 Data B - 2 Data B - 3 Data B - 4 Data B - 5 timestamp timestamp timestamp timestamp timestamp timestamp timestamp timestamp timestamp timestamp CORRELATION Data A - 1 Data A - 2 Data B - 1 Data A - 4 Data A - 5 Data B - 2 Data A - 2 Data A - 3 Data B - 3 Data A - 5 timestamp timestamp timestamp timestamp timestamp timestamp timestamp timestamp timestamp timestamp 62

狀 (State) / 0 理 0 ( ) 0 理流易了 ( ; disassembly) 63

LA - 數 (asynchronous) (synchronous) 狀 (Trigger state machine) (Acquisition memory) 64

(Triggering) 4 LA 料 4 LA 料 4 65

來 4 ( ) 0 料識 ( ) 0 (Timer)/ 數 (Counters) 4 狀 / (Levels) 0 串列 4 (Actions) 0 度 0 列料 66

4 Events Word Recognition Sequence Recognition External Event Actions Stop/Start Storage External Pulse Pause Data Storage Trigger Range Recognition Counter Timer Go State x Control Timer Control Counter 67

Trigger State Machine 4 列 4 狀 0Control Counters/Timers 0Go To State X 0Trigger other modules 0Trigger System Trigger State Machine State 0 State 1 State 2 State 3 68

Trigger State Machine 4 狀 0AND/OR Events 0If/Then/Else State 0 IF (test 0) Else Else Else IF IF (test 1) (test 2) IF (test 3) Conditions Conditions Conditions Conditions Actions Actions Actions Actions 69

Level vs. State Triggering 4 Level vs. State Triggering 0 列理 vs. 列理 4 State Triggering 0 念 = 量 70

Trigger Libraries 4 0 0 參數 0TLA Libraries 71

Triggering 4 更易 0 4 0, 路, 列... 0If A, Then B, Else C 72

LA - 數 (asynchronous) (synchronous) 狀 (Trigger state machine) (Acquisition memory) 73

4 (Acquisition memory) 0 料 0 錄度 0 度 (Deeper memory) = 更 ( 料 ) 4 (Transitional Timing) 力 4 (Qualified Storage) 力 74

度 CAUSE OF PROBLEM PRE-TRIGGER DATA VISIBLE SYMPTOM Trigger Point POST-TRIGGER DATA You CAN'T acquire this data without deeper memory! A B C EXAMPLE: TRIGGER POSITION: DATA CAPTURED: A End of Memory All Pre-Trigger B Center of Memory Half Pre-Trigger/ Half Post-Trigger C Beginning of Memory All Post-Trigger 75

I/O Program - Reads Data & Writes Data Initialize Idel Loop Data Read Process Data Wait for Device Ready Data Write Store Store 料 76

Simultaneous State/Timing - All Through The Same Probe Other Logic Analyzers Multiple probing connections Multiple probe loads per signal Complex user interface setup Extra cost TLA 7000 Series Single probing connection Single probe load per signal Easy-to-access Standard High-Speed Timing Modules General-Purpose Logic Analyzer Modules TLA 7000 Series Logic Analyzer Module 77

Logic Analyzer Support Package 78

Support Package 4 What do you need? 0CPU or Bus 0Package (DIP, PLCC, LCC, PGA, PQFP ) 0Run Control ( Like ICE function ) 4Non-intrusive tool 0High-Level Language support (IEEE 695, OMFx86 ) 0Monitor Multiple CPU or/and Bus 79

Support Package 4 Include Software, Adapter, Disassembly 0Need installation to LA 0Connect to Target Board 0Re-load the support package 0Setup Trigger condition 0Viewing the acquisition data in data window 80

Current Processor/Bus Support TMS @ Intro 8086/88 80186/188 80286 80386DX 80386SX 80386EX i486 P54/P55 P6 8031/51 8096/C196 80C196NX i960ca/cf i960jx i960hx i960rp 68000/10 68020 68030 68040 68060 MCF5202/0 3 CPU32/683 40 68360 R3051/52/8 1 29030/35/40 Z80 PPC60x TMS320C3 x APIC SCSI TMS Post- Intro 80c167 8x251Sx 8x296SA AGP 1X/2X i960rp/rd Pentium II Pentium III MCF5202/04/06 P54/55 MPC505/509 MPC860/821 MPC850/823/801 MPC8260 PPC750/740 PPC403 AMD K6-2 SH-3 Cyrix 6x86 68HC12 TMS320C6201 AGP4X RAMBUS 81 AE Support 1750a 29000/050 320c20/25/32/40/50 6502/802/rc02 6809 68302 68HC11/16 8085 80c166 Arm core GPIB PacqMem 34/68/102/136 PPC603ev Serial TSC701 Z180 M-Core 80C3xx 80C5xx 68180 Third Party Support Compact PCI EISA/ISA MIPS R3081 MIPS R4000 MIPS R5000 MIPS RM5200 MIPS R7000 MIPS RC647x PCI (several variations) PCMCIA Card Bus SIMM DIMM S-DIMM USB VME MPC8240 Strong ARM SA110 5630x

Software Debug solution 4Multi-Processor Embedded Software requires: 0Disassembler Support (see Appendix A) 4Disassembler for processor support 082x0, 74xx, 7x0, 8x0, Mcore, 68K, ColdFire, DSP 4Disassembler for Bus support 0PCI-ExpressGen.2,SATA, Inifiniband, rapid I/O, PCI, CPCI, GBE, USB, 1394, GPIB, Micro channel, Utopia 4Disassembler for Memory structures 0DDRIII1600,RAMBUS, DDR266, DDR400, DDRII667,FBD, PC133, DIMM, SIMM 0Require Deep and Time correlated acquisition 4Micro to Micro Correlation 4Micro to Bus Correlation 4Up to 256M Trace depth per channel 4156ps Timestamp resolution on all channels 82

Embedded Software Debugging Real-time Hardware Trace Real-time Instruction Trace Source Code Debug Non-intrusive 83

High Level Source Debug 84

Integrated HW/SW Development Run Control tools Integrated with Logic Analyzers LA TRACE bridges the gap Run Control JTAG/BDM Ethernet or Parallel interface Target System Real-time Trace Logic Analyzer Probes 4 Utilize logic analyzers to capture information and integrate with run control tools 4 Unify display of data in a single window 4 Key features 0 Sync Wind River ICE with the LA (cross trigger, data transfer) 0 Trace in Wind River's debug window that integrates with the LA 0 Event generation: ability to generate events from Wind River's source window 85

Embedded Systems Development Tools 4 Run Control 0Ability to set hardware/software breakpoints 0Correlated real-time trace of executing software - with Logic Analyzer 0Event Trace capability in native software environment - with Logic Analyzer 0Code instrumentation - with Logic Analyzer 0Code profiling with Cache enabled - with Logic Analyzer 0RTOS Task awareness - with Logic Analyzer 4 Logic Analyzer 0Analog & digital signal acquisition & analysis 0Multiple bus capture 4 Diassassembler for Micro/Buses 4 Fully Correlated Real time analysis 86

Output Window of a Typical Trace System LA Real time trace Data 87

Function Profile 4 All information is extracted From Logic acquired Analyzer Data 0Full Time Stamp available from LA. 0Full Function profile Min, Max & Average Entry to Exit Time 88

Basic Trace and Breakpoints Hardware Code Breakpoint 4 Ability to Set Hardware Code Breakpoint 0Once the Logic Analyzer BP is set, Run the Target until the Breakpoint initiates the Target Stopped MSG (Trigger). 89

Logic Analyzer Setup 4 The Logic Analyzer is configured by LATrace to trigger on 00040670 4 Signal Out will be generated by the TLA when 00040670 is on Address bus. 90

Debugging in a Multiple-Bus Environment 91

Multi-Processor/Bus Environment - Typical Embedded System - Master MPC750 MIPS R7000 Memory Structure RAMBUS DDR SDRAM 603e core 603e core PowerQuiccII Slave 1 PCI/Local Utopia PowerQuiccII Slave 2 PCI/Local Utopia DSP / FPGA / ASIC (Wireless Application) D S x T el c o IF C n t l C P U DSP Codi ng Mod. Filte ring I B u s Q B u s D / A C L K I Q GBE 1394 USB M O D L O R F 92

Five Real-time Instruction TraceWindows 8260 750 FireWire PCI MIP S 93

Integrated Real-time Instruction Trace 8260 750 R7000 PCI 94

Review Platform Architecture Probing IView - Performance Analysis - Function profile Real-Time Correlated Instruction Trace - Conditional Trace - Code instrumentation - Task-Aware Trace 95

External Logic Analyzer Approach Revisited 4 Route internal signals to debug pins 0 Make use of the programmable nature of FPGAs Approach is useful but has limitations 0 Changing probe points often takes recompile 4 Recompile of design changes timing and uses up engineering time 0 1:1 relationship between internal probe points and debug pins limits visibility There is a better FPGAView FPGA Tektronix Logic Analyzer Probe FPGAView Software Test Mux JTAG Cable PC Board JTAG 96

Introducing A Better Way Real-Time Logic Debug Solution for Altera FPGAs A Tektronix, Altera and First Silicon Solutions (FS2) collaboration <<TLA picture>> <<picture>> <<screen shot>> 19 Supports all Tektronix TLA Logic Analyzers Supports complete range of Altera FPGAs FPGAView from First Systems Solutions 97

Real-Time Logic Debug Solution for Altera FPGAs Benefits 4Enables real-time debugging of Altera FPGAs 0For R&D engineers designing with Altera FPGAs 0Allows design teams to view the internal operation of their Altera FPGA design 0Allows correlation of these signals with other board signals 4Increases productivity and cuts debugging time 0Change internal probe points in instant no need to recompile your design 0Monitor multiple internal signals per debug pin 4Easier to use and less intrusive than other debug methodologies! 98

Real-Time Logic Debug Solution for Altera FPGAs overview 4 Software package developed by First Silicon Solutions (www.fs2.com) 0 Supports Altera FPGA devices 0 Runs on Windows 2000 and Windows XP machines Function Multiplexer Control Software Logic Analyzer JTAG Cable Solution Altera Quartus II v5.1 FS2 FPGAView Tektronix TLA Series Logic Analyzer, running v4.3 or later Altera USB-Blaster or ByteBlaster PC Board FPGAView Software FPGA Altera Quartus II v5.1 Logic Analyzer Interface Tektronix Logic Analyzer Probe USB-Blaster or ByteBlaster JTAG 99

Using FPGAView 4 Easy Steps Create the Logic Analyzer Interface Block Configure FPGAView for your debug environment Map FPGA Pins to Logic Analyzer Make Your Measurement 4 Step 1 - Create the Logic Analyzer Interface Block 4 Step 2 - Configure FPGAView for your debug environment 4 Step 3 - Map FPGA Pins to Logic Analyzer 4 Step 4 - Make Your Measurement 100

Using FPGAView Step 1 Create the Logic Analyzer Interface Block 4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface 0Available in all editions of Quartus II, including free Web Edition Specify number of debug pins Specify Number of Banks Specify Mode Specify Clock (if using State Mode) Power-Up Mode 101

Using FPGAView Step 2 Configure FPGAView for your debug environment Specify JTAG Interface Specify TLA Interface Open.lai file 102

Using FPGAView Step 3 Map FPGA Pins to Logic Analyzer 4Use FPGAView to connect FPGA pins to logic analyzer 0Enables automatic channel name updating 0Drag & Drop operation 0Supports multiple LAIs / FPGAs / TLA modules 103

Using FPGAView Step 4 Make Your Measurement 4 Use Bank pull-down list to select Bank to measure 0 After selection, FPGAView sets up LAI via JTAG 0 Programs the TLA with the proper signal names 4 Makes it easy to interpret measurement results 4 Easily switch internal probe points by selecting a different Bank 0 No need to recompile your design 4 Correlate FPGA signals with other signals in your system 104

105 Introducing the Next Generation of the TLA 7000 & TLA5000Series of Logic Analyzers

TLA FAMILY 106

Expand the view of your analysis 15 10.4 38.1 cm 26.4 cm TLA7012 - Largest display on a logic analyzer! 15 Active TFT 107

Easier Access to Results 4 Windows XP Remote Desktop - Send only the screen 4 New Remote Hosted Mode - Send the data for full analysis Lab #1 LAN Internet Lab #2 Lab #3 108

TLA7000 Mainframes 4 TLA7012 Portable Mainframe 2 Module Mainframe 4 TLA7016 Benchtop Mainframe 6 Module Mainframe 109

TLA7012 Portable Mainframe 2 Module Mainframe Product Overview World s largest display on LA 15 inch 38.1 cm (1024x768 resolution) Optional touch screen Compatible with all TLA Modules 6x faster system data throughput PC Hosted UI with V5.0/5.1 TLA App SW Same width & depth as TLA715 2 inch 5.1 cm taller for larger display 110

TLA7012 Portable Mainframe 2 Module Mainframe Product Details Intel 2 GHz Pentium M-760 Intel 915GM chipset (533 MHz FSB) 1 GB DDR2 RAM (expandable to 2 GB) Gigabit Ethernet (GbE) LAN 7 USB 2.0 ports (3 front + 4 rear) 4.7 GB DVD R/RW drive Removable 3.5 80 GB SATA 7200 RPM Hard Drive Dual external display outputs (1600x1200) Optional 3.5 USB floppy available No PC Card, PS/2, serial nor parallel ports USB-to-serial/parallel adapters available via 3 rd parties Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages) USB Security Block for secure environments 111

TLA7012 Portable Configurations LAN 1 2 GbE Switch LAN 4 GbE Switch TLA7012 TLA7012 TekLink Cable TLA7012 Customersupplied PC TLA7012 3 LAN GbE Switch TL708EX Hub TekLink Cable TLA7012 TekLink Cable TLA7016 Config Master Expansion Max # Modules Max # Chs 1 Portable Only --- 2 272 2 Portable 1 Portable 4 544 3 Portable 1 Benchtop 8 1,088 4 Portable 7 Portables 16 2,176 TLA7012 112

TLA7016 Benchtop Mainframe 6 Module Mainframe Product Overview Supports up to 6 TLA modules Compatible with all TLA Modules Requires external PC running TLA App Gigabit Ethernet Slot0 Interface Module that supports DHCP client capability 6x faster system data throughput PC Hosted UI with V5.0/5.1 TLA App SW SW configurable as master or expansion Upgrade kit for TLA720, TLA721 & TLA7XM with ALL TLA7016 features 113

TLA7016 Benchtop Mainframe Accessories TLA7PC1 Benchtop Controller TLA7PC1 Benchtop Controller 020-2665-xx 21 Flat-Panel Display Intel 3 GHz Pentium 4 Intel 865G chipset (800 MHz FSB) 1 GB DDR2 RAM (expandable to 2 GB) Gigabit Ethernet (GbE) LAN 6 USB 2.0 ports (2 front + 4 rear) 4.7 GB DVD R/RW drive Removable 3.5 80 GB SATA 7200 RPM Hard Disk Optional external 3.5 USB floppy available 3x PS/2 (1 front & 2 rear), 1x serial and 1x parallel 3x full-size PCI slots (32-bit, 33 MHz) Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages) 21 Flat Panel Display 1600x1200 native resolution with DVI-D & 15-pin D-Sub inputs 020-2666-xx GbE 16-port Switch GbE Switch 16 autosensing ports TL708EX 8-port Instrument Hub and Expander TL708EX Used to connect 3-to-8 TLA701x mainframes Supports data communication, run control & real-time triggering Simple plug-and-play operation 114

TLA7016 Benchtop Configurations LAN LAN 1 TLA7PC1 Tek PC -OR- GbE Switch 3 TLA7PC1 Tek PC -OR- GbE Switch TLA7016 TLA7016 Customer-supplied PC 2 TLA7PC1 Tek PC GbE Switch LAN Customer-supplied PC TL708EX Hub -OR- TekLink Cable TLA7016 TekLink Cable Customer-supplied PC Config Master Expansion 1 Benchtop Only --- 2 Benchtop 1 Benchtop 3 Benchtop 7 Benchtops TLA7016 Max # Modules 6 12 48 Max # Chs 816 1,632 6,528 TLA7016 115

Easily reconfigure your logic analysis systems TLA721 and TLA7XM-Based System New TLA7016-Based System LAN GbE Switch TLA7016 TLA7PC1 Tek PC TLA7016 -OR - TL708EX Hub 4 30 Big Cables 0 120 screws 4 20 TLA7XM Modules Customer-supplied PC 4 8 GbE LAN Cables 4 8 TekLink Cables 0 32 screws 4 No TLA7XM Modules 50% fewer cables, easier connections, and no specialized expansion mainframes or modules! TekLink Cable 116

V5.0 TLA Application Software Features Simpler navigation with new lookand-feel Explorer window Toolbar buttons Tabbed windows Automated LA data measurements Hosted mode for online or offline operation from external PC Replaces TLAVu Simultaneously connect to multiple TLAs from one PC Only one TLA App-Offline per PC Compatible with all pre-v5.0 TLA setups and data V5.0/5.1 SW Runs On: TLA7012 & TLA7016 TLA520x TLA715 & TLA721 TLA714/720 TLA60x/61x/62x Any PC with WinXP Pro or Win2K Pro Compatible with: Windows XP Professional Windows 2000 Professional 117

Locate and Analyze your Problems More Efficiently Industry First Automated Digital Measurements and Drag-and-Drop Triggers 118

119

Automated 120 LA Data Measurements

121

Drag-n-drop 122 Triggering

Introducing the TLA7A/Bxx Logic Analyzer World's First and Fastest SiGe Logic Analyzer Enhanced iview - Simultaneous Analog & Digital Through the Same Probe Connectorless Compression High-Density Probing 123

The TLA7Axx Logic Analyzer Generational Advance! MagniVu Timing 8 GHz World s Fastest Channels 34 to 136 Ch 680 Ch Merged - 6528 Ch Max State Clock Rate 800 MHz Up to 1.25 Gb/s Data Rate Deep Timing 2 GHz @ 256 Mb World s Deepest Analog Probe Outputs Any of 136 ch Multiplexed to 4 Analog Outputs @ 2 GHz World s First Logic Analyzer with Analog Mux 124

TLA7Axx Module Overview 4 34, 68, 102 & 136 channel modules 4 8 GHz MagniVu timing @ 16 Kb 4 500 MHz deep timing @ 64 Mb (all ch) 4 1 GHz deep timing @ 128 Mb (1/2 ch) 4 2 GHz deep timing @ 256 Mb (1/4 ch) 4 450 MHz state @ 64 Mb (all ch) 4 800 MHz state @ 128 Mb (1/2 ch) 4 1.25 Gb/s data @ 256 Mb (1/4 ch) 4 Next Gen family of high-performance 0.7 pf probes 4 2 GHz analog mux provides any of 136ch to 4 ch analog probe output BNC 125

TLA7Axx Module Characteristics 4 34, 68, 102 & 136 channel modules 4 Up to 680 channels with 5 merged modules 0 All merged channels operate off single timebase 0 Only 102 & 136 channel modules can be merged 4 Up to 8,160 channels with 60 modules 0 TLA721 with 10 TLA7XM expansion mainframes 0 Typical correlation accuracy of 2 ns with any other module 4 4 Analog Probe Output BNCs on every module 4 Securely attach probes-to-module and modules-to-mainframe with captive screws 126

The TLA7Bxx Logic Analyzer Generational Advance! MagniVu Timing 50 GHz World s Fastest Channels 34 to 136 Ch 680 Ch Merged - 8,160 Ch Max State Clock Rate 1400 MHz Up to 2.8 Gb/s Data Rate Deep Timing 6.4 GHz @ 512 Mb World s Deepest Analog Probe Outputs Any of 136 ch Multiplexed to 4 Analog Outputs @ 3 GHz World s First Logic Analyzer with Analog Mux 127

New TLA module TLA7ACx Product TLA7AC2 TLA7AC3 TLA7AC4 Channels per Module 68 102 136 MagniVu Timing 125 ps (8 GHz) @ 16 Kb Deep Timing 500 ps (2 GHz) (1/4 channels) 1 ns (1 GHz) (1/2 channels) 2 ns (500 MHz) (all channels) State Clock/Data Standard 235 MHz Optional 450MHz Analog Mux (icapture) Standard Fixed Analog Outputs with 2 GHz Analog Bandwidth Optional Full Analog Mux Control with 2 GHz Analog Bandwidth Record Length Probes Standard - 2 Mb Optional - 8 Mb, 32 Mb, 128 Mb All P6800/P6900 Series probes 128

New TLA&Bxx module DIGITAL CHARACTERISTICS TLA7BB2 TLA7BB3 TLA7BB4 Digital Channels High Speed Timing (MagniVu) Deep Memory Timing State Speed Memory Depth Probes Analog Mux 68 102 136 50GS/s (20ps)-128k 800/1600/3200/6400 MS/s 1.4GHz/2.8Gbps Standard 2Mb, Maximum 64Mb P68xx and P69xx 3 GHz 129

Enhanced iview 4 iview - Integrated View 0 Introduced May 2001 0 Integrated view of analog and digital on a single TLA display 0 Still required separate LA & scope probes 4 Enhanced iview 0 Adds single analog and digital probing to iview Enhanced iview Single analog and digital probing with integrated view of analog and digital on a single TLA display. 130

Breakthrough Acquisition Technology iview BREAKTHROUGH TECHNOLOGY 50 GHz Timing Simultaneous with up to 2.8 MHz State with up to 3 GHz Analog Anytime on any channel on any model without reconnecting or reacquiring! 34 ch 34 ch 34 ch 34 ch 3 GHz Analog Mux + - 50 GHz Sample r Real-Time Clocking State Machine Trigger State Machine 50 GHz MagniVu Timing 128 Kb 2.8 GHz State or 6.4 GHz Deep Timing 2M Kb 256 Mb 4 ch Internal DSO or TDS Scope (iview) 80 ps glitch triggering & storage with 20 ps resolution 40 ps setup & hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution 20 ps timestamp resolution provides precise time correlation of all data - automatically! Separate MagniVu Trigger independent from main module trigger 131

TLA7A/Bxx Analog Probe Outputs 4 Single-point digital & analog probing! 4 3 GHz analog bandwidth on all channels 4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs (50Ω) 4 Analog probe outputs are always 'live': 0 Use external TDS oscilloscope to monitor signals when TLA7Axx idle 0 Convenient access for other instruments 132

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe External TDS oscilloscope or TLA oscilloscope modules DPO7000 TLA7Dx/Ex DSA/DPO70k/7k 133

Supported Tektronix Oscilloscopes 4 DSA70000 series DPO 0 20GHz bandwidth, 50 Gs/s sample rate 4 TDS7000 Series DPO 0 4 GHz bandwidth, 20 Gs/s sample rate 4 CSA7000 Series DPO 0 4 GHz bandwidth, 20 Gs/s sample rate 4 TDS6000 Series DSO 0 6 GHz bandwidth, 20 Gs/s sample rate 4 TDS3000/3000B Series DPO 0 500 MHz bandwidth, 2.5 Gs/s sample rate 4 Selected TDS600/700 Series Models 0 TDS724D/754C/754D/784C/784D/794D 0 TDS654C/684C/694C All DSA/DPO70K and 7k oscilloscopes require firmware V1.2 or later to work with iview. Before using any oscilloscope with iview, it is recommended that you install the latest firmware upgrade available from Tektronix (www.tek.com) 134

The icapture Toolset 4Quickly and easily find and characterize both analog and digital anomalies with the icapture tool set. 0 iview displays automatically time-correlated analog and digital data in a single logic analyzer display 0 iconnect enables simultaneous digital and analog acquisition through a single probe 0 iverify enables multi-channel analysis and validation using oscilloscope-generated eye diagrams 135

iview 4 iview displays automatically timecorrelated analog and digital data in a single logic analyzer display 136

Analog Mux Now iconnect 4 iconnect enables simultaneous digital and analog acquisition through a single logic analyzer probe 137

iverify 4 iverify enables multichannel analysis and validation using oscilloscope-generated eye diagrams 138

iverify 4 Quickly generate highresolution eye diagrams on multiple channels. 4 Analyze the data by performing measurements 0 Horizontal and vertical histograms 0 Eye-limit 0 4-point and 6-point polygon masks 0 Upper and lower masks 0 Slope 0 Statistical measurements 139

iverify Horizontal and Vertical Histograms 4 Perform Horizontal and Vertical Histograms Simultaneously 4 Provides Hit Data in Window Below 140

iverify Eye Limit Measurement 4 Automatic Eye Limit Measurement 0Eye Height 0Eye Width 141

iverify Four and Six Point Polygon Measurement 4 Four Point and Six Point Polygon Measurements with Number of Hits in Mask 142

iverify Slope Measurement 4 Automatic Slope Measurement in s/v 143

iverify Highlight Channel 4 Highlight Single Channels to Locate Problem Signals Quickly 144

LA Module Standard Probe 4 17 channels per probe (16 data + 1 clock/data) 4 Industry-standard podlets 4 Acquires Simultaneous 2 GHz Timing and 200 MHz State 4 2 pf probe loading P6419 P6410 145

New High-Density Probe 4 Connects 34 channels in an extremely small area 4 Full performance: 200 MHz state and 2 GHz timing 4 Less than 2.5 pf capacitive loading 4 Integral latching mechanism assures reliable connection 146

P68xx/P69xx Logic Analyzer Probe Overview 4 P6810 34-Ch General-Purpose Probe 4 P6860 34-Ch High-Density Probe 4 P6960 34-Ch High-Density Probe 4 P6880 34-Ch High-Density Differential Probe 4 P6980 34-Ch High-Density Differential Probe P6810 General-Purpose P6860 High-Density P6880 Differential High-Density 147

P68xx SiGe Probe Technology Probing BREAKTHROUGH 0.7 pf TOTAL Input Capacitance P6860 High-Density P6880 Differential High-Density P6810 General-Purpose 148

34-Ch High Density Active Probe 4 Simultaneous digital & analog measurements 4 High-density compression probing 4-2.0 V to +5.5 V operating range 4 Minimum input signal swing 0 300 mv or 25% of signal swing, whichever is greater (single-ended) 0 150 mv swing each side (differential) 4 +/-(25 mv +1%) digital threshold accuracy 4 Minimal loading of 0.7 pf @ 20KΩ to ground Two 17 ch probe heads 4 Spare elastomer holders 4 2 ea Thin (Black) 4 2 ea Thick (Gray) 4 PCB layout details in P6810/60/80 Probe Manual 149

34-CH High-Density Differential Active Probe Four 8/9 ch probe heads 4 Simultaneous digital and analog measurements 4 High-density compression probing 4 4 probe-heads support 8/9 Channels each (9 w/ clock/qual) 4 2x mode and 4x modes utilize 2 and 1 probe-head respectively 4 Full differential and single-ended data inputs and clock/quals 4-2.0 V to +5.5 V operating range 4 Minimum input signal swing 0 300 mv or 25% of signal swing, whichever is greater (single-ended) 0 150 mv swing each side (differential) 4 +/-(25 mv +1%) threshold accuracy 4 Minimal loading of 0.7 pf @ 20KΩ to ground 4 Spare elastomer holders 4 2 ea Thin (Black) 4 2 ea Thick (Gray) 4 PCB layout details in P6810/60/80 Probe Manual 150

TLA7Axx Differential Definitions For differential signals, the magnitude of the voltage difference Vmax Vmin (and Vmin-Vmax) must be greater than or equal to 150 mv. 151

High Density Compression Probing No PCB Connectors Required No PCB Connectors Costs Secure & Reliable Connections For P68xx probe design-in information: Refer to P68xx Probe Instruction Manual @ www.tek.com/la 152

34-Ch General-Purpose Active Probe 34 Podlets 4 Simultaneous digital & analog measurements 4 P6417 like with 34-individual active channel podlets 4 Full differential & single-ended data & clock/quals 4 0.100" and 2mm podlet & lead-set connection capability 4-2.0 V to +5.5 V operating range 4 Minimum input signal swing 0 300 mv or 25% of signal swing, whichever is greater (single-ended) 0 150 mv swing each side (differential) 4 +/-(25 mv +1%) threshold accuracy 4 0.7 pf @ 20KΩ to ground loading 4 Probing accessories standard: 4 2 x 1ch leadsets 4 4 x 8ch single-ended leadsets 4 4 x 8ch differential leadsets 4 40 SMT KlipChips 153

The debug power you need; the simplicity you want; and a price you can afford. TLA5000 Series Logic Analyzers 154

Unequaled High Performance Features GHz Deep Memory Timing ps MagniVu Timing MHz State Mb Deep Memory 155

Banner Specifications TLA5201 TLA5202 TLA5203 TLA5204 Channels 34 68 102 136 General-Purpose Deep Timing Memory Timing MagniVu High-Res Timing 2GHz/1GHz/500MHz (Quarter/Half/Full Ch) Ch) 125 ps (8GHz) State 235MHz Memory 2Mb Std 8Mb Opt 32Mb-Opt 156

TLA 7000/5000 Series: The Logic Analyzer for the Entire Digital Design Team Breakthrough Solutions for H/W and S/W Debug David Yang david.yang@tektronix.com (02)-27571517 157

158 Thank You For Attending!